PD - 95850

DIGITAL AUDIO MOSFET

IRLR9343
IRLU9343
Features IRLU9343-701
l Advanced Process Technology
l Key Parameters Optimized for Class-D Audio Key Parameters
Amplifier Applications VDS -55 V
l Low RDSON for Improved Efficiency
RDS(ON) typ. @ VGS = -10V 93 m:
l Low Qg and Qsw for Better THD and Improved

Efficiency RDS(ON) typ. @ VGS = -4.5V 150 m:

l Low Qrr for Better THD and Lower EMI Qg typ. 31 nC
l 175C Operating Junction Temperature for TJ max 175 C
Ruggedness
l Repetitive Avalanche Capability for Robustness and

Reliability D
l Multiple Package Options

D-Pak I-Pak
G
IRLR9343 IRLU9343
I-Pak Leadform 701
S IRLU9343-701
Refer to page 10 for package outline
Description
This Digital Audio HEXFET is specifically designed for Class-D audio amplifier applications. This MosFET utilizes the latest
processing techniques to achieve low on-resistance per silicon area. Furthermore, Gate charge, body-diode reverse recovery
and internal Gate resistance are optimized to improve key Class-D audio amplifier performance factors such as efficiency, THD
and EMI. Additional features of this MosFET are 175C operating junction temperature and repetitive avalanche capability.
These features combine to make this MosFET a highly efficient, robust and reliable device for Class-D audio amplifier
applications.

Absolute Maximum Ratings

Parameter Max. Units
VDS Drain-to-Source Voltage -55 V
VGS Gate-to-Source Voltage 20
ID @ TC = 25C Continuous Drain Current, VGS @ -10V -20 A
ID @ TC = 100C Continuous Drain Current, VGS @ 10V -14
IDM Pulsed Drain Current c -60
PD @TC = 25C Power Dissipation 79 W
PD @TC = 100C Power Dissipation 39
Linear Derating Factor 0.53 W/C
TJ Operating Junction and -40 to + 175 C
TSTG Storage Temperature Range
Clamping Pressure h N
Thermal Resistance
Parameter Typ. Max. Units
RJC Junction-to-Case g 1.9
RJA Junction-to-Ambient (PCB Mounted) gj 50 C/W
RJA Junction-to-Ambient (free air) g 110

Notes through are on page 10

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IRLR/U9343 & IRLU9343-701

Electrical Characteristics @ TJ = 25C (unless otherwise specified)

Parameter Min. Typ. Max. Units Conditions
BVDSS Drain-to-Source Breakdown Voltage -55 V VGS = 0V, ID = -250A
VDSS/TJ Breakdown Voltage Temp. Coefficient -52 mV/C Reference to 25C, ID = -1mA
RDS(on) Static Drain-to-Source On-Resistance 93 105 m VGS = -10V, ID = -3.4A e
150 170 VGS = -4.5V, ID = -2.7A e
VGS(th) Gate Threshold Voltage -1.0 V VDS = VGS, ID = -250A
VGS(th)/TJ Gate Threshold Voltage Coefficient -3.7 mV/C
IDSS Drain-to-Source Leakage Current -2.0 A VDS = -55V, VGS = 0V
-25 VDS = -55V, VGS = 0V, TJ = 125C
IGSS Gate-to-Source Forward Leakage -100 nA VGS = -20V
Gate-to-Source Reverse Leakage 100 VGS = 20V
gfs Forward Transconductance 5.3 S VDS = -25V, ID = -14A
Qg Total Gate Charge 31 47 VDS = -44V
Qgs Gate-to-Source Charge 7.1 VGS = -10V
Qgd Gate-to-Drain Charge 8.5 ID = -14A
Qgodr Gate Charge Overdrive 15 See Fig. 6 and 19
td(on) Turn-On Delay Time 9.5 VDD = -28V, VGS = -10Ve
tr Rise Time 24 ID = -14A
td(off) Turn-Off Delay Time 21 ns RG = 2.5
tf Fall Time 9.5
Ciss Input Capacitance 660 VGS = 0V
Coss Output Capacitance 160 pF VDS = -50V
Crss Reverse Transfer Capacitance 72 = 1.0MHz, See Fig.5
Coss Effective Output Capacitance 280 VGS = 0V, VDS = 0V to -44V
LD Internal Drain Inductance 4.5 Between lead,
nH 6mm (0.25in.)
LS Internal Source Inductance 7.5 from package
and center of die contact f

Avalanche Characteristics
Parameter Typ. Max. Units
EAS Single Pulse Avalanche Energyd 120 mJ
IAR Avalanche Currenti See Fig. 14, 15, 17a, 17b A
EAR Repetitive Avalanche Energy i mJ

Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
IS @ TC = 25C Continuous Source Current -20 MOSFET symbol D

(Body Diode) A showing the

ISM Pulsed Source Current -60 integral reverse G

(Body Diode)c p-n junction diode. S

VSD Diode Forward Voltage -1.2 V TJ = 25C, IS = -14A, VGS = 0V e

trr Reverse Recovery Time 57 86 ns TJ = 25C, IF = -14A
Qrr Reverse Recovery Charge 120 180 nC di/dt = 100A/s e

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 IRLR/U9343 & IRLU9343-701
100 100
VGS VGS
TOP -15V TOP -15V
-12V -12V

-I D, Drain-to-Source Current (A)

-I D, Drain-to-Source Current (A)

-10V -10V
-8.0V -8.0V
-5.5V -5.5V
-4.5V -4.5V
10 10 -3.0V
-3.0V
BOTTOM -2.5V BOTTOM -2.5V

1 1
-2.5V

-2.5V
60s PULSE WIDTH 60s PULSE WIDTH
Tj = 25C Tj = 175C
0.1 0.1
0.1 1 10 100 0.1 1 10 100

-VDS, Drain-to-Source Voltage (V) -VDS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

100.0 2.0

RDS(on) , Drain-to-Source On Resistance

T J = 25C ID = -14A
VGS = -10V
-I D, Drain-to-Source Current ()

T J = 175C

10.0 1.5
(Normalized)

1.0
1.0

VDS = -25V
60s PULSE WIDTH
0.1
0.5
0.0 5.0 10.0 15.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
-V GS, Gate-to-Source Voltage (V)
T J , Junction Temperature (C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature

10000 20
VGS = 0V, f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED ID= -14A
-VGS, Gate-to-Source Voltage (V)

C rss = C gd
VDS= -44V
16 VDS= -28V
C oss = C ds + C gd
VDS= -11V
C, Capacitance (pF)

1000
Ciss 12

Coss
8
Crss
100

4
FOR TEST CIRCUIT
SEE FIGURE 19
0
10
0 10 20 30 40 50
1 10 100
QG Total Gate Charge (nC)
-V DS, Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance vs.Drain-to-Source Voltage Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage
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IRLR/U9343 & IRLU9343-701
100.0 1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)

-I D, Drain-to-Source Current (A)

T J = 175C
-I SD, Reverse Drain Current (A)

10.0 100

T J = 25C 100sec
1.0 10

Tc = 25C
Tj = 175C 1msec
VGS = 0V Single Pulse 10msec
0.1 1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1 10 100 1000

-V SD, Source-to-Drain Voltage (V) -VDS , Drain-toSource Voltage (V)

Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area

20 2.5

-VGS(th) Gate threshold Voltage (V)

16
-I D , Drain Current (A)

2.0
12

ID = -250A

8
1.5

0 1.0
25 50 75 100 125 150 175 -75 -50 -25 0 25 50 75 100 125 150 175

T J , Junction Temperature (C) T J , Temperature ( C )

Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature

10
Thermal Response ( Z thJC )

1 D = 0.50

0.20
0.10 R1 R2
R1 R2 Ri (C/W) i (sec)
0.1 0.05 J C
J 1.162 0.000512
0.02 1 2
1 2 0.7370 0.002157
0.01
Ci= i/Ri
Ci i/Ri
0.01
SINGLE PULSE Notes:
( THERMAL RESPONSE ) 1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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RDS(on), Drain-to -Source On Resistance ( m)
IRLR/U9343 & IRLU9343-701
500
600

EAS, Single Pulse Avalanche Energy (mJ)

ID = -14A ID
TOP -4.0A
500 400 -5.5A
BOTTOM -14A

400
300

300

200
200 T J = 125C

100
100

T J = 25C
0 0
4.0 6.0 8.0 10.0 25 50 75 100 125 150 175

-V GS, Gate-to-Source Voltage (V) Starting T J, Junction Temperature (C)

Fig 12. On-Resistance Vs. Gate Voltage Fig 13. Maximum Avalanche Energy Vs. Drain Current
1000

Allowed avalanche Current vs

Duty Cycle = Single Pulse avalanche pulsewidth, tav
assuming Tj = 25C due to
100
avalanche losses. Note: In no
-Avalanche Current (A)

case should Tj be allowed to

0.01 exceed Tjmax

10
0.05
0.10

0.1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02

tav (sec)
Fig 14. Typical Avalanche Current Vs.Pulsewidth
Notes on Repetitive Avalanche Curves , Figures 14, 15:
140
(For further info, see AN-1005 at www.irf.com)
TOP Single Pulse 1. Avalanche failures assumption:
120 BOTTOM 1% Duty Cycle Purely a thermal phenomenon and failure occurs at a
ID = -14A
EAR , Avalanche Energy (mJ)

temperature far in excess of Tjmax. This is validated for

every part type.
100
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
80 3. Equation below based on circuit and waveforms shown in
Figures 17a, 17b.
60 4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
40 voltage increase during avalanche).
6. Iav = Allowable avalanche current.
20 7. T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25C in Figure 14, 15).
0 tav = Average time in avalanche.
D = Duty cycle in avalanche = tav f
25 50 75 100 125 150 175
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
Starting T J , Junction Temperature (C) PD (ave) = 1/2 ( 1.3BVIav) = DT/ ZthJC
Iav = 2DT/ [1.3BVZth]
Fig 15. Maximum Avalanche Energy Vs. Temperature EAS (AR) = PD (ave)tav
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IRLR/U9343 & IRLU9343-701
Driver Gate Drive
D.U.T Period D=
P.W.
Period
+ P.W.

VGS=10V *
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
- Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse

-
+
Recovery
Current
Body Diode Forward
Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
VDD

RG dv/dt controlled by RG VDD Re-Applied

Driver same type as D.U.T. + Voltage Body Diode Forward Drop
ISD controlled by Duty Factor "D" - InductorInductor
Curent
D.U.T. - Device Under Test Current

Ripple 5% ISD

* Reverse Polarity of D.U.T for P-Channel * VGS = 5V for Logic Level Devices

Fig 16. Peak Diode Recovery dv/dt Test Circuit for P-Channel
HEXFET Power MOSFETs
VDS L

RD
VDS
RG D.U.T
VDD
VGS
IAS A D.U.T.
-V DRIVER
-20V
GS RG -
tp 0.01
+ VDD

-10V
Pulse Width 1 s
Duty Factor 0.1 %
15V

Fig 17a. Unclamped Inductive Test Circuit Fig 18a. Switching Time Test Circuit

I AS
td(on) tr t d(off) tf
VGS
10%

90%
tp
VDS
V(BR)DSS

Fig 17b. Unclamped Inductive Waveforms Fig 18b. Switching Time Waveforms
Id
Vds

Vgs

L
VCC
DUT
0
Vgs(th)
1K

Qgs1 Qgs2 Qgd Qgodr

Fig 19a. Gate Charge Test Circuit Fig 19b Gate Charge Waveform
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 IRLR/U9343 & IRLU9343-701

D-Pak (TO-252AA) Package Outline

Dimensions are shown in millimeters (inches)

2.38 (.094)
6.73 (.265) 2.19 (.086)
6.35 (.250) 1.14 (.045)
0.89 (.035)
-A-
5.46 (.215) 1.27 (.050) 0.58 (.023)
5.21 (.205) 0.88 (.035) 0.46 (.018)

6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235) 10.42 (.410)
1.02 (.040) 9.40 (.370) LEAD ASSIGNMENTS
1.64 (.025) 1 2 3
1 - GATE
0.51 (.020) 2 - DRAIN
-B- MIN. 3 - SOURCE
1.52 (.060) 4 - DRAIN
1.15 (.045)
0.89 (.035)
3X
0.64 (.025) 0.58 (.023)
1.14 (.045) 0.46 (.018)
2X 0.25 (.010) M A M B
0.76 (.030)

2.28 (.090) NOTES:

1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
4.57 (.180) 2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).

D-Pak (TO-252AA) Part Marking Information

Notes : This part marking information applies to devices produced before 02/26/2001
EXAMPLE: T HIS IS AN IRFR120
WIT H AS SEMBLY
LOT CODE 9U1P INT ERNAT IONAL DAT E CODE
RECT IFIER IRFU120
YEAR = 0
LOGO 016
WEEK = 16
9U 1P

ASS EMBLY
LOT CODE

Notes : T his part marking information applies to devices produced after 02/26/2001

EXAMPLE: T HIS IS AN IRFR120

PART NUMBER
WIT H AS SEMBLY INT ERNAT IONAL
LOT CODE 1234 RECT IFIER IRFU120 DAT E CODE
AS SEMBLED ON WW 16, 1999 LOGO 916A YEAR 9 = 1999
IN T HE AS S EMBLY LINE "A" 12 34 WEEK 16
LINE A
ASS EMBLY
LOT CODE

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IRLR/U9343 & IRLU9343-701

I-Pak (TO-251AA) Package Outline

Dimensions are shown in millimeters (inches)

6.73 (.265) 2.38 (.094)

6.35 (.250) 2.19 (.086)
-A-
1.27 (.050) 0.58 (.023)
5.46 (.215)
0.88 (.035) 0.46 (.018)
5.21 (.205)
LEAD ASSIGNMENTS
4 1 - GATE
6.45 (.245) 2 - DRAIN
5.68 (.224) 3 - SOURCE
1.52 (.060) 6.22 (.245) 4 - DRAIN
1.15 (.045) 5.97 (.235)

1 2 3

-B- NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2.28 (.090) 9.65 (.380) 2 CONTROLLING DIMENSION : INCH.
1.91 (.075)
8.89 (.350) 3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).

1.14 (.045) 1.14 (.045)

3X 0.89 (.035)
0.76 (.030) 3X 0.89 (.035)
0.64 (.025)

2.28 (.090) 0.25 (.010) M A M B 0.58 (.023)

0.46 (.018)
2X

I-Pak (TO-251AA) Part Marking Information

Notes : T his part marking information applies to devices produced before 02/26/2001

EXAMPLE: T HIS IS AN IRFR120

INT ERNAT IONAL DAT E CODE
WIT H AS S EMBLY
RECT IFIER IRFU120
LOT CODE 9U1P YEAR = 0
LOGO 016
WEEK = 16
9U 1P

AS S EMBLY
LOT CODE

Notes : T his part marking information applies to devices produced after 02/26/2001

EXAMPLE: T HIS IS AN IRFR120 PART NUMBER

INT ERNAT IONAL
WIT H AS S EMBLY
RECT IFIER IRFU120 DAT E CODE
LOT CODE 5678
LOGO 919A YEAR 9 = 1999
AS SEMBLED ON WW 19, 1999
56 78 WEEK 19
IN T HE AS S EMBLY LINE "A"
LINE A
AS S EMBLY
LOT CODE

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 IRLR/U9343 & IRLU9343-701

D-Pak (TO-252AA) Tape & Reel Information

Dimensions are shown in millimeters (inches)
TR TRR TRL

16.3 ( .641 ) 16.3 ( .641 )

15.7 ( .619 ) 15.7 ( .619 )

12.1 ( .476 ) 8.1 ( .318 )

FEED DIRECTION FEED DIRECTION
11.9 ( .469 ) 7.9 ( .312 )

NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.

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IRLR/U9343 & IRLU9343-701
I-Pak Leadform Option 701 Package Outline
Dimensions are shown in millimeters (inches)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25C, L = 1.24mH,
RG = 25, IAS = -14A.
Pulse width 400s; duty cycle 2%.
This only applies for I-Pak, LS of D-Pak is
measured between lead and center of die contact
R is measured at TJ of approximately 90C.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
10
Contact factory for mounting information
Limited by Tjmax. See Figs. 14, 15, 17a, 17b for repetitive avalanche information
When D-Pak mounted on 1" square PCB (FR-4 or G-10 Material) .
For recommended footprint and soldering techniques refer to
application note #AN-994
Refer to D-Pak package for Part Marking, Tape and Reel information.
Data and specifications subject to change without notice.
This product has been designed for the Industrial market.
Qualification Standards can be found on IRs Web site.
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.4/04
www.irf.com
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/