TABLE OF CONTENTS

Certificate
Acknowledgement
Table of Contents
List of Figures
List of Tables
Abbreviations
Chapter 1: Introduction to VTS
1.1 Introduction
1.2 ATM Security using VTS
1.3 Active versus Passive Tracking
1.4 Types of ATM
1.5 Typical Architecture
1.6 History of ATM
1.6.1 Early Technology
1.6.2 New development in technology
1.7 ATM System Features
1.7.1 ATM Benefits
1.8 ATM in India
Chapter 2: Block Diagram of ATM
2.1 Block Diagram of anti theft ATM Using GSM and Modem
2.2 Hardware Components
2.2.1
2.2.1.1 Working of
2.2.1.2 Triangulation
 2.2.1.3 Augmentation
2.2.2 GSM
2.2.3 RS232 Interface
2.2.3.1 The scope of the standard
2.2.3.2 History of RS 232
2.2.3.3 Limitation of Standard
2.2.3.4 Standard details
2.2.3.5 Connectors
2.2.3.6 Cables
2.2.3.7 Conventions
2.2.3.8 RTS/CTS handshaking
2.2.3.9 3-wire and 5-wire RS-232
2.2.3.10 Seldom used features
2.2.3.11 Timing Signals
2.2.3.12 Other Serial interfaces similar to RS-232
2.2.4 LCD
2.2.4.1 Advantages and Disadvantages

Chapter 3:Working of ATM

3.1 Schematic Diagram of ATM
3.2 Circuit Description
3.3 Circuit Operation
3.3.1 Power
3.3.2 Serial Ports
3.4 Operating procedure
Chapter 4:Microcontroller ARM7
4.1 Features
4.2 The Pin Configuration
4.2.1 Special Function Registers (SFR)
4.3 Memory Organization
4.4 Timers
Chapter 5:GSM Module
5.1 GSM History
5.2 Services Provided by GSM
5.3 Mobile Station
5.4 Base Station Subsystem
5.4.1 Base Station Controller
5.5 Architecture of the GSM Network
5.6 Radio Link Aspects
5.7 Multiple Access and Channel Structure
5.8 Frequency Hopping
5.9 Discontinuous Reception
5.10 Power Control
5.11 Network Aspects
5.12 Radio Resources Management
5.13 Handover
5.14 Mobility Management
5.15 Location Updating
5.16 Authentication and Security
5.17 Communication Management
 5.18 Call Routing
Chapter 6: Receiver
6.1 History
6.1.1 Working and Operation
6.2 Data Decoding
Chapter 7:KEIL Software
7.1 Introduction
7.2 KEIL uVision4
7.3 KEIL Software Programing Procedure
7.3.1 Procedure Steps
7.4 Applications of KEIL Software
Chapter 8:Applications
8.1 Applications
8.2 Limitations
Chapter 9:Result Analysis
Chapter 10:Conclusion and Future Scope
References
 LIST OF FIGURES

Figure 1.1 Vehicle tracking system

Figure 2.1 Block diagram
Figure 2.2 A 25 pin connector as described in the RS-232 standard
Figure 2.3 Trace of voltage levels for uppercase ASCII "K" character
Figure 2.4 Upper Picture: RS232 signalling as seen when probed by an
actual oscilloscope
Figure 2.5 A general purpose alphanumeric LCD, with two lines of
characters.
Figure 3.1 Schematic diagram of vehicle tracing using GSM and
Figure 5.1 Mobile station SIM port
Figure 5.2 Baste Station Subsystem.
Figure 5.3 Siemens BSC
Figure 5.4 Siemens TRAU
Figure 5.5 General architecture of a GSM network
Figure 5.6 Signalling protocol structure in GSM
Figure 5.7 Call routing for a mobile terminating call
Figure 6.1 G.P.S receivers communicating with the satellite
Figure 9.1 Picture of final VTS kit
Figure 9.2 Message received from the VTS kit
 LIST OF TABLES

Table 2.1 Commonly used RS-232 signals and pin assignments

Table 2.2 Pin assignments
Table 2.3 RS-232 Voltage Levels
Table 2.4 TX and RX pin connection
 ABBREVIATIONS
VTS Vehicle Tracking System
GSM Global System for Mobile Communication
Global Positioning System
RI Ring Indicator
Tx Transmitter
Rx Receiver
SFR Special Function Register
LCD Liquid Crystal Display
RAM Random Access Memory
ROM Read Only Memory
RS-232 Recommended Standard
TTL Transistor Transistor Logic
CMOS Complementary Metal Oxide Semi-Conductor
UART Universal Asynchronous Receiver Transmitter
RST Reset
ALE Address Latch Enable
PSEN Program Store Enable
 ARM 7 MICROCONTROLLERS

INTRODUCTION:

The ARM was originally developed at Acorn Computers Limited of Cambridge , England,
between 1983 and 1985. It was the first RISC microprocessor developed for commercial use and
has some significant differences from subsequent RISC architectures. In 1990 ARM Limited
was established as a separate company specifically to widen the exploitation of ARM technology
and it is established as a market-leader for low-power and cost-sensitive embedded
applications. The ARM is supported by a toolkit which includes an instruction set emulator for
hardware modelling and software testing and benchmarking, an assembler, C and C++
compilers, a linker and a symbolic debugger.

The 16-bit CISC microprocessors that were available in 1983 were slower than standard memory
parts. They also had instructions that took many clock cycles to complete (in some cases, many
hundreds of clock cycles), giving them very long interrupt latencies.As a result of these
frustrations with the commercial microprocessor offerings, the design of a proprietary
microprocessor was considered and ARM chip was designed.
ARM 7TDMI-S Processor : The ARM7TDMI-S processor is a member of the ARM family of
general-purpose 32-bit microprocessors. The ARM family offers high performance for very
low-power consumption and gate count. The ARM7TDMI-S processor has a Von Neumann
architecture, with a single 32-bit data bus carrying both instructions and data. Only load, store,
and swap instructions can access data from memory. The ARM7TDMI-S processor uses a three
stage pipeline to increase the speed of the flow of instructions to the processor. This enables
several operations to take place simultaneously, and the processing, and memory systems to
operate continuously. In the three-stage pipeline the instructions are executed in three stages.

The three stage pipelined architecture of the ARM7 processor is shown in the above figure.
ARM7TDMIS stands for
T: THUMB ;
D for on-chip Debug support, enabling the processor to halt in response to a debug request,
M: enhanced Multiplier, yield a full 64-bit result, high performance
I: Embedded ICE hardware (In Circuit emulator)
S : Synthesizable

FEATURES OF ARM PROCESSORS

The ARM processors are based on RISC architectures and this architecture has provided small
implementations, and very low power consumption. Implementation size, performance, and very
low power consumption remain the key features in the development of the ARM devices.

The typical RISC architectural features of ARM are :

A large uniform register file

A load/store architecture, where data-processing operations only operate on register
contents, not directly on memory contents
Simple addressing modes, with all load/store addresses being determined from register
contents and instruction fields only uniform and fixed-length instruction fields, to
simplify instruction decode.
Control over both the Arithmetic Logic Unit (ALU) and shifter in most data-processing
instructions to maximize the use of an ALU and a shifter
Auto-increment and auto-decrement addressing modes to optimize program loops
Load and Store Multiple instructions to maximize data throughput
Conditional execution of almost all instructions to maximize execution throughput.
There are three basic instruction sets for ARM.
A 32- bit ARM instruction set
A 16 bit Thumb instruction set and
The 8-bit Java Byte code used in Jazelle state
The Thumb instruction set is a subset of the most commonly used32-bit ARM
instructions.Thumb instructions operate with the standard ARM register configurations
,enabling excellent interoperability between ARM and Thumb states.This Thumb state is nearly
65% of the ARM code and can provide 160%of the performance of ARM code when working
ona 16-bit memory system. This Thumb mode is used in embedded systems where memory
resources are limited. The Jazelle mode is used in ARM9 processor to work with 8-bit Java
code.
ARCHITECTURE OF ARM PROCESSORS:
The ARM 7 processor is based on Von Neman model with a single bus for both data and
instructions..( The ARM9 uses Harvard model).Though this will decrease the performance of
ARM, it is overcome by the pipe line concept. ARM uses the Advanced Microcontroller Bus
Architecture (AMBA) bus architecture. This AMBA include two system buses: the AMBA
High-Speed Bus (AHB) or the Advanced System Bus (ASB), and the Advanced Peripheral Bus
(APB).
The ARM processor consists of
Arithmetic Logic Unit (32-bit)
One Booth multiplier(32-bit)
One Barrel shifter
One Control unit
Register file of 37 registers each of 32 bits.
In addition to this the ARM also consists of a Program status register of 32 bits, Some
special registers like the instruction register, memory data read and write register and
memory address register ,one Priority encoder which is used in the multiple load and
store instruction to indicate which register in the register file to be loaded or stored and
Multiplexers etc.
ARM Registers : ARM has a total of 37 registers .In which - 31 are general-purpose registers
of 32-bits, and six status registers .But all these registers are not seen at once. The processor
state and operating mode decide which registers are available to the programmer. At any time,
among the 31 general purpose registers only 16 registers are available to the user. The remaining
15 registers are used to speed up exception processing. there are two program status registers:
CPSR and SPSR (the current and saved program status registers, respectively
In ARM state the registers r0 to r13 are orthogonalany instruction that you can apply to r0 you
can equally well apply to any of the other registers.

The main bank of 16 registers is used by all unprivileged code. These are the User mode
registers. User mode is different from all other modes as it is unprivileged. In addition to this
register bank ,there is also one 32-bit Current Program status Register(CPSR)
In the 15 registers ,the r13 acts as a stack pointer register and r14 acts as a link register and r15
acts as a program counter register.
Register r13 is the sp register ,and it is used to store the address of the stack top. R13 is used by
the PUSH and POP instructions in T variants, and by the SRS and RFE instructions from
ARMv6.

Register 14 is the Link Register (LR). This register holds the address of the next instruction after
a Branch and Link (BL or BLX) instruction, which is the instruction used to make a subroutine
call. It is also used for return address information on entry to exception modes. At all other times,
R14 can be used as a general-purpose register.
Register 15 is the Program Counter (PC). It can be used in most instructions as a pointer to the
instruction which is two instructions after the instruction being executed.
The remaining 13 registers have no special hardware purpose.
CPSR : The ARM core uses the CPSR register to monitor and control internal operations. The
CPSR is a dedicated 32-bit register and resides in the register file. The CPSR is divided into
four fields, each of 8 bits wide : flags, status, extension, and control. The extension and status
fields are reserved for future use. The control field contains the processor mode, state, and
interrupt mask bits. The flags field contains the condition flags. The 32-bit CPSR register is
shown below.
Processor Modes: There are seven processor modes .Six privileged modes abort, fast interrupt
request, interrupt request, supervisor, system, and undefined and one non-privileged mode
called user mode.
The processor enters abort mode when there is a failed attempt to access memory. Fast interrupt
request and interrupt request modes correspond to the two interrupt levels available on the ARM
processor. Supervisor mode is the mode that the processor is in after reset and is generally the
mode that an operating system kernel operates in. System mode is a special version of user mode
that allows full read-write access to the CPSR. Undefined mode is used when the processor
encounters an instruction that is undefined or not supported by the implementation. User mode is
used for programs and applications.
Banked Registers : Out of the 32 registers , 20 registers are hidden from a program at different
times. These registers are called banked registers and are identified by the shading in the
diagram. They are available only when the processor is in a particular mode; for example, abort
mode has banked registers r13_abt , r14_abt and spsr _abt. Banked registers of a particular
mode are denoted by an underline character post-fixed to the mode mnemonic or _mode.
When the T bit is 1, then the processor is in Thumb state. To change states the core executes a
specialized branch instruction and when T= 0 the processor is in ARM state and executes ARM
instructions. There are two interrupt request levels available on the ARM processor core
interrupt request (IRQ) and fast interrupt request (FIQ).

V, C , Z , N are the Condition flags .

V (oVerflow) : Set if the result causes a signed overflow

C (Carry) : Is set when the result causes an unsigned carry
Z (Zero) : This bit is set when the result after an arithmetic operation is zero, frequently
used to indicate equality
N (Negative) : This bit is set when the bit 31 of the result is a binary 1.

PIPE LINE : Pipeline is the mechanism used by the RISC processor to execute instructions at
an increased speed. This pipeline speeds up execution by fetching the next instruction while
other instructions are being decoded and executed. During the execution of an instruction ,the
processor Fetches the instruction .It means loads an instruction from memory.And decodes the
instruction i.e identifies the instruction to be executed and finally Executes the instruction and
writes the result back to a register.
The ARM7 processor has a three stage pipelining architecture namely Fetch , Decode and
Execute.And the ARM 9 has five stage Pipe line architecture.The three stage pipelining is
explained as below.

To explain the pipelining ,let us consider that there are three instructions Compare, Subtract and
Add.The ARM7 processor fetches the first instruction CMP in the first cycle and during the
second cycle it decodes the CMP instruction and at the same time it will fetch the SUB
instruction. During the third cycle it executes the CMP instruction , while decoding the SUB
instruction and also at the same time will fetch the third instruction ADD. This will improve the
speed of operation. This leads to the concept of parallel processing .This pipeline example is
shown in the following diagram.
As the pipeline length increases, the amount of work done at each stage is reduced, which allows
the processor to attain a higher operating frequency. This in turn increases the performance. One
important feature of this pipeline is the execution of a branch instruction or branching by the
direct modification of the PC causes the ARM core to flush its pipeline.
Exceptions, Interrupts, and the Vector Table :

Exceptions are generated by internal and external sources to cause the ARM processor to handle
an event, such as an externally generated interrupt or an attempt to execute an Undefined
instruction. The processor state just before handling the exception is normally preserved so that
the original program can be resumed after the completion of the exception routine. More than
one exception can arise at the same time.ARM exceptions may be considered in three groups
1. Exceptions generated as the direct effect of executing an instruction.Software interrupts,
undefined instructions (including coprocessor instructions where the requested coprocessor is
absent) and prefetch aborts (instructions that are invalid due to a memory fault occurring during
fetch) come under this group.
2. Exceptions generated as a side-effect of an instruction.Data aborts (a memory fault during a
load or store data access) are in this group.
3. Exceptions generated externally, unrelated to the instruction flow.Reset, IRQ and FIQ are in
this group.

The ARM architecture supports seven types of exceptions.

i.Reset
ii.Undefined Instruction
iii.Software Interrupt(SWI)
iv. Pre-fetch abort(Instruction Fetch memory fault)
v.Data abort (Data access memory fault)
vi. IRQ(normal Interrupt)
vii. FIQ (Fast Interrupt request).
When an Exception occurs , the processor performs the following sequence of actions:
It changes to the operating mode corresponding to the particular exception.
It saves the address of the instruction following the exception entry instruction in r14 of the
new mode.
 It saves the old value of the CPSR in the SPSR of the new mode.
It disables IRQs by setting bit 7 of the CPSR and, if the exception is a fast interrupt, disables
further fast interrupts by setting bit 6 of the CPSR.
It forces the PC to begin executing at the relevant vector address

Excdption / Interrupt Name Address High Address

Reset RESET 0X00000000 0Xffff0000
Undefined Instruction UNDEF 0X00000004 0Xffff0004
Software Interrupt SWI 0X00000008 0Xffff0008
Pre-fetch Abort PABT 0X0000000C 0Xffff000c
Data Abort DABT 0X00000010 0Xffff0010
Reserved --- 0X00000014 0Xffff0014
Interrupt Request IRQ 0X00000018 0Xffff0018
Fast Interrupt Request FIQ 0X0000001C 0Xffff001c
The exception Vector table shown above gives the address of the subroutine program to be
executed when the exception or interrupt occurs. Each vector table entry contains a form of
branch instruction pointing to the start of a specific routine.
Reset vector is the location of the first instruction executed by the processor when power is
applied. This instruction branches to the initialization code.

Undefined instruction vector is used when the processor cannot decode an instruction.

Software interrupt vector is called when you execute a SWI instruction. The SWI instruction is
frequently used as the mechanism to invoke an operating system routine.

Pre-fetch abort vector occurs when the processor attempts to fetch an instruction from an address
without the correct access permissions. The actual abort occurs in the decode stage.
Data abort vector is similar to a prefetch abort but is raised when an instruction attempts to
access data memory without the correct access permissions.

Interrupt request vector is used by external hardware to interrupt the normal execution flow of
the processor. It can only be raised if IRQs are not masked in the CPSR.

ARM Processor Families

There are various ARM processors available in the market for different application .These are
grouped into different families based on the core .These families are based on the ARM7,
ARM9, ARM10, and ARM11 cores. The numbers 7, 9, 10, and 11 indicate different core
designs. The ascending number indicates an increase in performance and sophistication.
Though ARM 8 was introduced during 1996, it is no more available in the market. The
following table gives a brief comparison of their performance and available resources.

The ARM7 core has a Von Neumannstyle architecture, where both data and instructions use the
same bus. The core has a three-stage pipeline and executes the architecture ARMv4T instruction
set. The ARM7TDMI was introduced in 1995 by ARM. It is currently a very popular core and is
used in many 32-bit embedded processors.

The ARM9 family was released in 1997. It has five stage pipeline architecture .Hence , the
ARM9 processor can run at higher clock frequencies than the ARM7 family. The extra stages
improve the overall performance of the processor. The memory system has been redesigned to
follow the Harvard architecture, with separate data and instruction .buses. The first processor in
the ARM9 family was the ARM920T, which includes a separate D + I cache and an MMU. This
processor can be used by operating systems requiring virtual memory support. ARM922T is a
variation on the ARM920T but with half the D +I cache size.
The latest core in the ARM9 product line is the ARM926EJ-S synthesizable processor core,
announced in 2000. It is designed for use in small portable Java-enabled devices such as 3G
phones and personal digital assistants (PDAs).

The ARM10 was released in 1999 . It extends the ARM9 pipeline to six stages. It also supports
an optional vector floating-point (VFP) unit, which adds a seventh stage to the ARM10 pipeline.
The VFP significantly increases floating-point performance and is compliant with the IEEE
754.1985 floating-point standard.
The ARM1136J-S is the ARM11 processor released in the year 2003 and it is designed for high
performance and power efficient applications. ARM1136J-S was the first processor
implementation to execute architecture ARMv6 instructions. It incorporates an eight-stage
pipeline with separate load store and arithmetic pipelines.
A brief comparison of different ARM families is presented below.
 ARM Year of Architecture Pipeline Operational Multiplier MIPS
Family Release Frequency
ARM7 1995 Von Neumann 3 stage 80 M.Hz 8x32 0.97
ARM9 1997 Harvard 5 stage 150M.Hz 8x32 1.1
ARM10 1999 Harvard 6 stage 260M.Hz 16x32 1.3
ARM11 2003 Harvard 8 stage 335M.Hz 16x32 1.2

ARM INSTRUCTION SET

ARM instructions process data held in registers and only access memory with load and store
instructions. ARM instructions commonly take two or three operands.
For example ,the ADD instruction adds the two values stored in registers r1 and r2 (the source
registers). It stores the result to register r3 (the destination register). ADD r3, r1, r2

ARM instructions are classified into data processing instructions, branch instructions, load-store
instructions, software interrupt instruction, and program status register instructions.

Data Processing Instructions :

The data processing instructions manipulate data within registers. They are move instructions,
Arithmetic instructions, logical instructions, comparison instructions, and multiply instructions.
Most data processing instructions can process one of their operands using the barrel shifter.

Data processing instructions are processed within the arithmetic logic unit (ALU). A unique and
powerful feature of the ARM processor is the ability to shift the 32-bit binary pattern in one of
the source registers left or right by a specific number of positions before it enters the ALU. This
shift increases the power and flexibility of many data processing operations.

There are data processing instructions that do not use the barrel shift, for example, the MUL
(multiply), CLZ (count leading zeros), and QADD (signed saturated 32-bit add) instructions.

i.Move Instructions : Move instruction copies R into a destination register Rd, where R is a
register or immediate value. This instruction is useful for setting initial values and transferring
data between registers.
Example1 : PRE r5 = 5
r7 = 8
MOV r7, r5 ;
POST r5 = 5
r7 = 5

The MOV instruction takes the contents of register r5 and copies them into register r7.
Example 2: MOVS r0, r1, LSL #1

MOVS instruction shifts register r1 left by one bit

Arithmetic Instructions : The arithmetic instructions implement addition and subtraction of

32-bit signed and unsigned values. the various addition and subtraction instructions are given in
table below.

SUB r0, r1, r2 ; This subtract instruction subtracts a value stored in register r2 from a value
stored in register r1. The result is stored in register r0.

RSB r0, r1, #0 ; This reverse subtract instruction (RSB) subtracts r1 from the constant value #0,
writing. the result to r0. You can use this instruction to negate numbers.

SUBS r1, r1, #1 ; The SUBS instruction is useful for decrementing loop counters. In this
example we subtract the immediate value one from the value one stored in
register r1. The result value zero is written to register r1.

Logical Instructions : These Logical instructions perform bitwise logical operations on the two
source registers.
BIC r0, r1, r2 ; BIC, carries out a logical bit clear. register r2 contains a binary pattern where
every binary 1 in r2 clears a corresponding bit location in register r1. This instruction is
particularly useful when clearing status bits and is frequently used to change interrupt masks in
the cpsr.

Comparison Instructions : The comparison instructions are used to compare or test a register
with a 32-bit value. This instruction affects only CPSR register flags.

Branch Instructions: A branch instruction changes the normal flow of execution of a main
program or is used to call a subroutine routine. This type of instruction allows programs to have
subroutines, if-then-else structures, and loops. The change of execution flow forces the program
counter pc to point to a new address.
Example 1: B forward ; (unconditional branch to forward)

ADD r1, r2, #4 ;

ADD r0, r6, #2 ;

ADD r3, r7, #4 ;

forward SUB r1, r2, #4 ;

Similarly Backward branch :

 backward : ADD r1, r2, #4 ;

SUB r1, r2, #4 ;

ADD r4, r6, r7 ;

B backward ; branch to the target backward.

The branch with link, or BL, instruction is similar to the B instruction but overwrites the

link register lr with a return address. It performs a subroutine call.

BL subroutine ; branch to subroutine

CMP r1, #5 ; compare r1 with 5

MOVEQ r1, #0 ; if (r1==5) then r1 = 0 :

Subroutine

MOV pc, lr ; return by moving pc = lr

The Branch Exchange (BX) and Branch Exchange with Link (BLX) are the third type of branch
instruction. The BX instruction uses an absolute address stored in register Rm. It is primarily
used to branch to and from Thumb code. The T bit in the cpsr is updated by the least significant
bit of the branch register. Similarly the BLX instruction updates the T bit of the cpsr with the
least significant bit and additionally sets the link register with the return address.

The details of the branch instructions are given in the table above.

Load-Store Instructions : Load-store instructions transfer data between memory and processor
registers. There are three types of load-store instructions:

Single-register transfer
Multiple-register transfer, and
 Swap.
Single-Register Transfer : These instructions are used for moving a single data item in and out
of a register. The data types supported are signed and unsigned words (32-bit), half-words (16-
bit), and bytes. Ex1: STR r0, [r1] ; = STR r0, [r1, #0] ; store the contents of register r0 to the
memory address pointed to by register r1.

Ex2 : LDR r0, [r1] ; = LDR r0, [r1, #0] ; load register r0 with the contents of the

memory address pointed to by register r1.

Multiple-Register Transfer : Load-store multiple instructions can transfer multiple registers

between memory and the processor in a single instruction. The transfer occurs from a base
address register Rn pointing into memory. Multiple-register transfer instructions are more
efficient than single-register transfers for moving blocks of data around memory and saving and
restoring context and stacks.

Load-store multiple instructions can increase interrupt latency. ARM implementations do not
usually interrupt instructions while they are executing. For example, on an ARM7 a load
multiple instruction takes 2 + N.t cycles, where N is the number of registers to load and t is the
number of cycles required for each sequential access to memory. If an interrupt has been raised,
then it has no effect until the load-store multiple instruction is complete.

Example 1: LDMIA r0!, {r1-r3} ; In this example, register r0 is the base register Rn and is
followed by !, indicating that the register is updated after the instruction is executed. In this case
the range is from register r1 to r3.

Example 2 : LDMIB : load multiple and increment before

Ex 3: LDMIB r0!, {r1-r3} ;

Ex 4 : LDMDA r0!, {r1-r3}

Stack Operations : The ARM architecture uses the load-store multiple instructions to carry out
stack operations. The pop operation (removing data from a stack) uses a load multiple
instruction; similarly, the push operation (placing data onto the stack) uses a store multiple
instruction.

A stack is either ascending (A) or descending (D). Ascending stacks grow towards higher
memory addresses; in contrast, descending stacks which grow towards lower memory addresses.
When a full stack (F)is used , the stack pointer sp points to an address that is the last used or full
location (i.e., sp points to the last item on the stack). In contrast, if an empty stack (E) is used ,
the sp points to an address that is the first unused or empty location (i.e., it points after the last
item on the stack).

Example1 : The STMFD instruction pushes registers onto the stack, updating the sp.

STMFD sp! , {r1,r4}; Store Multiple Full Descending Stack

PRE r1 = 0x00000002

r4 = 0x00000003

sp = 0x00080014

POST r1 = 0x00000002

r4 = 0x00000003

sp = 0x0008000c.

The stack operation is shown by the following diagram.

Example2: The STMED instruction pushes the registers onto the stack but updates register sp to
point to the next empty location as shown in the below diagram..
 PRE r1 = 0x00000002

r4 = 0x00000003

sp = 0x00080010

STMED sp! , {r1,r4} ; Store Multiple Empty Descending Stack

POST r1 = 0x00000002

r4 = 0x00000003

sp = 0x00080008

This operation is explained in the following figure.

Swap Instruction :

The Swap instruction is a special case of a load-store instruction. It swaps (Similar to exchange)
the contents of memory with the contents of a register. This instruction is an atomic operation
it reads and writes a location in the same bus operation, preventing any other instruction from
reading or writing to that location until it completes.Swap cannot be interrupted by any other
instruction or any other bus access. So, the system holds the bus until the transaction is
complete.
Ex 1: SWP : Swap a word between memory and a register tmp = mem32[Rn]
mem32[Rn] =Rm
Rd = tmp

Ex2 : SWPB Swap a byte between memory and a register tmp = mem8[Rn]
mem8[Rn] =Rm
 Rd = tmp.

Ex 3: SWP r0, r1, [r2] ; The swap instruction loads a word from memory into register
r0 and overwrites the memory with register r1.

Software Interrupt Instruction : A software interrupt instruction (SWI) is used to generate a

software interrupt exception, which can be used to call operating system routines.When the
processor executes an SWI instruction, it sets the program counter pc to the offset 0x8 in the
vector table. The instruction also forces the processor mode to SVC, which allows an operating
system routine to be called in a privileged mode. Each SWI instruction has an associated SWI
number, which is used to represent a particular function call or feature.

Ex: 0x00008000 SWI 0x123456

Here 0x123456, is the SWI number used by ARM toolkits as a debugging SWI. Typically
the SWI instruction is executed in user mode.

Program Status Register Instructions : There are two instructions available to directly control
a program status register (PSR). The MRS instruction transfers the contents of either the CPSR
or SPSR into a register.Similarly the MSR instruction transfers the contents of a register into
the CPSR or SPSR .These instructions together are used to read and write the CPSR and
SPSR.
MRS : copy program status register to a general-purpose register , Rd= PSR
MSR : move a general-purpose register to a program status register, PSR[field]=Rm
MSR : move an immediate value to a program status register, PSR[field]=immediate

Ex : MRS r1, CPSR

BIC r1, r1, #0x80 ; 0b01000000
MSR CPSR_C, r1.
The MSR first copies the CPSR into register r1. The BIC instruction clears bit 7 of r1. Register
r1 is then copied back into the CPSR, which enables IRQ interrupts. Here the code preserves all
the other settings in the CPSR intact and only modifies the I bit in the control field.
Loading Constants : In ARM instruction set there are no instructions to move the 32-bit
constant into a register. Since ARM instructions are 32 bits in size, they obviously cannot
specify a general 32-bit constant. To overcome this problem .two pseudo instructions are
provided to move a 32-bit value into a register.
LDR : load constant pseudo instruction Rd= 32-bit constant.
ADR : load address pseudo instruction Rd=32-bit relative address.
The first pseudo instruction writes a 32-bit constant to a register using whatever instructions are
available.
The second pseudo instruction writes a relative address into a register, which will be encoded
using a PC -relative expression.
Example 2: LDR r0, [pc, #constant_number-8-{PC}]

constant _number DCD 0xff00ffff.

Here the LDR instruction loads a 32-bit constant 0xff00ffff into register r0.

Example 3: The same constant can be loaded into the register r0 using the MVN instruction also.
MVN r0, #0x00ff0000
After execution r0 = 0xff00ffff.

Introduction to Thumb instruction set : Thumb encodes a subset of the 32-bit ARM
instructions into a 16-bit instruction set space. Since Thumb has higher performance than ARM
on a processor with a 16-bit data bus, but lower performance than ARM on a 32-bit data bus, use
Thumb for memory-constrained systems. Thumb has higher code densitythe space taken up in
memory by an executable programthan ARM. For memory-constrained embedded systems,
for example, mobile phones and PDAs, code density is very important. Cost pressures also limit
memory size, width, and speed.
Thumb execution is flagged by the T bit (bit [5] ) in the CPSR. A Thumb implementation of the
same code takes up around 30% less memory than the equivalent ARM implementation. Even
though the Thumb implementation uses more instructions ; the overall memory footprint is
reduced. Code density was the main driving force for the Thumb instruction set. Because it was
also designed as a compiler target, rather than for hand-written assembly code. Below example
explains the difference between ARM and Thumb code
From the above example it is clear that the Thumb code is more denser than the ARM code.
Exceptions generated during Thumb execution switch to ARM execution before executing the
exception handler . The state of the T bit is preserved in the SPSR, and the LR of the exception
mode is set so that the normal return instruction performs correctly, regardless of whether the
exception occurred during ARM or Thumb execution.
In Thumb state, all the registers can not be accessed . Only the low registers r0 to r7 can be
accessed. The higher registers r8 to r12 are only accessible with MOV, ADD, or CMP
instructions. CMP and all the data processing instructions that operate on low registers update
the condition flags in the CPSR
The list of registers and their accessibility in Thumb mode are shown in the following table..

S.No Registers Access

1 r0 r7
2 r8 r12
3 r13SP
4 r14 lr
5 r15 PC
6 CPSR
7 SPSR
Fully accessible
Only accessible by MOV ,ADD &CMP
Limited accessibility
Limited accessibility
Limited accessibility
Only indirect access
No access
Form the above discussion, it is clear that there are no MSR and MRS equivalent Thumb
instructions. To alter the CPSR or SPSR , one must switch into ARM state to use MSR and
MRS. Similarly, there are no coprocessor instructions in Thumb state. You need to be in ARM
state to access the coprocessor for configuring cache and memory management.

ARM-Thumb interworking is the method of linking ARM and Thumb code together for both
assembly and C/C++. It handles the transition between the two states. To call a Thumb routine
from an ARM routine, the core has to change state. This is done with the T bit of CPSR . The
BX and BLX branch instructions cause a switch between ARM and Thumb state while branching
to a routine. The BX lr instruction returns from a routine, also with a state switch if necessary.

The data processing instructions manipulate data within registers. They include move
instructions, arithmetic instructions, shifts, logical instructions, comparison instructions, and
multiply instructions. The Thumb data processing instructions are a subset of the ARM data
processing instructions.

Exs : ADC : add two 32-bit values and carry Rd = Rd + Rm + C flag

ADD : add two 32-bit values Rd = Rn + immediate
Rd = Rd + immediate
Rd = Rd + Rm

AND : logical bitwise AND of two 32-bit values Rd = Rd & Rm

ASR : arithmetic shift right Rd = Rm_immediate,
C flag= Rm[immediate 1]
Rd = Rd_Rs, C flag = Rd[Rs - 1]
BIC : logical bit clear (AND NOT) of two 32-bit Rd = Rd AND
NOT(Rm)values
CMN : compare negative two 32-bit values Rn + Rm sets flags
CMP : compare two 32-bit integers Rnimmediate sets flags RnRm sets flags
EOR : logical exclusive OR of two 32-bit values Rd = Rd EOR Rm

LSL : logical shift left Rd = Rm_ immediate,

C flag= Rm[32 immediate]
Rd = Rd_Rs, C flag = Rd[32 Rs]
LSR : logical shift right Rd = Rm_ immediate,
C flag = Rd [immediate 1]
Rd = Rd_ Rs, C flag = Rd[Rs 1]
MOV : move a 32-bit value into a register Rd = immediate
 Rd = Rn
Rd = Rm
MUL : multiply two 32-bit values Rd = (Rm * Rd)[31:0]
MVN : move the logical NOT of a 32-bit value into a register Rd = NOT(Rm)

NEG : negate a 32-bit value Rd = 0 Rm

ORR : logical bitwise OR of two 32-bit values Rd = Rd OR Rm
ROR : rotate right a 32-bit value Rd = Rd RIGHT_ROTATE Rs,
C flag= Rd[Rs1]
SBC : subtract with carry a 32-bit value Rd = Rd Rm NOT(C flag)
SUB : subtract two 32-bit values Rd = Rn immediate
Rd = Rd immediate
Rd = Rn Rm
sp = sp (immediate_2)
TST : test bits of a 32-bit value Rn AND Rm sets flags

Note : Thumb deviates from the ARM style in that the barrel shift operations (ASR, LSL, LSR,
and ROR) are separate instructions.

Thankful to the following people for their invaluable information .

References : 1. ARM System Developers Guide Designing and Optimizing System Software
Andrew N. Sloss , Dominic Symes and Chris Wright.
2. ARM-System on-Chip Architecture Steve Furber.

3. ARM Architecture Reference Manual Copyright 1996-1998, 2000, 2004,

2005
ARM Limited.
 CHAPTER 5
GSM MODULE
5.1 GSM History
The acronym for GSM is Global System for Mobile Communications. During the early 1980s,
analog cellular telephone systems were experiencing rapid growth in Europe, particularly in
Scandinavia and the United Kingdom, but also in France and Germany. Each country developed
its own system, which was incompatible with everyone else's in equipment and operation. This
was an undesirable situation, because not only was the mobile equipment limited to operation
within national boundaries, which in a unified Europe were increasingly unimportant, but there
was also a very limited market for each type of equipment, so economies of scale and the
subsequent savings could not be realized.
The Europeans realized this early on, and in 1982 the Conference of European Posts and
Telegraphs (CEPT) formed a study group called the Groupe Special Mobile (GSM) to study and
develop a pan-European public land mobile system. The proposed system had to meet certain
criteria:
1. Good subjective speech quality
2. Low terminal and service cost
3. Low terminal and service cost
4. Ability to support handheld terminals
5. Support for range of new services and facilities
6. Spectral efficiency
7. ISDN compatibility
8. Pan-European means European-wide. ISDN throughput at 64Kbs was never envisioned,
indeed, the highest rate a normal GSM network can achieve is 9.6kbs.
Europe saw cellular service introduced in 1981, when the Nordic Mobile Telephone System or
NMT450 began operating in Denmark, Sweden, Finland, and Norway in the 450 MHz range. It
was the first multinational cellular system. In 1985 Great Britain started using the Total Access
Communications System or TACS at 900MHz. Later, the West German C-Netz, the French
Radio COM 2000, and the Italian RTMI/RTMS helped make up Europe's nine analog
incompatible radio telephone systems. Plans were afoot during the early 1980s, however, to
create a single European wide digital mobile service with advanced features and easy roaming.
While North American groups concentrated on building out their robust but increasingly fraud
plagued and featureless analog network, Europe planned for a digital future.
In 1989, GSM responsibility was transferred to the European Telecommunication Standards
Institute (ETSI), and phase I of the GSM specifications were published in 1990. Commercial
service was started in mid-1991, and by 1993 there were 36 GSM networks in 22 countries.
Although standardized in Europe, GSM is not only a European standard. Over 200 GSM
networks (including DCS1800 and PCS1900) are operational in 110 countries around the world.
In the beginning of 1994, there were 1.3 million subscribers worldwide, which had grown to
more than 55 million by October 1997. With North America making a delayed entry into the
GSM field with a derivative of GSM called PCS1900, GSM systems exist on every continent,
and the acronym GSM now aptly stands for Global System for Mobile communications.
The developers of GSM chose an unproven (at the time) digital system, as opposed to the then-
standard analog cellular systems like AMPS in the United States and TACS in the United
Kingdom. They had faith that advancements in compression algorithms and digital signal
processors would allow the fulfilment of the original criteria and the continual improvement of
the system in terms of quality and cost. The over 8000 pages of GSM recommendations try to
allow flexibility and competitive innovation among suppliers, but provide enough
standardization to guarantee proper networking between the components of the system. This is
done by providing functional and interface descriptions for each of the functional entities defined
in the system.

5.2 Services Provided by GSM

From the beginning, the planners of GSM wanted ISDN compatibility in terms of the services
offered and the control signalling used. However, radio transmission limitations, in terms of
bandwidth and cost, do not allow the standard ISDN B-channel bit rate of 64 kbps to be
practically achieved.
Telecommunication services can be divided into bearer services, teleservices, and supplementary
services. The most basic teleservice supported by GSM is telephony. As with all other
communications, speech is digitally encoded and transmitted through the GSM network as a
digital stream. There is also an emergency service, where the nearest emergency-service provider
is notified by dealing three digits.
a) Bearer services: Typically data transmission instead of voice. Fax and SMS are examples.
b) Teleservices: Voice oriented traffic.
c) Supplementary services: Call forwarding, caller ID, call waiting and the like.

A variety of data services is offered. GSM users can send and receive data, at rates up to 9600
bps, to users on POTS (Plain Old Telephone Service), ISDN, Packet Switched Public Data
Networks, and Circuit Switched Public Data Networks using a variety of access methods and
protocols, such as X.25 or X.32. Since GSM is a digital network, a modem is not required
between the user and GSM network, although an audio modem is required inside the GSM
network to interwork with POTS.
Other data services include Group 3 facsimile, as described in ITU-T recommendation T.30,
which is supported by use of an appropriate fax adaptor. A unique feature of GSM, not found in
older analog systems, is the Short Message Service (SMS). SMS is a bidirectional service for
short alphanumeric (up to 160 bytes) messages. Messages are transported in a store-and-forward
fashion. For point-to-point SMS, a message can be sent to another subscriber to the service, and
an acknowledgement of receipt is provided to the sender. SMS can also be used in a cell-
broadcast mode, for sending messages such as traffic updates or news updates. Messages can
also be stored in the SIM card for later retrieval.
Supplementary services are provided on top of teleservices or bearer services. In the current
(Phase I) specifications, they include several forms of call forward (such as call forwarding when
the mobile subscriber is unreachable by the network), and call barring of outgoing or incoming
calls, for example when roaming in another country. Many additional supplementary services
will be provided in the Phase 2 specifications, such as caller identification, call waiting, multi-
party conversations.

5.3 Mobile Station

The mobile station (MS) consists of the mobile equipment (the terminal) and a smart card called
the Subscriber Identity Module (SIM). The SIM provides personal mobility, so that the user can
have access to subscribed services irrespective of a specific terminal. By inserting the SIM card
into another GSM terminal, the user is able to receive calls at that terminal, make calls from that
terminal, and receive other subscribed services.
The mobile equipment is uniquely identified by the International Mobile Equipment Identity
(IMEI). The SIM card contains the International Mobile Subscriber Identity (IMSI) used to
identify the subscriber to the system, a secret key for authentication, and other information. The
IMEI and the IMSI are independent, thereby allowing personal mobility. The SIM card may be
protected against unauthorized use by a password or personal identity number.
GSM phones use SIM cards, or Subscriber information or identity modules. They're the biggest
difference a user sees between a GSM phone or handset and a conventional cellular telephone.
With the SIM card and its memory the GSM handset is a smart phone, doing many things a
conventional cellular telephone cannot. Like keeping a built in phone book or allowing different
ring tones to be downloaded and then stored. Conventional cellular telephones either lack the
features GSM phones have built in, or they must rely on resources from the cellular system itself
to provide them. Let me make another, important point.
With a SIM card your account can be shared from mobile to mobile, at least in theory. Want to
try out your neighbours brand new mobile? You should be able to put your SIM card into that
GSM handset and have it work. The GSM network cares only that a valid account exists, not that
you are using a different device. You get billed, not the neighbour who loaned you the phone.
This flexibility is completely different than AMPS technology, which enables one device per
account. No switching around. Conventional cellular telephones have their electronic serial
number burned into a chipset which is permanently attached to the phone. No way to change out
that chipset or trade with another phone. SIM card technology, by comparison, is meant to make
sharing phones and other GSM devices quick and easy.

5.4 Base Station Subsystem:

The Base Station Subsystem is composed of two parts, the Base Transceiver Station (BTS) and
the Base Station Controller (BSC). These communicate across the standardized Abis interface,
allowing (as in the rest of the system) operation between components made by different
suppliers.
The Base Transceiver Station houses the radio transceivers that define a cell and handles the
radio-link protocols with the Mobile Station. In a large urban area, there will potentially be a
large number of BTSs deployed, thus the requirements for a BTS are ruggedness, reliability,
portability, and minimum cost.
The BTS or Base Transceiver Station is also called an RBS or Remote Base station. Whatever
the name, this is the radio gear that passes all calls coming in and going out of a cell site. The
base station is under direction of a base station controller so traffic gets sent there first. The base
station controller, described below, gathers the calls from many base stations and passes them on
to a mobile telephone switch. From that switch come and go the calls from the regular telephone
network. Some base stations are quite small; the one pictured here is a large outdoor unit. The
large number of base stations and their attendant controllers are a big difference between GSM
and IS-136.
5.4.1 Base Station Controller
The Base Station Controller manages the radio resources for one or more BTSs. It
handles radio-channel setup, frequency hopping, and handovers, as described below. The
BSC is the connection between the mobile station and the Mobile service Switching Centre
(MSC).
Another difference between conventional cellular and GSM is the base station
controller. It's an intermediate step between the base station transceiver and the mobile
switch. GSM designers thought this a better approach for high density cellular networks. As one
anonymous writer penned, "If every base station talked directly to the MSC, traffic would
become too congested. To ensure quality communications via traffic management,
the wireless infrastructure network uses Base Station Controllers as a way to segment the
network and control congestion. The result is that MSCs route their circuits to BSCs which
in turn are responsible for connectivity and routing of calls for 50 to 100 wireless base
stations."
Many GSM descriptions picture equipment called a TRAU, which stands for
Transcoding Rate and Adaptation Unit. Of course also known as a Trans-Coding Unit or
TCU, the TRAU is a compressor and converter. It first compresses traffic coming from the
mobiles through the base station controllers. That's quite an achievement because voice
and data have already been compressed by the voice coders in the handset. Anyway, it
crunches that data down even further. It then puts the traffic into a format the
 Mobile Switch can understand. This is the Trans-Coding part of its name, where code in
one format is converted to another. The TRAU is not required but apparently it saves quite a
bit of money to install one.
Here's how Nortel Networks sells their unit: Reduce transmission resources and realize
up to 75% transmission cost savings with the TCU."
"The Trans-Coding Unit (TCU), inserted between the BSC and MSC, enables speech
compression and data rate adaptation within the radio cellular network. The TCU is
designed to reduce transmission costs by minimizing transmission resources between the
BSC and MSC. This is achieved by reducing the number of PCM links going to the BSC,
since four traffic channels (data or speech) can be handled by one PCM time slot.
Additionally, the modular architecture of the TCU supports all three GSM vocoders
(Full Rate, Enhanced Full Rate, and Half Rate) in the same cabinet, providing you with a
complete range of deployment options."
Voice coders or vocoders are built into the handsets a cellular carrier
distributes. They're the circuitry that turns speech into digital. The carrier specifies
which rate they want traffic compressed, either a great deal or just a little. The cellular
system is designed this way, with handset vocoders working in league with the equipment of
the base station subsystem.

5.5 Architecture Of The Gsm Network

A GSM network is composed of several functional entities, whose functions and interfaces are
specified. Figure 1 shows the layout of a generic GSM network. The GSM network can be
divided into three broad parts. The Mobile Station is carried by the subscriber. The Base Station
Subsystem controls the radio link with the Mobile Station. The Network Subsystem, the main
part of which is the Mobile services Switching Centre (MSC), performs the switching of calls
between the mobile users, and between mobile and fixed network users. The MSC also handles
the mobility management operations. Not shown is the Operations and Maintenance Centre,
which oversees the proper operation and setup of the network. The Mobile Station and the Base
Station Subsystem communicate across the Um interface, also known as the air interface or radio
link. The Base Station Subsystem communicates with the Mobile services Switching Centre
across the A interface.
As John states, he presents a generic GSM architecture. Lucent, Ericsson, Nokia, and others
feature their own vision in their own diagrams.
Lucent GSM architecture/Ericsson GSM architecture/Nokia GSM architecture/Siemenss GSM
architecture.

5.6 Radio Link Aspects

The International Telecommunication Union (ITU), which manages the international allocation
of radio spectrum (among many other functions), allocated the bands 890-915 MHz for the
uplink (mobile station to base station) and 935-960 MHz for the downlink (base station to mobile
station) for mobile networks in Europe. Since this range was already being used in the early
1980s by the analog systems of the day, the CEPT had the foresight to reserve the top 10 MHz of
each band for the GSM network that was still being developed. Eventually, GSM will be
allocated the entire 2x25 MHz bandwidth.

5.7 Multiple Access and Channel Structure:

Since radio spectrum is a limited resource shared by all users, a method must be devised to
divide up the bandwidth among as many users as possible. The method chosen by GSM is a
combination of Time- and Frequency-Division Multiple Access (TDMA/FDMA). The FDMA
part involves the division by frequency of the (maximum) 25 MHz bandwidth into 124 carrier
frequencies spaced 200 kHz apart. One or more carrier frequencies are assigned to each base
station. Each of these carrier frequencies is then divided in time, using a TDMA scheme. The
fundamental unit of time in this TDMA scheme is called a burst period and it lasts 15/26 ms (or
approx. 0.577 ms). Eight burst periods are grouped into a TDMA frame (120/26 ms, or approx.
4.615 ms), which forms the basic unit for the definition of logical channels. One physical
channel is one burst period per TDMA frame.
i) Traffic channels
A traffic channel (TCH) is used to carry speech and data traffic. Traffic channels are defined
using a 26-frame multi-frame, or group of 26 TDMA frames. The length of a 26-frame multi-
frame is 120 ms, which is how the length of a burst period is defined (120 ms divided by 26
frames divided by 8 burst periods per frame). Out of the 26 frames, 24 are used for traffic, 1 is
used for the Slow Associated Control Channel (SACCH) and 1 is currently unused (see Figure
2). TCHs for the uplink and downlink are separated in time by 3 burst periods, so that the mobile
station does not have to transmit and receive simultaneously, thus simplifying the electronics.
ii) Control channels
Common channels can be accessed both by idle mode and dedicated mode mobiles. The
common channels are used by idle mode mobiles to exchange the signalling information required
to change to dedicated mode. Mobiles already in dedicated mode monitor the surrounding base
stations for handover and other information. Dedicated mode means a mobile is in use.

5.8 Frequency Hopping

The mobile station already has to be frequency agile, meaning it can move between a transmit/
receive, and monitor time slot within one TDMA frame, which normally are on different
frequencies. GSM makes use of this inherent frequency agility to implement slow frequency
hopping, where the mobile and BTS transmit each TDMA frame on a different carrier frequency.
The frequency hopping algorithm is broadcast on the Broadcast Control Channel. Since
multipath fading is dependent on carrier frequency, slow frequency hopping helps alleviate the
problem. In addition, co-channel interference is in effect randomized.
Here's a huge difference between conventional cellular (IS-136) and GSM: frequency hopping.
When enabled, slots within frames can leapfrog from one frequency to another. In IS-136, by
comparison, once assigned a channel your call stays on that pair of radio frequencies until the
call is over or you have moved to another cell.

5.9 Discontinuous Reception

Another method used to conserve power at the mobile station is discontinuous reception. The
paging channel, used by the base station to signal an incoming call, is structured into sub-
channels. Each mobile station needs to listen only to its own sub-channel. In the time between
successive paging sub-channels, the mobile can go into sleep mode, when almost no power is
used.

5.10 Power Control

There are five classes of mobile stations defined, according to their peak transmitter power, rated
at 20, 8, 5, 2, and 0.8 watts. To minimize co-channel interference and to conserve power, both
the mobiles and the Base Transceiver Stations operate at the lowest power level that will
maintain an acceptable signal quality. Power levels can be stepped up or down in steps of 2 dB
from the peak power for the class down to a minimum of 13 dBm (20 mill watts).
We need only enough power to make a connection. Any more is superfluous. If you can't make a
connection using one watt then two watts won't help at these near microwave frequencies. Using
less power means less interference or congestion among all the mobiles in a cell.
The mobile station measures the signal strength or signal quality (based on the Bit Error Ratio),
and passes the information to the Base Station Controller, which ultimately decides if and when
the power level should be changed. Power control should be handled carefully, since there is the
possibility of instability. This arises from having mobiles in co-channel cells alternating increase
their power in response to increased co-channel interference caused by the other mobile
increasing its power. This in unlikely to occur in practice but it is (or was as of 1991) under
study.
Two points: The first is that the base station can reach out to the mobile and turn down the
transmitting power the handset is using, Very cool. The second point is that a digital signal will
drop a call much more quickly than an analog signal. With an analog radio you can hear through
static and fading. But with a digital radio the connection will be dropped, just like your landline
modem, when too many 0s and 1s go missing. You need more base stations, consequently, to
provide the same coverage as analog.

5.11 Network Aspects

Ensuring the transmission of voice or data of a given quality over the radio link is only part of
the function of a cellular mobile network. A GSM mobile can seamlessly roam nationally and
internationally, which requires that registration, authentication, call routing and location updating
functions exist and are standardized in GSM networks. In addition, the fact that the geographical
area covered by the network is divided into cells necessitates the implementation of a handover
mechanism. These functions are performed by the Network Subsystem, mainly using the Mobile
Application Part (MAP) built on top of the Signalling.
The signalling protocol in GSM is structured into three general layers depending on the interface,
as shown in Figure 3. Layer 1 is the physical layer, which uses the channel structures discussed
above over the air interface. Layer 2 is the data link layer. Across the Um interface, the data link
layer is a modified version of the LAPD protocol used in ISDN (external link), called LAPDm.
Across the A interface, the Message Transfer Part layer 2 of Signalling System Number 7 is
used. Layer 3 of the GSM signalling protocol is itself divided into 3 sub layers.
1. Radio Resources Management
2. Controls the setup, maintenance, and termination of radio and fixed channels,
3. Including handovers.
4. Mobility Management
5. Manages the location updating and registration procedures, as well as security and
authentication.
6. Connection Management
7. Handles general call control, similar to CCITT Recommendation Q.931, and manage
Supplementary Services and the Short Message Service.

5.12 Radio Resources Management

The radio resources management (RR) layer oversees the establishment of a link, both radio and
fixed, between the mobile station and the MSC. The main functional components involved are
the mobile station, and the Base Station Subsystem, as well as the MSC. The RR layer is
concerned with the management of an RR-session [16], which is the time that a mobile is in
dedicated mode, as well as the configuration of radio channels including the allocation of
dedicated channels.
An RR-session is always initiated by a mobile station through the access procedure, either for an
outgoing call, or in response to a paging message. The details of the access and paging
procedures, such as when a dedicated channel is actually assigned to the mobile, and the paging
sub-channel structure, are handled in the RR layer. In addition, it handles the management of
radio features such as power control, discontinuous transmission and reception, and timing
advance.

5.13 Handover
In a cellular network, the radio and fixed links required are not permanently allocated for the
duration of a call. Handover, or handoff as it is called in North America, is the switching of an
on-going call to a different channel or cell. The execution and measurements required for
handover form one of basic functions of the RR layer.
There are four different types of handover in the GSM system, which involve transferring a call
between:
1. Channels (time slots) in the same cell
2. Cells (Base Transceiver Stations) under the control of the same Base Station Controller (BSC),
3. Cells under the control of different BSCs, but belonging to the same Mobile services
Switching Centre (MSC), and
4. Cells under the control of different MSCs.

The first two types of handover, called internal handovers, involve only one Base Station
Controller (BSC). To save signalling bandwidth, they are managed by the BSC without
involving the Mobile services Switching Centre (MSC), except to notify it at the completion of
the handover. The last two types of handover, called external handovers, are handled by the
MSCs involved. An important aspect of GSM is that the original MSC, the anchor MSC, remains
responsible for most call-related functions, with the exception of subsequent inter-BSC
handovers under the control of the new MSC, called the relay MSC.
Handovers can be initiated by either the mobile or the MSC (as a means of traffic load
balancing). During its idle time slots, the mobile scans the BroadcastControl Channel of up to 16
neighbouring cells, and forms a list of the six best candidates for possible handover, based on the
received signal strength. This information is passed to the BSC and MSC, at least once per
second, and is used by the handover algorithm.
The algorithm, for when a hand over decision should be taken is not specified in the GSM
recommendations. There are two basic algorithms used, both closely tied in with power control.
This is because the BSC usually does not know whether the poor signal quality is due to
multipath fading or to the mobile having moved to another cell. This is especially true in small
urban cells.
The 'minimum acceptable performance' algorithm gives precedence to power control over
handover, so that when the signal degrades beyond a certain point, the power level of the mobile
is increased. If further power increases do not improve the signal, then a handover is considered.
This is the simpler and more common method, but it creates 'smeared' cell boundaries when a
mobile transmitting at peak power goes some distance beyond its original cell boundaries into
another cell.
The 'power budget' method uses handover to try to maintain or improve a certain level of signal
quality at the same or lower power level. It thus gives precedence to handover over power
control. It avoids the 'smeared' cell boundary problem and reduces co-channel interference, but it
is quite complicated.

5.14 Mobility Management

The Mobility Management layer (MM) is built on top of the RR layer (radio resources), and
handles the functions that arise from the mobility of the subscriber, as well as the authentication
and security aspects. Location management is concerned with the procedures that enable the
system to know the current location of a powered-on mobile station so that incoming call routing
can be completed.

5.15 Location Updating

A powered-on mobile is informed of an incoming call by a paging message sent over the
PAGCH channel of a cell. One extreme would be to page every cell in the network for each call,
which is obviously a waste of radio bandwidth. The other extreme would be for the mobile to
notify the system, via location updating messages, of its current location at the individual cell
level. This would require paging messages to be sent to exactly one cell, but would be very
wasteful due to the large number of location updating messages. A compromise solution used in
GSM is to group cells into location areas. Updating messages are required when moving between
location areas, and mobile stations are paged in the cells of their current location area.
In conventional cellular location messages are sent to the exact cell a mobile is in. To review, the
VLR Data Base, or Visited or Visitor Location Register, contains all the data needed to
communicate with the mobile switch. Levine says this data includes:
1. Equipment identity and authentication-related data
2. Last known Location Area (LA)
3. Power Class and other physical attributes of the mobile or handset
4. List of special services available to this subscriber
5. More data entered while engaged in a Call
6. Current cell
7. Encryption keys

The location updating procedures, and subsequent call routing, use the MSC and two location
registers: the Home Location Register (HLR) and the Visitor Location Register (VLR). When a
mobile station is switched on in a new location area, or it moves to a new location area or
different operator's PLMN, it must register with the network to indicate its current location. In
the normal case, a location update message is sent to the new MSC/VLR, which records the
location area information, and then sends the location information to the subscriber's HLR. The
information sent to the HLR is normally the SS7 address of the new VLR, although it may be a
routing number. The reason a routing number is not normally assigned, even though it would
reduce signalling, is that there is only a limited number of routing numbers available in the new
MSC/VLR and they are allocated on demand for incoming calls. If the subscriber is entitled to
service, the HLR sends a subset of the subscriber information, needed for call control, to the new
MSC/VLR, and sends a message to the old MSC/VLR to cancel the old registration.
A procedure related to location updating is the IMSI (International Mobile Subscriber Identity)
attach and detach. A detach lets the network know that the mobile station is unreachable, and
avoids having to needlessly allocate channels and send paging messages. an attach is similar to a
location update, and informs the system that the mobile is reachable again. The activation of
IMSI attach/detach is up to the operator on an individual cell basis.

5.16 Authentication and Security

Since the radio medium can be accessed by anyone, authentication of users to prove that they are
who they claim to be is a very important element of a mobile network. Authentication involves
two functional entities, the SIM card in the mobile, and the Authentication Centre (AUC). Each
subscriber is given a secret key, one copy of which is stored in the SIM card and the other in the
AUC. During authentication, the AUC generates a random number that it sends to the mobile.
Both the mobile and the AUC then use the random number, in conjunction with the subscriber's
secret key and a ciphering algorithm called A3, to generate a signed response (SRES) that is sent
back to the AUC. If the number sent by the mobile is the same as the one calculated by the AUC,
the subscriber is authenticated.
The same initial random number and subscriber key are also used to compute the ciphering key
using an algorithm called A8. This ciphering key, together with the TDMA frame number, use
the A5 algorithm to create a 114 bit sequence that is XORed with the 114 bits of a burst (the two
57 bit blocks). Enciphering is an option for the fairly paranoid, since the signal is already coded,
interleaved, and transmitted in a TDMA manner, thus providing protection from all but the most
persistent and dedicated eavesdroppers.
Another level of security is performed on the mobile equipment itself, as opposed to the mobile
subscriber. As mentioned earlier, each GSM terminal is identified by a unique International
Mobile Equipment Identity (IMEI) number. A list of IMEIs in the network is stored in the
Equipment Identity Register (EIR).
The status returned in response to an IMEI query to the EIR is one of the following:
White-listed: The terminal is allowed to connect to the network.
Grey-listed: The terminal is under observation from the network for possible problems.
Black-listed: The terminal has either been reported stolen, or is not type approved (the correct
type of terminal for a GSM network). The terminal is not allowed to connect to the network.

5.17 Communication Management

The Communication Management layer (CM) is responsible for Call Control (CC),
supplementary service management, and short message service management. Each of these may
be considered as a separate sub layer within the CM layer. Call control attempts to follow the
ISDN procedures specified in Q.931, although routing to a roaming mobile subscriber is
obviously unique to GSM. Other functions of the CC sub layer include call establishment,
selection of the type of service (including alternating between services during a call), and call
release.

5.18 Call Routing

Unlike routing in the fixed network, where a terminal is semi-permanently wired to a central
office, a GSM user can roam nationally and even internationally. (With, if needed, a properly
enabled handset.) The directory number dialled to reach a mobile subscriber is called the Mobile
Subscriber ISDN (MSISDN), which is defined by the E.164 numbering plan. This number
includes a country code and a National Destination Code which identifies the subscriber's
operator. The first few digits of the remaining subscriber number may identify the subscriber's
HLR within the home PLMN.
An incoming mobile terminating call is directed to the Gateway MSC (GMSC) function. The
GMSC is basically a switch which is able to interrogate the subscriber's HLR to obtain routing
information, and thus contains a table linking MSISDNs to their corresponding HLR. A
simplification is to have a GSMC handle one specific PLMN. It should be noted that the GMSC
function is distinct from the MSC function, but is usually implemented in an MSC.
PLMN: Public land mobile network. In this context a cellular telephone network. PLMN is
chiefly a European usage.
The routing information that is returned to the GMSC is the Mobile Station Roaming Number
(MSRN), which is also defined by the E.164 numbering plan. MSRNs are related to the
geographical numbering plan, and not assigned to subscribers, nor are they visible to subscribers.
The most general routing procedure begins with the GMSC querying the called subscriber's HLR
for an MSRN. The HLR typically stores only the SS7 address of the subscriber's current VLR,
and does not have the MSRN (see the location updating section). The HLR must therefore query
the subscriber's current VLR, which will temporarily allocate an MSRN from its pool for the
call. This MSRN is returned to the HLR and back to the GMSC, which can then route the call to
the new MSC. At the new MSC, the IMSI corresponding to the MSRN is looked up, and the
mobile is paged in its current location area.
 CHAPTER 6
RECEIVER
6.1 History
The Global Positioning System () is a Global Navigation Satellite System (GNSS) developed by
the United States Department of Defense. It is the only fully functional GNSS in the world. It
uses a constellation of between 24 and 32 Medium Earth Orbit satellites that transmit precise
microwave signals, which enable receivers to determine their current location, the time, and
their velocity. Its official name is NAVSTAR . Although NAVSTAR is not an acronym, a few
acronyms have been created for it. The satellite constellation is managed by the United States
Air Force 50th Space Wing. is often used by civilians as a navigation system.
After Korean Air Lines Flight 007 was shot down in 1983 after straying into the USSR's
prohibited airspace, President Ronald Reagan issued a directive making freely available for
civilian use as a common good. As suggested by physicist D. Fanelli.
A few years before, Since then, has become a widely used aid to navigation worldwide, and a
useful tool for map-making, land surveying, commerce, scientific uses, and hobbies such as geo-
caching. Also, the precise time reference is used in many applications including the scientific
study of earthquakes. is also a required key synchronization resource of cellular networks, such
as the Qualcomm CDMA air interface used by many wireless carriers in a multitude of countries.
The first satellite navigation system, Transit, used by the United States Navy, was first
successfully tested in 1960. Using a constellation of five satellites, it could provide a
navigational fix approximately once per hour. In 1967, the U.S. Navy developed the Imation
satellite which proved the ability to place accurate clocks in space, a technology that relies upon.
In the 1970s, the ground-based Omega Navigation System, based on signal phase comparison,
became the first worldwide radio navigation system.
The design of is based partly on similar ground-based radio navigation systems, such as
LORAN and the Decca Navigator developed in the early 1940s, and used during World War II.
Additional inspiration for the came when the Soviet Union launched the first Sputnik in 1957. A
team of U.S. scientists led by Dr. Richard B. Kershner were monitoring Sputnik's radio
transmissions. They discovered that, because of the Doppler Effect, the frequency of the signal
being transmitted by Sputnik was higher as the satellite approached, and lower as it continued
away from them. Theyrealized that since they knew their exact location on the globe, they could
pinpoint where the satellite was along its orbit by measuring the Doppler distortion.

6.1.1 Working and Operation

When people talk about "a ," they usually mean a receiver. The Global Positioning
System () is actually a constellation of 27 Earth-orbiting satellites (24 in operation and three
extras in case one fails). The U.S. military developed and implemented this satellite
network as a military navigation system, but soon opened it up to everybody else.
Each of these 3,000- to 4,000-pound solar-powered satellites circles the globe at
about 12,000 miles (19,300 km), making two complete rotations every day. The orbits are
arranged so that at anytime, anywhere on Earth, there are at least four satellites "visible" in the
sky.
A receiver's job is to locate four or more of these satellites, figure out the distance to
each, and use this information to deduce its own location. This operation is based on a simple
mathematical principle called trilateration. receiver calculates its position on earth based
on the information it receives from four located satellites. This system works pretty
well, but inaccuracies do pop up. For one thing, this method assumes the radio signals
will make their way through the atmosphere at a consistent speed (the speed of light). In
fact, the Earth's atmosphere slows the electromagnetic energy down somewhat,
particularly as it goes through the ionosphere and troposphere. The delay varies
depending on where you are on Earth, which means it's difficult to accurately factor this into
the distance calculations. Problems can also occur when radio signals bounce off large
objects, such as skyscrapers, giving a receiver the impression that a satellite is farther
away than it actually is. On top of all that, satellites sometimes just send out bad almanac
data, misreporting their own position.
Differential (D) helps correct these errors. The basic idea is to gauge inaccuracy
at a stationary receiver station with a known location. Since the D hardware at the station already
knows its own position, it can easily calculate its receiver's inaccuracy. The station then
broadcasts a radio signal to all D-equipped receivers in the area, providing signal
correction information for that area. In general, access to this correction information makes
D receivers much more accurate than ordinary receivers.
6.2 Data Decoding
G.P.S receiver continuously sends data and the microcontroller receives the data whenever it
requires. The data sent by the G.P.S is a string of characters which should be decoded to the
standard format. This is done by the program which we implement in the controller.
 CHAPTER 7
KEIL SOFTWARE
7.1 Introduction
Many companies provide the ARM7 assembler, some of them provide shareware version of their
product on the Web, Kiel is one of them. We can download them from their Websites. However,
the size of code for these shareware versions is limited and we have to consider which assembler
is suitable for our application.

7.2 KEIL uVision4

Kiel uVision4 is an IDE (Integrated Development Environment) that helps you write, compile,
and debug embedded programs. It encapsulates the following components:
1. A project manager.
2. A make facility.
3. Tool configuration.
4. Editor.
5. A powerful debugger.
6. To help you get started, several example programs

Creating Your Own Application in uVision4

To create a new project in uVision4, you must:
1. Select Project - New Project.
2. Select a directory and enter the name of the project file.
3. Select Project - Select Device and select an 8051, 251, or C16x/ST10 device from the Device
Database
4. Create source files to add to the project.
5. Select Project - Targets, Groups, and Files. Add/Files, select Source Group1, and add the
source files to the project.
6. Select Project - Options and set the tool options. Note when you select the target device from
the Device Database all-special options are set automatically. You typically only need to
configure the memory map of your target hardware. Default memory model settings are optimal
for most
7.3 KEIL Software Programing Procedure
How to write embedded C program in Keil Software?
Following steps are to be followed in order to develop code and test the equipment with
software.

7.3.1 Procedure Steps

Step-1:
Install KEIL MicroVision-4 in your PC, Then after Click on that KEIL UVision-4 icon. After
opening the window go to toolbar and select Project Tab then close previous project.
Step-2:
Next select New Project from Project Tab.
Step-3:
Then it will open Create New Project window. Select the path where you want to save project
and edit project name.
Step-4:
Next it opens Select Device for Target window, It shows list of companies and here you can
select the device manufacturer company.
Step-5:
For an example, for your project purpose you can select the chip as 89c51/52 from Atmel Group.
Next Click OK Button, it appears empty window here you can observe left side a small window
i.e., Project Window. Next create a new file.
Step-6:
From the Main tool bar Menu select File Tab and go to New, then it will open a window, there
you can edit the program.
Step-7:
Here you can edit the program as which language will you prefer either Assembly or C.
Step-8:
After editing the program save the file with extension as .c or .asm, if you write a program in
Assembly Language save as .asm or if you write a program in C Language save as .c in the
selected path. Take an example and save the file as test.c.
Step-9:
Then after saving the file, compile the program. For compilation go to project window select
source group and right click on that and go to Add files to Group.
Step-10:
Here it will ask which file has to Add. For an example here you can add test.c as you saved
before.
Step-11:
After adding the file, again go to Project Window and right click on your c file then select
Build target for compilation. If there is any Errors or Warnings in your program you can
check in Output Window that is shown bottom of the Keil window.
Step-12:
Here in this step you can observe the output window for errors and warnings.
Step-13:
If you make any mistake in your program you can check in this slide for which error and where
the error is by clicking on that error.
Step-14:
After compilation then next go to Debug Session. In Tool Bar menu go to Debug tab and select
Start/Stop Debug Session.
Step-15:
Here a simple program for LEDs Blinking. LEDS are connected to PORT-1. You can observe
the output in that port.
Step-16:
To see the Ports and other Peripheral Features go to main toolbar menu and select peripherals.
Step-17:
In this slide see the selected port i.e, PORT-1.
Step-18:
Start to trace the program in sequence manner i.e., step by step execution and observe the output
in port window.
Step-19:
After completion of Debug Session Create an Hex file for Burning the Processor. Here to create
a Hex file goes to project window and right click on Target next select Option for Target.
Step-20:
It appears one window; here in target tab modify the crystal frequency as you connected to
your microcontroller.
Step-21:
Next go to Output tab. In that Output tab click on Create HEX File and then click OK.
Step-22:
Finally Once again compile your program. The Created Hex File will appear in your path folder.

7.4 Applications of KEIL Software

Select Project - Rebuild all target files or Build target.
i) Debugging an Application in uVision4:
To debug an application created using uVision4,
You must:
1. Select Debug - Start/Stop Debug Session.
2. Use the Step toolbar buttons to single-step through your program. You may enter G, main in
the Output Window to execute to the main C function.
3. Open the Serial Window using the Serial #1 button on the toolbar.
4. Debug your program using standard options like Step, Go, Break, and so on.
ii) Peripheral Simulation:
The uvision4 debugger provides complete simulation for the CPU and on chip peripherals of
most embedded devices. To discover which peripherals of a device are supported, in u vision4.
Select the Simulated Peripherals item from the Help menu. You may also use the web-based
device database. We are constantly adding new devices and simulation support for on-chip
peripherals so be sure to check Device Database often.
 CHAPTER 8
APPLICATIONS

When some technology comes to be used at practical level it happens to cherish both plus as well
as minus points of its own. But sometimes technology may be positive in itself but its application
can be misused. Before we go ahead to give space to any technology in our house or work place
we should have pre-estimates of its fall outs.
The positive aspects of the tracking system can be summarized as follows:
1. Core benefit of tracking vehicle is that one can monitor ones vehicle from a distance whether
on individual or commercial level. It helps busy parents to keep a watch on the children even
from their office and control their roaming here and there. Thus can put a check on their rash
driving. This gives immense relief to business owners as it gives them information about the
misuse of company vehicle or delay in delivering services or drivers violation of speed code, if
any. All this keeps a check on wastage of fuel, time and ensures the better services. With the use
of this technology one need not enquire the location of the vehicle by phone again and again.
One can get all the required details just by a click on the internet. Map on the screen displays the
position of vehicle at a particular time.
2. In view of long journeys and night journeys by car the technology can provide a safety
network to the person in condition of emergency. It can cut time of journey short by providing
the information regarding location, speed, distance from the destination leading to best route
planning.
3. Best feature of the technology is that it is easy to use. just an automated unit is needed to be
installed in the vehicle and connected to the centre which may be provided by some company.
This instrument is monitored by the tracking company which keeps all the records or its
customers locations. All details of location etc. are communicated to the user by cell phone or
internet connection. Increasing productivity of your mobile workers.
4. It helps monitoring employee driving habits and activities.
5. Helps you locate your employees are on-the-road.
6. Helps you verify the employee time sheet.
7. Helps you in monitoring all your vehicles.
8. Helps you in timely delivery of the consignments
9. Helps you monitor the vehicle speeds
10. Helps you in tracking the movement of vehicles on the road

The negative aspects of the tracking system can be summarized as follows:

No technology is free from dark areas. This technology helps monitoring vehicles and children
as well and ensures increased productivity at commercial level and safety at personal level. But
at the same time it encroachesthe privacy of the individual. The liberty of the person gets
restricted. This may lead to business owner to measure the performance of the employee by these
stats only and there leaves no room for human analysis.
Thus technology carries its whites and blues. It depends on the user how to make it.

8.1 Applications
Commercial fleet operators are by far the largest users of vehicle tracking systems. These
systems are used for operational functions such as routing, security, dispatch and collecting on-
board information.
These systems are also used in consumer vehicles as devices for preventing theft and retrieving
stolen/lost vehicles. The signal sent out by the installed device help the police to track the
vehicle. These tracking systems can be used as an alternative for traditional car alarms or in
combination with it. Installing tracking systems can thus bring down the insurance costs for your
vehicle by reducing the risk factor.
Vehicle Tracking systems often have several alternatives, like sending automatic alerts to a
phone or email if the vehicle is moved without due authorization. They can also work as one
layer of several combined security measures.
Apart from security concerns, the tracking systems can also help users such as taxi services to
improve their customer service. The systems enable the operators to identify the empty taxis and
direct the nearest one to pick up the customer.
Vehicle tracking systems can also be applied for monitoring driving behaviour for both
commercial and individual situations. Parents for instance can use tracking devices to keep an
eye on their teenage sons driving.
The applications for this project are in military, navigation, automobiles, aircrafts, fleet
management, remote monitoring, remote control, security systems, teleservices, etc.

Some main advantages of implementing this system are as follows:

1. Fleet monitoring
2. Vehicle scheduling
3. Route monitoring
4. Driver monitoring
5. Accident analysis
6. Geo-fencing geo-coding

8.2 Limitations
1. This program is highly sensitive to the camera position and the environment, so a considerable
amount of tuning has to be done each time a new video is taken or camera position is changed
and even more so if the video is of an entirely new environment.
2. The other limitation is the traffic problem, the program will not able to detect which vehicle to
track if it finds some vehicle in the -6*step_y and +6*step_y of the current guess. If the nearby
vehicle is same as the one in the model. As in our data images if we bring maruti-800 near the
car than the probability of error increases manifolds.
3. If there is noise in the edge detected image, we can't really track the vehicle. What is meant by
noise is that if some humans are coming near to the car then the edge detected image will have
the edges of that human or animal or tree, then the program will try to match those edges with
the car model. The program might treat this match as a success but really it will be off the track.
4. We could not model the curves in the maruti-800, like in some images the driver and the
steering can be seen, but we could not find a solution for that. Also the body of the Maruti can be
best modelled as combination of curves and the lines.
5. Also if distance between the vehicle positions in the two consecutive frames is too much then
this tracking program can't detect the vehicle in the second frame and will try to track it in the
subsequent frame.
6. The main limitation of the software is the real time implementation, this cant be implemented
with this much time efficiency in any of the real time applications. This limitation is mainly due
to the processing time.
 CHAPTER 9
RESULT ANALYSIS

We a team of 4 members have successfully completed our Project on Tracking Down Vehicle
and Locking it remotely using GSM technologies.
We first tried to understand the working of our project through the schematic and then we
proceeded to build the circuit as per the schematic. Initially we faced few problems with the
modem, as it wont work efficiently inside buildings. And also the GSM modem suffered
problems with the coverage area of the Mobile Service Provider. So, we used Airtel as it has
maximum coverage area. In order to solve this problem we can use dedicated servers and
purchasing satellite space so that we can track down the vehicle anytime and anywhere.
The overall developed circuit looks as in the following figure:

The above circuit works mainly by receiving messages from a mobile phone. There are three
messages/commands by which we can track and control the vehicle. They are,
i) TRACK
ii) LOCKD
iii) NLOCK
i) TRACK: Initiates the modem and receives the Latitude and Longitude position and this
information will be sent to the mobile from which it received the message.
ii) LOCKD: When this message is sent, then the Microcontroller initiates the motor which is
located in between the passage of fuel to stop and which in turn stops the vehicle.
iii) NLOCK: This command makes the motor to start again so that the vehicle starts running.
This project can further be crafted by restricting the usage of limited mobile numbers to get
access to the device. This can be made by altering the program.
The message which is sent to the mobile will be as shown in the following figure:

With the knowledge in Electronics and Communications we have successfully completed our
project with perfect results.
 CHAPTER 10
CONCLUSION & FUTURE SCOPE

The project titled tracing down the vehicle using GSM and satellite communication is a model
for vehicle tracking unit with the help of receivers and GSM modem. Vehicle Tracking System
resulted in improving overall productivity with better fleet management that in turn offers better
return on your investments. Better scheduling or route planning can enable you handle larger
jobs loads within a particular time. Vehicle tracking both in case of personal as well as business
purpose improves safety and security, communication medium, performance monitoring and
increases productivity. So in the coming year, it is going to play a major role in our day-to-day
living.
We have completed the project as per the requirements of our project. Finally the aim of the
project i.e. to trace the vehicle is successfully achieved.
Future Scope
1. We can use the EEPROM to store the previous Navigating positions up to 256 locations and
we can navigate up to N number of locations by increasing its memory.
2. We can reduce the size of the kit by using +GSM on the same module.
3. We can increase the accuracy up to 3m by increasing the cost of the receivers.
4. We can use our kit for detection of bomb by connecting to the bomb detector.
5. With the help of high sensitivity vibration sensors we can detect the accident.
6. Whenever vehicle unexpectedly had an accident on the road with help of vibration sensor we
can detect the accident and we can send the location to the owner, hospital and police.
7. We can use our kit to assist the traffic. By keeping the kits in the entire vehicles and by
knowing the locations of all the vehicles.
8. If anybody steals our car we can easily find our car around the globe. By keeping vehicle
positioning vehicle on the vehicle.
 References

[1]. Chen, H., Chiang, Y. Chang, F., H. Wang, H. (2010). Toward Real-Time Precise Point
Positioning: Differential Based on IGS Ultra Rapid Product, SICE Annual Conference, The
Grand Hotel, Taipei, Taiwan August 18-21.
[2]. Asaad M. J. Al-Hindawi, IbraheemTalib, Experimentally Evaluation of /GSM Based
System Design, Journal of Electronic Systems Volume 2 Number 2 June 2012
[3]. Chen Peijiang, Jiang Xuehua, Design and Implementation of Remote monitoring system
based on GSM, vol.42, pp.167-175. 2008.
[4]. V.Ramya, B. Palaniappan, K. Karthick, Embedded Controller for Vehicle In-Front Obstacle
Detection and Cabin Safety Alert System, International Journal of Computer Science &
Information Technology (IJCSIT) Vol 4, No 2, April 2012.
[5]. www.8051projects.com
[6]. www.wikipedia.org.com
[7]. www.atmel.com
[8]. www.tatateleservices.com
[9]. www.roseindia.net