Index

Dont Care Condition, 3.30 Behavioural Modelling, 11.15

2:1 MUX, 5.28 Bi-directional shift register, 7.35
3-Bit flash ADC, 8.19 Binary
4:1 MUX, 5.29 addition, 1.19
4-Bit Parallel Adder-Subtractor, 5.16 arithmetic, 1.18
8:1 MUX, 5.30 code, 2.2
divider, 5.23
A division, 1.21
A Direct Conversion, 8.16 multiplication, 1.21
A/D Converter, 8.16 multiplier, 5.21
Absorption property, 3.3 number system, 1.2
Accuracy, 8.13 ripple Counter, 7.2
ADC configuration, 8.16 subtraction, 1.19
ADC voltage resolution, 8.24 Boolean
Adder, 5.3 Algebra, 3.1
Addition operators, 11.8 circuits, 5.1
Advantages of PLDS, 10.6 Expression, 3.6
Alphanumeric Code, 2.9 BOUDETS code, 2.9
Analog v/s Digital, 8.1 Brain teaser, 2.11,1.28, 4.40
AND logic gate, 9.9 Buffer Gate, 4.10
Applications of MUX, 5.42
Architecture, 11.12 C
Arithmetic and Logical Circuits, 5.3 Canonical Form, 3.14
Arithmetic operations, 1.18 case statement, 11.18
Associative property, 3.3 Classification of Codes, 2.1
Asynchronous down counter, 7.6 clock pulse width, 6.36
Asynchronous Sequential Circuit, 6.2 codes, 2.1
Asynchronous up-down counter, 7.8 Coincident Decoding, 10.5
Combinational Logic Circuit, 5.2
B combinational logic, 5.1
Basics of memory, 10.2 Commutative property, 3.3
BCD adder, 5.19 Complementation/ Negation Law, 3.5
I.2 Digital Electronics, an easy approach to learn

Complements, 1.14 Erasable ROM, 10.15

Consensus law, 3.4 Error detecting and correcting code,
Constant, 11.11 2.7
Conversion time, 8.25 Essential prime implicants, 3.32
Counter decoder, 7.5
Counter Type ADC, 8.22 F
counter, 7.1 Field Programmable Gate Array, 10.11
Cyclic Code, 2.11 Finite State Machine (FSM), 6.3
Five Variable K-Map, 3.33
D Flash Memory, 10.16
D/A converter, 8.7 flash type ADC, 8.21
DAC configuration, 8.3 Flip Flop, 6.20
Data Types, 11.2 Floating Point Representation, 1.27
Dataflow Modelling, 11.13 FPGA structure, 10.11
Decimal number system, 1.2 Full adder, 5.5
De-Morgans law, 3.6, 3.7
Demultplexer (DEMUX), 5.43
G
Description of modes, 7.44 Gate delay, 9.4
Design flexibility, 10.6 Gated SR latch, 6.17
Design of parity checker, 5.64 Graphic symbol of gates, 4.11
Digital Logic Families, 9.1 Gray code, 2.4
Digital To Analog Converter, 8.3 Gray to binary conversion, 2.5
Diode Logic, 9.8 Gray-binary conversion, 2.4
Diode Transistor Logic (DTL), 9.12
Distributive property, 3.3 H
Dither, 8.25 Half adder, 5.3
duality principle, 3.7 Half subtractor, 5.11
Duality Theorem, 3.4 hamming code, 2.7
duality theorem, 3.7 Hamming distance, 2.7
Dynamic Random Access Memory, Hexadecimal number system, 1.2
10.12 High Threshold Logic (HTL), 9.13

E I
EBCDIC code, 2.9 IC Gates, 4.14
ECL characteristics, 9.18 Idempotent Law, 3.5
elseif statement, 11.17 Identifier, 11.10
Emitter Coupled Logic(ECL), 9.17 Identity law, 3.5
Encoder, 5.49 if statement, 11.16
Entity Declaration, 11.11 Improved reliability, 10.6

Included factor law, 3.4
Inhibitive Inputs, 4.28
Input voltage range, 8.25
J Non-Binary Code, 2.2
JK Flip Flop, 6.28
Johnson or Twisted Ring Counter, 7.28
K
Karnaugh Map, 3.1, 3.18
L O
left shift register, 7.37
Limitations, 10.13
Linearity, 8.13
Logic diagram, 5.4
Logic expression, 4.4
Logic expression, 5.5
logic family, 9.1
Logic gates, 4.1
Logic symbol, 5.12
Logic System, 4.1
Logical operators, 11.7
Lower power, 10.6
M Parallel binary adder, 5.8
Magnetic Memory, 10.16
Magnitude Comparator, 5.24
Master slave latches, 6.38
Master-slave JK latch, 6.38
Mealy state machine, 6.3
memory stores, 10.1
Miscellaneous operators, 11.9
Moore state machine, 6.4
Morse code, 2.2
Multiplexer (MUX), 5.27
Multiplying operators, 11.9
N Programmable Read Only Memory,
NAND based SR latch, 6.11
Index I.3
Negative level logic system, 4.2
Noise margin, 9.4
Non Degenerated Forms, 4.39
Non-weighted code, 2.4
NOR based S - R latch, 6.5
Not Gate (Inverter), 4.3
Null Law, 3.5
Number Systems, 1.2
Octal addition, 1.22
Octal arithmetic, 1.22
Octal division, 1.24
Octal multiplication, 1.23
Octal number system, 1.2
Octal subtraction, 1.23
Odd parity bit, 5.64
Offset error, 8.14
Operation, 5.17
OR logic gate, 9.8
P
Packed BCD, 2.3
Parity bit, 2.6
Parity checker, 5.64
Parity generator, 65
Parity Generator/Checker, 5.64
Positive level logic system, 4.2
Power dissipation, 9.6
Prime Implicants, 3.31
Priority encoder, 5.52
Programmable Array Logic (PAL), 10.8
Programmable Logic Array (PLA),
10.9
Programmable Logic Devices (PLDS),
10.6
10.7
I.4 Digital Electronics, an easy approach to learn

Propagation delay, 9.4 Static Random Access Memory, 10.13

Q Structural Modelling, 11.21
Subtractors, 5.11
Quine-Mccluskey, 3.1
Sum Of Product, 3.14
R Synchronous Sequential Circuit, 6.2
R - 2R Ladder type DAC, 8.7 T
Race Around Condition, 6.35
Temperature sensitivity, 8.14
Random Access Memory, 10.12
Timing diagram of NOT gate, 4.4
Read Only Memory, 10.15
Totem pole output configuration, 9.14
Reduced complexity, 10.6
Transportation law, 3.4
Reflective Code, 2.10
Tristate configuration of TTL, 9.16
Relational operators, 11.7
Truth Table, 3.16
Resistor Transistor Logic(RTL), 9.10
Rise time and fall time, 9.7 U
RTL NOR gate, 9.11
Unary operators, 11.9
S Universal Gates, 4.18
Sequential logic circuits, 5.2 V
Sequential logic, 6.1
Settling time, 8.13 Variable, 11.11
Seven Segment Display, 5.58 VHDL code, 11.2
Shift operators, 11.8 VHDL Libraries, 11.1
Signals, 11 VHDL, 11.1
Signed - 1s complement representa-
W
tion, 1.17
Signed Binary Numbers, 1.16 Weighted code, 2.2
Signed magnitude representation, 1.17 Weighted resistor type DAC, 8.3
Specification of ADC, 8.24 Wire delay, 9.4
Specification of Logic Devices, 9.2 Wired Logic, 4.29
Specifications for DAC, 8.12
SR Flip Flop, 6.22
S-R Latch (Set-Reset), 6.5