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LM2840/1/2-ADJL
VIN
VIN CB D1
SHDN SW
GND FB
R1
CIN R2 COUT
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM2840-Q1, LM2841-Q1, LM2842-Q1
LM2841, LM2842, LM2840
SNVS540J MARCH 2009 REVISED FEBRUARY 2017 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.1 Application Information............................................ 10
2 Applications ........................................................... 1 8.2 Typical Applications ................................................ 10
3 Description ............................................................. 1 9 Power Supply Recommendations...................... 15
4 Revision History..................................................... 2 10 Layout................................................................... 16
5 Pin Configuration and Functions ......................... 3 10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 16
6 Specifications......................................................... 3
6.1 Absolute Maximum Ratings ..................................... 3 11 Device and Documentation Support ................. 17
6.2 ESD Ratings.............................................................. 3 11.1 Custom Design With WEBENCH Tools ............. 17
6.3 Recommended Operating Conditions....................... 4 11.2 Device Support...................................................... 17
6.4 Thermal Information .................................................. 4 11.3 Documentation Support ........................................ 17
6.5 Electrical Characteristics .......................................... 4 11.4 Related Links ........................................................ 17
6.6 Typical Characteristics .............................................. 6 11.5 Receiving Notification of Documentation Updates 17
11.6 Community Resources.......................................... 18
7 Detailed Description .............................................. 8
11.7 Trademarks ........................................................... 18
7.1 Overview ................................................................... 8
11.8 Electrostatic Discharge Caution ............................ 18
7.2 Functional Block Diagram ......................................... 8
11.9 Glossary ................................................................ 18
7.3 Feature Description................................................... 8
7.4 Device Functional Modes.......................................... 9 12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
8 Application and Implementation ........................ 10
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Added Thermal Information table ........................................................................................................................................... 4
DDC Package
6-Pin SOT
Top View
CB 1 6 SW
GND 2 5 VIN
FB 3 4 SHDN
Not to scale
Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
1 CB I SW FET gate bias voltage. Connect CBOOT capacitor between CB and SW.
2 GND Ground connection
Feedback pin: Set feedback voltage divider ratio with VOUT = VFB (1 + (R1 / R2)). Resistors must be from
3 FB I
100 to 10 k to avoid input bias errors.
Logic level shutdown input. Pull to GND to disable the device and pull high to enable the device. If this function
4 SHDN I
is not used tie to VIN . DO NOT ALLOW TO FLOAT.
5 VIN I Power input voltage pin: 4.5-V to 42-V normal operating range.
6 SW O Power FET output: Connect to inductor, diode, and CBOOT capacitor.
6 Specifications
6.1 Absolute Maximum Ratings
(1) (2)
See
MIN MAX UNIT
VIN 0.3 45 V
SHDN 0.3 (VIN + 0.3 V) < 45 V
SW voltage 0.3 45 V
CB voltage above SW voltage 7 V
FB voltage 0.3 5 V
Power dissipation (3) Internally Limited
Maximum junction temperature 150 C
Storage temperature, Tstg 65 150 C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal
resistance, RJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated
using: PD (MAX) = (TJ(MAX) TA)/RJA. Exceeding the maximum allowable power dissipation causes excessive die temperature, and the
regulator goes into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. Thermal
shutdown engages at TJ=175C (typical) and disengages at TJ= 155C (typical).
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(1) All limits specified at room temperature (TA = 25C) unless otherwise specified. All room temperature limits are 100% production tested.
All limits at temperature extremes are ensured through correlation using standard Statistical Quality Control (SQC) methods. All limits
are used to calculate Average Outgoing Quality Level (AOQL).
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The package thermal impedance is calculated in accordance to JESD 51-7.
(3) Thermal Resistances were simulated on a 4-layer, JEDEC board
(4)
0.9
RDSON Switch ON resistance See
TJ = 40C to 125C 1.6
0
ILSW Switch leakage current VIN = 42 V A
TJ = 40C to 125C 0.5
525
LM2840 (5) mA
TJ = 40C to 125C 900
525
ICL Switch current limit LM2841 (5) mA
TJ = 40C to 125C 900
1.15
LM2842 (5) A
TJ = 40C to 125C 1.7
0.1
IFB Feedback pin bias current LM284[0,1,2] (6) A
TJ = 40C to 125C 1
(1) All limits specified at room temperature (TA = 25C) unless otherwise noted. Room temperature limits are production tested. Limits at
temperature extremes are ensured through correlation using standard Statistical Quality Control (SQC) methods. Limits are used to
calculate Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25C and represent the most likely norm.
(3) The part numbers in this table represent both the Q1 and non-Q1 versions of the respective parts.
(4) Includes the bond wires, RDSON from VIN pin to SW pin.
(5) Current limit at 0% duty cycle. May be lower at higher duty cycle or input voltages below 6 V.
(6) Bias currents flow into pin.
4 Submit Documentation Feedback Copyright 20092017, Texas Instruments Incorporated
(7)
100
tON(min) Minimum ON-time See ns
TJ = 40C to 125C 150
110
X option ns
TJ = 40C to 125C 370
tOFF(min) Minimum OFF-time
104
Y option ns
TJ = 40C to 125C 200
550
X option, VFB = 0.5 V
TJ = 40C to 125C 325 750 kHz
X option, VFB = 0 V 140
fSW Switching frequency
1.25
Y option, VFB = 0.5 V
TJ = 40C to 125C 0.95 1.5 MHz
Y option, VFB = 0 V 0.35
94%
X option
TJ = 40C to 125C 88%
DMAX Maximum duty cycle
87%
Y option
TJ = 40C to 125C 81%
3.7
On threshold
Undervoltage lockout TJ = 40C to 125C 4.4
VUVP V
thresholds 3.5
Off threshold
TJ = 40C to 125C 3.25
1
Device ON
TJ = 40C to 125C 2.3
V SHDN Shutdown threshold V
0.9
Device OFF
TJ = 40C to 125C 0.3
0.05
VSHDN = 2.3 V (6)
Shutdown pin input bias TJ = 40C to 125C 1.5
ISHDN A
current 0.02
VSHDN = 0 V
TJ = 40C to 125C 1.5
100 100
VIN = 12V
VIN = 12V
80 80
VIN = 36V
EFFICIENCY (%)
EFFICIENCY (%)
VIN = 36V
60 60
VIN = 24V
VIN = 24V
40 40
20
20
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0
0.0 0.1 0.2 0.3
LOAD CURRENT (A) LOAD CURRENT (A)
LM2842X VOUT = 3.3 V LM2841X VOUT = 3.3 V
60
50
40
30
20
10
0
0 20 40 60 80 100 120
600
400
200
0
1.0 1.6 2.2 2.8 3.4 4.0
Figure 5. Input UVLO Voltage vs Temperature Figure 6. Switch Current Limit vs SHDN Pin Voltage
1.0
0.9
0.7
0.6
0.4
1.1 1.7 2.3 2.8 3.4 4.0
Figure 7. Switch Current Limit vs SHDN Pin Voltage Figure 8. SHDN Pin Current vs SHDN Pin Voltage
7 Detailed Description
7.1 Overview
The LM284x and LM284x-Q1 SIMPLE SWITCHER regulators are easy-to-use, non-synchronous, step-down
DC-DC converters with a wide input voltage range up to 42 V. The devices are capable of delivering up to
100mA, 300-mA, or 600-mA DC load current with excellent line and load regulation. These devices are available
in fixed frequency of 550 kHz and 1.25 MHz. The family requires few external components, and the pin
arrangement was designed for simple, optimum PCB layout.
VIN
+ Max Duty
+ Cycle Limit
OSC
Inductor
Current
SET DC Measurement
FB LIMIT
+
PWM BUCK FET
Comp RESET DRIVE Driver
- SW
UVLO
-
Error TSD
Amp
+ UVLO
Comp
Voltage
Soft Thermal Regulator
Bandgap Shutdown BG
Start
GND
SHDN
Copyright 2016, Texas Instruments Incorporated
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
LM2840/1/2-ADJL 0.1 PF
4.5V to 42V IN C
VIN D1
B
MA2YD26
SHDN SW
R1
GND FB
3.4k
CIN R2 COUT
2.2 PF 1.02k 10 PF
The ESR term usually plays the dominant role in determining the voltage ripple. Low-ESR ceramic capacitors are
recommended. Capacitors in the range of 22 F to 100 F are a good starting point with an ESR of 0.1 or
less.
Figure 10. Switching Node and Output Voltage Waveforms Figure 11. Load Transient Waveforms
VIN = 12 V IOUT = 50 mA
VOUT = 3.3 V Top trace: VOUT, 1V/div, DC-Coupled
T = 40 s/div Bottom trace: SHDN, 2V/div, DC-Coupled
LM2840/1/2-ADJL 0.15 PF
7V to 42V IN
VIN CB D1
MA2YD26
SHDN SW
R1
GND FB
5.62k
CIN R2 COUT
2.2 PF 1.02k 47 PF
L1
CBOOT 47 PH 12V OUT
LM2840/1/2-ADJL 0.15 PF
15V to 42V IN
CB D1
VIN
MA2YD26
SHDN SW
R1
GND FB
14.7k
CIN R2 COUT
2.2 PF 1k 22 PF
L1
CBOOT 47 PH 15V OUT
LM2840/1/2-ADJL 0.15 PF
18V to 42V IN
D1
VIN CB
MA2YD26
SHDN SW
R1
GND FB
28k
CIN R2 COUT
2.2 PF 1.5k 22 PF
L1
CBOOT 0.8V OUT
10 PH
LM2840/1/2-ADJL 0.15 PF
4.5V to 12V IN
VIN D1
CB
MA2YD26
SHDN SW
R1
GND FB
30.9
CIN R2 COUT
2.2 PF 787 100 PF
10 Layout
11.7 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH, SIMPLE SWITCHER are registered trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.8 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.9 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 28-Feb-2017
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
LM2840XMK-ADJL/NOPB ACTIVE SOT-23-THIN DDC 6 1000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 SE8B
& no Sb/Br)
LM2840XMKX-ADJL/NOPB ACTIVE SOT-23-THIN DDC 6 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 SE8B
& no Sb/Br)
LM2840XQMK/NOPB ACTIVE SOT-23-THIN DDC 6 1000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 SE9B
& no Sb/Br)
LM2840YMK-ADJL/NOPB ACTIVE SOT-23-THIN DDC 6 1000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 SF1B
& no Sb/Br)
LM2840YQMK/NOPB ACTIVE SOT-23-THIN DDC 6 1000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 SF2B
& no Sb/Br)
LM2840YQMKX/NOPB ACTIVE SOT-23-THIN DDC 6 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 SF2B
& no Sb/Br)
LM2841XMK-ADJL/NOPB ACTIVE SOT-23-THIN DDC 6 1000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 STFB
& no Sb/Br)
LM2841XMKX-ADJL/NOPB ACTIVE SOT-23-THIN DDC 6 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 STFB
& no Sb/Br)
LM2841XQMK/NOPB ACTIVE SOT-23-THIN DDC 6 1000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 SB1B
& no Sb/Br)
LM2841YMK-ADJL/NOPB ACTIVE SOT-23-THIN DDC 6 1000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 STTB
& no Sb/Br)
LM2841YMKX-ADJL/NOPB ACTIVE SOT-23-THIN DDC 6 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 STTB
& no Sb/Br)
LM2841YQMK/NOPB ACTIVE SOT-23-THIN DDC 6 1000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 SB2B
& no Sb/Br)
LM2841YQMKX/NOPB ACTIVE SOT-23-THIN DDC 6 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 SB2B
& no Sb/Br)
LM2842XMK-ADJL/NOPB ACTIVE SOT-23-THIN DDC 6 1000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 STVB
& no Sb/Br)
LM2842XMKX-ADJL/NOPB ACTIVE SOT-23-THIN DDC 6 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 STVB
& no Sb/Br)
LM2842XQMK/NOPB ACTIVE SOT-23-THIN DDC 6 1000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 SB3B
& no Sb/Br)
LM2842XQMKX/NOPB ACTIVE SOT-23-THIN DDC 6 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 SB3B
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 28-Feb-2017
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
LM2842YMK-ADJL/NOPB ACTIVE SOT-23-THIN DDC 6 1000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 STXB
& no Sb/Br)
LM2842YMKX-ADJL/NOPB ACTIVE SOT-23-THIN DDC 6 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 STXB
& no Sb/Br)
LM2842YQMK/NOPB ACTIVE SOT-23-THIN DDC 6 1000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 SB4B
& no Sb/Br)
LM2842YQMKX/NOPB ACTIVE SOT-23-THIN DDC 6 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 SB4B
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 28-Feb-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Mar-2017
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Mar-2017
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Mar-2017
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM2840XMK-ADJL/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0
LM2840XMKX-ADJL/NOP SOT-23-THIN DDC 6 3000 210.0 185.0 35.0
B
LM2840XQMK/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0
LM2840YMK-ADJL/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0
LM2840YQMK/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0
LM2840YQMKX/NOPB SOT-23-THIN DDC 6 3000 210.0 185.0 35.0
LM2841XMK-ADJL/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0
LM2841XMKX-ADJL/NOP SOT-23-THIN DDC 6 3000 210.0 185.0 35.0
B
LM2841XQMK/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0
LM2841YMK-ADJL/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0
LM2841YMKX-ADJL/NOP SOT-23-THIN DDC 6 3000 210.0 185.0 35.0
B
LM2841YQMK/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0
LM2841YQMKX/NOPB SOT-23-THIN DDC 6 3000 210.0 185.0 35.0
LM2842XMK-ADJL/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0
LM2842XMKX-ADJL/NOP SOT-23-THIN DDC 6 3000 210.0 185.0 35.0
B
LM2842XQMK/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0
LM2842XQMKX/NOPB SOT-23-THIN DDC 6 3000 210.0 185.0 35.0
LM2842YMK-ADJL/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0
LM2842YMKX-ADJL/NOP SOT-23-THIN DDC 6 3000 210.0 185.0 35.0
B
LM2842YQMK/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0
LM2842YQMKX/NOPB SOT-23-THIN DDC 6 3000 210.0 185.0 35.0
Pack Materials-Page 3
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Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designers non-
compliance with the terms and provisions of this Notice.
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