A 12-bit – 35-MS/s Pipeline ADC with Dynamic

Element Matching correction for ILC/CALICE

Integrated Read-Out
RARBI Fatah, Student Member, IEEE, DZAHINI Daniel, Member, IEEE, GALLIN-MARTEL Laurent

Abstract–A low power 12 bits analog to digital converter is a

critical part of a fully integrated readout system for the next ILC
ECAL. We present here a new design of 12-bit ADC up to 35- Shaper_1 Memory 12 bits
preamp
Shaper_1 Memory
preamp Slow
MS/s using a pipelined architecture in a CMOS 0.35 m process. Shaper_10 Memory ADC
Shaper_10 Memory

The first front-end stage of 2.5 bits includes an efficient dynamic Memory 12 bits Shaper_1 Memory
Shaper_1
element matching scheme permitting to average its gain errors. preamp Slow preamp
Memory Shaper_10 Memory 12 bits
Shaper_10 ADC
The back-end converter is a set of seven 1.5 bit stages followed by Fast
a 3 bit full flash. The dynamic range covered is 2V. The analog ADC

part of the converter can be quickly (in a couple of s) switched to

a standby mode that reduces the DC power dissipation. The size Shaper_1 Memory 12 bits Shaper_1 Memory
of this converters layout including the output pads is preamp Slow preamp
Shaper_10 Memory ADC Shaper_10 Memory
1.4mm*1.3mm, and the total power dissipation is only 45mW.

I. INTRODUCTION a) b)

F OR the next International Linear Collider (ILC), the front- Fig. 1. Overview of the front-end read-out in a) low speed configuration,
and b) high speed configuration
end electronics for the electromagnetic calorimeter is really
challenging. Mechanical constraints lead to the necessity to
integrate in the same chip many different critical stages of the A pipelined architecture is used. For high dynamic
read-out electronics: charge preamplifiers, multi gain shapers, converters (>10 bit), and high speed (beyond 10MHz), this
analog memories, ADC, and digital back-end. The average architecture is usually considered as a good compromise
power consumption budget is limited to only 25μW per between the power dissipation and the speed [5]-[7]. An
channel. This key design feature is reachable by taking overview block diagram of the converter is shown in figure 2.
advantage of a power pulsing system with a 1/100 duty cycle,
thanks to the beam timing of ILC. The design of the analog to
digital converter must deal with the power dissipation
constraint which is one of the main concerns for the
electronics. Two configurations are possible in the future read-
out electronics: the slow one, where one use a slow-speed
ADC per read-out channel, and the high speed one, where a
V in
high speed converter is used to multiplex many read-out
channels. Those two configurations are shown in figure 1 a)
and b) respectively.
We present here a high speed converter configuration
designed to multiplex many analog channels to one ADC. The
chip is composed by an ADC and a 3 to 1 analog multiplexer. Fig. 2. General block diagram of a pipelined A/D converter
This design makes the assumption that a high speed converter
helps to minimize the total power dissipation related to each The ADC is composed of a set of pipelined stages. Each
channel [1]-[4]. stage produces a digital estimate of an incoming held signal,
then converts this estimate back to the analog, and subtracts
the result from the held input. This residue is then amplified
before being transferred to the next stage. Eventually the last
stage is a full flash converter which determines the least
significant bit (LSB). The successive digital results from the
pipelined stages are appropriately delayed throughout a bit
alignment network. Then a digital correction stage helps to
This work is on behalf The CALICE Collaboration. recover the errors due to the offset of the comparators.
F. Rarbi is a PhD Student in the LPSC, CNRS/IN2P3 Laboratory, Therefore, low offset comparators are not necessary and the
Université de Grenoble (e-mail: rarbi@lpsc.in2p3.fr).
total power consumption is reduced. The power dissipation is
D. Dzahini and L. Gallin-Martel are with the LPSC, CNRS/IN2P3,
Université de Grenoble (e-mail: dzahini@lpsc.in2p3.fr).
optimized for each stage following a power scaling in the
successive pipeline stages.
This paper summarizes hereafter the design of three
prototypes of the converter and we present some testing and
simulation results. Neither calibration nor trimming
approaches were used for these designs [8]. The last prototype
included an analog 3 to 1 multiplexer, which is the first step
for a larger multiplexer for the calorimeter readout chip.
II. THE PIPELINE ADC
A. Prototype N°1 using only 1.5 bit stages
The converter consists of ten 1.5 bit sub-ADC followed by a
2 bit full flash stage as shown in figure 2.
Figure 3 illustrates a very simplified diagram of a 1.5 bit
The DNL is almost ±1LSB, and the INL is ±4LSB.
This prototype deals with CALICE requirements and it is
closed to the matching limits for the capacitors in the .35 µm
process used. One solution to improve further the linearity and
the total power consumption is to include a first multi-bit
stage. Thus a second prototype was designed.
B. A 2.5 bit stage architecture
This new version produces 2.5 bits in the first stage
followed with seven 1.5 bit stages and a last 3 bit full flash.
The architecture of this second prototype is illustrated in
figure 5.
Vin residue
+
+ x4

-
pipeline stage. The actual implementation in our design is ADC S/H

differential. The A/D block consists of two non critical DEM DAC
comparators. The D/A conversion, subtraction, amplification, MDAC

2.5 bits
and S/H functions are performed by a switched capacitor
circuit with a resolution of 1.5 bit per stage and an Front-end stage Back-end ADC
amplification gain of 2. Hence the transfer function of this
stage 1 stage 2 stage 8 FLASH
stage is: Vs=2*Vin-αVref . Vin …
2,5 bits 1,5 bits 1,5 bits 3 bits
α is set to 0 or 1 or -1, depending on the output codes (b0,
b1); ±Vref specifies the dynamic range.
data delay + digital correction
12 bits
Fig. 5. Block diagram of a pipelined converter with a multi-bit stage

Increasing the number of bits in the front-end stage, relaxes

Fig. 3. Bloc diagram of a 1.5 bit sub-converter stage.
The prototype has been tested successfully at 25 MHz with
a power supply of 3.3 V. The total power consumption was
only 37mW.
The Differential Non linearity (DNL) and the Integral Non
Linearity (INL) are presented respectively in figure 4 a) and b)
respectively.
the matching conditions necessary for the back-end; but it
makes the amplifier more power consuming to deal with the
gain bandwidth product requirements. The gain errors in this
first stage are digitally controlled by means of a dynamic
element matching (DEM) algorithm for a random choice of
the DAC capacitors cells. This algorithm helps to minimize
the non linearity.
In figure 5 is shown a very simplified diagram of a 2.5 bit
stage as a front end stage of the pipeline converter. The ADC
block consists of six non critical comparators. The DAC
conversion, subtraction, amplification, and S/H functions are
performed by a switched capacitor structure as one can see in
figure 6. This block is the multiplier-DAC (MDAC). It is
composed of four capacitors.

a) b)
Fig. 6. A 2.5 bits MDAC a) sampling phase; b) amplifying

The incoming signal is sampled during phase “Φ1” (figure 6

a) b) a). It is amplified by charge redistribution during phase “Φ2”
Fig. 4. Linearity results a) DNL, b) INL
(figure 6 b)). During this amplification phase, one plate of the
sampling capacitors (Csi) is connected to a reference voltage
Vrefi which will be subtracted from the amplified signal. The
residue resulting from this operation is transmitted to the next
pipeline stage. The value selected for Vrefi is respectively 0 or
(-Vref) or (Vref) depending on the comparators outputs. The
amplification gain is 4. Hence the transfer function of this
stage is: Vs=4*Vin-(α+β+γ)*Vref where α, β and γ are set to 0, -
1 or 1, depending on the output codes of the sub-ADC. ±Vref
specifies the dynamic range. The transfer characteristic for a
2.5 bit stage is shown in figure 7.
Fig. 7. A 2.5 bit residue transfer curve
The expression “2.5 bit” is used to emphasize that only 7
combinations out of the 8 are acceptable for the output codes.
The code (1, 1, 1) is avoided, thereby the amplifier will not
saturate and this leaves room for the digital error correction.
C. Prototype n° 2 with a 2.5 bit stage: testing results
A prototype including a multi-bit first stage was designed. The
die photograph of this first prototype is shown in figure 8.
This chip has been tested at 25MHz with a power supply of
3.3V. The total power consumption was only 42mW.
Fig. 8. ADC die photograph
In this prototype, “Butterfly DEM” architecture is used. A
simplified block diagram of “butterfly” architecture is shown
in figure 9. It is composed by a cascaded transmission gate.
The control command of each block is generated randomly by
a 12-bit LFSR. Therefore, an input code could have many
output configurations.
input(0) output(0)
input(1) output(1)
From
sub-ADC
To sub-DAC
input(2) output(2)
input(3) output(3)
Fig. 9. Butterfly DEM block diagram
This architecture is a full access network: each input could
be connected to each output. But it is a blocking network: if
input(1) is connected to output (2), input (0) will not be
connected to output (3). Another drawback is the delay time
introduced between input and output due to cascaded block.
The Integral Non Linearity (INL) is shown in figure 10. It is
almost ±8LSB.
Fig. 10. Testing result for prototype n°2.
In figure 11 is shown the FFT for a 1MHz sine wave input
signal with 2V peak-to-peak amplitude. The FFT is calculated
with 16,384 points.
SFDR=47dB
Fig. 11. FFT with 16,384 points: prototype n°2.
In this second prototype we have some problem of linearity.
Indeed, the SFDR is around 47dB and the INL is up to 8LSB.
Two sources for these problems are afterward identified: the
layout and the matching of the capacitor need improvement.
We discover also a mistake in the comparators: they present
an important hysteresis. Another mistake was found in the
routing of the DEM block due to the time delay introduced in
the path between its input and its output.
 To improve those results a new prototype was design: gain [9], at just a little expense of power dissipation. The Bode
comparator hysteresis was reduced, capacitor layout was diagram simulations results are given in figure 15.
modified and a new DEM version was designed. We present
hereafter this new prototype which includes a 3 to 1 analog
multiplexer.
D. A 2.5 bit stage in the prototype n°3: simulation results.
In this new prototype, several modifications were made:
dynamic comparators and a new DEM architecture are used.

The sub-ADC is composed of 6 low offset and low power

dynamic comparators. The simplified schematic of the
comparator is shown in figure 12.

Fig. 14. A regulated folded-cascode OTA

AdB

Fig. 12. The dynamic comparator

f (°)
The maximum offset of these comparators must be limited
to Vref/8, where ±Vref is the full dynamic range. The
comparator’s offset is less than ±40mV as one can see in the
Monte Carlo simulations in figure 13.

Comparator Offset nb = 50 F (Hz)

Fig. 15. Bode diagram for the OTA on a 4pF load.

16 μ = 369.1 mV
14 σ = 18.7 mV
12 As we can see on the Bode diagram (figure 15), the cut off
diffmax = 80 mV
10 frequency at closed-loop gain of 4 (e.g: 12dB) is
8 approximately 80MHz. Therefore a 25MHz sampling
6 frequency is easily attainable.
4
The linearity simulations of our first Multiplier and DAC
2
0 stage are given in Figure 16. One can notice a full range
-2 integral non linearity (INL) in the order of 1 LSB.

0,6

0,4
Fig. 13. Offset of dynamic comparator (monte carlo simulation with 50
0,2
bins)
0
The output codes from the comparators are used thereafter -1,5 -1 -0,5 0 0,5 1 1,5
-0,2
by the DAC to rebuild the analog residue. A precise
amplification by 4 is performed by four equivalent capacitors -0,4

as shown in figure 6. The matching of Cf with all Cs is the -0,6 -1.2LSB

main issue for this amplification, and it is the main source of -0,8
to
non linearity for the converter. .5LSB
-1

To expect a 12 bit resolution feature, the amplifier (OTA) in -1,2

the first stage must have a high open loop gain (more than 72 -1,4
dB). The folded-cascode architecture used is shown in figure
14. Auxiliary amplifiers are added to increase the open loop Multi-bit MDAC linearity (LSB@12bit)
Fig. 16. Non linearity of the MDAC 2.5 bit.
 E. Dynamic Element Matching (DEM)
Dynamic Element Matching permits to improve linearity of
the ADC. In fact, it changes harmonic distortions into noise.
The DEM block diagram is shown on figure 17. The same
architecture is used in [10].

1TG

From
comparator To DAC
…

output control

Fig. 19. Layout photograph of the full prototype: analog multiplexer+ADC

III. THE 3 INPUTS ANALOG MULTIPLEXER

Random Command We present in this section the architecture and some
Generator control simulation results of the 3 to 1 analog multiplexer.
Fig. 17. DEM Block diagram.
A. Analog Multiplexer architecture
It is composed by a random generator and a command block The analog multiplexer is designed to link the analog
control which permit both to connect randomly one capacitor channels to the high speed ADC. It uses a pseudo-differential
as a feedback capacitor on the OTA. The “yellow” block on and flip-flop architecture to overcome the capacitor’s
figure 16 is used to make a link between output comparators to matching problem. A simplified schematic of the multiplexer
MDAC switches through only one transistor gate to be no is shown on figure 20.
sensitive to propagation time. The command control block is
not sensitive to delay time contrary to the yellow block.
Matlab simulation results of the DEM principle are shown
on figure 18. When DEM is “off” a) we have harmonic
distortions which degrade linearity. On figure 18 b) DEM is
“on”. We can notice that harmonic distortions are changed
into noise. The noise floor is a little bit increased.

SFDR=63dB SFDR=83dB

Write mode Read mode

a) b)
Fig. 20. Analog multiplexer schematic in a) write mode, and b) read
mode.

a) b)
Fig. 18. Matlab simulation results a) without DEM and b) with DEM.
This design was submitted in a CMOS 0.35µ process from
Austria Micro System. The full layout photograph of the
prototype is shown in figure 19. The prototype is composed by
an analog multiplexer followed by a pipeline ADC with a
multi-bit first stage converter. The 3 input analog multiplexer
design and simulation results are presented in the next part.
During the write mode a), input signals are sampled through
capacitors Csi. After that, each capacitor is connected
sequentially as capacitor feedback on the amplifier. The same
capacitor is used as sampled and read component: we have
then no gain error in the analog multiplexer due to capacitor
mismatch.
B. Simulation results
Two full range ramps with opposite slope are set on the
external channels while a constant 2mV low signal is put in
the middle. Simulation results are shown on figure 21.
The error found (213µV) is less than 1 LSB at 12 bit and 2V
dynamic range, and the impact on the low level signal is only
140µV.

Low signal (2mV)
140µV accuracy
54.4µV
25µV
to
-28.7µV -213µV
to
213µV
Fig. 21. Multiplexer simulation results.
IV. AVERAGE POWER CONSUMPTION
We present in this section some simulation results about
power consumption of this chip: the 3 inputs analog
multiplexer followed by a 12-bit pipeline A/D converter using
2.5 bits in the first stage.
The total power consumption of the analog multiplexer is
around 5.4mW according to our simulations up to 25MHz.
This power consumption comes mainly from the amplifier.
And the pipeline ADC has a power consumption about 40mW.
It means the full chip: analog multiplexer and the ADC
dissipates 45.4mW with a sampling frequency of 25MHz.
For the next ILC experiment, we choose to use only one fast
ADC per chip. Each chip is composed of 64-channels and the
depth of the analog memory will be sixteen. The ADC and
multiplexer power consumption per chip is about 4 μW by
using power pulsing concept. This leads to an equivalent
power consumption about only 125nW per channel. These
results show a power consumption for both the multiplexer
and the ADC of only 0.5% of the total power consumption
which was estimated to 25μW per channel.
V. CONCLUSION
The design of two prototypes of a 12 bit 25MS/s pipelined
ADC has been reported. A third one is used with a 3 three
inputs analog multiplexer which will be extend to 64 in the
future. The first chip consumes very reasonable power
dissipation: only 37mW. A 1.5 bit/stage architecture is used
for the converter in a differential configuration. It has almost
±1LSB of DNL and ±4LSB of INL. This converter is a high
speed version for the future International Linear Collider
calorimeter detector (CALICE collaboration). The second
version has been designed to improve linearity and power
dissipation. A 2.5 bit first stage is used in this second chip. To
improve some problem encountered in this prototype a new
ADC was designed: dynamic comparator and a new DEM
architecture are used. A front-end stage in this new version is
composed by a 3 input analog multiplexer to make the
connection between 3 channels and the fast ADC. A very
efficient fast power pulsing is integrated with this circuit to
reduce the total DC power dissipation according to the beam
low duty cycle.
ACKNOWLEDGMENT
The authors are grateful to J. Bouvier and Eric Lagorio for
the testing board design and technical advice.
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