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LLC DC/DC Resonant Converter with PLL Control Scheme
by
Wei-Cheng Ju*
(ABSTRACT)
This thesis proposes a capacitively loaded loop (LLC) DC/DC resonant converter with
phase-locked loop (PLL) control scheme. The PLL control scheme enables the switching
frequency of the converter to continuously track the resonant frequency of the LLC resonant
tank, which means the switching frequency is adjusted in order to obtain the required voltage
gain.
including the LLC resonant tank and the output resistance, the voltage-gain
characteristic of the LLC resonant tank is changed; this causes the fixed- and
converters switching frequency will be lower than the resonant frequency of the LLC
Thus, this thesis presents a PLL control scheme, the use of which makes the
switching frequency of the converter continuously track the resonant frequency of the
I
LLC resonant tank by detecting the phase signals of the input and transformer
secondary output voltages of the LLC resonant tank. Based on this resonant
frequency, the switching frequency is adjusted to obtain the required voltage gain.
In this thesis, the mathematic software Mathcad is used to complete the characteristic
analysis and the parameters design of the LLC resonant tank. Meanwhile, the
simulation software SIMPLIS is utilized to complete the system analysis and the
compensator design of the LLC DC/DC resonant converter in order to ensure overall
system stability.
The proposed 200W LLC DC/DC resonant converter with PLL control scheme is
then designed and implemented to validate and demonstrate the performance and
Keywords: capacitively loaded loop (LLC), phase-locked loop (PLL), resonant tank,
DC/DC converter.
* The student
** The advisor
II
LLC
* ** **
LLC
LLC
LLCLLC
LLC
LLC
LLC
LLC
MathcadLLC
SIMPLISLLC
200W
LLC
*
**
III
Catena
IV
Table of Contents
2.4. Analysis of the Transformer for the LLC DC/DC Resonant Converter ..........18
4.1. Introduction..............................................................................................................................41
V
4.2.3. Design of the Transformer for the LLC DC/DC Resonant Converter ...........55
REFERENCES...........................................................................................................79
VI
List of Figures
Figure 1.1. Distributed power system structure. .......................................................2
Figure 1.2. Conventional LLC DC/DC resonant converter [13]. .............................2
Figure 1.3. Improved LLC DC/DC resonant converter [16]. ...................................3
Figure 1.4. Voltage gain of the LLC DC/DC resonant converter..............................3
Figure 2.1. (a) LLC DC/DC resonant converter, and (b) simulation waveforms for
the LLC DC/DC resonant converter. .....................................................8
Figure 2.2. Circuit diagram during Mode 1. .............................................................9
Figure 2.3. Circuit diagram during Mode 2. .............................................................9
Figure 2.4. Circuit diagram during Mode 3. ...........................................................10
Figure 2.5. Circuit diagram during Mode 4. ...........................................................10
Figure 2.6. Circuit diagram during Mode 5. ........................................................... 11
Figure 2.7. Circuit diagram during Mode 6. ........................................................... 11
Figure 2.8. Circuit of the LLC DC/DC resonant converter.....................................12
Figure 2.9. Simplified circuit of the LLC DC/DC resonant converter....................12
Figure 2.10. Equivalent circuit for DC analysis. ......................................................13
Figure 2.11. Equivalent circuit for DC analysis........................................................13
Figure 2.12. DC characteristics of the LLC DC/DC resonant converter. .................14
Figure 2.13. Optimal terminal of the LLC resonant tank with equivalent resistor: (a)
LLC resonant tank with equivalent resistor, and (b) changing the
arrangement from parallel to series......................................................15
Figure 2.14. (a) Equivalent circuit, and (b) the curve of efficiency vs. equivalent
resistance..............................................................................................17
Figure 2.15. Structure of the transformer..................................................................18
Figure 2.16. Reluctance model for the structure of the transformer. ........................18
Figure 2.17. Electrical circuit model of the transformer for the LLC DC/DC
resonant converter. ...............................................................................19
Figure 2.18. Analysis of the transformer during Mode 1. ........................................19
Figure 2.19. Equivalent circuit during Mode 1.........................................................20
Figure 2.20. Analysis of the transformer during Mode 2. ........................................21
Figure 3.1. Configuration of the LLC DC/DC resonant converter. ........................24
Figure 3.4. Relationship between amplitude of voltage gain Vo/Vi and operating
frequency..............................................................................................26
VII
Figure 3.5. Block diagram of the PLL control scheme...........................................28
Figure 3.8. Gains and phases of Vs/Vin with different values of R in the LLC
Figure 3.9. Relationship between phase of Vs/Vin and the different equivalent
Figure 3.10. Relationship between phase of Vs/Vin and the different resonant
Figure 3.11. Gains of Vs/Vin and phases of VLr/Vs with different values of R in the
Figure 3.12. Relationship between the phase of VLr/Vs and the different equivalent
Figure 3.13. Relationship between the phase of VLr/Vs and the different resonant
Figure 4.1. Detailed circuit diagram of the proposed LLC DC/DC resonant
Figure 4.2. Operating region of the LLC DC/DC resonant converter. ...................45
Figure 4.4. Gain and phase of the LLC DC/DC resonant converter:......................47
Figure 4.5. (a) Circuit for open-loop small-signal analysis of LLC DC/DC resonant
Figure 4.6. (a) Compensator structure for LLC DC/DC resonant converter (b) Gain
VIII
Figure 4.7. (a) Circuit for closed-loop small-signal analysis of LLC DC/DC
Figure 4.8. (a) Output voltage at different load conditions (b) Output voltage at
different input voltage (c) Simulation results of load change from full
Figure 4.10. Detailed schematic of the prototype circuit for the proposed LLC
Figure 4.11. (a) Circuit block diagram, (b) waveforms for Vo and VDS2 at the rated
load and with 400V input voltage, and (c) waveforms for VDS2 and IDS2
Figure 4.12. (a) Circuit block diagram, (b) waveforms for Vo and VDS2 at the rated
load and with 300V input voltage, and (c) waveforms for VDS2 and IDS2
Figure 4.13. (a) Circuit block diagram, (b) waveforms for Vo and VDS2 at 75% of the
rated load and with 400V input voltage, and (c) waveforms for VDS2
and IDS2 at 75% of the rated load and with 400V input voltage...........63
Figure 4.14. (a) Circuit block diagram, (b) waveforms for Vo and VDS2 at 75% of the
rated load and with 300V input voltage, and (c) waveforms for VDS2
and IDS2 at 75% of the rated load and with 300V input voltage...........64
Figure 4.15. (a) Circuit block diagram, (b) waveforms for Vo and VDS2 at 50% of the
rated load and with 400V input voltage, (c) waveforms for VDS2 and
IDS2 at 50% of the rated load and with 400V input voltage. ................66
Figure 4.16. (a) Circuit block diagram, (b) waveforms for Vo and VDS2 at 50% of the
rated load and with 300V input voltage, and (c) waveforms for VDS2
IX
and IDS2 at 50% of the rated load and with 300V input voltage...........67
Figure 4.17. (a) Circuit block diagram, (b) waveforms for Vo and VDS2 at 25% of the
rated load and with 400V input voltage, and (c) waveforms for VDS2
and IDS2 at 25% of the rated load and with 400V input voltage...........69
Figure 4.18. (a) Circuit block diagram, (b) waveforms for Vo and VDS2 at 25% of the
rated load and with 300V input voltage, and (c) waveforms for VDS2
and IDS2 at 25% of the rated load and with 300V input voltage...........70
Figure 4.19. (a) Circuit block diagram, (b) waveforms for Vo and VDS2 at 10% of the
rated load and with 400V input voltage, and (c) waveforms for VDS2
and IDS2 at 10% of the rated load and with 400V input voltage...........72
Figure 4.20. (a) Circuit block diagram, (b) waveforms for Vo and VDS2 at 10% of the
rated load and with 300V input voltage, and (c) waveforms for VDS2
and IDS2 at 10% of the rated load and with 300V input voltage...........73
Figure 4.21 Output voltages versus input voltages at different load conditions.....74
Figure 4.22 Output voltages versus output powers at different input voltages. .....74
Figure 4.23 Test result of load change from full load to 25% load. .......................74
Figure 4.24. Efficiency of the proposed LLC DC/DC resonant converter at different
Figure 4.25. Efficiency of the proposed LLC DC/DC resonant converter at different
X
List of Tables
Table 4.1. Specifications of the LLC DC/DC resonant converter with PLL control. ..43
XI
Chapter 1. Introduction
1.1. Background
As illustrated in Figure 1.1, in a distributed power system (DPS) [1-5], the LLC
converts the 400VDC to 48VDC for the load system. The conventional LLC DC/DC
resonant converter [11-15], as shown in Figure 1.2, is composed of input voltage VDC,
the half-bridge converter with diodes Q1 and Q2, the LLC resonant tank, step-down
transformer T, the full-wave rectifier with diodes D1 and D2, and output capacitor Co.
An improved LLC DC/DC resonant converter has been proposed [16], as shown
in Figure 1.3. The improved LLC DC/DC resonant converter differs from the
conventional one in the following respects. One is that the resonant capacitor is
divided into two capacitors, thus allowing the input current ripple to be reduced.
The other one is that two clamping diodes are put in parallel with the resonant
stress on the resonant capacitor is limited, and thus a low-voltage capacitor can be
used.
For the requirement of hold up time, the system is required running at full power
for 20 ms when AC input is lost. During hold up time, the energy will draw from
400 V bus capacitor which causes voltage drop on 400 V bus. Therefore, for a
normal design, the front-end DC/DC converter input voltage range will be 300 V to
400 V. As shown in Figure 1.4, while the input voltage of the LLC DC/DC resonant
converter drops to 300 V, the operating frequency of the converter must be reduced in
1
order to make the converter operate at the required voltage gain. Thus, the required
because the converters operating frequency could be lower than its resonant
frequency [19] which means the switches of the converter are not operated in
thesis proposes a PLL control scheme for the LLC DC/DC resonant converter.
48VDC
Load
400VDC
System
Power Front-end
Factor DC/DC High Voltage
Correction Converter VRM
Q1
Cr Lr T D1
VDC
Co R
ns
Lm np
Q2
ns D2
2
Q1 Cr1 Dc1 L D1
r
T
VDC ns Vs Co R
Vin Lm np
ns
Q2 Cr2 Dc2
D2
2
Vs Q =
Zo
where Z o =
Lr 8
, REQ = 2 n 2 R
0.1 REQ Cr
Vin
1.5 0.3 VDC=300V
0.5
1 VDC=400V
2
0.5 4
Q=6
0
0 0.5 1 1.5 2
fs / fr
Figure 1.4. Voltage gain of the LLC DC/DC resonant converter.
3
1.2. Motivation
Generally speaking, the PLL control scheme has been widely used in
signal-processing and digital systems. The PLL control scheme presented in [20]
involves detecting the phase signals of both the resonant-tank input voltage and the
two leakage inductor terminals in the transformer. The papers [21-22] give
approaches for sensing the capacitor voltage. With the PLL control scheme, the
work [23], the inductor voltage is sensed for PLL control scheme to tolerate lower
equivalent resistance of the lamps at the steady state and to have the operating
frequency of ballasts continuously track the resonant frequency of the resonant tank.
The concept and IC [24-25] show the regulation of the phase between the midpoint
voltage and resonant inductor current, including plots showing the zero-phase point
tracking the resonant frequency. This is expected based on the input impedance of
the tank. However, the work presented in this manuscript appears to show the same
result, but also senses the inductor voltage. In other work [26], a digital approach for
phase control is presented, including sensing either the resonant inductor current or
voltage. A discrete circuit is given in other research [27] that also senses the
resonant inductor voltage and effectively controls the phase. Another paper [28]
Therefore, this thesis proposed the PLL control scheme for the LLC DC/DC
resonant converter. With the PLL control scheme, the operating frequency of the
inverter continuously tracks the resonant frequency while the phase difference of the
inverter at the resonant frequency is always fixed. Thus, the lowest operating
frequency is the resonant frequency. Based on the lowest operating frequency, the
4
operating frequency of the inverter is changed to make the inverter operate at the
required voltage gain. However, because the operating frequency will not be lower
than the resonant frequency of the LLC resonant tank, the switches of the inverter are
both operated in ZVS condition so that turn-on switching losses are reduced.
5
1.3. Thesis Outline
This thesis is comprised of five chapters plus the References. The chapters are
organized as follows.
Chapter 1 is the background review of the LLC DC/DC resonant converter that is
Chapter 2 briefly introduces the analysis of the LLC DC/DC resonant converter,
including its operating principles, its modeling, its optimal design, and the structure of
its transformer.
Chapter 3 introduces the PLL control scheme for the LLC DC/DC resonant
converter, and analyzes the phase characteristics of the LLC resonant tank.
Chapter 4 shows the design of the prototype circuit and demonstrates its
Chapter 5 gives the conclusions of this thesis and proposes some ideas for future
work.
6
Chapter 2. Analysis of the LLC DC/DC
Resonant Converter
This chapter first introduces the operational principles of the LLC DC/DC
resonant converter. After this brief review, this chapter will present the derivation of
the converters DC analysis. In the subsequent section, the matched load is analyzed
in order to achieve optimal efficiency. Additionally, the transformer used for the
The operational principles of the LLC DC/DC resonant converter are discussed
in this section. The operational principles can be divided into two time intervals.
In the first time interval, resonance occurs between resonant capacitor Cr and resonant
inductor Lr. In the other time interval, resonance occurs between resonant capacitor
Cr, resonant inductor Lr, and magnetic inductor Lm. Therefore, the LLC DC/DC
frequencies at the different time intervals. Figure 2.1 (b) shows the simulation
waveforms of the LLC DC/DC resonant converter. At this time, the LLC DC/DC
switching cycle includes six operational modes, and each mode will be explained in
detail as follows.
7
Is1
Q1
Cr Lr ID1
VDC
D1 Io
VCr ILr Co R
Is2 ns
Lm np
Q2 ILm
ns D
2
ID2
(a)
Vgs Q1 Q2
ILr
IL
ILm
Voltage gain
2 Vcr
Region 2
ID ID1 ID2
1.5
0.2
Region 1
0.4
1 Is1
0.6
Region 3
1
0.5 Is2
3
Q=5
0
0.4 0.6 0.8 1 1.2
fs/fr t0 t1 t2 t3 t4 t5 t6
Figure 2.1. (a) LLC DC/DC resonant converter, and (b) simulation waveforms for the
LLC DC/DC resonant converter.
8
Mode 1 (t0-t1):
At t0, switch Q2 is turned off. Since the current of Lr is negative, it flows
through the body diode of switch Q1, which creates a ZVS condition for Q1. The
and resonant inductor Lr. At the same time, secondary diode D1 is conducting and
the voltage of Lm is clamped by the output voltage. Therefore, the current ID1 begins
to rise. This mode ends when the current of Lr becomes positive at t1.
Q1 Is1
Cr Lr ID1
VDC
VCr D1 Io
ILr Co R
Is2 ns
Lm np
Q2 ILm
ns D
2
ID2
Figure 2.2. Circuit diagram during Mode 1.
Mode 2 (t1-t2):
At t1, switch Q1 is turned on. At this moment, the current of Lr becomes
positive and the current flows through Q1. The current of Lr increases because of the
diode D1 is still conducting and the voltage of Lm is clamped by the output voltage,
which means the current of Lm increases linearly. This mode ends while the current
of Lr is equal to the current of Lm and the current ID1 reaches zero at t2.
Q1 Is1
Cr Lr ID1
VDC
D1 Io
VCr ILr Co R
Is2 ns
Lm np
Q2 ILm
ns D
2
ID2
9
Mode 3 (t2-t3):
When the inductor currents of Lr and Lm are equal, the secondary voltage of the
transformer is lower than the output voltage, which means the output is separated
from the transformer. Therefore, the current ID1 is zero during this mode.
Secondary diodes D1 and D2 are not conducting. Since Lm is not clamped by the
Q1 Is1
Cr Lr ID1
VDC
VCr D1 Io
ILr Co R
Is2 ns
Lm np
Q2 ILm
ns D
2
ID2
Figure 2.4. Circuit diagram during Mode 3.
Mode 4 (t3-t4):
Switch Q1 is turned off at t3. The current of Lr flows through the body diode of
switch Q2, which creates a ZVS condition for Q2. The current of Lr starts to decrease
because of the resonance between resonant capacitor Cr and resonant inductor Lr. At
the same time, secondary diode D2 is conducting and the voltage of Lm is clamped by
the output voltage. Hence, the current ID2 begins to rise. This mode ends when the
Is1
Q1
Cr Lr ID1
VDC
D1 Io
VCr ILr Co R
Is2 ns
Q2 Lm np
ILm
ns D2
ID2
10
Mode 5 (t4-t5):
At t4, switch Q2 is turned on. At this moment, the current of Lr becomes
negative and the current flows through Q2. The current of Lr decreases because of
the resonance between resonant capacitor Cr and resonant inductor Lr. However,
diode D2 is still conducting and the voltage of Lm is clamped by the output voltage,
which means the current of Lm decreases linearly. This mode ends while the current
of Lr is equal to the current of Lm and the current ID2 reaches zero at t5.
Is1
Q1
Cr Lr ID1
VDC
D1 Io
VCr ILr Co R
Is2 ns
Lm np
Q2 ILm
ns D2
ID2
Mode 6 (t5-t6):
During this mode, the inductor currents of Lr and Lm are equal, the secondary
voltage of the transformer is lower than the output voltage, which means the output is
separated from the transformer. Therefore, secondary diodes D1 and D2 are not
conducting and the current ID2 is zero. Since Lm is not clamped by the output
voltage, Lm is free to participate in the resonance between Cr and Lr. For the next
switching cycle, the operational principles are the same as those analyzed above.
Is1
Q1
Cr Lr ID1
VDC
D1 Io
Is2 VCr ILr ns
Co R
Lm np
Q2 ILm
ns D
2
ID2
11
2.2. DC Analysis of the LLC DC/DC Resonant Converter [13]
Figure 2.8 shows the circuit of the LLC DC/DC resonant converter. In order to
conduct the DC analysis for the LLC DC/DC resonant converter, the circuit must be
simplified. By using the equivalent AC resistor as presented in other work [29], the
LLC resonant tank can be simplified, as illustrated in Figure 2.9. The simplified
circuit is composed of voltage source Vin, capacitor Cr, two inductors (Lr and Lm), and
the equivalent resistor REQ. Then, using the equivalent circuit model presented in
previous work [30], the circuit can be easily derived, as illustrated in Figure 2.10.
Transformer
D1
Cr V
Lr
n : 1
Lr R Vo
ICr
Vin Lm
REQ D2
Figure 2.8. Circuit of the LLC DC/DC resonant converter.
Cr Lr
Vin Lm REQ Vs
12
Cr Lr js Lr
1 js Lm
js Cr
Vin REQ Vs
Lm
Figure 2.10. Equivalent circuit for DC analysis.
1
js Cr js Lr
Vin js Lm REQ Vs
Figure 2.11. Equivalent circuit for DC analysis.
Under DC conditions, the capacitor can be considered as an open circuit and the
inductor can be considered as a short circuit. Then, the equivalent circuit is further
simplified, as shown in Figure 2.11. Using the circuit shown in Figure 2.11, the DC
Vs j n k L
= , (2.2.1)
1
j n 1 + k L 2 + k L (1 n ) Q
Vin 2
s 1 L Lr Z 8
where n = , r = , kL = m , Zo = , Q = o , REQ = 2 R n 2 .
r Lr Cr Lr Cr REQ
Figure 2.12 shows the relationship between the voltage gain and frequency with
different load conditions from Q=0.2 to Q=5. In this figure, the high resonant
13
frequency is determined by resonant inductor Lr and resonant capacitor Cr. However,
the lower resonant frequency is determined by capacitor Cr and the series inductors of
Lr and Lm. For this application, it is preferable for the MOSFET to operate in ZVS.
In order to ensure ZVS operation, the converter is designed to operate above the
Lm.
3
Vs
Vin 2.5
ZVS Region
0.2
2
1.5
0.4
1
0.6
ZCS Region
1
0.5
2
3
Q=5
0
0.4 0.6 0.8 1 1.2
fs/fr
14
2.3. Matched Load for Optimal Efficiency
The matched load for optimal efficiency is discussed in this section. In order to
calculate the efficiency of the LLC DC/DC resonant converter, the circuits equivalent
series resistance (ESR), RESR, needs to be considered in the circuit, as shown in Figure
2.13 (a); this includes resonant capacitor Cr, resonant inductor Lr, magnetic inductor
Lm, and equivalent resistance REQ. In order to easily calculate the optimal efficiency,
the circuit in Figure 2.13 (a) can be converted to a series format, as illustrated in
RESR Cr Lr
Vin Lm REQ VS
(a)
Lm
RESR Cr Lr 1+q p 2
q p 2 R EQ
1+q p 2
Zi ZL
(b)
Figure 2.13. Optimal terminal of the LLC resonant tank with equivalent resistor: (a)
LLC resonant tank with equivalent resistor, and (b) changing the
arrangement from parallel to series.
15
According to Figure 2.13 (b), input impedance Zi and efficiency can be
1 L q p 2 REQ q p 2 REQ
Z i = RESR + + j Lr + j m 2 + , ZL = , (2.3.1)
jCr 1+ qp 1+ qp2 1 + qp2
Lm
where q p = , and
REQ
Re [ Z L ] q p 2 REQ
= = . (2.3.2)
Re [ Z i ] q p 2 REQ + RESR (1 + q p 2 )
equating to zero the first derivative of Equation (2.3.2), which corresponds to REQ:
= 0. (2.3.3)
REQ
From Equation (2.3.4), the maximum efficiency can be found while the parallel
quality factor qp =1 and the REQ is equal to matched resistance REQ,OPT, which is the
REQ ,OPT
OPT = . (2.3.5)
REQ ,OPT + 2 RESR
Based on the parameters of the LLC resonant tank, in which the values of Cr, Lr,
and Lm are 66 nF, 43 H, and 240 H, respectively, the curves of efficiency vs. load
16
resistance at the resonant frequency can be plotted as shown in Figure 2.14.
According to Figure 2.14(b), the maximum efficiency is achieved around the matched
RESR Cr Lr
Vin Lm REQ VS
(a)
0.94
0.93 fs=100kHz
0.92
REQ,OPT=150
0.91
0.9
50 200 350 500
REQ()
(b)
Figure 2.14. (a) Equivalent circuit, and (b) the curve of efficiency vs. equivalent
resistance at the resonant frequency.
17
2.4. Analysis of the Transformer for the LLC Resonant Converter
In this section, the structure of the transformer for the LLC DC/DC resonant
converter is discussed [13]. As illustrated in Figure 2.15, the structure has the same
air gap for all legs and the same winding structure. According to the duality
modeling method [31], the reluctance model can be easily derived, as shown in Figure
2.16.
i2
i1
n2
n1 i3
n3
A gap1
R1 =
0 AC
A gap 2
R2 =
0 AC
A gap 0
R0 =
0 AC
Through the reluctance model, the electrical circuit of the transformer for the
LLC DC/DC resonant converter can be obtained easily, as shown in Figure 2.17; it
consists of one set of ideal transformer and three inductors. However, the ideal
transformer has the same turns ratio as the real physical structure, and the three
18
inductors correspond to each air gap. Based on the electrical circuit model, the
L0 n12 A gap1
3 L1 = , where R1 =
1
n3
R1 0 AC
L1 L2 n1 4 n12 A gap 2
L2 = , where R2 =
n3 R2 0 AC
5 n12 A
L0 = , where R0 = gap 0
n2 R0 0 AC
2
Figure 2.17. Electrical circuit model of the transformer for the LLC DC/DC resonant
converter [13].
Based on the electrical circuit model, the analysis of the transformer is divided
into two modes, as shown in Figure 2.18 and Figure 2.20. During Mode 1,
secondary winding n3 is connected to the output voltage. From the circuit in Figure
2.18, the equations of input current and input voltage can be derived, as follows:
iin i0 3
1 n1
L0 n3 Vo
i1 L1 L2 v1
n3 4
Vin
v2 5
2 n2
Mode 1
Figure 2.18. Analysis of the transformer during Mode 1 [13].
19
di1 n2
L1 + v1 = Vin ,
dt n1
di0 n
L0 + v1 + 2 v1 = Vin ,
dt n1
n3
v1 = Vo , and
n1
iin = i0 + i1 . (2.4.1)
Due to Equation (2.4.1), the relationship of the input current and voltage can be
obtained, as follows:
L1 L0 diin 1 L1
Vin = + Vo n2 + n1 . (2.4.2)
L1 + L0 dt n3 L1 + L0
Figure 2.19 shows the equivalent circuit during Mode 1. By comparing Figure
2.19 and Figure 2.18, the relationship can be obtained, as shown in Equation (2.4.3).
Due to Equation (2.4.3), inductor Lr and primary winding na are derived, as illustrated
in Equation (2.4.4).
iin
1 na : n3 3
Lr
Vin Lm Vo
2 4
L1 L0 diin 1 L1 diin 1
Vin = + Vo n2 + n1 Vin = Lr + Vo na
L1 + L0 dt n3 L1 + L0 dt n3 (2.4.3)
Lr na
20
L1 L0
Lr =
L1 + L0
(2.4.4)
L1
na = n2 + n1
L1 + L0
2.20. Using the same analysis described for Mode 1, inductor Lm can be derived as
follows:
na 2 L1 + L0
Lm = L2 . (2.4.5)
n1 L1 + L2 + L0
2
iin i0
1 n1
L0
i1 L 1 L2 v1
Vin
v2
2 n2
Mode 2
The preceding discussion shows the relationships among primary winding na,
resonant inductor Lr, and magnetic inductor Lm. Based on these equations, the
21
2.5. Summary
This chapter introduces the operational principles of the LLC resonant converter,
which includes six modes. Then, in Section 2.2, the DC analysis of the LLC DC/DC
the matched load for maximum efficiency is explored. Finally, the magnetic design
22
Chapter 3. Proposed PLL Control Scheme for
LLC DC/DC Resonant Converter
Generally speaking, the characteristics of the LLC resonant tank are affected by
the input voltage and the output impedance; this means the LLC resonant tank does
not operate at the required voltage gain. Therefore, in order to operate at the
Figure 3.1 shows the configuration of the LLC DC/DC resonant converter, which
consists of DC bus voltage VDC, the DC/AC inverter, the rectifier and the load. The
current-feedback, or PLL controls. The following sections will discuss these control
schemes in detail.
23
Figure 3.1. Configuration of the LLC DC/DC resonant converter.
Frequency Control
Frequency Control Schemes
Schemes
of DC/AC Inverter
of DC/AC Inverter
Fixed-Frequency Control
Fixed-Frequency Control Variable-Frequency Control
Variable-Frequency Control
Voltage- or
Voltage- or Current-
Current-
Phase-LockedLoop
Phase-Locked LoopControl
Control
FeedbackControl
Feedback Control
24
3.1.1. Fixed-Frequency and Variable-Frequency Controls
inverter. However, due to the variation in input voltage and output impedance, the
inverter with fixed-frequency control does not actually regulate the voltage gain.
Therefore, fixed-frequency control is not suitable for the LLC DC/DC resonant
half-bridge inverter. With the adjustable operating frequency, the LLC resonant tank
schemes use either voltage feedback or current feedback [18-19]. Figure 3.3 shows
3.3, the detected feedback signal of the circuit is sent to the control circuit to adjust
the operating frequency, and thus the required voltage gain is achieved.
Figure 3.4 shows the relationship between the amplitude of voltage gain Vo/Vi
and the operating frequency. Figure 3.4 illustrates the different voltage gains, which
are caused by variations in the resonant tank and output impedance. When the
converter is operated with the voltage gain required by the LLC resonant tank, the
operated at the required voltage gain while the operating frequency is fstable1.
However, the operating frequency can not provide the required voltage gain for
Curve2. Meanwhile, the operating frequency may be lower than resonant frequency
f1, which increases the turn-on switching losses. Current-feedback control has the
same drawback. Therefore, in this thesis PLL control is proposed to overcome the
25
DC/AC Inverter
VDC
LLC
Resonant Rectifier Load
Tank
Voltage- or Current-
Feedback Control
Figure 3.4. Relationship between amplitude of voltage gain Vo/Vi and operating
frequency.
26
3.1.2. Phase-Locked-Loop Control
schemes, the PLL control scheme is presented [20-23]. This scheme is also a
Figure 3.5 shows the PLL control scheme, which controls the operating
frequency by locking the phase differences, such as those caused by input voltage,
input current, output voltage, inductor voltage, capacitor voltage, etc. With the PLL
control scheme, the operating frequency of the inverter continuously tracks the
resonant frequency while the phase difference of the inverter at the resonant
frequency of the inverter is changed to make the inverter operate at the required
voltage gain. However, because the operating frequency will not be lower than
the resonant frequency of the LLC resonant tank, the switches of the inverter are
both operated in a ZVS condition. Meanwhile, turn-on switching losses are not
increased. For this reason, the PLL control scheme is better than both
27
Figure 3.5. Block diagram of the PLL control scheme.
At present, the PLL control scheme has been widely used in signal-processing
and digital systems. The concept and IC [24-25] show the regulation of the phase
between the midpoint voltage and resonant inductor current, including plots showing
the zero-phase point tracking the resonant frequency. This is expected based on the
input impedance of the tank. However, the work presented in this manuscript
appears to show the same result, but also senses the inductor voltage. In other work
[26], a digital approach for phase control is presented, including sensing either the
resonant inductor current or voltage. A discrete circuit is given in other research [27]
that also senses the resonant inductor voltage and effectively controls the phase.
Another paper [28] gives an approach for designing ballast with phase control. In
this thesis, the CD4046 is used as the PLL control IC, and the principle of the PLL is
described as follows.
28
These three parts are connected to form a closed-loop frequency-control system.
Since error voltage Ve(t) at the output of the phase comparator is zero, there is no
signal input applied to the PLL system, which means VCO control voltage Vd(t) is
zero. At the same time, Vd(t) causes the VCO to operate at a set frequency, which is
called the center frequency, fo, [32]. However, while an input signal is applied to the
PLL system, the phase comparator compares the phase and frequency of the signal
input with the VCO frequency and produces an error voltage proportional to the phase
and frequency difference of the input signal and the VCO. Error voltage Ve(t) is
filtered by the LPF and is applied as the control input voltage of the VCO.
Therefore, Vd(t) varies in a direction that reduces the frequency, thus reducing the
frequency difference between the VCO and the signal-input frequency. When the
input frequency is adequately close to the VCO frequency, the closed-loop nature of
the PLL is locked in. Hence, except for a finite phase difference, the VCO frequency
Input
Signal
Vs(t) Vo(t)
fs fo
Phase
Comparator
Ve(t)
Low-Pass Filter
Vd(t)
VCO
CD4046 PLL
29
3.2. Phase Characteristics of the LLC Resonant Tank
The section presents the phase characteristics of the LLC resonant tank. The
LLC resonant tank, as shown in Figure 3.7, consists of capacitor Cr, two inductors (Lr
and Lm), and equivalent resistance REQ. However, in order to determine a proper
detecting point for tracking the resonant frequency by using the PLL control scheme,
the phase characteristics Vs/Vin and VLr/Vin of the LLC resonant tank must be
analyzed as follows.
Cr VLr
Lr
ICr
Vin Lm REQ VS
Zi
Referring to Figure 3.7, the transfer function of Vs/Vin can be obtained at the
Vs ( Z Lm || REQ )
AV = = , (3.2.1)
Vin Z Cr + Z Lr + ( Z Lm || REQ )
1 8
where Z Lr = j Lr , Z Cr = , Z Lm = j Lm , REQ = 2 n 2 R .
jCr
In order to conduct the simulation for the LLC resonant tank, capacitor Cr, two
inductors (Lr and Lm), and three different values of resistance R are respectively 42 nF,
30
60 H, 240 H, 12 , 60 and 120 . Figure 3.8 shows the gains and phases of
Vs/Vin with different values of R. By observing the simulation results for gains and
phases, the phase angle of Vs/Vin at the resonant frequency is 90o while R is equal to
120 . However, when the value of R decreases at the resonant frequency, the phase
10
R=120
R=60
0
-10 R=12
1k 10k 100k 1M 10M
f(Hz)
V
s
Vin
180o
150o
100o
90o
R=12
50o
R=60
R=120
0o
1k 10k 100k 1M 10M
f(Hz)
Figure 3.8. Gains and phases of Vs/Vin with different values of R in the LLC
resonant tank.
31
The following section shows the analysis and design of the LLC DC/DC
resonant converter in detail to observe the relationship between the phases at the
Equation (3.2.2) shows the input impedance of the LLC resonant tank; using this
1 j Lm REQ
Zi = + j Lr +
jCr j Lm + REQ
(3.2.2)
2 Lm 2 REQ REQ 2 ( m + n 2 1) 2 Lm 2 (1 n 2 )
= +j .
REQ 2 + 2 Lm 2 Cr ( REQ 2 + 2 Lm 2 )
1 L 8
where, n = , r = , k L = m , REQ = 2 n 2 R, m = n 2 QL .
r Lr Cr Lr
1
1 2
r EQ
R 2
R 4
2 R 2
L 2
2
2 (1 + k L ) + Lm + 4 (1 + k L ) + (1 k L ) + Lm
2
fr = 2 4
EQ EQ m
2 Lm r r r 2
(3.2.3)
Vs m REQ ( m + n 1) j Lm m REQ (n 1)
2 2 2
= (3.2.4)
R 2 ( m + 2 1) + 2 L 2 ( 2 1)
2 2
Vin
EQ n m n
When the phase of Vs/Vin is 90o, the real part of the voltage gain Vs/Vin is zero.
Then, Equation (3.2.6) is obtained by solving Equation (3.2.5), which shows the
32
V m REQ 2 ( m + n 2 1)
Re =
s
=0 (3.2.5)
Vin REQ 2 ( m + n 2 1) + 2 Lm 2 (n 2 1)
2 2
1 2 Lr Cr
Lm = (3.2.6)
2 Cr
Vs m REQ 2 ( m + n 2 1) j Lm m REQ (n 2 1)
A= = . (3.2.7)
R ( m + 1) + L ( 1)
2 2 2 2 2 2 2
Vin
EQ n m n
A Cr REQ
Lr = . (3.2.8)
A 2 Cr
Figure 3.9 and Figure 3.10 are obtained by Equations (3.2.3), (3.2.4), (3.2.8) and
(3.2.9). Figure 3.9 shows the relationship between the phase of Vs/Vin at the
resonant frequency and the different equivalent resistances REQ in the steady state, in
which the value of the resonant capacitor is 0.1 nF, the gain ranges between 1 and 50,
and the operating frequencies are 50 kHz, 100 kHz, and 150 kHz. The figure shows
that the phase difference of Vs/Vin remains at 90o, regardless of the operating
frequencies and the required gains. Figure 3.10 shows the relationship between the
phase of Vs/Vin at the resonant frequency and the different resonant capacitors Cr in
the steady state, in which the value of the equivalent resistance REQ is 150 , the
33
gain ranges between 1 and 50, and the operating frequencies are 50 kHz, 100 kHz,
and 150 kHz. The figure shows that the phase difference of Vs/Vin remains at 90o,
V
s
Vin f = f r
Cr=0.1nF
100o
90o
A=1~50
50o
0.1k 1k 10k
REQ()
Figure 3.9. Relationship between phase of Vs/Vin and the different equivalent
resistances REQ at the resonant frequency.
V
s
Vin f = f r REQ=150
100o
90o
A=1~50
50o
0.1n 1n 10n 100n
Cr(F)
Figure 3.10. Relationship between phase of Vs/Vin and the different resonant
capacitors Cr at the resonant frequency.
34
3.2.2. VLr/Vs of the LLC Resonant Tank
According to Figure 3.7, the transfer function of VLr/Vs can be obtained at the
VLr Z Lr
AVLr = = , (3.2.10)
Vs ZCr + Z Lr + ( Z Lm || REQ )
1 8
where Z Lr = j Lr , ZCr = , Z Lm = j Lm , REQ = 2 n2 R .
jCr
For the simulation of the LLC resonant tank, capacitor Cr, two inductors (Lr and
Lm), and the three different values of resistance R are respectively 42 nF, 60 H, 240
H, 12 , 60 and 120 . Figure 3.11 shows the gains of Vo/Vs and phases of
VLr/Vs with different values of R. The simulation results for gains and phases reveal
that the phase angle of VLr/Vs at the resonant frequency is 90o while R is equal to 120
frequency, the phase angles of VLr/Vs are always equal to 90o. However, according
to Figure 3.11, the phase signal causes the PLL control scheme error malfunction.
Therefore, the phase angle of Vo/Vs will be locked at 90o for the LLC DC/DC
35
Vo
(dB)
Vs
20
10
R=120
R=60
0
-10 R=12
1k 10k 100k 1M 10M
f(Hz)
V
Lr
Vs
180o
150o
100o
90o
R=12 R=60
50o
R=120
0o
3 4 5 6
1k 10k 100k 1M 10M
f(Hz)
Figure 3.11. Gains of Vo/Vs and phases of VLr/Vs with different values of R in the
LLC resonant tank.
36
The following section shows the analysis and design of the LLC DC/DC
resonant converter in detail in order to observe the relationship between the phases at
(3.2.11).
=
(n 2 QL + n 2 1) REQ + Lm (n 2 1)
2 2
Vs
1 L
where n = , r = , QL = m
r Lr Cr Lr
(3.2.11)
When the phase of VLr/Vs is 90o, the real part of the voltage gain VLr/Vs is zero.
Then, Equation (3.2.13) is obtained by solving Equation (3.2.12), which shows the
n 2 REQ 2 (n 2 QL + n 2 1) + n 2 2 Lm 2 (n 2 1)
=0 (3.2.12)
(n QL + n 1) REQ + Lm (n 1)
2 2
2 2 2
REQ 2 (1 n 2 QL ) + 2 Lm 2
Lr = (3.2.13)
2 ( Cr REQ 2 + Lm n 2 QL )
Assume that the voltage gain of Vo/Vs is A in the steady state, as shown in
REQ
Lm = . (3.2.14)
A2 1
37
Based on Equation (3.2.14), Equation (3.2.13) becomes
C R + A2 ( A2 1) C R A2
1
r EQ r EQ
Lr = 2 . (3.2.15)
Cr A2 ( A2 1)
Figure 3.12 and Figure 3.13 can be obtained through Equations (3.2.3), (3.2.4),
(3.2.14) and (3.2.15). Figure 3.12 shows the relationship between the phase of
VLr/Vs at the resonant frequency and the different equivalent resistances REQ in the
steady state, in which the value of the resonant capacitor is 0.1 nF, the gain ranges
between 2 and 50, and the operating frequencies are 50 kHz, 100 kHz, and 150 kHz.
The figure shows that the phase difference of VLr/Vs remains at 90o, regardless of the
operating frequencies and the required gains. Figure 3.13 shows the relationship
between the phase of VLr/Vs at the resonant frequency and the different resonant
capacitors Cr in the steady state, in which the value of equivalent resistance REQ is 150
, the gain ranges between 2 and 50, and the operating frequencies are 50 kHz, 100
kHz, and 150 kHz. The figure shows that the phase difference of VLr/Vs remains at
38
V
Lr
VS f = f r Cr=0.1nF
100o
90o
A=2~50
50o
0o
0.1k 1k 10k
REQ()
Figure 3.12. Relationship between the phase of VLr/Vs and the different equivalent
resistances REQ at the resonant frequency.
V
Lr
VS f = f r REQ=150
100o
90o
A=2~50
50o
0o
0.1n 1n 10n
Cr(F)
Figure 3.13. Relationship between the phase of VLr/Vs and the different resonant
capacitors Cr at the resonant frequency.
39
3.3. Summary
This chapter has proposed a PLL control technique for the LLC DC/DC resonant
Section 3.2 are helpful for choosing and designing the LLC resonant tank. With the
tracks the resonant frequency of the LLC resonant tank at different input voltages and
load conditions.
40
Chapter 4. Implementation and
Experimental Results
4.1. Introduction
Figure 4.1 shows the detailed circuit diagram of the proposed LLC DC/DC
resonant converter with PLL control. The LLC resonant tank includes a Cr-Lr-Lm
resonant-tank network where Cr is made up of Cr1 and Cr2, Lr is the primary leakage
According to the analysis presented in Section 3.2, the phase differences of Vs/Vin
and VLr/Vin are always equal to 90o at the resonant frequency despite the value of
output impedance R. However, a comparison of Figures 3.8 and 3.11 shows that
using the phase angle of Vs/Vin for the PLL control scheme can achieve better
performance. Therefore, the phase angle of Vs/Vin will be locked at 90o for the LLC
41
Figure 4.1. Detailed circuit diagram of the proposed LLC DC/DC resonant converter
with PLL control.
42
4.2. Design of the Proposed LLC DC/DC Resonant Converter
This section introduces the design of the LLC DC/DC resonant converter; its
Table 4.1. Specifications of the LLC DC/DC resonant converter with PLL control.
Specifications Values
Output Voltage 48 V
As shown in Figure 4.1, the input voltage of the LLC resonant tank is a square
wave, and the duty cycle of the square wave is 50%. In order to simplify the
analysis of the LLC resonant tank, the fundamental wave of the sinusoidal input
voltage of the LLC resonant tank is approximated as shown in Equation (4.2.1), which
is used to derive the voltage gain of the LLC DC/DC resonant converter as follows:
2
Vrms = VDC , and
(4.2.1)
43
Vo
A= . (4.2.2)
Ns 2
VDC
Np
Based on Equation (4.2.2), the required voltage gains are 1.42 and 1 while the
Vs
Vin
2
Zo Lr 8
Q = where Z o = , REQ = 2 n 2 R
REQ Cr
0.2
1.5
VDC=300V
0.4
1 VDC=400V
0.6
1
0.5
3
Q=5
0
0 0.5 1 1.5 2
fs/fr
Figure 4.2 shows the operating region of the LLC DC/DC resonant converter
when the input voltage ranges from 300 V to 400 V. According to Figure 4.2, the
limited range of Q is from 0.4 to 0. Therefore, in order for the converter to operate
at the required voltage gain, the value of Q must be lower than 0.4. The definition of
Q is shown as follows:
Zo Lr 8
Q = where Z o = , REQ = 2 n 2 R . (4.2.3)
REQ Cr
44
Vs
Vin
2
Zo Lr 8
Q = where Z o = , REQ = 2 n 2 R
REQ Cr
0.2
1.5
VDC=300V
0.4
1 VDC=400V
0.6
1
0.5
3
Q=5
0
0 0.5 1 1.5 2
fs/fr
Based on Equations (3.2.6) and (3.2.13), the relationship between Cr and Lr can
be obtained, as follows:
1
f=
2 Lr Cr
. (4.2.4)
According to Equation (4.2.4), the value of the resonant capacitor and inductor
Lr = 43 H , Cr = 66nF .
As analyzed in the previous section, the matched load for optimal efficiency can
be found as follows:
45
REQ ,OPT = Lm . (4.2.5)
Based on Equation (4.2.5), REQ,OPT = 155.63 and f=100 kHz at rated load
condition and 400 V input voltage, the value of Lm can be found as follows:
Lm 240 H .
According to these design steps, all of the parameters for the LLC resonant tank
can be obtained. The values of the designed component parameters for the LLC
Cr Lr
43H
66nF
Vin Lm REQ Vs
240H
By use of the parameters shown above, the gain and phase of the proposed LLC
DC/DC resonant converter can be obtained, as illustrated in Figure 4.4, which shows
that the voltage gain of Vs/Vin is 1 when the input voltage is 400 V. Moreover, the
switching frequency of the LLC resonant tank is 100 kHz and the phase difference of
Vs/Vin is approximately 0o. However, when the input voltage is reduced to 300 V,
the switching frequency of the LLC resonant tank is adjusted to 61 kHz. Therefore,
the voltage gain of Vs/Vin is 1.42, and the phase angle of Vs/Vin is approximately 11o.
46
Vs
(dB)
Vin
3
2.5 R=12
1.5 VDC=300V
1.42
1 VDC=400V
fs=61kHz fs=100kHz
0.5
0 0.5 1 1.5 2
fs/fr
(a)
V
s
Vin
o
180
150o R=12
100o
90o
50o
11o
0o
0 0.5 1 1.5 2
fs/fr
(b)
Figure 4.4. Gain and phase of the LLC DC/DC resonant converter:
(a) gain of Vs/Vin, and (b) phase of Vs/Vin.
47
4.2.2. Design of the Compensator for the LLC DC/DC Resonant Converter
The compensator used for LLC DC/DC resonant converter is analyzed in this
(b). Then, the following will introduce the design and implementation of the
48
Q1
Cr1 Dc1
Lr T Vo D1
Vs
Vin
Co R
ns
Lm np
n s D2
Q2 Cr2 Dc2
Vc
Driver VCO
Vp
Vs
VDC
Vo
(a)
Gain(dB)
40
20
0
-20
-40
-60
Phase(deg)
60
-20
-60
-100
-140
-180
100 1k f(Hz) 10k 100k
(b)
Figure 4.5. (a) Circuit for open-loop small-signal analysis of LLC DC/DC resonant
converter (b) Bode plot of open-loop control-to-output transfer function of
LLC DC/DC resonant converter.
49
With above discussion, the compensator used for LLC DC/DC resonant
converter is shown in Figure 4.6 (a) which is composed of one integrator, one pole
and one zero. The transfer function of this compensator is derived, as shown in
Equation (4.2.6).
Vc
=
(1 + sR2C1 ) =
K ( s + fz )
(4.2.6)
Vo sR1 1 + sR2C1C2 / ( C1 + C2 ) s ( s + f p )
Assuming C1 C2 , the frequencies of the pole and zero are derived, as shown
in Equation (4.2.7).
1 1
fz = , fp = (4.2.7)
2 R2C1 2 R2C2
Based on Figure 4.5, in order to compensate this system, the zero is placed at
3kHz and the pole is placed at 100kHz. Then, using Equation (4.2.7), the parameters
Figure 4.6 (c) shows the simulation waveform of the bode plot for the proposed
compensator. According to Figure 4.6 (c), the turning points are approximately
3kHz and 100kHz which are corresponded to the design values of the compensator.
50
R2 C1
R1
C2
Vo
Vc
Vref
(a)
Gain
-1
fz fp -1
Gain Spectrum
(b)
Gain(dB)
80
60
40
20
Phase(deg)
160
140
120
100
100 1k 10k 100k 1M
f(Hz)
(c)
Figure 4.6. (a) Compensator structure for LLC DC/DC resonant converter (b) Gain
spectrum of the compensator (c) Simulation waveforms of Bode plot for
the compensator.
51
Figure 4.7 (a) shows the circuit diagram of closed-loop LLC DC/DC resonant
control-to-output transfer function is shown in Figure 4.7 (b) which is obtained from
the simulation software, SIMPLIS. According to Figure 4.7 (b), the phase margin
(P.M.) of this system is 40o. Figure 4.8 (a) and (b) show the simulation results for
the closed-loop LLC DC/DC resonant converter at different load conditions and input
voltages. However, based on Figure 4.8 (a) and (b), the system has provided a
constant output voltage at the load conditions which range from 25% to rated load
condition and at input voltages which range from 300V to 400V. Figure 4.8 (c)
shows the simulation results for the proposed LLC DC/DC resonant converter under
load change. The output voltage is within 5% regulation when the load changes
52
Q1
Cr1 Dc1
Lr T Vo D1
Vs
Vin
Co R
ns
Lm np
Vp
ns D2
Q2 Cr2 Dc2 R2 C1
C2 R1
Driver VCO
Vref
Vs
Vo
(a)
Gain(dB)
40
0
-40
-80
-120
Phase(deg)
0
-50
-100
-150
-200 P.M.=40o
(b)
Figure 4.7. (a) Circuit for closed-loop small-signal analysis of LLC DC/DC resonant
converter (b) Bode plot for closed-loop control-to-output transfer function
of LLC DC/DC resonant converter.
53
Vo(V)
50
48
46
44 400V
350V
42
300V
40
50 100 150 200 250 300
Po(W)
(a)
Vo(V)
50
48
46
44 300W
200W
42 100W
40
300 320 340 360 380 400
Vin(V)
(b)
From full load to 25% load
From 25% load to full load 48.5
49
48
Vo
48.6
Vo 48.2
47.8
47.5
47
47.4 46.5
47
4
4
3
Io 3
Io 2 2
1 1
0 25.4 25.5 25.6 25.7 25.8 25.9 26
25 25.1 25.2 25.3 25.4 25.5
(c)
Figure 4.8. Simulation results using SIMPLIS: (a) Output voltage at different load
conditions (b) Output voltage at different input voltage (c) load change
from full load to 25% load.
54
4.2.3. Design of the Transformer for the LLC DC/DC Resonant Converter
This section describes the detailed parameters of the transformer for the LLC
DC/DC resonant converter. For the structure shown in Figure 4.9, two outer legs are
i2
i1
n2
n1 i3
n3
The structure of the transformer shown in Figure 4.9 reveals that L1=L2=0.5Lo.
Based on this relationship and Equations (2.4.4) and (2.4.5), the parameters of the
windings n1, na and n2 are derived as shown in Equation (4.2.8). For the proposed
LLC DC/DC resonant converter, the core used is EE40 and the air gap is 0.5 mm for
all legs.
L1 A gap1
n1 =
0 AC
8 n12 Lm
na = (4.2.8)
9 Lr
1
n2 = na n1
3
According to Equation (4.2.8) and the information about the EE core, the values
55
n1 22, na 42, n2 35 .
Because the turns ratio of the transformer is equal to 4, the value of secondary
n3 10 .
However, the primary windings of the transformer are built with three stands of
SWG#29 wire. On the secondary side, the windings of the transformer are built with
56
4.3. Implementation of Proposed Resonant Converter
Figure 4.10 shows the complete circuit of the LLC DC/DC resonant converter
with PLL control. The prototype circuit in this thesis is modified from the circuit
voltage-regulator circuit. The gate signals of the half-bridge switches are provided
by gate driver L6384, in which the variable-frequency pulse signals are produced
from the VCO of the CD4046. Then, the half-bridge circuit is used to drive the LLC
DC/DC resonant converter. With the PLL control scheme, the operating frequency
of the LLC DC/DC resonant converter continuously tracks the resonant frequency,
and thus the resonant converter can operate at the required voltage gain. In addition,
the maximum and minimum operating frequencies on the IC CD4046 can be set using
one external capacitor and two resistances. Phase detection is realized by a simple
capacitive coupled clipping network and a series of NAND gates, which sharpen the
phase-signal edges and reduce noise. The voltage-regulator circuit regulates the
output voltage by detecting the feedback voltage, which is sensed by the voltage
divider. By comparing this averaged voltage with the reference voltage, the input
voltage of the VCO for the CD4046 can be decreased, and thus the oscillator
frequency can be also decreased. This method increases the output voltage until the
57
Figure 4.10. Detailed schematic of the prototype circuit for the proposed LLC DC/DC
58
4.4. Experimental Results for the PLL-Controlled LLC DC/DC
Resonant Converter
Figure 4.11 (b) shows the experimental waveforms for transformer secondary
output voltage Vs and input voltage Vin of the proposed LLC DC/DC resonant
converter at the rated load and with 400V input voltage. The relationship shows that
the phase difference at the rated load is -10o, which approaches the previous analysis
shown in Figure 4.4 (b). Figure 4.11 (c) shows the experimental waveforms for the
IDS2 flows through the body diode of switch Q2, which creates a ZVS condition for
primary switch Q2. Therefore, both half-bridge switches work in ZVS at the rated
load.
Figure 4.12 (b) shows the experimental waveforms for transformer secondary
output voltage Vs and input voltage Vin, of the proposed LLC DC/DC resonant
converter at the rated load and with 300V input voltage. The relationship shows that
the phase difference at the rated load is 2o, which approximates the previous analysis
shown in Figure 4.4 (b). The experimental waveforms for the half-bridge bottom
MOSFET are shown in Figure 4.12 (c). These waveforms show that drain-source
current IDS2 flows through the body diode of switch Q2, which creates a ZVS
condition for primary switch Q2. Thus, both half-bridge switches work in ZVS at the
rated load.
59
Q1 Cr1 Dc1
Lr T Vs D1
Vin
VDC Co R
ns
Lm np
IDS2 n s D2
Q2 Cr2 Dc2
(a)
Vs
Vin
-10o Phase Difference
Input Voltage=400V ; Switching Frequency = 100kHz
Vs(10V/div) ; Vin(10V/div) ; Time Base(5s)
(b)
VDS2
IDS2
Figure 4.11. (a) Circuit block diagram, (b) waveforms for Vs and Vin at the rated load
and with 400V input voltage, and (c) waveforms for VDS2 and IDS2 at the
rated load and with 400V input voltage.
60
Q1 Cr1 Dc1
Lr T Vs D1
Vin
VDC Co R
ns
Lm np
IDS2 n s D2
Q2 Cr2 Dc2
(a)
Vs
Vin
2o Phase Difference
Input Voltage=300V ; Switching Frequency = 61.2kHz
Vs(10V/div) ; Vin(10V/div) ; Time Base(10s)
(b)
VDS2
IDS2
Figure 4.12. (a) Circuit block diagram, (b) waveforms for Vs and Vin at the rated load
and with 300V input voltage, and (c) waveforms for VDS2 and IDS2 at the
rated load and with 300V input voltage.
61
Figure 4.13 (b) shows the experimental waveforms for transformer secondary
output voltage Vo and input voltage VDS2 of the proposed LLC DC/DC resonant
converter at 75% of the rated load and with 400V input voltage. The relationship
shows that the phase difference at 75% of the rated load is -8o, which approaches the
previous analysis shown in Figure 4.4 (b). The experimental waveforms for the
half-bridge bottom MOSFET are shown in Figure 4.13 (c). These waveforms
illustrate that drain-source current IDS2 flows through the body diode of switch Q2,
which creates a ZVS condition for primary switch Q2. Therefore, both half-bridge
Figure 4.14 (b) shows the experimental waveforms for transformer secondary
output voltage Vo and input voltage VDS2 of the proposed LLC DC/DC resonant
converter at 75% of the rated load and with 300V input voltage. The relationship
shows that the phase difference at 75% of the rated load is 3o, which approximates the
previous analysis shown in Figure 4.4 (b). The experimental waveforms for the
half-bridge bottom MOSFET are shown in Figure 4.14 (c). The waveforms show
that drain-source current IDS2 flows through the body diode of switch Q2, which
creates a ZVS condition for primary switch Q2. Consequently, both half-bridge
62
Q1 Cr1 Dc1
Lr T Vs D1
Vin
VDC Co R
ns
Lm np
IDS2 n s D2
Q2 Cr2 Dc2
(a)
Vo
VDS2
-8o Phase Difference
Input Voltage=400V ; Switching Frequency = 103.6kHz
Vo(10V/div) ; VDS2(10V/div) ; Time Base(5s)
(b)
VDS2
IDS2
Figure 4.13. (a) Circuit block diagram, (b) waveforms for Vo and VDS2 at 75% of the
rated load and with 400V input voltage, and (c) waveforms for VDS2 and
IDS2 at 75% of the rated load and with 400V input voltage.
63
Q1 Cr1 Dc1
Lr T Vs D1
Vin
VDC Co R
ns
Lm np
IDS2 n s D2
Q2 Cr2 Dc2
(a)
Vo
VDS2
3o Phase Difference
Input Voltage=300V ; Switching Frequency = 61.5kHz
Vo(10V/div) ; VDS2(10V/div) ; Time Base(10s)
(b)
VDS2
IDS2
Figure 4.14. (a) Circuit block diagram, (b) waveforms for Vo and VDS2 at 75% of the
rated load and with 300V input voltage, and (c) waveforms for VDS2 and
IDS2 at 75% of the rated load and with 300V input voltage.
64
Figure 4.15 (b) shows the experimental waveforms for transformer secondary
output voltage Vo and input voltage VDS2 of the proposed LLC DC/DC resonant
converter at 50% of the rated load and with 400V input voltage. The relationship
shows that the phase difference at 50% of the rated load is -5o, which approaches the
previous analysis shown in Figure 4.4 (b). The experimental waveforms for the
half-bridge bottom MOSFET are shown in Figure 4.15 (c). These waveforms
illustrate that drain-source current IDS2 flows through the body diode of switch Q2,
which creates a ZVS condition for primary switch Q2. Therefore, both half-bridge
Figure 4.16 (b) shows the experimental waveforms for transformer secondary
output voltage Vo and input voltage VDS2, of the proposed LLC DC/DC resonant
converter at 50% of the rated load and with 300V input voltage. The relationship
shows that the phase difference at 50% of the rated load is 1o, which approximates the
previous analysis shown in Figure 4.4 (b). The experimental waveforms for the
half-bridge bottom MOSFET are shown in Figure 4.16 (c). These waveforms reveal
that drain-source current IDS2 flows through the body diode of switch Q2, which
creates a ZVS condition for primary switch Q2. Consequently, both half-bridge
65
Q1 Cr1 Dc1
Lr T Vs D1
Vin
VDC Co R
ns
Lm np
IDS2 n s D2
Q2 Cr2 Dc2
(a)
Vo
VDS2
-55oo Phase
phase Difference
difference
Input Voltage=400V ; Switching Frequency = 103.4kHz
Vo(10V/div) ; VDS2(10V/div) ; Time Base(5s)
(b)
VDS2
IDS2
Figure 4.15. (a) Circuit block diagram, (b) waveforms for Vo and VDS2 at 50% of the
rated load and with 400V input voltage, (c) waveforms for VDS2 and IDS2
at 50% of the rated load and with 400V input voltage.
66
Q1 Cr1 Dc1
Lr T Vs D1
Vin
VDC Co R
ns
Lm np
IDS2 n s D2
Q2 Cr2 Dc2
(a)
Vo
VDS2
1o Phase Difference
Input Voltage=300V ; Switching Frequency = 61.5kHz
Vo(10V/div) ; VDS2(10V/div) ; Time Base(5s)
(b)
VDS2
IDS2
Figure 4.16. (a) Circuit block diagram, (b) waveforms for Vo and VDS2 at 50% of the
rated load and with 300V input voltage, and (c) waveforms for VDS2 and
IDS2 at 50% of the rated load and with 300V input voltage.
67
Figure 4.17 (b) shows the experimental waveforms for transformer secondary
output voltage Vo and input voltage VDS2 of the proposed LLC DC/DC resonant
converter at 25% of the rated load and with 400V input voltage. The relationship
shows that the phase difference at 25% of the rated load is -4o, which approaches the
previous analysis shown in Figure 4.4 (b). The experimental waveforms for the
half-bridge bottom MOSFET are shown in Figure 4.17 (c). These waveforms
illustrate that drain-source current IDS2 flows through the body diode of switch Q2,
which creates a ZVS condition for primary switch Q2. Therefore, both half-bridge
Figure 4.18 (b) shows the experimental waveforms for transformer secondary
output voltage Vo and input voltage VDS2 of the proposed LLC DC/DC resonant
converter at 25% of the rated load and with 300V input voltage. The relationship
shows that the phase difference at 25% of the rated load is 0o, which approximates the
previous analysis shown in Figure 4.4 (b). The experimental waveforms for the
half-bridge bottom MOSFET are shown in Figure 4.18 (c). These waveforms reveal
that drain-source current IDS2 flows through the body diode of switch Q2, which
creates a ZVS condition for primary switch Q2. Consequently, both half-bridge
68
Q1 Cr1 Dc1
Lr T Vs D1
Vin
VDC Co R
ns
Lm np
IDS2 n s D2
Q2 Cr2 Dc2
(a)
Vo
VDS2
-4o Phase Difference
Input Voltage=400V ; Switching Frequency = 103.1kHz
Vo(10V/div) ; VDS2(10V/div) ; Time Base(5s)
(b)
VDS2
IDS2
Figure 4.17. (a) Circuit block diagram, (b) waveforms for Vo and VDS2 at 25% of the
rated load and with 400V input voltage, and (c) waveforms for VDS2 and
IDS2 at 25% of the rated load and with 400V input voltage.
69
Q1 Cr1 Dc1
Lr T Vs D1
Vin
VDC Co R
ns
Lm np
IDS2 n s D2
Q2 Cr2 Dc2
(a)
Vo
VDS2
0o Phase Difference
Input Voltage=300V ; Switching Frequency = 61.9kHz
Vo(10V/div) ; VDS2(10V/div) ; Time Base(5s)
(b)
VDS2
IDS2
Figure 4.18. (a) Circuit block diagram, (b) waveforms for Vo and VDS2 at 25% of the
rated load and with 300V input voltage, and (c) waveforms for VDS2 and
IDS2 at 25% of the rated load and with 300V input voltage.
70
Figure 4.19 (b) shows the experimental waveforms for transformer secondary
output voltage Vs and input voltage Vin of the proposed LLC DC/DC resonant
converter at 10% of the rated load and 400V input voltage. The relationship shows
that the phase difference at 10% of the rated load is -3o, which approaches the
previous analysis shown in Figure 4.4 (b). The experimental waveforms for the
half-bridge bottom MOSFET are shown in Figure 4.19 (c). According to the
waveforms, drain-source current IDS2 flows through the body diode of switch Q2,
which creates a ZVS condition for primary switch Q2. Therefore, both half-bridge
Figure 4.20 (b) shows the experimental waveforms for transformer secondary
output voltage Vs and input voltage Vin of the proposed LLC DC/DC resonant
converter at 10% of the rated load and with 300V input voltage. The relationship
shows that the phase difference at 10% of the rated load is 1o, which approximates the
previous analysis shown in Figure 4.4 (b). The experimental waveforms for the
half-bridge bottom MOSFET are shown in Figure 4.20 (c). These waveforms reveal
that drain-source current IDS2 flows through the body diode of switch Q2, which
creates a ZVS condition for primary switch Q2. Consequently, both half-bridge
71
Q1 Cr1 Dc1
Lr T Vs D1
Vin
VDC Co R
ns
Lm np
IDS2 n s D2
Q2 Cr2 Dc2
(a)
V s
Vin
-3o Phase Difference
Input Voltage=400V ; Switching Frequency = 103.6kHz
Vs(10V/div) ; Vin(10V/div) ; Time Base(5s)
(b)
VDS2
IDS2
Figure 4.19. (a) Circuit block diagram, (b) waveforms for Vs and Vin at 10% of the
rated load and with 400V input voltage, and (c) waveforms for VDS2 and
IDS2 at 10% of the rated load and with 400V input voltage.
72
Q1 Cr1 Dc1
Lr T Vs D1
Vin
VDC Co R
ns
Lm np
IDS2 n s D2
Q2 Cr2 Dc2
(a)
Vs
Vin
1o Phase Difference
Input Voltage=300V ; Switching Frequency = 61.5kHz
Vs(10V/div) ; Vin(10V/div) ; Time Base(10s)
(b)
VDS2
IDS2
Figure 4.20. (a) Circuit block diagram, (b) waveforms for Vs and Vin at 10% of the
rated load and with 300V input voltage, and (c) waveforms for VDS2 and
IDS2 at 10% of the rated load and with 300V input voltage.
73
Figure 4.21 shows the measured output voltages versus the input voltages at
different load conditions. When the load condition is below 200W, the output
voltage is within 5% regulation. Figure 4.22 shows the measured output voltages
versus the load conditions at different input voltages. When the load condition is
below 200W, the output voltage is within 5% regulation. Figure 4.23 shows the test
result for the proposed LLC DC/DC resonant converter under load change. The
48
46
44 300W
200W
42 100W
40
300 320 340 360 380 400
Vin(V)
Figure 4.21 Output voltages versus input voltages at different load conditions.
Vo(V)
50
48
46
44 400V
350V
42 300V
40
50 100 150 200 250 300
Po(W)
Figure 4.22 Output voltages versus output powers at different input voltages.
From 25% load to full load From full load to 25% load
Vo Vo
Io Io
Figure 4.23 Test result of load change from full load to 25% load
74
Figure 4.24 shows the measured efficiency of the proposed LLC DC/DC
resonant converter at different input voltages and rated load conditions. The
measured maximum efficiency is approximately 91.8% at the rated load and with
400V input voltage. Figure 4.25 shows the measured efficiency of the proposed
LLC DC/DC resonant converter at different load conditions and with 400V input
voltage. The maximum efficiency is achieved at the rated load, which is nearly
91.8%.
75
4.5. Summary
This chapter has shown the design and implementation of the proposed circuit.
The PLL control scheme is implemented by detecting the phase signals of the input
voltage and the output voltage. The PLL control scheme prevents the operating
frequency of the circuit from being lower than the resonant frequency of the LLC
resonant tank. The experimental results show that both half-bridge switches work in
a ZVS condition at different input voltages and load conditions. In addition, with the
76
Chapter 5. Conclusions and Future Work
The preceding analysis of phase characteristics facilitates the choice and design of the
LLC resonant tank. The PLL control scheme allows the operating frequency of the
converter to continuously track the resonant frequency of the LLC resonant tank at
different input voltages and load conditions; this means the resonant frequency of the
LLC resonant tank will not be lower than the switching frequency, thus affording a
reduction in turn-on switching losses. Due to the PLL control scheme, this converter
same time, the LLC resonant tank has higher PF because of PLL control, the higher
efficiency is achieved.
The DC analysis derived in this thesis has also simplified the design of the LLC
matched load for maximum efficiency has been explored. The magnetic design for
the LLC DC/DC resonant converter has also been discussed. Based on the model,
the integrated magnetic structure has the same amount of air gap on all legs, which is
The PLL control scheme has been implemented by detecting the phase signals of
the input voltage and the transformer secondary output voltage. The experimental
results have shown that both half-bridge switches work in a ZVS condition at
different input voltages and load conditions. In addition, with the optimal-efficiency
77
design, the maximum efficiency (approximately 91.8%) has been achieved at the rated
load.
The recommended future research work for the LLC DC/DC resonant converter
frequencies, such as 200 kHz or higher, to reduce the volume of the magnetic
component.
z By use of the integrated magnetic module for the LLC resonant tank, the power
78
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