Infineon-DesignGuide Quasi Resonant CoolSET Generation5-ATI-V01 00-En

5th Generation Quasi-Resonant Design
Guide
AN-Design Guide-ICE5QSAG and ICE5QRxxxxAx
About this document

Scope and purpose
This document is an engineering report that describes how to design Quasi-Resonant flyback converter
by using the Infineons latest 5th generation Quasi-Resonant Controller, ICE5QSAG and CoolSET,
ICE5QRxxxxAx which offer high efficiency, low standby power with selectable entry and exit standby
power option, wider VCC operating range with fast start up, robust line protection with input OVP,
brownout and various mode of protections for a high reliable system.
Intended audience
This document is intended for power supply design/application engineer, students, etc., who wish to
design power supply with 5th generation Quasi-Resonant Controller, ICE5QSAG and CoolSET,
ICE5QRxxxxAx.
Table of Contents
About this document ........................................................................................................... 1
1 Abstract ................................................................................................................................ 3
2 Description ........................................................................................................................... 4
2.1 List of features........................................................................................................................ 4
2.2 Pin layout ............................................................................................................................... 4
2.2.1 FB (Feedback & Burst entry/exit control) ........................................................................... 4
2.2.2 VIN (Input Line OVP & Brownout) ...................................................................................... 5
2.2.3 CS (Current Sense) ........................................................................................................... 5
2.2.4 ZCD (Zero Crossing Detection).......................................................................................... 5
2.2.5 GATE (Gate Drive Output, Controller only) ........................................................................ 5
2.2.6 SOURCE (Source, Controller only) .................................................................................... 5
2.2.7 DRAIN (Drain, CoolSETTM only) ......................................................................................... 5
2.2.8 VCC (Positive Voltage Supply) .......................................................................................... 5
2.2.9 GND (Ground) ................................................................................................................... 5
3 Overview of Quasi-Resonant flyback converter ................................................................ 6
4 Functional description and component design ................................................................. 9
4.1 VCC pre-charging and typical VCC voltage during start up .................................................... 9
4.1.1 VCC capacitor ................................................................................................................. 10
4.2 Soft-start .............................................................................................................................. 10
4.3 Normal operation .................................................................................................................. 10
4.3.1 Digital Frequency Reduction ............................................................................................ 11
4.3.1.1 Minimum ZC Count Determination .............................................................................. 11
4.3.1.2 Up/down counter ......................................................................................................... 11
4.3.1.3 Switch on determination .............................................................................................. 12
4.3.2 Switch off determination................................................................................................... 12
4.4 Active Burst Mode with selectable power level ..................................................................... 13
4.4.1 WEIKENG INTERNATIONAL CO.,LTD.
Entering Active Burst Mode Operation ............................................................................. 13
4.4.2 During Active Burst Mode Operation ................................................................................
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5th Generation Quasi-Resonant Design Guide
Abstract
4.4.3 Leaving Active Burst Mode Operation .............................................................................. 14

4.5 Current sense....................................................................................................................... 15
4.6 Feedback ............................................................................................................................. 16
4.7 Zero crossing detection ........................................................................................................ 17
4.8 Gate drive (ICE5QSAG only) ................................................................................................ 17
4.9 Line Over Voltage, brownout and Line selection................................................................... 18
4.10 Protection features ............................................................................................................... 19
4.11 Others .................................................................................................................................. 20
5 Typical application circuit ................................................................................................. 21
6 PCB layout recommendation............................................................................................. 23
7 Output Power of 5th generation Quasi-Resonant ICs ....................................................... 24
8 5th Generation Quasi-Resonant FLYCAL design example ............................................... 28
8.1 Input Diode Bridge (BR1): .................................................................................................... 28
8.2 Input Capacitor (C13): .......................................................................................................... 29
8.3 Transformer Design (TR1): ................................................................................................... 30
8.4 Sense Resistor (R14): .......................................................................................................... 32
8.5 Winding Design: ................................................................................................................... 33
8.6 Reverse Voltage of Diode (D21, D12): ................................................................................. 36
8.7 Clamping Network (R11, C15, and D11): ............................................................................. 36
8.8 Output Capacitors (C22, C23, C24): ..................................................................................... 37
8.9 Output Filter (L21, C24): ....................................................................................................... 37
8.10 VCC Capacitors (C16, C17): ................................................................................................ 38
8.11 Losses:................................................................................................................................. 38
8.12 Heat Dissipater:.................................................................................................................... 40
8.13 Regulation Loop: .................................................................................................................. 41
8.14 Zero crossing and output OVP: ............................................................................................ 44
8.15 Line OVP, brownout and Line selection: ............................................................................... 45
9 References .......................................................................................................................... 47
Revision History ................................................................................................................. 47
WEIKENG INTERNATIONAL CO.,LTD.

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Abstract
1 Abstract
This design guide describes how to design Quasi-Resonant flyback converter using
ICE5QSAG/ICE5QRxxxxAx which is the 5th generation of Quasi-Resonant PWM controller/CoolSET
developed by Infineon.
The IC is optimized for off-line switch power supply applications such as Home Appliances/White Goods,
TV, PC, Server, Blu-ray player, Set-top box and notebook adapter. The improved digital frequency
reduction with proprietary quasi-resonant operation offers lower EMI and higher efficiency for wide AC
range by reducing the switching frequency difference between low and high line. The enhanced active
burst mode power enables flexibility not only in standby power operation range selection but also Quasi-
Resonant switching even in burst mode. The product has a wide operating range (10~25.5 V) of IC
power supply and lower power consumption. The numerous protection functions including robust line
protection with input OVP and brownout give a full protection of the power supply system in failure
situations. All of these make the ICE5QSAG an outstanding controller for Quasi-Resonant flyback
converter in the market.

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Description
2 Description
2.1 List of features
Integrated 700 V/800 V avalanche rugged CoolMOS 1
Novel Quasi-Resonant operation and propriety implementation for low EMI
Enhanced Active Burst Mode with selectable entry and exit standby power
Active Burst Mode to reach the lowest standby power <100 mW
Fast startup achieved with cascode configuration
Digital frequency reduction for better overall system efficiency
Built-in digital soft start
Cycle-by-cycle peak current limitation
Maximum on/off time limitation to avoid audible noise during start up and power down
Robust line protection with input OVP and brownout
Auto restart mode protection for VCC Over Voltage, VCC Under Voltage, Over load/Open Loop,
Output Over Voltage, Over Temperature and CS (Current Sense) short to GND
Limited charging current for VCC short to GND
Pb-free lead plating, halogen free mold compound, RoHS compliant
2.2 Pin layout
PG-DSO-12
FB 1 12 GND
VIN 2 11 VCC
CS 3 10 NC
ZCD 4 9 NC
FB 1 PG-DIP-7 8 GND
PG-DSO-8
FB 1 8 GND
VIN 2 7 VCC
VIN 2 7 VCC
CS 3 DRAIN 5 8 DRAIN
CS 3 6 SOURCE
ZCD 4 5 GATE ZCD 4 5 DRAIN DRAIN 6 7 DRAIN
ICE5QSAG ICE5QRxxxxAZ ICE5QRxxxxAG

Figure 1 Pin Configuration
2.2.1 FB (Feedback & Burst entry/exit control)

FB pin combines the functions of feedback loop control, selectable burst entry/exit control and
overload/open loop protection.

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Description
2.2.2 VIN (Input Line OVP & Brownout)

VIN pin is connected to the bus via resistor divider (see Figure 2) to sense the line voltage. This pin
combines the functions of input Line OVP, Brownout and minimum ZC count setting between low and
high line.
2.2.3 CS (Current Sense)

CS pin is connected to the shunt resistor for the primary current sensing externally and to the PWM
signal generator block for switch-off determination (together with the feedback voltage) internally.
Moreover, CS pin short to ground protection is sensed by this pin.
2.2.4 ZCD (Zero Crossing Detection)

ZCD pin combines the functions of startup, zero crossing detection and output over voltage protection.
During the start up, it is used to provide a voltage level to the gate of power switch CoolMOSTM to charge
VCC capacitor.
2.2.5 GATE (Gate Drive Output, Controller only)

The GATE pin is the output of the internal driver stage, which has a rise time of 117 ns and a fall time of
27 ns when driving a 1 nF capacitive load.
2.2.6 SOURCE (Source, Controller only)

The SOURCE pin is connected to the source of external power switch Q1 (see Figure 2) which is in
series connection with internal low side MOSFET and internal VCC diode D.
2.2.7 DRAIN (Drain, CoolSETTM only)

The DRAIN pin is connected to the drain of the integrated 700V/800V CoolMOSTM.
2.2.8 VCC (Positive Voltage Supply)

The VCC pin is the positive voltage supply to the IC. The operating range is 10~25.5 V.
2.2.9 GND (Ground)

The GND pin is the common ground of the controller/CoolSETTM.

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Overview of Quasi-Resonant flyback converter
3 Overview of Quasi-Resonant flyback converter

Figure 2 and Figure 3 show a typical application of ICE5QSAG and ICE5QRxxxxAx in Quasi-Resonant
flyback converter. In this converter, the mains input voltage is rectified by the diode bridge and then
smoothed by the capacitor Cbus where the bus voltage Vbus is available. The transformer has one primary
winding W p, one or more secondary windings (W s1 and W s1), and one auxiliary winding W a. When Quasi-
Resonant control is used for the flyback converter, the typical waveforms are shown in Figure 4. The
voltage from the auxiliary winding provides information about demagnetization of the power transformer
and the output voltage.
As shown in Figure 4, after switch-on of the power switch the voltage across the shunt resistor RCS
shows a spike caused by the discharging of the drain-source capacitor. After the spike, the voltage VCS
shows information about the real current through the main inductance of the transformer Lp. Once the
measured current signal VCS exceeds the maximum value determined by the feedback voltage VFB, the
power switch is turned off. During this on-time, a negative voltage proportional to the input bus voltage is
generated across the auxiliary winding.
RSTARTUP Wp DO1 Lf1

Cbus Snubber CO1 Cf1 VO1
Ws1
85 ~ 300 VAC RVCC DVCC
CVCC
DO2 Lf2
CO2 Cf2 VO2
DZC RZC Wa Ws2
Dr1~Dr4
CZC
VCC ZCD
RI1
D
Power Management Power CPS
VIN
MOSFET
PWM controller RZCD GATE

RI2
Current Mode Control Rb1 Rb2 Rovs1 # Rovs3
Cycle-by-Cycle Gate SOURCE
GND current limitation Driver
Digital Control
CS Rc1
Active Burst Mode FB
# RSel
Zero Crossing
# Optional ICE5QSAG RCS Cc1 Cc2
Detection Optocoupler
RSel (Burst mode level 2) Controller TL431
Rovs3 (V02 feedback) Protections Rovs2
Figure 2 Typical application of controller
Figure 3 Typical application of CoolSETTM

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The drain-source voltage of the power switch VDS will raise very fast after MOSFET is turned off. This is
caused by the energy stored in the leakage inductance of the transformer. A snubber circuit, RCD in
most cases, can be used to limit the maximum drain source voltage caused. After the oscillation 1, the
drain-source voltage goes to its steady value. Here, the voltage vR is the reflected value of the secondary
voltage at the primary side of the transformer and is calculated as:
( + ) (Eq 23)1
=

where, VR : reflected voltage
Vout : output voltage
VFOut: forward voltage of the secondary diode
NP : number of primary turns of the transformer
NS : number of secondary turns of the transformer
After the oscillation 1 is damped, the drain-source voltage of the power switch shows a constant value of
Vbus+VR until the transformer is fully demagnetized. This duration builds up the first portion of the off-time
toff1.
After the secondary side current falls to zero, the drains-source voltage of the power switch shows
another oscillation (oscillation 2 in Figure 4, this is also mentioned as the main oscillation in this
document). This oscillation happens in the circuit consisting of the equivalent main inductance of the
transformer Lp and the capacitor across the drain-source (or drain-ground) terminal CDS which includes
Co(er) of the MOSFET. The frequency of this oscillation is calculated as:
1 (Eq 109)
2 =
2
where, fOSC2 : oscillation 2 in Figure 4
LP : primary main inductance of the transformer
CDS : capacitance across drain to source/ground of the power switch
The amplitude of this oscillation begins with a value of vR and decreases exponentially with the elapsing
time, which is determined by the losses factor of the resonant circuit. The first minimum of the drain
voltage appears at the half of the oscillation period after the time t4 and can be approximated as:
_ = (Eq 110)
In the Quasi-Resonant control, the power switch is switched on at the minimum of the drain-source
voltage. From this kind of operation, the switching-on losses are minimized, and switching noise due to
dVDS/dt is reduced compared to a normal hard-switching flyback converter.

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1
Equation is used in Section 8 (5th Generation Quasi-Resonant FLYCAL design example)
Application Note 7 Revision 1.0
2017-03-10
vOUT ton toff1 toff2
vDS V
oscillation 1 vclmp oscillation 2
vbus
Vrefl
t
tdelay1
tdelay2
vZCD TOSC
v1
tLEB vFB
i SEC
t
t1 t2 t3 t4 t5 t6 t7
TOSC
Figure 4 Typical waveforms of fifth generation Quasi-Resonant flyback converter

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Functional description and component design
4 Functional description and component design

4.1 VCC pre-charging and typical VCC voltage during start up
When AC line input voltage is applied as shown in Figure 2 and Figure 3, a rectified voltage appears
across the capacitor Cbus. The pull up resistor RSTARTUP provides a current to charge the Ciss (input
capacitance) of power switch and gradually generate one voltage level. If the voltage over Ciss is high
enough, power switch on and VCC capacitor will be charged through primary inductance of transformer
LP, power switch and internal diode with two steps constant current source IVCC_ Charge11 and IVCC_ Charge31.
A very small constant current source (IVCC_Charge1) is charged to the VCC capacitor till VCC reach VCC_SCP to
protect the controller from VCC pin short to ground during the startup. After this, the second step
constant current source (IVCC_Charge3) is provided to charge the VCC capacitor further, until the VCC voltage
exceeds the turned-on threshold VVCC_ON. As shown in the time phase I in Figure 5, the VCC voltage
increase almost linearly with two steps.
Note: Recommended typical value for RSTARTUP is 50 M (20 M~100 M), RSTARTUP value is
directly proportional to tStartUp and inversely proportional to no load standby power
VVCC
VVCC_ON I II III
VVCC_OFF
tA tB
VVCC_SCP t
IVCC
IVCC_Normal
t
0
IVCC_Charge1
IVCC_Charge2/3
-IVCC t1 t2
Figure 5 VCC voltage and current at start up
The time taking for the VCC pre-charging can then be approximately calculated as:
_ (_ _ ) (Eq 56B)2
StartUp = A + B = +
_1 _3
where, VVCC_SCP : VCC short circuit protection voltage

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IVCC_Charge3 : VCC charge current 3
1
IVCC_ Charge1/2/3 is charging current from the controller to VCC capacitor during start up
2
2017-03-10
When the VCC voltage exceeds the VCC turned on threshold VVCC_ON at time t1, the IC begins to operate
with soft start. Due to power consumption of the IC and the fact that there is still no energy from the
auxiliary winding to charge the VCC capacitor before the output voltage is built up, the VCC voltage drops
(Phase II). Once the output voltage is high enough, the VCC capacitor receives the energy from the
auxiliary winding from the time t2 onward and delivering the IVCC_ Normal1 to the controller. The VCC then will
reach a constant value depending on output load.
4.1.1 VCC capacitor

Since there is a VCC under voltage protection, the capacitance of the VCC capacitor should be selected
to be high enough to ensure that enough energy is stored in the VCC capacitor so that the VCC voltage
will never touch the VCC under voltage protection threshold VVCC_OFF before the output voltage is built up.
Therefore, the minimum capacitance should fulfil the following requirement:
_3 (Eq 56A)2
>
_ _
where, IVCC_Charge3 : VCC charge current 3
tss : Soft start time
4.2 Soft-start
After the supply voltage of IC is higher than 16 V, which corresponding to t1 of Figure 5, IC will start
switch with a soft-start. The soft-start function is built inside the IC in a digital manner. During soft-start,
the peak current of the power switch is controlled by an internal voltage reference instead of the voltage
on FB pin. The maximum voltage on CS pin for peak current control is increased step by step as shown
in Figure 6. The maximum duration of soft start is 12 ms with 3 ms for each step. During soft-start, the
over load protection function is disabled.
Vcs (V)
VCS_Peak
0.75
0.60
0.45
0.30
ton 3 6 9 12 Time(ms)
Figure 6 Maximum current sense voltage during soft start
4.3 Normal operation

During normal operation, the IC consists of a digital signal processing circuit including an up/down
counter, a zero-crossing counter (ZC counter) and a comparator, and an analog circuit including a
1
IVCC_ Normal is supply current from VCC capacitor or auxiliary winding to the controller during normal operation
2
2017-03-10
current measurement unit and a comparator. The switch-on and -off time points are each determined by
the digital circuit and the analog circuit, respectively. As input information for the switch-on
determination, the zero-crossing input signal and the value of the up/down counter are needed, while the
feedback signal VFB and the current sensing signal VCS are necessary for the switch-off determination.
Details about the full operation of the controller in normal operation are illustrated in the following
paragraphs.
4.3.1 Digital Frequency Reduction

As mentioned above, the digital signal processing circuit consists of an up/down counter, a ZC counter
and a comparator. These three parts are the key to implement digital frequency reduction with
decreasing load. In addition, a ringing suppression time controller is implemented to avoid mis-triggering
by the high frequency oscillation, when the output voltage is very low under conditions such as soft start
period or output short circuit. Functionality of these parts is described as in the following.
4.3.1.1 Minimum ZC Count Determination

To reduce the switching frequency difference between low and high line, minimum ZC count
determination is implemented. Minimum ZC count is set to 1 if VIN less than VIN_REF which represents for
low line. For high line, minimum ZC count is set to 3 after VIN higher than VIN_REF. There is also a
hysteresis VIN_REF with certain blanking time tVIN_REF for stable AC line selection between low and high.
4.3.1.2 Up/down counter

The up/down counter stores the number of the zero crossing where the main power switch is switched
on after demagnetization of the transformer. This value is fixed according to the feedback voltage, VFB,
which contains information about the output power. Indeed, in a typical peak current mode control, a high
output power results in a high feedback voltage, and a low output power leads to a low regulation
voltage. Hence, according to VFB, the value in the up/down counter is changed to vary the power
MOSFET off-time according to the output power. In the following, the variation of the up/down counter
value according to the feedback voltage is explained.
The feedback voltage VFB is internally compared with three threshold voltages VFB_LHC, VFB_HLC and VFB_R
at each clock period of 48 ms. The up/down counter counts then upward, keep unchanged or count
downward, as shown in Table 1.
Table 1 Operation of up/down counter
VFB up/down counter action
Always lower than VFB_LHC Count upwards till n=8/101
Once higher than VF_LHC, but always lower than VFB,HLC Stop counting, no value changing
Once higher than VFB_HLC, but always lower than VFB_R Count downwards till n=1/32
Once higher than VFB_R Set up/down counter to n=1/32
The number of zero crossing is limited and therefore, the counter varies among 1 to 8 (for low line) 3 to
10 (for high line) and any attempt beyond this range is ignored. When VFB exceeds VFB_R voltage, the
up/down counter is reset to 1 (low line) and 3 (high line) in order to allow the system to react rapidly to a
sudden load increase. The up/down counter value is also reset to 1 (low line) and 3 (high line) at the
start-up time, to ensure an efficient maximum load start up. Figure 7 shows some examples on how
up/down counter is changed according to the feedback voltage over time.
The use of two different thresholds VFB_LHC and VFB_HLC to count upward or downward is to prevent
frequency jittering when the feedback voltage is close to the threshold point.
1
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clock T=48ms clock T=48ms
t t
VFB VFB
VFB_R1 VFB_R3
VFB_HLC VFB_HLC
VFB_LHC VFB_LHC
Up/down t Up/down t
n+1
n+2
n+3
n+3
n+3
n+2
n+1
n+1
n+2
n+3
n+3
n+3
n+2
n+1
counter 1 counter 3
n
n
n
Case 1 5 6 7 8 8 8 7 6 5 1 Case 1 6 7 8 9 9 9 8 7 6 3
Case 2 2 3 4 5 5 5 4 3 2 1 Case 2 4 5 6 7 7 7 6 5 4 3
Case 3 8 8 8 8 8 8 7 6 5 1 Case 3 10 10 10 10 10 10 9 8 7 3
low line High line

Figure 7 Up/down counter operation
4.3.1.3 Switch on determination

After the gate drive goes to low, it cannot be changed to high during ring suppression time.
After ring suppression time, the gate drive can be turned on when the ZC counter value is higher or
equal to up/down counter value.
However, it is also possible that the oscillation between primary inductor and drain-source capacitor
damps very fast and IC cannot detect enough zero crossings and ZC counter value will not be high
enough to turn on the gate drive. In this case, a maximum off time is implemented. After gate drive has
been remained off for the period of TOffMax, the gate drive will be turned on again regardless of the
counter values and VZCD. This function can effectively prevent the switching frequency from going lower
than 20 kHz. Otherwise it will cause audible noise during start up.
4.3.2 Switch off determination

In the converter system, the primary current is sensed by an external shunt resistor, which is connected
between source terminal of the internal low side MOSFET and the common ground. The sensed voltage
across the shunt resistor VCS is applied to an internal current measurement unit, and its output voltage V1
is compared with the regulation voltage VFB. Once the voltage V1 exceeds the voltage VFB, the output flip-
flop is reset. As a result, the main power switch is switched off. The relationship between the V1 and the
VCS is described by:
1 = + (Eq 111A)
where, V1 : output voltage of comparator

GPWM : PWM output gain
VCS : voltage across the current sense resistor
VPWM : Offset for Voltage Ramp
To avoid mis-triggering caused by the voltage spike across the shunt resistor at the turn on of the main
power switch, a leading edge blanking time, tLEB, is applied to the output of the comparator. In other
words, once the gate drive is turned on, the minimum on time of the gate drive is the leading edge
blanking time.
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In addition, there is a maximum on time, tOnMax, limitation implemented in the IC. Once the gate drive has
been in high state longer than the maximum ON time, it will be turned off to prevent the switching
frequency from going too low because of long on time.
4.4 Active Burst Mode with selectable power level

At light load condition, the IC enters Active Burst Mode operation to minimize the power consumption.
Details about Active Burst Mode operation are explained in the following paragraphs.
The burst mode entry level can be selected by changing the different resistor RSel at FB pin. There are 2
levels to be selected with different resistor which are targeted for lower range of active burst mode power
(Level 1) and higher range of active burst mode power (Level 2). The following table shows the control
logic for the entry and exit level with the FB voltage.
Table 2 Two levels entry and exit active burst mode power
Level RSel VFB VCS Entry level Exit level
VFB_EBLX VFB_LB
1 Open VFB > VREF_B VCS_BL1 = 0.31 V 0.90 V 2.75 V
2 580 k~670 k VFB < VREF_B VCS_BL2 = 0.35 V 1.05 V 2.75 V
During IC first startup, the RefGOOD signal is logic low when VCC < 4 V. The low RefGOOD signal will reset
the Burst Mode level Detection latch. When the Burst Mode Level Detection latch is low and IC is in OFF
state, the FB resistor is isolated from the FB pin and a current source Isel is turned on instead.
From VCC = 4 V to Vcc on threshold, the FB pin will start to charge to a voltage level associated with RSel
resistor. When VCC reaches Vcc on threshold, the FB voltage is sensed. The burst mode thresholds are
then chosen according to the FB voltage level. The Burst Mode Level Detection latch is then set to high.
Once the detection latch is set high, any change of the FB level will not change the threshold level.
When Vcc reaches VCC on threshold, a timer of 2 s is started. After the 2 s timer ends, the current
source is turned off while the FB resistor is connected to FB pin (see Figure 8).
Vdd
Isel
UVLO S2
S 2s
R delay
RFB
Refgood
S1
Burst mode detection FB
latch
Vcsth_burst Selection Compare VREF,B

RSel
VFB_burst Logic logic
Control unit
Figure 8 Burst mode detect and adjust
4.4.1 Entering Active Burst Mode Operation

For determination of entering Active Burst Mode operation, three conditions apply:
the feedback voltage is lower than the threshold of VFB_EBLX
the up/down counter is 8 for low line and 10 for high line and
a certain blanking time tFB_BEB (20 ms).
Once all of these conditions are fulfilled, the Active Burst Mode flip-flop is set and the IC enters Active
Burst Mode operation. This multi-condition determination for entering Active Burst Mode operation

2017-03-10
prevents mis-triggering of entering Active Burst Mode operation, so that the controller enters Active Burst
Mode operation only when the output power is really low during the preset blanking time.
4.4.2 During Active Burst Mode Operation

After entering the Active Burst Mode the feedback voltage rises as VOUT starts to decrease due to the
inactive PWM section. One comparator observes the feedback signal if the voltage level VFB_BOn is
exceeded. In that case the internal circuit is again activated by the internal bias to start with switching.
Turn-on of the power switch is triggered by ZC counter with a fixed value of 8 ZC for low line and 10 ZC
for high line. Turn-off is resulted if the voltage across the shunt resistor at CS pin hits the threshold
VCS_BL1/ VCS_BL2.
If the output load is still low, the feedback signal decreases as the PWM section is operating. When
feedback signal reaches the low threshold VFB_BOff , the internal bias is reset again and the PWM section
is disabled until next time regulation signal increases beyond the VFB_BOn threshold. In Active Burst Mode,
the feedback signal is changing like a saw tooth between VFB_BOff and VFB_BOn (see Figure 9).
4.4.3 Leaving Active Burst Mode Operation

The feedback voltage immediately increases if there is a high load jump. This is observed by a
comparator. As the current limit is 31% (Level 1) and 35% (Level 2) during Active Burst Mode, a certain
load is needed so that feedback voltage can exceed VFB_LB. After leaving active burst mode, maximum
current can now be provided to stabilize output voltage. In addition, the up/down counter will be set to 1
(low line) or 3 (high line) immediately after leaving Active Burst Mode. This is helpful to reduce the output
voltage undershoot.

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VFB Entering
Leaving Active
Active Burst
Burst Mode
Mode
VFB_LB
VFB_BOn
VFB_BOff
VF_EB
Time to 8th/10th ZC and t

VCS Blanking Window (tBEB)
1.0V Current limit level during

Active Burst Mode
VCS_B
VVCC t
VVCC_OFF
VO t
Max. Ripple < 1%
t
Figure 9 Signals in Active Burst Mode
4.5 Current sense

The PWM comparator inside the IC has two inputs: one from current sense pin and the other from
feedback voltage. Before being sent to the PWM comparator, there is an offset and operational gain on

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current sense voltage. In normal operation, the relationship between feedback voltage and maximum
current sense voltage is determined by equation 10.
= + (Eq 111B)
where, VFB : feedback voltage
VCS : voltage across the current sense resistor
GPWM : PWM output gain
VPWM : Offset for Voltage Ramp
The absolute maximum current sense voltage, VCS is 1 V. Therefore, the current sense resistor can be chosen
according to the maximum required peak current in the transformer as shown in equation 11.
_ (Eq 21)1
=

where, RSense : current sense resistor
VCS_N : peak current limitation in normal operation (1 V)
IPMax : peak current of primary inductance
In addition, a leading edge blanking (LEB) is already built inside the current sense pin. The typical value
of leading edge blanking time is 220 ns, which can be thought as a minimum on time.
Note: In case of higher switch-on noise at CS Pin, IC may switch off immediately after LEB time
especially at light load high line condition. To avoid this, noise filtering ceramic capacitor C112
(e.g., 100 pF~100 nF, see Figure 12) can be added.
4.6 Feedback
Inside the IC, the feedback (FB) pin is connected to the (VREF) 3.3 V voltage source through a pull-up
resistor RFB. Outside the IC, this pin is connected to the collector of opto-coupler. Normally, a ceramic
capacitor CFB, 1nF for example, can be put between this pin and ground for smoothing the signal.
Feedback voltage will be used for a few functions as following:
It determines the maximum current sense voltage, equivalent to the transformer peak current.
It determines the ZC counter value according to load condition
Regulation loop with single feedback calculation is explained in the section 8.13. For dual output system
with dual feedback control can be calculated as below.
Optocoupler VOut1 VOut2
I25=W 1 x I25A=W 2 x I26

I26 R25A
R22 R23 R25
R24 C25
C26
TL431
VREF_TL=2.5
V R26
I26= I25 + I25A
Figure 10 Regulation loop with dual feedback
_ (Eq 112)
26 =
26
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1 _ (Eq 112A)
25 =
1 26
_ (Eq 112B)
25 =
2 26
where, W 1 : weighted factor of VOut1 (important factor of VOut1)
W2 : weighted factor of VOut2 (important factor of VOut2),
{e.g., W 1 has a weight of 60% (0.6) and W 2 has a weight of 40% (0.4)}
4.7 Zero crossing detection

The circuit components connected to zero crossing (ZCD) pin include resistors RZC, RZCD and capacitor
CZC. The values of three components shall be chosen so that the three functions combined to this pin will
perform as designed.
At first, the ratio between RZC and RZCD is chosen first to set the trigger level of output overvoltage
protection. Assuming the protection level of output voltage is VOut_OVP, the turns of auxiliary winding is NA
and the turns of secondary output winding is NS, the ratio is calculated as:

< __ (Eq 113)
+ _
where, RZCD : internal resistor at ZCD pin

RZC : external resistor at ZCD pin
RZCD_OVP_Min : minimum voltage of output Over Voltage threshold
NS : number of secondary turns of the transformer
NA : number of auxiliary turns of the transformer
VOut_OVP : user defined output over voltage threshold
Secondly, as shown in Figure 4, there are two delay times for detection of the zero crossing and turn on
of the power switch. The delay time tdelay1 is the delay from the drain-source voltage cross the bus
voltage to the ZCD voltage follows below VZCD_CT_Typ (100 mV). This delay time can be adjusted through
changing CZC. The second one, tdelay2, is the delay time from ZC voltage follows below 100 mV to the
MOSFET is turned on. This second delay time is determined by IC internal circuit and cannot be
changed. Therefore, the capacitance CZC is chosen to adjust the delay time tdelay1 and power switch is
turned on at the valley point of drain-source voltage. This is normally done through experiment.
In addition, as shown in Figure 4, an overshoot is possible on ZCD voltages when power switch is turned
off. This is because of the oscillation 1 on drain voltage, shown in Figure 4 may be coupled to the
auxiliary winding. Therefore, the capacitance CZC and ratio can be adjusted to obtain the tradeoff
between the output over voltage protection accuracy and the valley switching performance.
If, however, the amplitude of the ring at the ZCD pin is too small and the zero crossing cannot be
detected, it is advised to increase the drian_source capacitor, CDS of the power switch. But this capacitor
would incur switching loss, the value is suggested to be as small as possible; best to be <100 pF.
Furthermore, to avoid mis-triggering of ZCD detection just after power switch is turned off, a ring
suppression time is provided. The ring suppression time is 2.5 s typically if VZCD is higher than 0.45 V
and it is 25 s typically if VZCD is lower than 0.45 V. During the ring suppression time, IC cannot be
turned on again. Therefore, the ring suppression time can also be thought as a minimum off time.
4.8 Gate drive (ICE5QSAG only)

Inside Gate pin, a totem-drive circuit is integrated. The gate drive voltage is 10 V, which is enough for
most of the available MOSFET. In case of a 1nF load capacitance, the typical values of rise time and fall
time are117 ns and 27 ns respectively. In practice, a gate resistor can be used to adjust the turn-on
speed of the MOSFET. In addition, to accelerate the turn off speed, the gate resistor can be anti-
2017-03-10
paralleled with an ultrafast diode like 1N4148. To avoid the oscillation during turn-off of the MOSFET, it
is suggested that the loop area of the driver, through gate resistor and MOSFET gate, source and back
to IC ground should be as small as possible.
Note: Gate to Source discharge resistor of the power switch Q1 (see Figure 2) is not allowed to
add in ICE5QSAG as GATE pin is connected to the ZCD pin internally via RZCD. (with Gate to
Source discharge resistor, IC cannot start up at all due to due to Q1 GATE is shorted to SOURCE
and VGS (Gate threshold voltage of Q1)cannot rise up during first start up.
4.9 Line Over Voltage, brownout and Line selection

The input line over voltage and brownout protections are detected by sensing the voltage level at VIN pin
through the resistors divider from the bulk capacitor. Once the voltage level at VIN pin hits above 2.9V,
the IC stops switching and enters into line OVP mode. When the VIN pin voltage lower than 2.9 V and
the Vcc hits 16V, the line OVP mode is released.
If the VIN pin voltage is lower than 0.4 V, the IC stop switching and enters into brownout mode and it
only releases brownout mode when VIN pin voltage higher than 0.66 V. Note that there is no power
switch (see Figure 2/Figure 3) switching but it always detect VIN level in every restart cycle during line
OVP or brownout mode. The input line sensing resistors (see Figure 2/Figure 3) RI1 and RI2 can be
calculated as below.
Choose RI1=9 M,
Case 1: Line OVP is the first priority,

1 _ (Eq 105A) 1
2 =
(__ 2) _
where, RI1 : high side line input sensing resistor (Typ. 9 M)
RI2 : low side line input sensing resistor
VVIN_LOVP : line over voltage threshold (Typ. 2.9 V)
VLINE_OVP_AC : user defined line over voltage (VAC) for the system
1 + 2
( _ 2 ) +
_ = (Eq 106)1
2
where, VVIN_BI : brownin threshold voltage (Typ. 0.66 V)
VDC_Ripple : bus capacitor DC ripple voltage which depends on AC line frequency and load
(0~30 V)
VBrownIn_AC : brownin voltage for the system (VAC)
+ 2 (Eq 107) 2
( _ 1 ) + _
2
_ =
2
where, VVIN_BO : brownout threshold voltage (Typ. 0.4 V)
VBrownOut_AC : brownout voltage for the system (VAC)
+ (Eq 108)1
( _ 1 2 ) + _
2
_ =
2
1
2
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where, VVIN_REF : VIN voltage threshold for line selection (Typ. 1.52 V)
VBrownOut_AC : brownout voltage for the system (VAC)
Case 2: Brownout is the first priority,

_ 1 (Eq 105B) 1
2 =
(_ 2) _
where, VVIN_BI : brownin threshold voltage (Typ. 0.66 V)
VLineBI_AC : user defined brownin voltage (VAC) for the system
+ (Eq 107) 1
( _ 1 2 ) + _
2
_ =
2
1 _ (Eq 114)
2 + _
_ =
2
where, VVIN_LOVP : line over voltage threshold (Typ. 2.9 V)
VLineOVP_AC : line over voltage (VAC) for the system
4.10 Protection features

Protection is one of the major factors to determine whether the system is safe and robust. Therefore
sufficient protection is necessary. ICE5QSAG and ICE5QRxxxxAx provide a comprehensive protection
to ensure the system is operating safely. The protections include Line Over Voltage, Brownout, VCC
Over Voltage and Under Voltage, Over Load, Output Over Voltage, Over Temperature (Controller
Junction), CS Short to GND and VCC Short to GND. When those faults are found, the system will go into
the protection mode. It is then until the fault is removed, the system resumes to normal operation. A list
of protections and the failure conditions are shown in the below table.
Table 3 Protection function of ICE5QSAG and ICE5QRxxxxAx
Protection Function Failure Condition Protection Mode
Line Over Voltage VVIN > 2.9 V Non switch Auto
Restart
Brownout VVIN < 0.4 V Non switch Auto
Restart
VCC Over Voltage VVCC > 25.5 V Odd skip Auto Restart
VCC Under Voltage VVCC < 10 V Auto Restart
Over Load VFB > 2.75 V & last for 30 ms Odd skip Auto Restart
Output Over Voltage VZCD > 2 V & last for 10 consecutive Odd skip Auto Restart
pulses
Over Temperature (Junction TJ > 140C with 40C hysteresis to Non switch Auto
temperature of controller chip only ) reset Restart
CS Short to Gnd VCS < 0.1 V, last for 5 s and 3 Odd skip Auto Restart
consecutive pulses
VCC Short to Gnd VVCC< 1.1 V, IVCC_Charge10.2 A Cannot start up
(VVCC=0 V, RStartUp=50 M and
VDRAIN=90 V)

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4.11 Others
For quasi-resonant flyback converter, it is possible that the operation frequency goes too low, which
normally resulted in audible noise. To prevent it in the IC, a maximum ON time and OFF time are
provided.
The maximum ON time is 35 s typically. If the gate is maintained ON for 35 s, IC will turn off the gate
regardless of the current sense voltage.
When the power switch is OFF and IC cannot detect enough number of ZC to turn on, IC will wait till the
maximum off time, 42.5 s typically, is reached, then only turn on the power switch. Please note that
even a non-zero ZCD pin voltage cannot prevent IC from turning on the power switch. Therefore, during
soft-start, a CCM operation of the converter is expected.
For the transformer design, it is recommend to design minimum switching frequency (at minimum line
with maximum load) should be greater than or equal to 40 kHz. The maximum switching frequency
should not be higher than 200 kHz in any line and load condition due to Leading Edge Blanking time and
minimum ringing suppression time.

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Typical application circuit
5 Typical application circuit

50W Dual output demo board with ICE5QSAG and 16 W demo board with ICE5QR4780AZ are shown
below.
Figure 11 Schematic of DEMO_5QSAG_50W1

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Typical application circuit
Figure 12 Schematic of DEMO_5QR4780AZ_16W1

2017-03-10
PCB layout recommendation
6 PCB layout recommendation

In power supply system, PCB layout is a key point for a successful design. Following are some
suggestions for this (see Figure 11 and Figure 12).
1. Minimize the loop with pulse share current or voltage; examples are the loop formed by the bus
voltage source, primary winding, main power switch (Q11 (see Figure 11) in controller and
CoolSET power switch CoolMOS is inside IC) and current sensing resistor or the loop
consisting of secondary winding, output diode and output capacitor, or the loop of VCC power
supply.
2. Star ground at bulk capacitor C13: all primary grounds should be connected to the ground of bulk
capacitor C13 separately in one point. It can reduce the switching noise going into the sensitive pins
of CoolSET device effectively. The primary star ground can be split into four groups as follows,
i. Combine Signal (all small signal grounds connecting to the CoolSET GND pin such as
filter capacitor ground C17, C18, C19, C111, C112 and opto-coupler ground) and Power
ground (Current Sense resistor R14 and R14A).
ii. VCC ground includes the VCC capacitor ground C16 and the auxiliary winding ground, pin
2 of the power transformer.
iii. EMI return ground includes Y capacitor C12.
iv. DC ground from bridge rectifier, BR1
3. Filter capacitor close to the controller ground: Filter capacitors, C17, C18, C19, C111 and C112
should be placed as close to the controller ground and the controller pin as possible so as to reduce
the switching noise coupled into the controller.
4. High voltage traces clearance: High voltage traces should keep enough spacing to the nearby
traces. Otherwise, arcing would incur.
i. 400 V traces (positive rail of bulk capacitor C13) to nearby trace: > 2.0 mm
ii. 700/800 V traces {drain pin of power switch (Q11 (see Figure 11) in controller and drain
pin of CoolSET IC11 (see Figure 12)} to nearby trace: > 3 mm
5. Recommended minimum 232mm2 copper area at drain pin to add on PCB for better thermal
performance for CoolSET.

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Output Power of 5th generation Quasi-Resonant ICs
7 Output Power of 5th generation Quasi-Resonant ICs

Table 4 Output Power of 5th generation Quasi-Resonant Controller
1 1
Type Package Marking 220VAC 20% 85-300 VAC
ICE5QSAG PG-DSO-8 5QSAG 109 W 60 W
Table 5 Output Power of 5th generation Quasi-Resonant CoolSET

2 3 3
Type Package Marking VDS RDSon 220VAC 20% 85-300 VAC
ICE5QR4770AZ PG-DIP-7 5QR4770AZ 700 V 4.73 27 W 15 W
ICE5QR4770AG PG-DSO-12 5QR4770AG 700 V 4.73 27 W 15 W
The calculated output power curves giving the typical output power versus ambient temperature are
shown below. The curves are derived based on a typical discontinuous mode flyback in an open frame
design at Ta=50C, TJ=125C (integrated high voltage MOSFET), using minimum drain pin copper area
in a 2 oz copper single sided PCB and steady state operation only (no design margins for abnormal
operation modes are included). The output power figure is for selection purpose only. The actual power
can vary depending on particular designs.
Figure 13 Output power curve of ICE5QR4770AZ
1
Calculated maximum output power rating in an open frame design at Ta=50C, TJ=125C. The output power figure is for
reference purpose only. The actual power can vary depending on particular designs. Please contact to a technical expert from
Infineon for more information.
2
Typ. at TJ =25C (inclusive of low side MOSFET)
3
Calculated maximum output power rating in an open frame design at Ta=50C, TJ=125C (integrated high voltage MOSFET)
and using minimum drain pin copper area in a 2 oz copper single sided PCB. The output power figure is for selection purpose
only. The actual power can vary depending on particular designs. Please contact to a technical expert from Infineon for more
information.
2017-03-10

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Figure 18 Output power curve of ICE5QR4770AG

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5th Generation Quasi-Resonant FLYCAL design example
8 5th Generation Quasi-Resonant FLYCAL design example

16 W 12 V Quasi-Resonant flyback converter with ICE5QR4780AZ design example is as shown below.
Procedure Example
Define Input Parameters:-
Minimum AC input voltage: VAC Min 85 V
Maximum AC input voltage: VAC Max 320 V
Line frequency: fAC 60 Hz
Bulk capacitor(C13) DC ripple voltage: VDC Ripple 24.5 V
Output voltage: VOut 12 V
Forward voltage of output diode: VF Out 0.3 V
Output ripple voltage: VOut Ripple 0.24 V
Maximum output power: POut Max 16 W
Nominal output power: POut Nom 16 W
Minimum output power: POut Min 3.2 W
Efficiency: 85 %
Optocoupler gain: Gc(200%) 2
Reflection voltage: VR 90 V
VCC voltage: VVcc 14 V
Forward voltage of Vcc diode(D12): VF Vcc 0.6 V
5th Generation QR CoolSET: CoolSET
ICE5QR4780Z
Switching Frequency at VAC Min & POut
fs 55 kHz
Max:
Breakdown Voltage: VDS Max 600 V
Drain to source capacitance of
MOSFET (including Co(er) of MOSFET): CDS 7 pF
Effective output capacitance of
CO(er) 3 pF
MOSFET:
Startup resistor
RStartUp 50 M
RStartUp(R18+R18A+R18B):
Maximum ambient temperature: Ta 50 C
8.1 Input Diode Bridge (BR1):

There is no special requirement imposed on the input
rectifier and storage capacitor in the Flyback
converter. The components will be chosen to meet
the power rating and hold-up requirements.
Max. Input Power:
POutMax 16W
PInMax (Eq 1) PInMax 18.82W
0.85
Power Factor cos 0.6
Input RMS Current:

2017-03-10
PInMax 18.82W
I ACRMS (Eq 2) I ACRMS 0.369 A
VACMin cos 85V 0.6
Max. DC Input Voltage:
VDC max PK VACMax 2 (Eq 3) VDCMaxPk 320V 2 452.55V
8.2 Input Capacitor (C13):

Min. Peak Input Voltage at no load condition:
VDCMinPk VACMin 2 (Eq 4) VDCMinPk 85V 2 120.2V
VDCMin VDCMinPk VDCRipple (Eq 5) VDCMin 120.2V 24.5V 95.69V
Discharging time at each half-line cycle:
1 VDCMin 1 95.69V
sin sin
TD
1
1
VDCMinPk
(Eq 6) TD
1
1 120.2V 6.61ms
4 f AC 90 4 60 Hz 90

Required Energy at discharging time of Input
Capacitor:
WIN PINMax TD (Eq 7) WIN 18.82W 6.61ms 0.12W s
Input Capacitor (cal.):
2 WIN 2 0.12W s
CIN (Eq 8) CIN 47.04F
V DCMinPk V DCMin
2 2
120.2V 2 95.69V 2
Alternatively, a rule of thumb of choosing Input
Capacitor may be applied:
Input Voltage Factor
115V 2F/W
230V 1F/W
85V265V 23F/W
CIN PINMax factor (Eq 9) CIN 18.82 2.5 47.05F
Select an Input Capacitor from the Epcos Databook of

Aluminum Electrolytic Capacitors
The following types are preferred:
For 85C Applications:
Series B43303 2000hrs life time
B43501 10000hrs life time
For 105C Applications:
Series B43504 2000hrs life time
B43505 5000hrs life time
Choose the Rated Voltage greater or equal to the

Since VDCMaxPk = 452.55V, choose 500V
calculated VDCMaxPk
Choose the Capacitance greater or equal to the
calculated CIN from Eq8 Since CIN= 47F, choose 47F

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Input Capacitor(C13): CIN 47 F

Recalculation after Input Capacitor chosen:
2 WIN
VDCMin VDCMinPk
2
(Eq 10) VDCMin 120.22 2 0.12 95.69V
C IN 47
Note that special requirements for hold up time,
including cycle skip/dropout, or other factors
which affect the resulting minimum DC input
voltage and capacitor time should be considered
at this point as well.
8.3 Transformer Design (TR1):

Max. Duty Cycle:
VR 90
DMax (Eq 11) DMax 0.48
VR VDCMin 90 95.69
Discontinuous Conduction Mode (DCM)

VDS
VDS_Maximum
VClamp
VDS_Norminl
VR
VDC
0 ton toff t
B(flux density)
0 t
IP
I IP_Max
IAV
0 t
IS
0 t
Figure 21 Typical waveforms of DCM operation

2017-03-10
1
1 =
= 2 1 95.69 2
[
1
2 ( +1)+( )] (Eq 12) [
95.69 2
55 18.82 (
90
+ 1) + ( 55 7)]

= 1
18.82
I AV
PInMax I AV 0.41A
VDCMin DMax
(Eq 13) 95.69 0.48
VDCMin DMax 95.69 0.48

I I 0.82 A
LP f s
(Eq 14) 1103 55 103
Maximum Current of Primary

Inductance:
I 0.84
I PMax I AV (Eq 15) I PMax 0.41 0.82 A
2 2
IValley I PMax I (Eq 16) IValley 0.82 0.82 0 A
RMS Current of Primary Inductance :
0.82 2 0.48
I 2 D max (Eq 17) I PRMS [3 (0.41) 2 ( ) ] 0.33 A
I PRMS [3 ( I AV ) 2 ( ) ] 2 3
2 3
Select Core: E 20/10/6
Material = N87
Select Core Type & data from Epcos "Ferrite
BS = 390mT @100C
Magnetic Design Tool" or "Datasheet".
Ae = 32mm2
Fix Max. Flux Density:
BW = 11mm
Typically, BMax0.2T0.4T for Ferrite Cross
AN = 34mm2
depending on Core Material.
lN = 41.2mm
We choose 300mT for Material N87.
Maximum Flux Density BMax 300 mT

Number of Primary Inductance (cal.):
I PMax L p 0.82 110 3
NP (Eq 18) NP 86.57Turns
BMax Ae 0.3 32 10 6
Number of Primary Turns: NP 88 Turns
Number of Secondary Turns (cal.):
N P VOUT VFDIODE 88 12 0.3
NS (Eq 19) N S _ cal 12.03Turns
VR 90
Number of Secondary Turns: NS 12 Turns
Number of Vcc Turns (cal.):
N P VVcc VFVcc 66 14 0.6
NVcc (Eq 20) N Aux _ cal 14.24Turns
VR 90
Number of Vcc Turns: NVcc 14 Turns

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8.4 Sense Resistor (R14):

The Sense Resistance can be used to individually
define the max. peak current and thus the max. power
transmitted.
Caution:
When calculating the max. peak current, short term
peaks in output power must also be taken into
consideration.
Sense Resistor(R14):
Vcsth 1
RSense (Eq 21) RSense 1.21
I PMax 0.83
Power Rating of Sense Resistor:
PSR I PRMS RSense PSR 0.33 1.21 0.13W
2 2
(Eq 22)
Verification of reflection voltage, duty cycle and
maximum flux density
Reflected Voltage:
VOUT VFOut N P 12 0.3 88 90.20V
VR (Eq 23) VR
NS 12
Max. Turn-On Duty Cycle:
LP ( I PMax IValley ) f S 1103 (0.82 A 0 A) 55 103
Dmax (Eq 24) Dmax 0.48
VDC min 95.69
Max. Turn-Off Duty Cycle:
LP ( I PMax I Valley ) f S 1103 (0.82 A 0 A) 55 103
D' max (Eq 25) D'max 0.51
VR 90.2
Max. Flux Density:
LP I PMax 1 103 0.82
Bmax (Eq 26) Bmax 295mT
N P Ae 88 32 106
Maximum Secondary Current and load factor:
PO ( n ) 16
K L(n) (Eq 27) K L (1) 1
PO 16
NP 88
I SMax K L ( n ) I PMax (Eq 28) I SMax 1 0.82 6.04 A
NS 12
Secondary RMS Current:
1 DMax VR 1 0.48 90.2
I SRMS I PRMS (Eq 29) I SRMS 0.33 2.49 A
DMax VOut VFOut 0.48 12 0.3

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8.5 Winding Design:

Safety Standard Margin:
M=4mm for European Safety Standard
M=3.2mm for UL1950
M=0 for triple insulated wire
Safety Standard Margin: M 0 mm

Copper Space Factor: fCu 0.3 (Range 0.2 0.4)
Effective Bobbin Width:
BWE BW 2 M (Eq 30) BWe 11 0 11mm
Effective Winding Cross Section:
AN BWe 34 11
ANe (Eq 31) ANe 34mm2
BW 11
The Winding Cross Section AN has to be subdivided
according to the number of windings:
Primary Winding 0.5
Secondary Winding 0.45
Auxiliary Winding 0.05
Wire Copper Area for Primary Winding:
0.5 f Cu ANe 0.5 0.3 34
AP (Eq 32) AP 0.06mm2
NP 88
Wire Copper Area for Secondary Winding:
0.45 f Cu ANe 0.45 0.3 34mm2
AS (Eq 33) AS 0.38mm2
NS 12
Wire Copper Area for Auxiliary Winding:
0.05 f Cu ANe 0.05 0.3 34mm2
AVcc (Eq 34) AVcc 0.03mm2
N Aux 14
Wire Size in AWG unit can be calculated:
AWG 9.97 1.8277 2 logd (Eq 35)
Wire Diameter from Copper Area:
A
d 2 (Eq 36)

Wire Diameter from AWG unit:
1.8277 AWG

29.97 (Eq 37)
d 10 2
Wire Size in AWG unit using combination of Eq. 35

and Eq. 36:
AP 0.06mm2
AWGPc 9.97 1.8277 2 log 2

AWG Pc 9.97 1.8277 2 log 2

AWGPc = 30

2017-03-10
AS 0.38mm2
AWGSc 9.97 1.8277 2 log 2

AWGSc 9.97 1.8277 2 log 2

AWGSc = 21
AAux 0.03mm2
AWGVccc 9.97 1.8277 2 log 2

AWGVccc 9.97 1.8277 2 log 2

AWGVccc = 32
It is a good practice to use smaller wires in parallel
instead of using one big wire. However, the following
conditions should be satisfied for choosing Wire Size
and Number of Parallel Wires:
- EffCuAreaX (Eq 40) AX (Eq 34/35)
- SX (Eq 41) 8 A/mm2
- NPX 10
- 0.18 mm Wire Diameter 0.6 mm
Note: X = P/Primary or S/Secondary Winding
Wire Size in AWG unit for Primary: AWGP 30
Num. of Parallel Wires for Primary: NPP 1
Insulation Thickness of Primary Wire: INSP 0.02 mm
Wire Size in AWG unit for Secondary: AWGS 21
Num. of Parallel Wires for Secondary: NPS 1
Insulation Thickness of Secondary Wire: INSS 0.02 mm
Typically, the Auxiliary Winding consists of only one
wire and its size is insignificant due to low current.
Recalculate Wire Diameter using Eq. 37:
1.8277 AWGP 1.8277 30

29.97 29.97
d P 10 2
d P 10 2
0.25mm
1.8277 AWGS 1.8277 21

29.97
d S 10 2 29.97
d S 10 2
0.72mm
Eff. Copper Area:
2
d
EffCuArea NP (Eq 38)
2
2
2 0.25
d EffCuArea P 88 0.05mm
2
EffCuArea P P NPP 2
2
2 2
d 0.72mm
EffCuArea S S NPS EffCuArea S 12 0.41mm
2
2 2
Current Density:
I RMS
S (Eq 39)
EffCuArea
I PRMS 0.33 A
SP SP 6.35
EffCuArea P 0.05 mm2

2017-03-10
I SRMS 2.49 A
SS SS 6.01
EffCuArea S 0.41 mm2
Wire Outer Diameter including Insulation:
Od d 2 INS (Eq 40)
OdP d P 2 INS P OdP 0.25 2 0.02 0.29mm
Od S d S 2 INS S OdS 0.72 2 0.02 0.76mm
Max. Number of Turns per Layer:
BWe
NL (Eq 41)
Od NP
BWe 11
NLP NLP 37Turns / Layer
Od P NPP 0.29 1
BWe 11
NLS NLS 14Turns / Layer
OdS NPS 0.76 1
Min. Number of Layers:
N
Ln (Eq 42)
NL
N 88
LnP P LnP 3Layers
NLP 37
N 12
LnS S LnS 1Layers
NLS 14
8.6 Reverse Voltage of Diode

(D21, D12):
The output rectifier diodes in Flyback converters are
subjected to large Peak and RMS current stress. The
Values depend on the load and operating mode. The
Voltage Requirements depend on the output voltage
and transformer winding ratio.
Max. Reverse Voltage for output diode:
N 12
VRDiode VOUT VDCMaxPk S (Eq 43A) VRDiode 12 452.54 73.71V
NP 88
Max. Reverse Voltage for Vcc diode:
N 14
VRDiode VVcc VDCMaxPk Vcc (Eq 43B) VRDiode 14 452.54 86.00V
NP 88
8.7 Clamping Network (R11, C15,

and D11):
Clamping Voltage:
VClamp VDSMax V DCMaxPkVR (Eq 44) VClamp 600 452.54 90.2 57.25V

2017-03-10
For calculating the clamping network, it is necessary

to know the leakage inductance. The most common
approach is to have the Leakage Inductance value
given in a percentage of the Primary Inductance.
If it is known that the transformer construction is very
consistent, measuring the Primary Leakage
Inductance by shorting the Secondary Windings will
give an exact number (assuming the availability of a
good LCR analyser)
Leakage Inductance in % of LP: LLK% 1.06%
Leakage Inductance:
LLK LLK % LP (Eq 45) LLK 1.06% 1103 10.7H
Clamping Capacitor :
CClamp
2
I PMax LLK
CClamp
0.82 10.7 106
2
0.9nF
VR VClamp VClamp (Eq 46)
90.2 57.25 57.25
Clamping Capacitor: CClamp 1 nF
Clamping Resistor:
V 57.25 90.2 90.2

Clamp VR VR
2 2
2 2
RClamp 68.2k
RClamp (Eq 47) 0.5 10.7 10 6 1.51A 55 10 3
2
0.5 LLK I 2
PMax fS
Clamping Resistor: RClamp 68 k
8.8 Output Capacitors (C22, C23,

C24):
Output Capacitors are highly stressed in Flyback
converters. Normally, capacitors are chosen based on
3 major parameters: Capacitance, Low ESR and
Ripple Current Rating.
To calculate Output Capacitors, the Max. Voltage
Overshoot in case of switching off at Max. load
condition must be set.
Max. Voltage Overshoot: VOUT 0.5 V
After switching off the load, the control loop needs
about 1020 internal clock periods to reduce the
duty cycle.
Number of Clock Periods: nCP 20
Max. Output Current:
POutMax 16
I OutMax (Eq 48) I OutMax 1.33 A
VOut 12
Ripple Current:
I Ripple I SRMS 2 I OutMax 2 (Eq 49) I Ripple 2.492 1.332 2.1A

Output Capacitance (cal.):

2017-03-10
I OUT max nCP 1.33 20

COut (Eq 50) COut 970F
VOUT f 0.5 55 103
The output capacitor can be selected as the following
conditions can be summarized as the following: We choose Epcos B41889(Very Low Impedance)
- Rated Voltage of Cap. (1.45VOut) 1000F 16V (RESR=0.028, IacR=2.8A @ 100kHz
- (IacRnc) close to IRipple 85C)
- (COUTnc) close to COUT_cal
- nc 5
Output Capacitor: COut 1000 F
Number of Parallel Capacitors: nc 1
8.9 Output Filter (L21, C24):

The Output Filter consists of one Capacitor and one
Inductor in a L-C filter topology.
Zero Frequency of Output Capacitors and associated
ESR:
1 1
f ZCOut (Eq 51) f ZCOut 5.68kHz
2 RESR COut 2 0.028 1000 106
This equation is based on the assumption that all
output capacitors have the same capacitance and
ESR.
Ripple Voltage at 1st Stage:
I SMax RESR 6.04 0.028
VRipple1 (Eq 52) VRipple1 0.17V
nc 1
The Inductance is required to compensate the Zero
Frequency caused by output capacitors:
L-C Filter Inductance: LOUT 2.2 H
L-C Capacitor (cal.):
C LC
COut RESR 2
(Eq 53) CLC
1000 10 6
0.028
356F
2
LOut 2.2 106

L-C Capacitor: CLC 470 F
Frequency of L-C Filter:
1 1
f LC (Eq 54) f LC 4.95kHz
2 CLC LOUT 2 470 106 2.2 106
Ripple Voltage at 2nd Stage:
1 1
2 f CLC 2 55 103 470 106
VRipple2 VRipple1 (Eq 55) VRipple2 0.17 1.36mV
1
2 f LOUT
1
2 55 103 470 10 6

2 55 103 2.2 10 6
2 f CLC

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8.10 VCC Capacitors (C16, C17):

The VCC Capacitor needs to ensure the power
supply of the IC until the power can be provided by
the VCC Winding.
In addition, it is recommended to use a 100 nF
Ceramic Capacitor very close between pin 7 & 8 in
parallel to the VCC Capacitor. Alternatively, an HF-
type electrolytic with low ESR and ESL may be used.
VCC Capacitor:
IVCC_Charge3 from datasheet: IVCC_Charge3 3 mA
tSS from datasheet: tSS 12 ms
IVCC _ Charg e3 t SS 3 103 12 103
CVcc (Eq 56A) CVcc 6F
VVCC _ ON VVCC _ OFF 16 10
Vcc Capacitor: CVcc 10 F
Start Up time:
VVCC_SCP from datasheet: VVCC_SCP 1.1 V
_ (_ _ ) 1.1 10 106 (16 1.1) 10 106
StartUp = + (Eq 56B) StartUp = + = 108
_1 _3 0.2 103 3 103
8.11 Losses:
Diode Bride Forward Voltage: VF 1V
Input Diode Bridge Loss:
PDIN 2 I ACRMS VF (Eq 57) PDIN 2 0.36 1 0.74W
Copper Resistivity @ 100C: 100 0.0172 mm2/m
Copper Resistance:
l N N 100
RCu (Eq 58)
EffCuArea
l N P 100 mm2
RPCu N 41.2mm 88 0.0172
RPCu m 1205.44m
EffCuArea P
0.05mm2
l N S 100 mm2
RSCu N 41.2mm 12 0.0172
RSCu m 20.57m
EffCuArea S
0.41mm2
Copper Resistance Loss on Primary Side:
PPCu I PRMS RPCu PPCu 0.33 1205.44 130.26mW
2 2
(Eq 59)
Copper Resistance Loss on Secondary Side:

PSCu I SRMS RSCu PSCu 2.49 20.57 127.06mW
2 2
(Eq 60)
Total Copper Resistance Loss:
PCu PPCu PSCu (Eq 61) PCu 130.26 127.06 257.32mW

2017-03-10
Output Rectifier Diode Loss:

PDOut I SRMS VFOut (Eq 62) PDOut 2.49 0.6 0.75W
Clamping Network Loss:
VClamp VR 57.25 90.2
PClamper 12 LLK I PMax
2
fS (Eq 63) PClamper 12 10.7 106 0.82 55 103
2
0.51W
VClamp 57.25
Junction Temperature: Tj 125 C

On-Resistance at Junction Temperature:
T j 25C 12525
0.8
RDSon@T j RDSon@ 25C 1 (Eq 64) RDSon@T j 4.03 1 8.59
100 100
MOSFET Losses in VACmin scenario:
Switching Loss in VACmin scenario:

PSON1 12 Co(er ) CDS (VDCMin VR ) 2 f S (Eq 65) PSON1 12 3 4 1012 95.69 90.2 55 103 5.792W
2
Conduction Loss in VACmin scenario:

PD1 I PRMS RDSon@T j PD1 0.33 8.59 928.3mW
2 2
(Eq 66)
Total MOSFET Loss in VACmin scenario:

PMOSFET1 PSON1 PD1 (Eq 67) PMOSFET1 5.792W 928.3mW 928.3mW
MOSFET Losses in VACmax scenario:
Switching Loss in VACmax scenario:

PSON 2 12 Co(er ) CDS (VDCMaxPk VR ) 2 f S (Eq 68) PSON1 12 3 4 1012 424.26 90.2 72 103 32.86mW
2
Conduction Loss in VACmax scenario:

L I f 1 103 0.82 72 103
PD 2 13 R DSon@ T j I PMax P PMax S PD 2 13 8.59 0.82 255.15mW
2 2
(Eq 69)
V DCMaxPk 424.26
Total MOSFET Loss in VACmax scenario:

PMOSFET 2 PSON 2 PD 2 (Eq 70) PMOSFET 2 32.86mW 255.15mW 288mW
MOSFET Losses:
PMOSFET max PMOSFET1 , PMOSFET 2 (Eq 71) PMOSFET max928.3mW,288mW 928.3mW
8.12 Heat Dissipater:

All CoolSET in DSO/DIP package cannot use a
Heat Sink but the Copper Area is possible. However,
all CoolMOS can use a Heat Sink.
Thermal Resistance:
In case NO Heat Sink (for CoolSET)
Typical thermal Resistance [K/W]:
RthJA=96 K/W (DIP-7)
RthJA=110 K/W (DSO-12)
RthJA=185 K/W (DSO-8)
Rth RthJA (Eq 72) Rth 96K / W

2017-03-10
In case WITH Heat Sink (for controller)

Rth RthJC RthHT RthHS (Eq 73)
where RthJC : TR. Junction-Case From CoolMOS/Power Switch Datasheet
RthHT : TR. Case-Heat Sink Typ. 1K/W
RthHS : TR. Heat Sink-Ambient Depending on Heat Sink
Delta Temperature from MOSFET Losses:
T PMOSFET Rth (Eq 74) T 928.3mW 96K / W 89.1K
Max. Junction Temperature:
T j max Ta T (Eq 75) T j max 50C 89.1 139.1C
Max. Junction Temperature must not exceed the
limitation stated in the Datasheet, typically 150C.
Controller Loss:
PController VVcc IVCC _ Normal (Eq 76) PController 13.75 0.9 103 12.4mW
Total Loss:
PLosses PDIN PCu PDOut
(Eq 77) PLosses 0.74 0.25 0.75 0.51 0.9283 0.0124 3.2W
PClamp PMOSFET PController
Efficiency after Losses Consideration:

POutMax 16
L (Eq 78) L 83.35%
POutMax PLosses 16 3.2
Please note that the calculated efficiency above is
based on the worst case scenario where the highest
loss is present.

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8.13 Regulation Loop:
Reference: TL431
Optocoupler: SFH617-3
VOut
R22 R23 R25
VREF
R24 C25
RFB
FB C26
VFB
TL431 R26
Figure 22 Regulation loop
TL431 Reference Voltage: VREF_TL 2.5 V

Min. Current for TL431 Diode: IKAmin 1 mA
Max. Current of SFH617-3 Diode: IFmax 10 mA
Forward Voltage of Optocoupler Diode: VFOpto 1.25 V
Optocoupler gain GC(200%) 2
CoolSET Trimmed Reference Voltage: VREF 3.3 V
CoolSET : VFBmax 2.75 V
RFB (FB pull-up resistor): RFB 15 k
R26 Value of Voltage Divider: R26 10 k
Primary Side:
Max. Feedback Current:
VREF 3.3
I FB max (Eq 79) I FB max 0.22mA
RFB 15 103
Min. Feedback Current:
VREF VFB max 3.3 2.75
I FB min (Eq 80) I FB min 0.036mA
RFB 15 103
Secondary Side:
R25 Value of Voltage Divider:
V 12
R25 R26 Out 1 (Eq 81) R25 15 103 1 38k
V 2.5
REF _ TL
R26 Value of Voltage Divider: R25 38 k

2017-03-10
R22 Value to supply Opto. Diode:

VOUT VFOpto VREF _ TL 12 1.25 2.5
R22 (Eq 82) R22 825
I F max 10 103
R22 Value to supply Opto. Diode: R22 820
R23 Value to supply TL431 Diode:
I 0.036 103
VFOpto R 22 FB min 1.25 820

R 23 Gc (Eq 83)
R 23 2 1.26k
I KAmin 1 103
R4 Value to supply TL431 Diode: R23 1.2 k
Output Voltage from Regulation Loop:
R25 38 103
VOUT _ RL 1 VREF _ TL (Eq 84) VOUT _ RL 1 2.5V 12V
R26 10 10
3

Regulation Loop Elements:
VIN FPWR(p) FLC(p) Vout
KFB KVD
_
Fr(p)
+
Vref
Figure 23 Block diagram of regulation loop
Feedback Transfer Characteristic:

Gc RFB 2 15 103
K FB (Eq 85) K FB 36.59
R22 820
Gain of Feedback Transfer Characteristic:
GFB 20 logK FB (Eq 86) GFB 20 log 35.81 31.27dB
Voltage Divider Transfer Characteristic:

VREF _ TL R25 38 103
KVD (Eq 87) KVD 0.21
VOUT _ RL R25 R26 38 103 10 103
Gain of Voltage Divider Transfer Characteristic:
GVD 20 logKVD (Eq 88) GVD 20 log0.21 13.62dB
Zeroes and Poles of Transfer Characteristics:
Resistance at Max. Load Pole:
2
VOUT 122
RLH
_ RL
(Eq 89) RLH 9
POutMax 16
Resistance at Min. Load Pole:
2017-03-10
2
VOUT 122
RLL
_ RL
(Eq. 90) RLL 45
POutMin 3.2
Poles of Power stage at Max. Load Pole:
1 1
f OH f OH 35.37Hz
RLH nc COUT
(Eq 91)

9 1 1000 106
Poles of Power stage at Min. Load Pole:
1 1
f OL f OL 7.07Hz
RLL nc COUT
(Eq 92)

45 1 1000 106
In order to have sufficient phase margin at low load
condition, we choose the Zero Frequency of the
compensation network to be at the middle between
the min. and max. load poles of the power stage.
Zero Frequency of the Compensation Network:
f 7.07
0.5log OL 0.5log
(Eq 93)
f OM f OH 10 f OH
f OM 35.37 10 35.37
15.82Hz
With adjustment of the transfer characteristics of the

regulator, we want to reach equal gain within the
operating range and to compensate the pole fo of the
power stage FPWR()
Because of the compensation of the output
capacitor's zero (Eq 53), we neglect it as well as the
LC-Filter pole (Eq 56). Consequently, the transfer
characteristic of the power stage is reduced to a
single-pole response.
In order to calculate the gain of the open loop, we
have to choose the crossover frequency.
We calculate the gain of the Power stage with Max.
Output Power at the chosen crossover frequency.
Zero dB Crossover Frequency: fg 3 kHz
Transient Impedance Calculation:
Transient Impedance defines the direct relationship
between the level of the Peak Current and the
Feedback pin voltage. It is required for the calculation
of the power stage amplification.
Transient Impedance:
VFB R 1.21 V
Z PWM AV Sense (Eq 94) Z PWM 2 2.42
I PK Vcsth 1 A
Power stage at Crossover Frequency:

Lp f P
FPWR f g
RLH 3 3
1

1 f 1 9 1 10 55 10 0.85 1 0.0707
Z PWM 2 2 (Eq 95) F
PWR g 2.42 2 2
f 3 103
1 g
1

f 35.37
OH
Gain of Power stage at Crossover Frequency:

GPWR f g 20 log FPWR f g (Eq 96) GPWR 3kHz 20 log0.0707 23.01dB

2017-03-10
At the Crossover Frequency (fg), we calculate the

Open Loop Gain:
GOL Gs Gr 0 (Eq 97)
With the equations for the transfer characteristics, we
calculate the gain of the regulation loop at fg:
Gs GFB GPWR GVD (Eq 98) Gs 31.27 23.01 13.62 5.39dB
Separated components of the regulator:

Gr 0 Gs (Eq 99) Gr 0 5.39dB 5.39dB
R24 Value of Compensation Network:

R 25 R26
Gr 5.39
38 103 10 103
R24 10 20
(Eq 100) R24 10 20 14.68k
R25 R26 38 103 10 103
R24 Value of Compensation Network: R24 15 k
C26 Value of Compensation Network:
1 1
C 26 (Eq 101) C 26 3.53nF
2 R24 f g 2 15 103 3 103
Use table E12, find the closest higher value
C26 Value of Compensation Network: C26 3.3 nF
C25 Value of Compensation Network:
1
C 25 C 26 (Eq 102) C 25
1
3.3 109 667.52nF
2 R24 f OM 2 15 103 15.82
C25 Value of Compensation Network: C25 680 nF
8.14 Zero crossing and output

OVP:
RZC(R15) Value of zero crossing and output OVP:
User defined VOut_OVP Value: VOut_OVP 15.9 V
RZCD value from datasheet: RZCD 3 k
N VOut _ OVP VFOut 14 15.9 0.3
R15 RZCD VCC 1 (Eq 103) R15 3 103 1 26.84k

N S1 VZCD _ OVP _ Min 12 1.9

R15 Value of zero crossing and output
R15 27 k
OVP:
C19 Value of zero crossing and output OVP:
Measured fosc2 (see Figure 4): fosc2 800 kHz
Delay time of controller: tdelay 100 ns
1 27 103 3 103
C19 tan2 100 109 800 103
1
1 R15 RZCD 1 134 pF
C19 tan2 tdelay fosc2 (Eq 104) 4 27 103 3 103 2 800 103
4 R15 RZCD 2 fosc2
C19 Value of zero crossing and output

C19 120 pF
OVP:

2017-03-10
8.15 Line OVP, brownout and Line

selection:
The voltage divider resistors RI1 (R18+R18A+R18B) and
RI2 (R19) can be used to define the line OVP and
brownout of the system.
R19 Value for Line OVP and brownout:
User defined VLine_OVP_AC value: VLine_OVP_AC 320 V
VVIN_LOVP Value from datasheet: VVIN_LOVP 2.9 V
VVIN_LOVP Value from datasheet: VVIN_BO 0.4 V
VVIN_LOVP Value from datasheet: VVIN_BI 0.66 V
VVIN_REF Value from datasheet: VVIN_REF 1.52 V
Selected RI1 (R18+R18A+R18B) Value: RI1 9 M
18 _ 9 109 2.9
19 > (Eq 105A) R19 > = 58.04
(__ 2) _ (320 2) 2.9
RI2 (R19) Value for Line OVP and
R19 58.3 k
brownout:
VBrownIn_AC value with the selected R19:

1 + 2 9 109 + 58.3 103
( _ ) + (0.66 )
2 (Eq 106) 58.3 103
_ = _ = = 73
2 2
VBrownOut_AC value with the selected R19 and VDC Ripple

(for full load condition):
1 + 2 9 109 + 58.3 103
( _ ) + (0.4 ) + 24.5
2 (Eq 107) 58.3 103
_ = _ = = 61
2 2
VBrownOut_AC value with the selected R19 and negelect
VDC Ripple (for light load condition):
9 109 + 58.3 103
(0.4 )
58.3 103
_ = = 44
2
VLineSelection_AC value with the selected R19 and VDC

Ripple (for full load condition):
1 + 2 9 109 + 58.3 103

( _ ) + (1.52 ) + 24.5
2 (Eq 108) 58.3 103
_ = _ = = 184
2 2
VLineSelection_AC value with the selected R19 and

negelect VDC Ripple (for light load condition):
9 109 + 58.3 103
(1.52 )
58.3 103
_ = = 167
2

2017-03-10
References
9 References
[1] ICE5QSAG datasheet, Infineon Technologies AG
[2] ICE5QRxxxxAx datasheet, Infineon Technologies AG
[3] AN-201609_PL83_024-50W 12V 5V SMPS Demo Board with ICE5QSAG
[4] AN-201609_PL83_025-16W 12V 5V SMPS Demo Board with ICE5QR4780AZ
[5] FlyCal_Quasi-Resonant Q5 CoolSET_V1.0
Revision History
Major changes since the last revision
Page or Reference Description of change
-- First release.

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Trademarks of Infineon Technologies AG
AURIX, C166, CanPAK, CIPOS, CoolGaN, CoolMOS, CoolSET, CoolSiC, CORECONTROL, CROSSAVE, DAVE, DI-
POL, DrBlade, EasyPIM, EconoBRIDGE, EconoDUAL, EconoPACK, EconoPIM, EiceDRIVER, eupec, FCOS, HITFET,
HybridPACK, Infineon, ISOFACE, IsoPACK,
i-Wafer, MIPAQ, ModSTACK, my-d, NovalithIC, OmniTune, OPTIGA, OptiMOS, ORIGA, POWERCODE, PRIMARION,
PrimePACK, PrimeSTACK, PROFET, PRO-SIL, RASIC, REAL3, ReverSave, SatRIC, SIEGET, SIPMOS,
SmartLEWIS, SOLID FLASH, SPOC, TEMPFET, thinQ!, TRENCHSTOP, TriCore.
Trademarks updated August 2015
Other Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
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81726 Munich, Germany product. Before implementation of the product,
the recipient of this application note must verify WARNINGS
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5th Generation Quasi-Resonant Design

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4.4.3 Leaving Active Burst Mode Operation .............................................................................. 14

WEIKENG INTERNATIONAL CO.,LTD.

WEIKENG INTERNATIONAL CO.,LTD.

2.2 Pin layout

ZCD 4 5 GATE ZCD 4 5 DRAIN DRAIN 6 7 DRAIN

ICE5QSAG ICE5QRxxxxAZ ICE5QRxxxxAG

2.2.1 FB (Feedback & Burst entry/exit control)

WEIKENG INTERNATIONAL CO.,LTD.

2.2.2 VIN (Input Line OVP & Brownout)

2.2.3 CS (Current Sense)

2.2.4 ZCD (Zero Crossing Detection)

2.2.5 GATE (Gate Drive Output, Controller only)

2.2.6 SOURCE (Source, Controller only)

2.2.7 DRAIN (Drain, CoolSETTM only)

2.2.8 VCC (Positive Voltage Supply)

2.2.9 GND (Ground)

WEIKENG INTERNATIONAL CO.,LTD.

3 Overview of Quasi-Resonant flyback converter

RSTARTUP Wp DO1 Lf1

PWM controller RZCD GATE

Figure 2 Typical application of controller

Figure 3 Typical application of CoolSETTM

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where, VR : reflected voltage

Vout : output voltage

VFOut: forward voltage of the secondary diode

NP : number of primary turns of the transformer

NS : number of secondary turns of the transformer

where, fOSC2 : oscillation 2 in Figure 4

LP : primary main inductance of the transformer

CDS : capacitance across drain to source/ground of the power switch

WEIKENG INTERNATIONAL CO.,LTD.

vOUT ton toff1 toff2

Figure 4 Typical waveforms of fifth generation Quasi-Resonant flyback converter

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4 Functional description and component design

Figure 5 VCC voltage and current at start up

where, VVCC_SCP : VCC short circuit protection voltage

4.1.1 VCC capacitor

where, IVCC_Charge3 : VCC charge current 3

tss : Soft start time

Figure 6 Maximum current sense voltage during soft start

4.3 Normal operation

4.3.1 Digital Frequency Reduction

4.3.1.1 Minimum ZC Count Determination

4.3.1.2 Up/down counter

clock T=48ms clock T=48ms

low line High line

4.3.1.3 Switch on determination

4.3.2 Switch off determination

where, V1 : output voltage of comparator

4.4 Active Burst Mode with selectable power level

Vcsth_burst Selection Compare VREF,B

VFB_burst Logic logic

Figure 8 Burst mode detect and adjust

4.4.1 Entering Active Burst Mode Operation

Application Note 13 Revision 1.0

4.4.2 During Active Burst Mode Operation

4.4.3 Leaving Active Burst Mode Operation

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Time to 8th/10th ZC and t

1.0V Current limit level during