Professional Documents
Culture Documents
Package Types
MCP3423
CH1- 2 7 CH2+ CH1- 2 9 Adr0 CH1- 2 13 CH4+
VSS 3 8 SCL
MCP3424
VDD 3 6 VSS CH2+ 3 12 CH3-
SDA 4 5 SCL CH2+ 4 7 SDA
CH2- 4 11 CH3+
CH2- 5 6 VDD
VSS 5 10 Adr1
VDD 6 9 Adr0
MCP3422 MCP3423
2x3 DFN* SDA 7 8 SCL
3x3 DFN*
CH1+ 1 8 CH2- CH1+ 1 10 Adr1
CH1- 2 EP 7 CH2+ CH1- 2 9 Adr0
9 EP
VDD 3 6 VSS VSS 3 11 8 SCL
SDA 4 5 SCL CH2+ 4 7 SDA
CH2- 5 6 VDD
MCP3422
Voltage Reference
(2.048V)
VREF
CH1+ SCL
ADC I2C
MUX
CH1- PGA
Converter Interface SDA
CH2+
VSS VDD
MCP3423
Voltage Reference Adr1
(2.048V)
Adr0
VREF
CH1+
SCL
CH1- MUX ADC I2C
PGA
Converter Interface SDA
CH2+
VSS VDD
MCP3424
CH1+ Adr1
Voltage Reference
CH1- (2.048V)
Adr0
VREF
CH2+
SCL
ADC
MUX
CH2- I2C
PGA
Converter Interface SDA
CH3+
CH3-
Gain = 1,2,4, or 8
Clock
CH4+ Oscillator
CH4-
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40C to +85C, VDD = +5.0V, VSS = 0V,
CHn+ = CHn- = VREF/2, VINCOM = VREF /2. All ppm units use 2*VREF as differential full scale range.
Parameters Sym Min Typ Max Units Conditions
Analog Inputs
Differential Full Scale Input FSR 2.048/PGA V VIN = [CHn+ - CHn-]
Voltage Range
Maximum Input Voltage Range VSS-0.3 VDD+0.3 V (Note 1)
Differential Input Impedance ZIND (f) 2.25/PGA M During normal mode operation
(Note 2)
Common Mode input ZINC (f) 25 M PGA = 1, 2, 4, 8
Impedance
System Performance
Resolution and No Missing 12 Bits DR = 240 SPS
Codes 14 Bits DR = 60 SPS
(Effective Number of Bits)
16 Bits DR = 15 SPS
(Note 3)
18 Bits DR = 3.75 SPS
Data Rate DR 176 240 328 SPS 12 bits mode
(Note 4) 44 60 82 SPS 14 bits mode
11 15 20.5 SPS 16 bits mode
2.75 3.75 5.1 SPS 18 bits mode
Output Noise 1.5 VRMS TA = +25C, DR = 3.75 SPS,
PGA = 1, VIN+ = VIN- = GND
Integral Non-Linearity INL 10 35 ppm of DR = 3.75 SPS, FSR = Full
FSR Scale Range (Note 5)
Internal Reference Voltage VREF 2.048 V
Gain Error (Note 6) 0.05 0.35 % PGA = 1, DR = 3.75 SPS
Note 1: Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins.
This parameter is ensured by characterization and not 100% tested.
2: This input impedance is due to 3.2 pF internal input sampling capacitor.
3: This parameter is ensured by design and not 100% tested.
4: The total conversion speed includes auto-calibration of offset and gain.
5: INL is the difference between the endpoints line and the measured code at the center of the quantization band.
6: Includes all errors from on-board PGA and VREF.
7: This parameter is ensured by characterization and not 100% tested.
8: MCP3423 and MCP3424 only.
9: Addr_Float voltage is applied at address pin.
10: No voltage is applied at address pin (left floating).
Note: Unless otherwise indicated, TA = -40C to +85C, VDD = +5.0V, VSS = 0V, CHn+ = CHn- = VREF/2,
VINCOM = VREF/2.
0.0035 8
TA = +25C
TA = +25C
Integral Non-Linearity
5
0.002 PGA = 4
PGA = 2
4
0.0015 PGA = 8 PGA = 4
PGA = 2 3
0.001 PGA = 1
2
0.0005 1
0 0
2.5 3 3.5 4 4.5 5 5.5 -100 -75 -50 -25 0 25 50 75 100
VDD (V) Input Signal (% of FSR)
FIGURE 2-1: INL vs. Supply Voltage FIGURE 2-4: Output Noise vs. Input
(VDD). Voltage.
0.0035 2
PGA = 1 PGA = 1 TA = +25C
Integral Non-Linearity
0.003 1.5
PGA = 8
Total Error (mV)
0.0025 1
(% of FSR)
0.002 0.5
2.7V
0.0015 0
PGA = 4
-0.5 PGA = 2
0.001 5V
-1
0.0005
5.5V -1.5
0
-2
-60 -40 -20 0 20 40 60 80 100 120 140
-100 -75 -50 -25 0 25 50 75 100
o
Temperature ( C) Input Voltage (% of Full-Scale)
FIGURE 2-2: INL vs. Temperature. FIGURE 2-5: Total Error vs. Input Voltage.
20 0.2
15 0.1
Gain Error (% of FSR)
PGA = 8
Offset Error (V)
10 PGA = 8 0
PGA = 1
5 PGA = 4 -0.1
0 -0.2
-5 -0.3
-10 -0.4 PGA = 2
PGA = 2
-15 PGA = 1 -0.5
PGA = 4
-20 -0.6
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (C) Temperature (C)
FIGURE 2-3: Offset Error vs. FIGURE 2-6: Gain Error vs. Temperature.
Temperature.
200 3
Data Rate = 3.75 SPS
180
140 1
120 0
VDD = 2.7V
100
V DD = 5.0V
-1
80
60 -2
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (C) Temperature (C)
FIGURE 2-7: IDDA vs. Temperature. FIGURE 2-10: Oscillator Drift vs.
Temperature.
1 0
-10 Data Rate = 3.75 SPS
0.9
0.8 -20
-30
0.7 V DD = 5.5V Magnitude (dB)
-40
IDDS (A)
0.6 -50
0.5 -60
0.4 VDD = 5.0V
-70
0.3 -80
0.2 -90
0.1 VDD = 2.7V -100
0 -110
-120 0.1 1 10 100 1000 10000
-60 -40 -20 0 20 40 60 80 100 120 140 0.1 1 10 100 1k 10k
Temperature (C) Input Signal Frequency (Hz)
14
VDD = 5.5V
12 V DD = 5.0V
10
IDDB (A)
8
VDD = 4.5V
6
4
2 VDD = 2.7V
0
-60 -40 -20 0 20 40 60 80 100 120 140
Temperature (C)
3.1 Analog Inputs (CHn+, CHn-) 3.2 Supply Voltage (VDD, VSS)
CHn+ and CHn- are differential input pins for VDD is the power supply pin for the device. This pin
channel n. The user can also connect CHn- pin to VSS requires an appropriate bypass ceramic capacitor of
for a single-ended operation. See Figure 6-4 for about 0.1 F to ground to attenuate high frequency
differential and single-ended connection examples. noise presented in application circuit board. An
The maximum voltage range on each differential input additional 10 F capacitor (tantalum) in parallel is also
pin is from VSS-0.3V to VDD+0.3V. Any voltage below or recommended to further attenuate current spike
above this range will cause leakage currents through noises. The supply voltage (VDD) must be maintained
the Electrostatic Discharge (ESD) diodes at the input in the 2.7V to 5.5V range for specified operation.
pins. VSS is the ground pin and the current return path of the
This ESD current can cause unexpected performance device. The user must connect the VSS pin to a ground
of the device. The input voltage at the input pins should plane through a low impedance connection. If an
be within the specified operating range defined in analog ground path is available in the application PCB
Section 1.0 Electrical Characteristics and (printed circuit board), it is highly recommended that
Section 4.0 Description of Device Operation. the VSS pin be tied to the analog ground path or
isolated within an analog ground plane of the circuit
See Section 4.5 Input Voltage Range for more board.
details of the input voltage range.
Figure 3-1 shows the input structure of the device. The
device uses a switched capacitor input stage at the
front end. CPIN is the package pin capacitance and
typically about 4 pF. D1 and D2 are the ESD diodes.
CSAMPLE is the differential input sampling capacitor.
VDD
Sampling
Switch
D1 VT = 0.6V
RSS CHn SS RS
VSS
LEGEND
V = Signal Source ILEAKEAGE = Leakage Current at Analog Pin
RSS = Source Impedance SS = Sampling Switch
CHn = Analog Input Pin RS = Sampling Switch Resistor
CPIN = Input Pin Capacitance CSAMPLE = Sample Capacitance
VT = Threshold Voltage D1, D2 = ESD Protection Diode
3.3 Serial Clock Pin (SCL) 3.4 Serial Data Pin (SDA)
SCL is the serial clock pin of the I2C interface. The SDA is the serial data pin of the I2C interface. The SDA
device act only as a slave and the SCL pin accepts pin is used for input and output data. In read mode, the
only external serial clocks. The input data from the conversion result is read from the SDA pin (output). In
Master device is shifted into the SDA pin on the rising write mode, the device configuration bits are written
edges of the SCL clock and output from the slave (input) though the SDA pin. The SDA pin is an open-
device occurs at the falling edges of the SCL clock. drain N-channel driver. Therefore, it needs a pull-up
The SCL pin is an open-drain N-channel driver. resistor from the VDD line to the SDA pin. Except for
Therefore, it needs a pull-up resistor from the VDD line start and stop conditions, the data on the SDA pin must
to the SCL pin. Refer to Section 5.3 I2C Serial Com- be stable during the high period of the clock. The high
munications for more details of I2C Serial Interface or low state of the SDA pin can only change when the
communication. clock signal on the SCL pin is low. Refer to Section 5.3
I2C Serial Communications for more details of I2C
Serial Interface communication.
Typical range of the pull-up resistor value for SCL and
SDA is from 5 k to 10 k for standard (100 kHz) and
fast (400 kHz) modes, and less than 1 k for high
speed mode (3.4 MHz).
TABLE 4-4: EXAMPLE OF CONVERTING OUTPUT CODE TO VOLTAGE (WITH 18 BIT SETTING)
Input Voltage
Digital Output Code MSB Example of Converting Output Codes to Input Voltage
[CHn+ - CHn-] PGA]
VREF 011111111111111111 0 (216+215+214+213+212+211+210+29+28+27+26+25+24+23+22+21+20)
x LSB(15.625V)/PGA = 2.048 (V) for PGA = 1
VREF - 1 LSB 011111111111111111 0 (216+215+214+213+212+211+210+29+28+27+26+25+24+23+22+21+20)
x LSB(15.625V)/PGA = 2.048 (V) for PGA = 1
2 LSB 000000000000000010 0 (0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+21+0)x LSB(15.625V)/PGA
= 31.25 (V) for PGA = 1
1 LSB 000000000000000001 0 (0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+20)x LSB(15.625V)/PGA
= 15.625 (V)for PGA = 1
0 000000000000000000 0 (0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0)x LSB(15.625V)/PGA
= 0 V (V) for PGA = 1
-1 LSB 111111111111111111 1 -(0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+20)x LSB(15.625V)/PGA
= - 15.625 (V)for PGA = 1
-2 LSB 111111111111111110 1 -(0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+21+0)x LSB(15.625V)/PGA
= - 31.25 (V)for PGA = 1
- VREF 100000000000000000 1 -(217+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0) x
LSB(15.625V)/PGA = - 2.048 (V) for PGA = 1
-VREF 100000000000000000 1 -(217+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0) x
LSB(15.625V)/PGA = - 2.048 (V) for PGA = 1
a. Device power-up.
b. General Call Reset SDA
(See Section 5.4 General Call).
c. General Call Latch
(See Section 5.4 General Call).
The device samples the logic status (address pins) FIGURE 5-2: General Call Latch
during the above events, and latches the values until a Command and Voltage Output at Address Pin
new latch event occurs. During normal operation (after Left Floating (MCP3423 and MCP3424).
the address pins are latched), the address pins are
internally disabled from the rests of the internal circuit.
1 9 1 9
SCL
SDA 1 1 0 1 A2 A1 A0 C1 C0 S1 S0 G1 G0
SCL
FIGURE 5-4:
Repeat of D17 (MSB) D D D D D D D D D D D D D D D D D D C C S S G G
SDA 1 1 0 1 A2 A1 A0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 1 0
1 9
C C S S G G
1 0 1 0 1 0
Timing Diagram For Reading From The MCP3422/3/4 With 18-Bit Mode.
See Figure 5-1 for details in Address Byte.
Stop bit or NAK bit can be issued any time during reading.
Data bits on clocks 1 - 6th in 2nd byte are repeated MSB and can be ignored.
Configuration byte repeats as long as clock is provided after the 5th byte.
DS22088C-page 23
MCP3422/3/4
1 9 1 9 1 9 1 9
SCL
FIGURE 5-5:
DS22088C-page 24
SDA 1 1 0 1 A2 A1 A0 D D D D D D D D D D D D D D D D C C S S G G
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 1 0
MCP3422/3/4 Address Byte Upper Data Byte Lower Data Byte Configuration Byte
(Optional)
To continue: ACK by Master
To end: NAK by Master
1 9
C C S S G G
1 0 1 0 1 0
(Optional)
Timing Diagram For Reading From The MCP3422/3/4 With 12-Bit to 16-Bit Modes.
SDA
TF THIGH TR
SCL TSU:STA
TSU:STO
TLOW TSU:DAT
THD:DAT TBUF
SDA THD:STA
TSP 0.7VDD
0.3VDD
TAA
MCP3424
MCP4725
1 1 1 A2 A1 A0 1
CHn-
0
SDA MCP342X
Start Stop
Bit Device bits Address bits Bit
R/W (b) Single-ended Input Signal Connection:
MCP342X Excitation
Response
R1
FIGURE 6-3: I2C Bus Connection Test. CHn+
Input Signal
Sensor R2
CHn-
MCP342X
Charging To Battery
Current
R1
Battery MCP3422
VBAT VIN
(Rechargeable) 1 CH1+ CH2-8
2 CH1- CH2+7
3 VDD VSS 6
R2 0.1 F 4 SDA SCL 5
SCL
10 F To MCU
SDA (MASTER)
R2
V IN = ------------------ V BAT 5 k
R1 + R2 5 k
R1 and R2 = Voltage Divider VDD
MCP3424 MCP9800
MCP9800
1 CH1+ CH4- 14 SDA
SCL 2 CH1- 13
CH4+
SDA SCL
3 CH2+ CH3- 12
4 CH2- CH3+ 11
0.1 F 5 VSS Adr1 10 VDD
6 VDD Adr0 9
7 SDA SCL 8
MCP9800
MCP9800
10 F
SDA
Heat
SCL SCL
SCL
SDA TO MCU
SDA (MASTER)
5 k
5 k
VDD
VDD VDD
Pressure Sensor Pressure Sensor
(NPP301) (NPP301)
MCP3424
1 CH1+ CH4- 14
2 CH1- CH4+ 13
VIN VDD
3 CH2+ CH3- 12
VIN
VDD 4 CH2- CH3+ 11
5 VSS Adr1 10 VDD
6 VDD Adr0 9 R1
0.1 F 7 SDA SCL 8
R1
R2 Thermistor
10 F
Thermistor R2 TO MCU
(MASTER)
5 k
5 k
VDD
R2
V IN = ------------------- V DD
R1 + R2
R1 and R2 = Voltage Divider
Analog
Input
XXX AGM
YWW 929
NN 25
XXXXXX 3422A0
YWWNNN 929256
XXXXXXXX 3422A0E
XXXXXNNN SN^^256
e3
YYWW 0929
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
XXXXXX 3423E
YWWNNN 929256
XXXXXXXXXXX MCP3424
XXXXXXXXXXX e3
E/SL^^
YYWWNNN 0929256
XXXXXXXX MCP3424E
YYWW 0929
NNN 256
!""#$%&
' 2%
& %!
%
*
") '
%
*
$%%
"%
%%
133)))&
&3
*
D e
b
N N
L
E E2
EXPOSED PAD
NOTE 1
NOTE 1
1 2 2 1
D2
TOP VIEW BOTTOM VIEW
A3 A1 NOTE 2
4% 55,,
&
5&% 6 67 8
6!&(
$ 6 9
%
./0
7
:
% 9
%"$$ .
0%%*
+ ,2
7
5
% /0
7
;"% , +/0
,#
""5
% + < ..
,#
"";"% , . < .
0%%;"% ( . +
0%%5
% 5 + .
0%% % ,#
"" = < <
'
!"
#$
%!
&'(!%&! %(
%
")%%
%
"
*
&
&
#
"%
( %
"
+ *
) !%
"
&
"%
,-.
/01 / &
%
#%!
))%!%%
,21
$
&
'! !)%!%%
'$$&%
!
) 0 +0
!""#$%&
' 2%
& %!
%
*
") '
%
*
$%%
"%
%%
133)))&
&3
*
()"
*
+ )%)* &
' 2%
& %!
%
*
") '
%
*
$%%
"%
%%
133)))&
&3
*
E
E1
NOTE 1
1 2
e
c
A A2
A1 L1 L
4% 55,,
&
5&% 6 67 8
6!&(
$ 6 9
%
>./0
7
:
% < <
"
"*
*
. 9. .
%"$$ < .
7
;"% , /0
"
"*
;"% , +/0
7
5
% +/0
2%5
% 5 > 9
2%
% 5 .,2
2%
I ? < 9?
5
"*
9 < +
5
";"% ( <
'
!"
#$
%!
&'(!%&! %(
%
")%%
%
"
&
","%!"
&"$
%! "$
%! %
#
".&&
"
+ &
"%
,-.
/01 / &
%
#%!
))%!%%
,21
$
&
'! !)%!%%
'$$&%
!
) 0 /
)"
*
+)((, !""#$%)*-&
' 2%
& %!
%
*
") '
%
*
$%%
"%
%%
133)))&
&3
*
e
N
E1
NOTE 1
1 2 3
h
b
h
c
A A2
A1 L
L1
4% 55,,
&
5&% 6 67 8
6!&(
$ 6 9
%
/0
7
:
% < < .
"
"*
*
. < <
%"$$@ < .
7
;"% , >/0
"
"*
;"% , +/0
7
5
% /0
0&$
A
%B . < .
2%5
% 5 <
2%
% 5 ,2
2%
? < 9?
5
"*
< .
5
";"% ( + < .
"$%
.? < .?
"$%
/%%& .? < .?
'
!"
#$
%!
&'(!%&! %(
%
")%%
%
"
@$%0%
%
+ &
","%!"
&"$
%! "$
%! %
#
".&&
"
&
"%
,-.
/01 / &
%
#%!
))%!%%
,21
$
&
'! !)%!%%
'$$&%
!
) 0 ./
)"
*
+)((, !""#$%)*-&
' 2%
& %!
%
*
") '
%
*
$%%
"%
%%
133)))&
&3
*
.
!""#$%&
' 2%
& %!
%
*
") '
%
*
$%%
"%
%%
133)))&
&3
*
D e
b
N N
L
K
E E2
EXPOSED
PAD
NOTE 1 NOTE 1
1 2 2 1
D2
TOP VIEW BOTTOM VIEW
A3 A1 NOTE 2
4% 55,,
&
5&% 6 67 8
6!&(
$ 6
%
./0
7
:
% 9
%"$$ .
0%%*
+ ,2
7
5
% +/0
,#
""5
% +. 9
7
;"% , +/0
,#
"";"% , .9 .
0%%;"% ( 9 . +
0%%5
% 5 + .
0%% % ,#
"" = < <
'
!"
#$
%!
&'(!%&! %(
%
")%%
%
"
*
&
&
#
"%
( %
"
+ *
) !%
"
&
"%
,-.
/01 / &
%
#%!
))%!%%
,21
$
&
'! !)%!%%
'$$&%
!
) 0 >+/
.
!""#$%&
' 2%
& %!
%
*
") '
%
*
$%%
"%
%%
133)))&
&3
*
.
()"
*
+ /%)* &
' 2%
& %!
%
*
") '
%
*
$%%
"%
%%
133)))&
&3
*
D
N
E1
NOTE 1
1 2
b
e
c
A A2
L
A1
L1
4% 55,,
&
5&% 6 67 8
6!&(
$ 6
%
./0
7
:
% < <
"
"*
*
. 9. .
%"$$ < .
7
;"% , /0
"
"*
;"% , +/0
7
5
% +/0
2%5
% 5 > 9
2%
% 5 .,2
2%
? < 9?
5
"*
9 < +
5
";"% ( . < ++
'
!"
#$
%!
&'(!%&! %(
%
")%%
%
"
&
","%!"
&"$
%! "$
%! %
#
".&&
"
+ &
"%
,-.
/01 / &
%
#%!
))%!%%
,21
$
&
'! !)%!%%
'$$&%
!
) 0 /
.0
)"
*
+)((, !""#$%)*-&
' 2%
& %!
%
*
") '
%
*
$%%
"%
%%
133)))&
&3
*
E1
NOTE 1
1 2 3
e
h
b
h
c
A A2
A1 L
L1
4% 55,,
&
5&% 6 67 8
6!&(
$ 6
%
/0
7
:
% < < .
"
"*
*
. < <
%"$$@ < .
7
;"% , >/0
"
"*
;"% , +/0
7
5
% 9>./0
0&$
A
%B . < .
2%5
% 5 <
2%
% 5 ,2
2%
? < 9?
5
"*
< .
5
";"% ( + < .
"$%
.? < .?
"$%
/%%& .? < .?
'
!"
#$
%!
&'(!%&! %(
%
")%%
%
"
@$%0%
%
+ &
","%!"
&"$
%! "$
%! %
#
".&&
"
&
"%
,-.
/01 / &
%
#%!
))%!%%
,21
$
&
'! !)%!%%
'$$&%
!
) 0 >./
.0
12
+)2(
+)"
*
+)10 0""#$%1))* &
' 2%
& %!
%
*
") '
%
*
$%%
"%
%%
133)))&
&3
*
E
E1
NOTE 1
1 2
e
b
c
A A2
A1 L1 L
4% 55,,
&
5&% 6 67 8
6!&(
$ 6
%
>./0
7
:
% < <
"
"*
*
9 .
%"$$ . < .
7
;"% , >/0
"
"*
;"% , + .
"
"*
5
% . .
2%5
% 5 . > .
2%
% 5 ,2
2%
? < 9?
5
"*
<
5
";"% ( < +
'
!"
#$
%!
&'(!%&! %(
%
")%%
%
"
&
","%!"
&"$
%! "$
%! %
#
".&&
"
+ &
"%
,-.
/01 / &
%
#%!
))%!%%
,21
$
&
'! !)%!%%
'$$&%
!
) 0 9/
A5 = 1 0 1
MCP3424
A6 = 1 1 0
a) MCP3424-E/SL: 4-Channel ADC,
A7 = 1 1 1 14LD SOIC package.
* Default option. Contact Microchip factory for other address b) MCP3424T-E/SL: Tape and Reel,
options. 4-Channel ADC,
14LD SOIC package.
c) MCP3424-E/ST: 4-Channel ADC,
14LD TSSOP pkg.
d) MCP3424T-E/ST: Tape and Reel,
4-Channel ADC,
14LD TSSOP pkg.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
03/26/09