A B C D E

1 1

2
Alpine/Snowboard 1.5 2

Schematics Document
Mobile Yonah uFCPGA with Intel
3
Calistoga_GM/PM+ICH7-M core logic 3

, 21, 2006
REV:0.1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sheet 1 of 47
A B C D E
 A B C D E

Compal confidential
File Name : LA-3101P/LA-3111P
ZZZ1 ZZZ1

Snowboard 1.5 Only

14W_PCB 15W_PCB
1 LS-3061P Mobile Yonah 1

GDDR2 VRAM uFCBGA-479/uFCPGA-478 CPU

64/128 MB Clock Gen.
VGA board ICS9LPR325AKLFT
page15
page4,5,6

LVDS H_A#(3..31)
FSB
Connector Nvidia H_D#(0..63) 533/667MHz
page18
VGA board G 72MV
PCI-E x 16
VGA board
DDR2 -667 DDR2-SO-DIMM X2
Intel Calistoga GMCH BANK 0, 1, 2, 3 page 13,14

PCBGA 1466 Dual Channel

CRT & TV OUT LVDS I/F
page7,8,9,10,11,12 MO DEM
2
page17 2
Ver 1.5 page 28

LVDS DMI
Connector page16
AMP&Audio Jack
AZALIA page30

USB2.0
Intel ICH7-M PCI-E Audio Codec
mBGA-652 ADI 1986A
SATA page29
3.3V / 33 MHz
PCI BUS
page19,20,21,22
ATA100
Finger print
page36

RTL8100CL 1394+Card Reader CardBus CMOS Camera

10/100M LAN RICOH R5C832 ENE CB1410 LPC BUS page36
3
page27 page26 page24 3

BlueTooth Conn
page28

RJ45 CONN 1394 Conn Card reader(XD Slot 0 EC

SD/MMC/MS) USB conn X4
page27 page26 page25 ENE KB910L page31
page26 page33
SUB Board page32,36
PCI Express
*1394 CONN
*RJ45 CONN
*DC JACK Touch Pad Int.KBD Mini card Slot
page28
*RJ11 CONN page32
*TVOUT CONN page32
*MIC IN JACK
*USB CONN
*HP OUT JACK BIOS SATA HDD
*SWITCH page34
*LED
*SWITCH Connector page23

4 PATA CDROM 4

Connector page23

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 2 of 47
A B C D E
 A

Voltage Rails SKU ID Table

+5VS
Vcc 3.3V +/- 5%
+3VS
Ra 100K +/- 5%
power Board ID Rb V AD_BID min V AD_BID typ V AD_BID max
plane +2.5VS
+1.8VS
0 0 0 V 0 V 0 V
+B 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+5VALW +1.8V +1.5VS
LDO3 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VALW +5V +1.2VS
LDO5
+VGA_CORE * 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+0.9VS
4 56K +/- 5% 1.036 V 1.185 V 1.264 V
State 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+CPU_CORE
+VCCP
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V

S0 O O O O SKU ID HDL00 SKU

* 0 UMA W/FPR W/BT
S1 1 UMA WO/FPR W/BT
O O O O
2 UMA W/FPR WO/BT
S3 3 UMA WO/FPR WO/BT
O O O X
4 VGA W/FPR W/BT
S5 S4/AC 5 VGA WO/FPR W/BT
O O X X
6 VGA W/FPR WO/BT
S5 S4/ Battery only
7 VGA WO/FPR WO/BT
O X X X
MB ID HDL00 SKU
S5 S4/AC & Battery H HDL00
don't exist X X X X
L HDL10

O MEANS ON S3 : STR
X MEANS OFF S4 : STD
S5 : SOFT OFF
1 BOM Structure USB PORT LIST 1

MARK FUNCTION
External PCI Devices @ NC FOR ALL PORT DEVICE
Device IDSEL# REQ#/GNT# Interrupts
GIGA@ 8110SBL(SCL)Giga LAN 0 LEFT SIDE
13 94 AD22 0 PIRQG/H
10/100@ 8100CL 10/100Mb LAN 1 BLUE TOOTH
LAN AD17 3 PIRQF
UMA@ Internal 945GM 2 RIGHT SIDE
CardBus AD20 2 PIRQA
VGA@ External G7xM 3 CMOS
4 RIGHT SIDE
5 FINGER PRINTER
6 RIGHT SIDE
EC SM Bus1 address EC SM Bus2 address 7 NC
Device Address Device Address
Smart Battery 0001 011X b ADM1032 1001 100X b
EEPROM(24C16/02) 1010 000X b

ICH6 SM Bus address

Device Address
Clock Generator
( ICS954226) 1101 001Xb
DDRII DIMM0 1010 000Xb
DDRII DIMM1 1010 010Xb

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 3 of 47
A
 5 4 3 2 1

+VCCP

This shall place near CPU

ITP_TDI R98 1 2 56_0402_5%
<7> H_A#[3..31] H_D#[0..63] <7>
JP1A ITP_TMS R97 1 2 56_0402_1%

H_A#3 J4 E22 H_D#0 ITP_TDO R101 1 2 56_0402_5%

H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2 ITP_BPM#5 R103 1 56_0402_5%
M3 A5# D2# E26 2
H_A#6 K5 H22 H_D#3
H_A#7 A6# D3# H_D#4 ITP_TRST# R95 56_0402_5%
M1 A7# D4# F23 1 2
H_A#8 N2 G25 H_D#5
H_A#9 A8# D5# H_D#6 ITP_TCK R96 56_0402_5%
J1 A9# D6# E25 1 2
D H_A#10 H_D#7 D
N3 A10# D7# E23
H_A#11 P5 K24 H_D#8
H_A#12 A11# D8# H_D#9
P2 A12# D9# G24
H_A#13 L1 J24 H_D#10
H_A#14 A13# D10# H_D#11
P4 A14# D11# J23
H_A#15 P1 H26 H_D#12 ITP_DBRESET# R85 1 2 @ 200_0402_5% PAD T13
H_A#16 A15# D12# H_D#13
R1 A16# D13# F26
H_A#17 Y2 K22 H_D#14 ITP_BPM#0 PAD T17
H_A#18 A17# D14# H_D#15 ITP_BPM#1 T18
U5 A18# D15# H25 PAD
H_A#19 R3 N22 H_D#16 ITP_BPM#2 PAD T20
H_A#20 A19# D16# H_D#17 ITP_BPM#3 T16
W6 A20# D17# K25 PAD
H_A#21 U4 P26 H_D#18 ITP_BPM#4 PAD T19
H_A#22 A21# D18# H_D#19
Y5 A22# D19# R23
H_A#23 U2 L25 H_D#20
H_A#24 A23# D20# H_D#21
R4 A24# D21# L22
H_A#25 T5 ADDR GROUP DATA GROUP L23 H_D#22
H_A#26 A25# D22# H_D#23
T3 A26# D23# M23
H_A#27 W3 P25 H_D#24
H_A#28 A27# D24# H_D#25
W5 A28# D25# P22
H_A#29 Y4 P23 H_D#26
H_A#30 A29# D26# H_D#27
W2 A30# D27# T24 +3VS
H_A#31 Y1 R24 H_D#28
<7> H_REQ#[0..4] A31# D28#
L26 H_D#29 U16
H_REQ#0 D29# H_D#30 H_THERMDA
K3 REQ0# D30# T25 2 D+ VDD1 1 2 1
H_REQ#1 H2 N24 H_D#31 C311 C310 0.1U_0402_16V4Z
H_REQ#2 REQ1# D31# H_D#32 H_THERMDC
K2 REQ2# D32# AA23 1 2 3 D- ALERT# 6
H_REQ#3 J3 AB24 H_D#33 2200P_0402_50V7K
H_REQ#4 REQ3# D33# H_D#34 EC_SMB_CK2 THERM#
L5 REQ4# D34# V24 <33> EC_SMB_CK2 8 SCLK THERM# 4 2 1 +3VS
V26 H_D#35 10K_0402_5% R226
H_ADSTB#0 D35# H_D#36 EC_SMB_DA2
<7> H_ADSTB#0 L2 ADSTB0# D36# W25 <33> EC_SMB_DA2 7 SDATA GND 5
H_ADSTB#1 V4 U23 H_D#37
<7> H_ADSTB#1 ADSTB1# D37#
U25 H_D#38
C D38# H_D#39 G781F_SOP8 C
D39# U22
AB25 H_D#40 Address:100_1100
D40# H_D#41
D41# W22
Y23 H_D#42
CLK_CPU_BCLK A22 D42# H_D#43
<15> CLK_CPU_BCLK BCLK0 D43# AA26
CLK_CPU_BCLK# A21 HOST CLK Y26 H_D#44
<15> CLK_CPU_BCLK# BCLK1 D44# H_D#45
D45# Y22
AC26 H_D#46
D46# H_D#47
D47# AA24
H_ADS# H1 AC22 H_D#48
<7> H_ADS# ADS# D48#
H_BNR# E2 AC23 H_D#49
<7> H_BNR# BNR# D49#
H_BPRI# G5 AB22 H_D#50
<7> H_BPRI# BPRI# D50#
H_BR0# F1 AA21 H_D#51
<7> H_BR0# BR0# D51#
H_DEFER# H5 AB21 H_D#52
<7> H_DEFER# DEFER# D52#
H_DRD Y# F21 AC25 H_D#53
<7> H_DRDY# DRDY# D53#
R84 H_HIT# G6 AD20 H_D#54
<7> H_HIT# HIT# D54#
56_0402_5% H_HITM# E4 CONTROL AE22 H_D#55
<7> H_HITM# HITM# D55#
1 2 H_IERR# D20 AF23 H_D#56
+VCCP H_LOCK# IERR# D56# H_D#57
<7> H_LOCK# H4 LOCK# D57# AD24
H_RESET# B1 AE21 H_D#58
<7> H_RESET# RESET# D58#
AD21 H_D#59
D59# H_D#60
<7> H_RS#[0..2] D60# AE25
H_RS#0 F3 AF25 H_D#61
H_RS#1 RS0# D61# H_D#62 +5VS
F4 RS1# D62# AF22
H_RS#2 G3 AF26 H_D#63
H_TRDY# RS2# D63#
<7> H_TRDY# G2 TRDY# +VSB 1 2
J26 H_DINV#0
DINV0# H_DINV#0 <7>
M26 H_DINV#1 C303
DINV1# H_DINV#1 <7> C309
ITP_BPM#0 AD4 V23 H_DINV#2 10U_1206_16V4Z
BPM0# DINV2# H_DINV#2 <7> +3VS
ITP_BPM#1 AD3 AC20 H_DINV#3 2 1
BPM1# DINV3# H_DINV#3 <7>

1
2
5
6
ITP_BPM#2 AD1
B ITP_BPM#3 BPM2# 0.1U_0603_25V7K D Q19 B
AC4

P
BPM3# H_DSTBN#[0..3] <7>

2
H23 H_DSTBN#0 3 +IN G SI3456BDV-T1-E3_TSOP6
DSTBN0# <33> EN_FAN1
ITP_DBRESET# C20 M24 H_DSTBN#1 1 FAN1_ON 3 R222
<21> ITP_DBRESET# DBR# DSTBN1# OUT
H_DBSY# E1 W24 H_DSTBN#2 2 S 10K_0402_5%
<7> H_DBSY# DBSY# DSTBN2# -IN
H_DPSLP# B5 AD23 H_DSTBN#3 U15A
<20> H_DPSLP# H_DSTBP#[0..3] <7>

4
DPSLP# DSTBN3#

G
H_DPRSTP# E5 G22 H_DSTBP#0 LM358A_SO8
<20,45> H_DPRSTP#

1
H_DPWR# DPRSTP# DSTBP0# H_DSTBP#1
<7> H_DPWR# D24 N25

4
ITP_BPM#4 DPWR# DSTBP1# H_DSTBP#2
<45> H_PROCHOT# AC2 PRDY# MISC DSTBP2# Y25
ITP_BPM#5 AC1 AE24 H_DSTBP#3 JP2
PREQ# DSTBP3#
+VCCP 1 R83 2 H_PROCHOT# D21
PROCHOT# 1 2 FAN1
1
68_0402_5% R218
2

1000P_0402_50V7K

C305 10U_0805_10V4Z
H_PW RGOOD D6 100K_0402_5%
<20> H_PWRGOOD PWRGOOD 3

1
H_CPUSLP# D7 1 1
<7,20> H_CPUSLP# SLP#

1
ITP_TCK AC5 R219 ACES_85205-0300
ITP_TDI TCK H_A20M# 150K_0402_5%
AA6 TDI A20M# A6 H_A20M# <20>
ITP_TDO AB3 A5 H_FERR# D11 @
TDO FERR# H_FERR# <20> 2 2
R71 1 2 @ 1K_0402_5% TEST1 C26 C4 H_IGNNE# 1N4148_SOD80
H_IGNNE# <20>

2
R74 TEST1 IGNNE#
1 2 51_0402_5% TEST2 D25 B3 H_INIT#
H_INIT# <20>

2
TEST2 INIT#

C307
ITP_TMS AB5 C6 H_INTR
TMS LINT0 H_INTR <20>
ITP_TRST# AB6 B4 H_NMI
TRST# LINT1 H_NMI <20>
LEGACY CPU
THERMAL
H_THERMDA A24 D5 H_STPCLK#
H_THERMDC THERMDA DIODE STPCLK# H_SMI#
H_STPCLK# <20>
A25 THERMDC SMI# A3 H_SMI# <20> <33> FAN_SPEED1 1
H_THERMTRIP# C7 5
<7,20> H_THERMTRIP# THERMTRIP# +IN
7 C308
OUT 1000P_0402_50V7K
H_THERMDA, H_THERMDC routing together. 6 -IN 2
TYCO_1-1674770-2_Yonah~D U15B
Trace width / Spacing = 10 / 10 mil ME@ LM358A_SO8

A +VCCP A

+VCCP
1

R100
R73 H_DPSLP# 1 2

@ 56_0402_5% @ 56_0402_5%
R99 Security Classification Compal Secret Data Compal Electronics, Inc.
2 2

H_DPRSTP# 1 2 2005/10/06 2006/10/06 Title

Issued Date Deciphered Date
B

@ 56_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
E

H_PROCHOT# 3 1 OCP# AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
OCP# <21>
Q4 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
@ PMBT3904_SOT23 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 4 of 47
5 4 3 2 1
 5 4 3 2 1

+VCCP +CPU_CORE
Length match within 25 mils JP1B JP1C
D D
The trace width 18 mils space

1
<45> VCCSENSE VCCSENSE AF7 AB26 AE18 K1
VCCSENSE VSS VCC VSS
+CPU_CORE 7 mils <45> VSSENSE VSSENSE AE7 VSSSENSE VSS AA25 AE17 VCC VSS J2
R69 R93 AD25 AB15 M2
+CPU_GTLREF 1K_0402_1% 100_0402_1% VSS VCC VSS
VSS AE26 AA15 VCC VSS N1
1 2 VCCSENSE B26 AB23 AD15 T1
2
+1.5VS VCCA VSS VCC VSS

0.01U_0402_16V7K
VSS AC24 AC15 VCC VSS R2

10U_0805_10V4Z
R94 K6 AF24 AF15 V2
100_0402_1% +VCCP VCCP VSS VCC VSS
J6 VCCP VSS AE23 AE15 VCC VSS W1
1

1 2 VSSENSE 1 1 M6 AA22 AB14 A26

VCCP VSS VCC VSS

C132

C122
N6 AD22 AA13 D26
R62
2K_0402_1%
T6
VCCP
VCCP
YONAH VSS
VSS AC21 AD14
VCC
VCC
VSS
VSS C25
R6 VCCP VSS AF21 AC13 VCC VSS F25
2 2
K21 AB19 AF14 B24
2

VCCP VSS VCC VSS

J21 VCCP VSS AA19 AE13 VCC VSS A23
M21 VCCP VSS AD19 AB12 VCC VSS D23
Close to CPU pin N21
T21
VCCP VSS AC19
AF19
AA12
AD12
VCC YONAH VSS E24
B21
Close to CPU pin AD26 VCCP VSS VCC VSS
within 500mils. R21 VCCP VSS AE19 AC12 VCC VSS C22
within 500mils. V21 VCCP VSS AB16 AF12 VCC VSS F22
W21 AA16 AE12 E21

POWER, GROUNG, RESERVED SIGNALS AND NC

VCCP VSS VCC VSS
V6 VCCP VSS AD16 AB10 VCC VSS B19
G21 VCCP VSS AC16 AB9 VCC VSS A19
VSS AF16 AA10 VCC VSS D19
VSS AE16 AA9 VCC VSS C19
<45> H_PSI# H_PSI# AE6 AB13 AD10 F19
PSI# VSS VCC VSS
VSS AA14 AD9 VCC VSS E19
CPU_VID0 AD6 AD13 AC10 B16
<45> CPU_VID0 VID0 VSS VCC VSS
CPU_VID1 AF5 AC14 AC9 A16
<45> CPU_VID1 VID1 VSS VCC VSS
CPU_VID2 AE5 AF13 AF10 D16
<45> CPU_VID2 VID2 VSS VCC VSS
CPU_VID3 AF4 AE14 AF9 C16
<45> CPU_VID3 VID3 VSS VCC VSS
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 CPU_VID4 AE3 AB11 AE10 POWER, GROUND F16
C <45> CPU_VID4 VID4 VSS VCC VSS C
CPU_VID5 AF2 AA11 AE9 E16
<45> CPU_VID5 VID5 VSS VCC VSS
CPU_VID6 AE2 AD11 AB7 B13
<45> CPU_VID6 VID6 VSS VCC VSS
VSS AC11 AA7 VCC VSS A14
133 0 0 1 VSS AF11 AD7 VCC VSS D13
+CPU_GTLREF AD26 GTLREF VSS AE11 AC7 VCC VSS C14
VSS AB8 B20 VCC VSS F13
CPU_BSEL0 B22 AA8 A20 E14
<15> CPU_BSEL0 BSEL0 VSS VCC VSS
166 0 1 CPU_BSEL1
1 <15> CPU_BSEL1
CPU_BSEL2
B23
C21
BSEL1 VSS AD8
AC8
F20
E20
VCC VSS B11
A11
<15> CPU_BSEL2 BSEL2 VSS VCC VSS
VSS AF8 B18 VCC VSS D11
COMP0 R26 AE8 B17 C11
COMP1 COMP0 VSS VCC VSS
U26 COMP1 VSS AA5 A18 VCC VSS F11
COMP2 U1 AD5 A17 E11
COMP3 COMP2 VSS VCC VSS
V1 COMP3 VSS AC6 D18 VCC VSS B8
VSS AF6 D17 VCC VSS A8
VSS AB4 C18 VCC VSS D8
+CPU_CORE E7 VCC VSS AC3 C17 VCC VSS C8
AB20 VCC VSS AF3 F18 VCC VSS F8
AA20 VCC VSS AE4 F17 VCC VSS E8
AF20 VCC VSS AB1 E18 VCC VSS G26
Resistor placed within AE20 VCC VSS AA2 E17 VCC VSS K26
27.4_0402_1%

54.9_0402_1%

27.4_0402_1%

54.9_0402_1%

AB18 AD2 B15 J25

0.5" of CPU pin.Trace VCC VSS VCC VSS
1

AB17 VCC VSS AE1 A15 VCC VSS M25

should be at least 25 AA18 VCC VSS B6 D15 VCC VSS N26
R70

R72

R102

R104

AA17 C5 C15 T26

mils away from any AD18
VCC VSS
F5 F15
VCC VSS
R25
VCC VSS VCC VSS
other toggling signal. AD17 E6 E15 V25
2

VCC VSS VCC VSS

AC18 VCC VSS H6 B14 VCC VSS W26
AC17 VCC VSS J5 A13 VCC VSS H24
AF18 VCC VSS M5 D14 VCC VSS G23
AF17 VCC VSS L6 C13 VCC VSS K23
VSS P6 F14 VCC VSS L24
B B
VSS R5 E13 VCC VSS P24
D2 RSVD VSS V5 B12 VCC VSS N23
F6 RSVD VSS U6 A12 VCC VSS T23
D3 RSVD VSS Y6 D12 VCC VSS U24
C1 RSVD VSS A4 C12 VCC VSS Y24
AF1 RSVD VSS D4 F12 VCC VSS W23
D22 RSVD VSS E3 E12 VCC VSS H21
C23 RSVD VSS H3 B10 VCC VSS J22
C24 RSVD VSS G4 B9 VCC VSS M22
AA1 RSVD VSS K4 A10 VCC VSS L21
AA4 RSVD VSS L3 A9 VCC VSS P21
AB2 RSVD VSS P3 D10 VCC VSS R22
AA3 RSVD VSS N4 D9 VCC VSS V22
M4 RSVD VSS T4 C10 VCC VSS U21
N5 RSVD VSS U3 C9 VCC VSS Y21
T2 RSVD VSS Y3 F10 VCC
V3 RSVD VSS W4 F9 VCC
B2 RSVD VSS D1 E10 VCC
C3 RSVD VSS C2 E9 VCC
T22 RSVD VSS F2 B7 VCC
B25 RSVD VSS G1 A7 VCC
F7 VCC

TYCO_1-1674770-2_Yonah~D TYCO_1-1674770-2_Yonah~D
ME@ ME@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 5 of 47
5 4 3 2 1
 5 4 3 2 1

D +CPU_CORE D

1 1 1 1 1 1 1 1
Place these capacitors on L8 C318 C326 C151 C171 C346 C169 C187 C184
(North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2

+CPU_CORE

1 1 1 1 1 1 1 1
Place these capacitors on L8 C325 C186 C341 C178 C316 C185 C166 C342
(North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2

+CPU_CORE

1 1 1 1 1 1 1 1
Place these capacitors on L8 C183 C170 C334 C319 C172 C333 C181 C176
(Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2

C C
+CPU_CORE

1 1 1 1 1 1 1 1
Place these capacitors on L8 C150 C165 C345 C173 C179 C177 C317 C182
(Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2

Mid Frequence Decoupling

+CPU_CORE

ESR <= 1.5m ohm

330U_V_2.5VK_R9

330U_V_2.5VK_R9

330U_V_2.5VK_R9

330U_V_2.5VK_R9

330U_V_2.5VK_R9

330U_V_2.5VK_R9
1 1 1 1 1 1

Capacitor > 1980uF

C324

C180

C175

C339

C320

C343
+ + + + + + North Side Secondary
South Side Secondary
2 2 2 2 2 2
B B

+VCCP

1
1 1 1 1 1 1
C109 + Place these inside
C190 C136 C138 C137 C189 C188 socket cavity on L8
220U_D2_4VM 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z (North side
2 2 2 2 2 2 2 Secondary)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 6 of 47
5 4 3 2 1
 5 4 3 2 1

U14

<4> H_D#[0..63] H_A#[3..31] <4> PM Description at page15.

U14A VGA@ U14B
H_D#0 F1 H9 H_A#3
H_D#1 HD0# HA3# H_A#4 DMI_TXN0 MCH_CLKSEL0
J1 HD1# HA4# C9 <21> DMI_TXN0 AE35 DMIRXN0 CFG0 K16 MCH_CLKSEL0 <15>
H_D#2 H1 E11 H_A#5 DMI_TXN1 AF39 K18 MCH_CLKSEL1
HD2# HA5# <21> DMI_TXN1 DMIRXN1 CFG1 MCH_CLKSEL1 <15>
H_D#3 J6 G11 H_A#6 DMI_TXN2 AG35 J18 MCH_CLKSEL2
HD3# HA6# <21> DMI_TXN2 DMIRXN2 CFG2 MCH_CLKSEL2 <15>
H_D#4 H3 F11 H_A#7 DMI_TXN3 AH39 F18 CFG3 PAD T9
HD4# HA7# <21> DMI_TXN3 DMIRXN3 CFG3
H_D#5 K2 G12 H_A#8 E15 CFG4 PAD T3
D H_D#6 HD5# HA8# H_A#9 CFG4 CFG5 D
G1 HD6# HA9# F9 CFG5 F15 CFG5 <11>
H_D#7 G2 H11 H_A#10 DMI_TXP0 AC35 E18 CFG6 PAD T10
HD7# HA10# <21> DMI_TXP0 DMIRXP0 CFG6
H_D#8 K9 J12 H_A#11 DMI_TXP1 AE39 D19 CFG7
HD8# HA11# <21> DMI_TXP1 DMIRXP1 CFG7 CFG7 <11>
H_D#9 K1 G14 H_A#12 DMI_TXP2 AF35 D16 CFG8 PAD T7
HD9# HA12# <21> DMI_TXP2 DMIRXP2 CFG8

DMI
H_D#10 K7 D9 H_A#13 DMI_TXP3 AG39 G16 CFG9
HD10# HA13# <21> DMI_TXP3 DMIRXP3 CFG9 CFG9 <11>
H_D#11 J8 J14 H_A#14 E16 CFG10 PAD T5
H_D#12 HD11# HA14# H_A#15 CFG10 CFG11
H4 HD12# HA15# H13 CFG11 D15 CFG11 <11>
H_D#13 J3 J15 H_A#16 DMI_RXN0 AE37 G15 CFG12
HD13# HA16# <21> DMI_RXN0 DMITXN0 CFG12 CFG12 <11>
H_D#14 K11 F14 H_A#17 DMI_RXN1 AF41 K15 CFG13
HD14# HA17# <21> DMI_RXN1 DMITXN1 CFG13 CFG13 <11>

CFG
H_D#15 G4 D12 H_A#18 DMI_RXN2 AG37 C15 CFG14 PAD T2
HD15# HA18# <21> DMI_RXN2 DMITXN2 CFG14
H_D#16 T10 A11 H_A#19 DMI_RXN3 AH41 H16 CFG15 PAD T8
HD16# HA19# <21> DMI_RXN3 DMITXN3 CFG15
H_D#17 W11 C11 H_A#20 G18 CFG16
HD17# HA20# CFG16 CFG16 <11>
H_D#18 T3 A12 H_A#21 H15 CFG17 PAD T1
H_D#19 HD18# HA21# H_A#22 DMI_RXP0 CFG17 CFG18
U7 HD19# HA22# A13 <21> DMI_RXP0 AC37 DMITXP0 CFG18 J25 CFG18 <11>
H_D#20 U9 E13 H_A#23 DMI_RXP1 AE41 K27 CFG19
HD20# HA23# <21> DMI_RXP1 DMITXP1 CFG19 CFG19 <11>
H_D#21 U11 G13 H_A#24 DMI_RXP2 AF37 J26 CFG20
HD21# HA24# <21> DMI_RXP2 DMITXP2 CFG20 CFG20 <11>
H_D#22 T11 F12 H_A#25 DMI_RXP3 AG41
HD22# HA25# <21> DMI_RXP3 DMITXP3
H_D#23 W9 B12 H_A#26
H_D#24 HD23# HA26# H_A#27
T1 HD24# HA27# B14 G_CLKP AG33 CLK_MCH_3GPLL CLK_MCH_3GPLL <15>
H_D#25 T8 C12 H_A#28 M_CLK_DDR0 AY35 AF33 CLK_MCH_3GPLL#
HD25# HA28# <13> M_CLK_DDR0 SM_CK0 G_CLKN CLK_MCH_3GPLL# <15>
H_D#26 T4 A14 H_A#29 M_CLK_DDR1 AR1
HD26# HA29# <13> M_CLK_DDR1 SM_CK1
H_D#27 W7 C14 H_A#30 M_CLK_DDR2 AW7 A27 CLK_MCH_DREFCLK#

CLK
HD27# HA30# <14> M_CLK_DDR2 SM_CK2 D_REF_CLKN CLK_MCH_DREFCLK# <15>
H_D#28 U5 D14 H_A#31 M_CLK_DDR3 AW40 A26 CLK_MCH_DREFCLK
HD28# HA31# <14> M_CLK_DDR3 SM_CK3 D_REF_CLKP CLK_MCH_DREFCLK <15>
H_D#29 T9
H_D#30 HD29# M_CLK_DDR#0
W6 HD30# <13> M_CLK_DDR#0 AW35 SM_CK0# D_REF_SSCLKN C40 MCH_SSCDREFCLK# CLK_MCH_SSCDREFCLK# <15>
H_D#31 T5 M_CLK_DDR#1 AT1 D41 MCH_SSCDREFCLK
H_D#32 AB7
HD31#
HD32#
HOST HREQ#0 D8 H_REQ#0
H_REQ#[0..4] <4> <13>
<14>
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#2 AY7
SM_CK1#
SM_CK2#
D_REF_SSCLKP CLK_MCH_SSCDREFCLK <15>
H_D#33 AA9 G8 H_REQ#1 M_CLK_DDR#3 AY40 H32 MCH_CLKREQ#
HD33# HREQ#1 <14> M_CLK_DDR#3 SM_CK3# CLK_REQ# MCH_CLKREQ# <15>
H_D#34 W4 B8 H_REQ#2
H_D#35 HD34# HREQ#2 H_REQ#3 DDR_CKE0_DIMMA
W3 HD35# HREQ#3 F8 <13> DDR_CKE0_DIMMA AU20 SM_CKE0

DDR MUXING
H_D#36 Y3 A8 H_REQ#4 DDR_CKE1_DIMMA AT20
HD36# HREQ#4 <13> DDR_CKE1_DIMMA SM_CKE1
H_D#37 Y7 DDR_CKE2_DIMMB BA29 A3
C HD37# <14> DDR_CKE2_DIMMB SM_CKE2 NC0 C
H_D#38 W5 DDR_CKE3_DIMMB AY29 A39
HD38# <14> DDR_CKE3_DIMMB SM_CKE3 NC1
H_D#39 Y10 B9 H_ADSTB#0 A4
HD39# HADSTB#0 H_ADSTB#0 <4> NC2
H_D#40 AB8 C13 H_ADSTB#1 DDR_CS0_DIMMA# AW13 A40
HD40# HADSTB#1 H_ADSTB#1 <4> <13> DDR_CS0_DIMMA# SM_CS0# NC3
H_D#41 W2 DDR_CS1_DIMMA# AW12 AW1
HD41# <13> DDR_CS1_DIMMA# SM_CS1# NC4
H_D#42 AA4 AG1 CLK_MCH_BCLK# DDR_CS2_DIMMB# AY21 AW41
HD42# HCLKN CLK_MCH_BCLK# <15> <14> DDR_CS2_DIMMB# SM_CS2# NC5
H_D#43 AA7 AG2 CLK_MCH_BCLK DDR_CS3_DIMMB# AW21 AY1
HD43# HCLKP CLK_MCH_BCLK <15> <14> DDR_CS3_DIMMB# SM_CS3# NC6
H_D#44 AA2 BA1

NC
HD44# H_DSTBN#[0..3] <4> NC7
H_D#45 AA6 K4 H_DSTBN#0 M_OCDOCMP0 AL20 BA2
H_D#46 HD45# HDSTBN#0 H_DSTBN#1 M_OCDOCMP1 SM_OCDCOMP0 NC8
AA10 HD46# HDSTBN#1 T7 AF10 SM_OCDCOMP1 NC9 BA3
H_D#47 Y8 Y5 H_DSTBN#2 BA39
H_D#48 HD47# HDSTBN#2 H_DSTBN#3 M_ODT0 NC10
AA1 HD48# HDSTBN#3 AC4 H_DSTBP#[0..3] <4> <13> M_ODT0 BA13 SM_ODT0 NC11 BA40
H_D#49 H_DSTBP#0 +1.8V M_ODT1
AB4 HD49# HDSTBP#0 K3 <13> M_ODT1 BA12 SM_ODT1 NC12 BA41
H_D#50 AC9 T6 H_DSTBP#1 M_ODT2 AY20 C1
HD50# HDSTBP#1 <14> M_ODT2 SM_ODT2 NC13
H_D#51 AB11 AA5 H_DSTBP#2 M_ODT3 AU21 AY41
HD51# HDSTBP#2 <14> M_ODT3 SM_ODT3 NC14
H_D#52 AC11 AC5 H_DSTBP#3 B2
H_D#53 HD52# HDSTBP#3 R29 SMRCOMPN NC15
AB3 HD53# 1 2 80.6_0402_1% AV9 SM_RCOMPN NC16 B41
+VCCP H_D#54 AC2 1 2 SMRCOMPP AT9 C41
H_D#55 HD54# H_DINV#0 R28 80.6_0402_1% SM_RCOMPP NC17
AD1 HD55# HDINV#0 J7 H_DINV#0 <4> NC18 D1
H_D#56 AD9 W8 H_DINV#1 AK1
HD56# HDINV#1 H_DINV#1 <4> SM_VREF0
H_D#57 AC1 U3 H_DINV#2 +DDR_MCH_REF AK41
HD57# HDINV#2 H_DINV#2 <4> SM_VREF1
54.9_0402_1%

54.9_0402_1%

H_D#58 AD7 AB10 H_DINV#3 T32

HD58# HDINV#3 H_DINV#3 <4> RESERVED1
1

H_D#59 AC6 R32

HD59# RESERVED2
R26

R27

H_D#60 AB5 R88 <21> PM_BMBUSY# PM_BMBUSY# G28 PM_BMBUSY# F3

H_D#61 HD60# H_RESET# 0_0402_5% <13,14> PM_EXTTS#0 PM_EXTTS#0 RESERVED3
AD10 HD61# HCPURST# B7 H_RESET# <4> F25 PM_EXTTS0# RESERVED4 F7

RESERVED
PM
H_D#62 AD4 E8 H_ADS# 2 1 PM_EXTTS#1 H26 PM_EXTTS1# AG11
HD62# HADS# H_ADS# <4> <21,45> DPRSLPVR RESERVED5
H_D#63 AC8 E7 H_TRDY# <4,20> H_THERMTRIP# H_THERMTRIP# G6 PM_THERMTRIP# AF11
H_TRDY# <4>
2

HD63# HTRDY# H_DPWR# ICH_POK RESERVED6

HDPWR# J9 H_DPWR# <4> <21,33> ICH_POK AH33 PWROK RESERVED7 H7
H8 H_DRD Y# 2 1 PLTRST_R# AH34 RSTIN# J19
HDRDY# H_DRDY# <4> <19,23,28> PLT_RST# RESERVED8
J13 C3 H_DEFER# R55 100_0402_1% A41
HVREF0 HDEFER# H_DEFER# <4> RESERVED9
+H_VREF K13 D4 H_HITM# <19> MCH_ICH_SYNC# K28 ICH_SYNC# A34
HVREF1 HHITM# H_HITM# <4> RESERVED10
H_XRCOMP E1 D3 H_HIT# D28
HXRCOMP HHIT# H_HIT# <4> RESERVED11
H_XSCOMP E2 B3 H_LOCK# D27
B HXSCOMP HLOCK# H_LOCK# <4> RESERVED12 B
H_YRCOMP Y1 C7 H_BR0# A35
HYRCOMP HBREQ0# H_BR0# <4> RESERVED13
H_YSCOMP U1 C6 H_BNR#
HYSCOMP HBNR# H_BNR# <4>
+H_SWNG0 E4 F6 H_BPRI# CALISTOGA_FCBGA1466~D
HXSWING HBPRI# H_BPRI# <4>
+H_SWNG1 W1 A7 H_DBSY# UMA@
HYSWING HDBSY# H_DBSY# <4>
E3 H_CPUSLP# Layout Note:
HCPUSLP# H_CPUSLP# <4,20>
24.9_0402_1%

24.9_0402_1%

+DDR_MCH_REF
1

trace width and

R23

R20

B4 H_RS#0
HRS0# H_RS#1
HRS1# E6 spacing is 20/20.
D6 H_RS#2 +3VS
HRS2#
H_RS#[0..2] <4>
2

CALISTOGA_FCBGA1466~D +1.8V
UMA@
R46

1
10K_0402_5%
R25 PM_EXTTS#0 2 1

Layout Note: 100_0402_1% R49

@ 10K_0402_5%

2
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 / +DDR_MCH_REF PM_EXTTS#1 2 1
0.1U_0402_16V4Z

H_SWNG1 trace width and spacing is 10/20.

1 1 R21
+VCCP +VCCP R45
C16

100_0402_1% @ 40.2_0402_1%
+VCCP M_OCDOCMP0 2 1
2

2
221_0603_1%

221_0603_1%
1

1
100_0402_1%

R31
1

R22

R18

@ 40.2_0402_1%
R30

M_OCDOCMP1 2 1
A A
2

+H_SWNG0 +H_SWNG1
2

+H_VREF
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

1
100_0402_1%

100_0402_1%
0.1U_0402_16V4Z

1 1
1

200_0402_1%

R24

R19

1
R36

C26

C19

C11

2 2 Security Classification Compal Secret Data Compal Electronics, Inc.

2

2
Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 7 of 47
5 4 3 2 1
 5 4 3 2 1

D D

U14D U14E
DDR_A_D[0..63] <13> DDR_B_D[0..63] <14>
DDR_A_BS#0 AU12 AJ35 DDR_A_D0 DDR_B_BS#0 AT24 AK39 DDR_B_D0
<13> DDR_A_BS#0 SA_BS0 SA_DQ0 <14> DDR_B_BS#0 SB_BS0 SB_DQ0
DDR_A_BS#1 AV14 AJ34 DDR_A_D1 DDR_B_BS#1 AV23 AJ37 DDR_B_D1
<13> DDR_A_BS#1 SA_BS1 SA_DQ1 <14> DDR_B_BS#1 SB_BS1 SB_DQ1
DDR_A_BS#2 BA20 AM31 DDR_A_D2 DDR_B_BS#2 AY28 AP39 DDR_B_D2
<13> DDR_A_BS#2 SA_BS2 SA_DQ2 <14> DDR_B_BS#2 SB_BS2 SB_DQ2
AM33 DDR_A_D3 AR41 DDR_B_D3
SA_DQ3 DDR_A_D4 SB_DQ3 DDR_B_D4
SA_DQ4 AJ36 SB_DQ4 AJ38
<13> DDR_A_DM[0..7] AK35 DDR_A_D5 <14> DDR_B_DM[0..7] AK38 DDR_B_D5
DDR_A_DM0 SA_DQ5 DDR_A_D6 DDR_B_DM0 SB_DQ5 DDR_B_D6
AJ33 SA_DM0 SA_DQ6 AJ32 AK36 SB_DM0 SB_DQ6 AN41
DDR_A_DM1 AM35 AH31 DDR_A_D7 DDR_B_DM1 AR38 AP41 DDR_B_D7
DDR_A_DM2 SA_DM1 SA_DQ7 DDR_A_D8 DDR_B_DM2 SB_DM1 SB_DQ7 DDR_B_D8
AL26 SA_DM2 SA_DQ8 AN35 AT36 SB_DM2 SB_DQ8 AT40
DDR_A_DM3 AN22 AP33 DDR_A_D9 DDR_B_DM3 BA31 AV41 DDR_B_D9
DDR_A_DM4 SA_DM3 SA_DQ9 DDR_A_D10 DDR_B_DM4 SB_DM3 SB_DQ9 DDR_B_D10
AM14 SA_DM4 SA_DQ10 AR31 AL17 SB_DM4 SB_DQ10 AU38
DDR_A_DM5 AL9 AP31 DDR_A_D11 DDR_B_DM5 AH8 AV38 DDR_B_D11
DDR_A_DM6 SA_DM5 SA_DQ11 DDR_A_D12 DDR_B_DM6 SB_DM5 SB_DQ11 DDR_B_D12
AR3 SA_DM6 SA_DQ12 AN38 BA5 SB_DM6 SB_DQ12 AP38
DDR_A_DM7 AH4 AM36 DDR_A_D13 DDR_B_DM7 AN4 AR40 DDR_B_D13
SA_DM7 SA_DQ13 DDR_A_D14 SB_DM7 SB_DQ13 DDR_B_D14
SA_DQ14 AM34 SB_DQ14 AW38
AN33 DDR_A_D15 AY38 DDR_B_D15
SA_DQ15 DDR_A_D16 SB_DQ15 DDR_B_D16
SA_DQ16 AK26 SB_DQ16 BA38
<13> DDR_A_DQS[0..7] AL27 DDR_A_D17 <14> DDR_B_DQS[0..7] AV36 DDR_B_D17
DDR_A_DQS0 SA_DQ17 DDR_A_D18 DDR_B_DQS0 SB_DQ17 DDR_B_D18
AK33 SA_DQS0 SA_DQ18 AM26 AM39 SB_DQS0 SB_DQ18 AR36
DDR_A_DQS1 AT33 AN24 DDR_A_D19 DDR_B_DQS1 AT39 AP36 DDR_B_D19
DDR_A_DQS2 SA_DQS1 SA_DQ19 DDR_A_D20 DDR_B_DQS2 SB_DQS1 SB_DQ19 DDR_B_D20
AN28 AK28 AU35 BA36

DDR SYS MEMORY A

DDR SYS MEMORY B

DDR_A_DQS3 SA_DQS2 SA_DQ20 DDR_A_D21 DDR_B_DQS3 SB_DQS2 SB_DQ20 DDR_B_D21
AM22 SA_DQS3 SA_DQ21 AL28 AR29 SB_DQS3 SB_DQ21 AU36
C DDR_A_DQS4 DDR_A_D22 DDR_B_DQS4 DDR_B_D22 C
AN12 SA_DQS4 SA_DQ22 AM24 AR16 SB_DQS4 SB_DQ22 AP35
DDR_A_DQS5 AN8 AP26 DDR_A_D23 DDR_B_DQS5 AR10 AP34 DDR_B_D23
DDR_A_DQS6 SA_DQS5 SA_DQ23 DDR_A_D24 DDR_B_DQS6 SB_DQS5 SB_DQ23 DDR_B_D24
AP3 SA_DQS6 SA_DQ24 AP23 AR7 SB_DQS6 SB_DQ24 AY33
DDR_A_DQS7 AG5 AL22 DDR_A_D25 DDR_B_DQS7 AN5 BA33 DDR_B_D25
SA_DQS7 SA_DQ25 DDR_A_D26 SB_DQS7 SB_DQ25 DDR_B_D26
SA_DQ26 AP21 SB_DQ26 AT31
<13> DDR_A_DQS#[0..7] AN20 DDR_A_D27 <14> DDR_B_DQS#[0..7] AU29 DDR_B_D27
DDR_A_DQS#0 SA_DQ27 DDR_A_D28 DDR_B_DQS#0 SB_DQ27 DDR_B_D28
AK32 SA_DQS0# SA_DQ28 AL23 AM40 SB_DQS0# SB_DQ28 AU31
DDR_A_DQS#1 AU33 AP24 DDR_A_D29 DDR_B_DQS#1 AU39 AW31 DDR_B_D29
DDR_A_DQS#2 SA_DQS1# SA_DQ29 DDR_A_D30 DDR_B_DQS#2 SB_DQS1# SB_DQ29 DDR_B_D30
AN27 SA_DQS2# SA_DQ30 AP20 AT35 SB_DQS2# SB_DQ30 AV29
DDR_A_DQS#3 AM21 AT21 DDR_A_D31 DDR_B_DQS#3 AP29 AW29 DDR_B_D31
DDR_A_DQS#4 SA_DQS3# SA_DQ31 DDR_A_D32 DDR_B_DQS#4 SB_DQS3# SB_DQ31 DDR_B_D32
AM12 SA_DQS4# SA_DQ32 AR12 AP16 SB_DQS4# SB_DQ32 AM19
DDR_A_DQS#5 AL8 AR14 DDR_A_D33 DDR_B_DQS#5 AT10 AL19 DDR_B_D33
DDR_A_DQS#6 SA_DQS5# SA_DQ33 DDR_A_D34 DDR_B_DQS#6 SB_DQS5# SB_DQ33 DDR_B_D34
AN3 SA_DQS6# SA_DQ34 AP13 AT7 SB_DQS6# SB_DQ34 AP14
DDR_A_DQS#7 AH5 AP12 DDR_A_D35 DDR_B_DQS#7 AP5 AN14 DDR_B_D35
SA_DQS7# SA_DQ35 DDR_A_D36 SB_DQS7# SB_DQ35 DDR_B_D36
SA_DQ36 AT13 SB_DQ36 AN17
AT12 DDR_A_D37 AM16 DDR_B_D37
SA_DQ37 DDR_A_D38 SB_DQ37 DDR_B_D38
<13> DDR_A_MA[0..13] SA_DQ38 AL14 <14> DDR_B_MA[0..13] SB_DQ38 AP15
DDR_A_MA0 AY16 AL12 DDR_A_D39 DDR_B_MA0 AY23 AL15 DDR_B_D39
DDR_A_MA1 SA_MA0 SA_DQ39 DDR_A_D40 DDR_B_MA1 SB_MA0 SB_DQ39 DDR_B_D40
AU14 SA_MA1 SA_DQ40 AK9 AW24 SB_MA1 SB_DQ40 AJ11
DDR_A_MA2 AW16 AN7 DDR_A_D41 DDR_B_MA2 AY24 AH10 DDR_B_D41
DDR_A_MA3 SA_MA2 SA_DQ41 DDR_A_D42 DDR_B_MA3 SB_MA2 SB_DQ41 DDR_B_D42
BA16 SA_MA3 SA_DQ42 AK8 AR28 SB_MA3 SB_DQ42 AJ9
DDR_A_MA4 BA17 AK7 DDR_A_D43 DDR_B_MA4 AT27 AN10 DDR_B_D43
DDR_A_MA5 SA_MA4 SA_DQ43 DDR_A_D44 DDR_B_MA5 SB_MA4 SB_DQ43 DDR_B_D44
AU16 SA_MA5 SA_DQ44 AP9 AT28 SB_MA5 SB_DQ44 AK13
DDR_A_MA6 AV17 AN9 DDR_A_D45 DDR_B_MA6 AU27 AH11 DDR_B_D45
DDR_A_MA7 SA_MA6 SA_DQ45 DDR_A_D46 DDR_B_MA7 SB_MA6 SB_DQ45 DDR_B_D46
AU17 SA_MA7 SA_DQ46 AT5 AV28 SB_MA7 SB_DQ46 AK10
DDR_A_MA8 AW17 AL5 DDR_A_D47 DDR_B_MA8 AV27 AJ8 DDR_B_D47
DDR_A_MA9 SA_MA8 SA_DQ47 DDR_A_D48 DDR_B_MA9 SB_MA8 SB_DQ47 DDR_B_D48
AT16 SA_MA9 SA_DQ48 AY2 AW27 SB_MA9 SB_DQ48 BA10
DDR_A_MA10 AU13 AW2 DDR_A_D49 DDR_B_MA10 AV24 AW10 DDR_B_D49
DDR_A_MA11 SA_MA10 SA_DQ49 DDR_A_D50 DDR_B_MA11 SB_MA10 SB_DQ49 DDR_B_D50
AT17 SA_MA11 SA_DQ50 AP1 BA27 SB_MA11 SB_DQ50 BA4
DDR_A_MA12 AV20 AN2 DDR_A_D51 DDR_B_MA12 AY27 AW4 DDR_B_D51
DDR_A_MA13 SA_MA12 SA_DQ51 DDR_A_D52 DDR_B_MA13 SB_MA12 SB_DQ51 DDR_B_D52
AV12 SA_MA13 SA_DQ52 AV2 AR23 SB_MA13 SB_DQ52 AY10
AT3 DDR_A_D53 AY9 DDR_B_D53
B SA_DQ53 DDR_A_D54 SB_DQ53 DDR_B_D54 B
SA_DQ54 AN1 SB_DQ54 AW5
AL2 DDR_A_D55 AY5 DDR_B_D55
DDR_A_CAS# SA_DQ55 DDR_A_D56 DDR_B_CAS# SB_DQ55 DDR_B_D56
<13> DDR_A_CAS# AY13 SA_CAS# SA_DQ56 AG7 <14> DDR_B_CAS# AR24 SB_CAS# SB_DQ56 AV4
<13> DDR_A_RAS# DDR_A_RAS# AW14 AF9 DDR_A_D57 DDR_B_RAS# AU23 AR5 DDR_B_D57
SA_RAS# SA_DQ57 <14> DDR_B_RAS# SB_RAS# SB_DQ57
DDR_A_WE# AY14 AG4 DDR_A_D58 DDR_B_WE# AR27 AK4 DDR_B_D58
<13> DDR_A_WE# SA_WE# SA_DQ58 <14> DDR_B_WE# SB_WE# SB_DQ58
T6 PAD SA_RCVENIN# AK23 AF6 DDR_A_D59 T4 PAD SB_RCVENIN# AK16 AK3 DDR_B_D59
SA_RCVENOUT# SA_RCVENIN# SA_DQ59 DDR_A_D60 SB_RCVENOUT# SB_RCVENIN# SB_DQ59 DDR_B_D60
T12 PAD AK24 SA_RCVENOUT# SA_DQ60 AG9 T11 PAD AK18 SB_RCVENOUT# SB_DQ60 AT4
AH6 DDR_A_D61 AK5 DDR_B_D61
SA_DQ61 DDR_A_D62 SB_DQ61 DDR_B_D62
SA_DQ62 AF4 SB_DQ62 AJ5
AF8 DDR_A_D63 AJ3 DDR_B_D63
SA_DQ63 SB_DQ63
check layout check layout
CALISTOGA_FCBGA1466~D CALISTOGA_FCBGA1466~D
UMA@ UMA@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 8 of 47
5 4 3 2 1
 5 4 3 2 1

D D

R54 +1.5VS_PCIE
U14C 24.9_0402_1%
H27 D40 PEGCOMP 1 2
SDVOCTRL_DATA EXP_COMPI
H28 SDVOCTRL_CLK EXP_COMPO D38 PEG_RXN[0..15] <18>
F34 PEG_RXN0
LVDSA0+ EXP_RXN0 PEG_RXN1
<37> LVDSA0+ B37 LA_DATA0 EXP_RXN1 G38
LVDSA1+ B34 H34 PEG_RXN2
<37> LVDSA1+ LA_DATA1 EXP_RXN2
LVDSA2+ A36 J38 PEG_RXN3
<37> LVDSA2+ LA_DATA2 EXP_RXN3
L34 PEG_RXN4
LVDSA0- EXP_RXN4 PEG_RXN5
C37 LA_DATA#0 EXP_RXN5 M38
<37> LVDSA0- LVDSA1- PEG_RXN6
<37> LVDSA1- B35 LA_DATA#1 EXP_RXN6 N34
LVDSA2- A37 P38 PEG_RXN7
<37> LVDSA2- LA_DATA#2 EXP_RXN7
R34 PEG_RXN8
LVDSB0+ EXP_RXN8 PEG_RXN9
<37> LVDSB0+ F30 LB_DATA0 EXP_RXN9 T38
LVDSB1+ PEG_RXN10

LVDS
<37> LVDSB1+ D29 LB_DATA1 EXP_RXN10 V34
LVDSB2+ F28 W38 PEG_RXN11
<37> LVDSB2+ LB_DATA2 EXP_RXN11 PEG_RXN12
EXP_RXN12 Y34
LVDSB0- G30 AA38 PEG_RXN13
<37> LVDSB0- LB_DATA#0 EXP_RXN13
LVDSB1- D30 AB34 PEG_RXN14
<37> LVDSB1- LB_DATA#1 EXP_RXN14
LVDSB2- F29 AC38 PEG_RXN15
<37> LVDSB2- LB_DATA#2 EXP_RXN15 PEG_RXP[0..15] <18>
LVDSAC+ A32 D34 PEG_RXP0
<37> LVDSAC+ LA_CLK EXP_RXP0
LVDSAC- A33 F38 PEG_RXP1
<37> LVDSAC- LVDSBC+ LA_CLK# EXP_RXP1 PEG_RXP2
<37> LVDSBC+ E26 LB_CLK EXP_RXP2 G34
LVDSBC- E27 H38 PEG_RXP3
<37> LVDSBC- LB_CLK# EXP_RXP3
J34 PEG_RXP4

PCI-EXPRESS GRAPHICS
EXP_RXP4 PEG_RXP5
D32 LBKLT_CTL EXP_RXP5 L38
C GMCH_ENBKL PEG_RXP6 C
<16> GMCH_ENBKL J30 LBKLT_EN EXP_RXP6 M34
H30 N38 PEG_RXP7
LCTLA_CLK EXP_RXP7 PEG_RXP8
H29 LCTLB_DATA EXP_RXP8 P34
LDDC_CLK G26 R38 PEG_RXP9
LDDC_DATA LDDC_CLK EXP_RXP9 PEG_RXP10
G25 LDDC_DATA EXP_RXP10 T34
<16> GMCH_LVDDEN GMCH_LVDDEN F32 V38 PEG_RXP11
LVDD_EN EXP_RXP11 PEG_RXP12
2 1 B38 LIBG EXP_RXP12 W34
R53 1.5K_0402_1% C35 Y38 PEG_RXP13
LVBG EXP_RXP13 PEG_RXP14
C33 LVREFH EXP_RXP14 AA34
C32 AB38 PEG_RXP15 PEG_M_TXN[0..15] <18>
LVREFL EXP_RXP15
2 1 TV_COMPS F36 PEG_TXN0 C153 VGA@ 0.1U_0402_16V4Z PEG_M_TXN0
R207 UMA@ 150_0603_1% TV_COMPS EXP_TXN0 PEG_TXN1 C124 VGA@ 0.1U_0402_16V4Z PEG_M_TXN1
<17> TV_COMPS A16 TVDAC_A EXP_TXN1 G40
2 1 TV_LUMA <17> TV_LUMA TV_LUMA C18 H36 PEG_TXN2 C142 VGA@ 0.1U_0402_16V4Z PEG_M_TXN2
R208 UMA@ 150_0603_1% TV_CRMA TVDAC_B EXP_TXN2 PEG_TXN3 C115 VGA@ 0.1U_0402_16V4Z PEG_M_TXN3
<17> TV_CRMA A19 TVDAC_C EXP_TXN3 J40

TV
2 1 TV_CRMA L36 PEG_TXN4 C155 VGA@ 0.1U_0402_16V4Z PEG_M_TXN4
R209 UMA@ 150_0603_1% EXP_TXN4
2 R42 1 J20 TV_IREF EXP_TXN5 M40 PEG_TXN5 C126 VGA@ 0.1U_0402_16V4Z PEG_M_TXN5
4.99K_0402_1% N36 PEG_TXN6 C148 VGA@ 0.1U_0402_16V4Z PEG_M_TXN6
EXP_TXN6 PEG_TXN7 C117 VGA@ 0.1U_0402_16V4Z PEG_M_TXN7
B16 TV_IRTNA EXP_TXN7 P40
B18 R36 PEG_TXN8 C157 VGA@ 0.1U_0402_16V4Z PEG_M_TXN8
TV_IRTNB EXP_TXN8 PEG_TXN9 C128 VGA@ 0.1U_0402_16V4Z PEG_M_TXN9
B19 TV_IRTNC EXP_TXN9 T40
V36 PEG_TXN10 C140 VGA@ 0.1U_0402_16V4Z PEG_M_TXN10
EXP_TXN10 PEG_TXN11 C119 VGA@ 0.1U_0402_16V4Z PEG_M_TXN11
J29 TV_DCONSEL1 EXP_TXN11 W40
K30 Y36 PEG_TXN12 C159 VGA@ 0.1U_0402_16V4Z PEG_M_TXN12
TV_DCONSEL0 EXP_TXN12 PEG_TXN13 C130 VGA@ 0.1U_0402_16V4Z PEG_M_TXN13
EXP_TXN13 AA40
AB36 PEG_TXN14 C144 VGA@ 0.1U_0402_16V4Z PEG_M_TXN14
EXP_TXN14 PEG_TXN15 C121 VGA@ 0.1U_0402_16V4Z PEG_M_TXN15
EXP_TXN15 AC40 PEG_M_TXP[0..15] <18>
3VDDCCL C26
<17> 3VDDCCL DDCCLK
CRT

3VDDCDA C25 D36 PEG_TXP0 C152 VGA@ 0.1U_0402_16V4Z PEG_M_TXP0

<17> 3VDDCDA DDCDATA EXP_TXP0
F40 PEG_TXP1 C123 VGA@ 0.1U_0402_16V4Z PEG_M_TXP1
CRT_VSYNC EXP_TXP1 PEG_TXP2 C141 VGA@ 0.1U_0402_16V4Z PEG_M_TXP2
<17> CRT_VSYNC H23 VSYNC EXP_TXP2 G36
<17> CRT_HSYNC CRT_HSYNC G23 H40 PEG_TXP3 C114 VGA@ 0.1U_0402_16V4Z PEG_M_TXP3
B CRT_B HSYNC EXP_TXP3 PEG_TXP4 C154 VGA@ 0.1U_0402_16V4Z PEG_M_TXP4 B
<17> CRT_B E23 BLUE EXP_TXP4 J36
2 1 CRT_R D23 L40 PEG_TXP5 C125 VGA@ 0.1U_0402_16V4Z PEG_M_TXP5
R210 UMA@ 150_0603_1% CRT_G BLUE# EXP_TXP5 PEG_TXP6 C147 VGA@ 0.1U_0402_16V4Z PEG_M_TXP6
<17> CRT_G C22 GREEN EXP_TXP6 M36
2 1 CRT_G B22 N40 PEG_TXP7 C116 VGA@ 0.1U_0402_16V4Z PEG_M_TXP7
R211 UMA@ 150_0603_1% CRT_R GREEN# EXP_TXP7 PEG_TXP8 C156 VGA@ 0.1U_0402_16V4Z PEG_M_TXP8
<17> CRT_R A21 RED EXP_TXP8 P36
2 1 CRT_B B21 R40 PEG_TXP9 C127 VGA@ 0.1U_0402_16V4Z PEG_M_TXP9
R212 UMA@ 150_0603_1% RED# EXP_TXP9 PEG_TXP10 C139 VGA@ 0.1U_0402_16V4Z PEG_M_TXP10
EXP_TXP10 T36
V40 PEG_TXP11 C118 VGA@ 0.1U_0402_16V4Z PEG_M_TXP11
EXP_TXP11 PEG_TXP12 PEG_M_TXP12
2 R47 1 J22 CRT_IREF EXP_TXP12 W36 C158 VGA@ 0.1U_0402_16V4Z
255_0402_1% Y40 PEG_TXP13 C129 VGA@ 0.1U_0402_16V4Z PEG_M_TXP13
EXP_TXP13 PEG_TXP14 C143 VGA@ 0.1U_0402_16V4Z PEG_M_TXP14
EXP_TXP14 AA36
AB40 PEG_TXP15 C120 VGA@ 0.1U_0402_16V4Z PEG_M_TXP15
EXP_TXP15

CALISTOGA_FCBGA1466~D
UMA@
+2.5VS +3VS
2.2K_0402_5%

2.2K_0402_5%
1

1
UMA@

R215

R216

R214 R217
UMA@

2.2K_0402_5% 2.2K_0402_5%
UMA@ UMA@
2

2
S

LDDC_CLK 3 1 EDID_CLK_LCD
EDID_CLK_LCD <37>
Q18
BSS138_SOT23
UMA@
G
2

A A
+2.5VS
2
G

LDDC_DATA 3 1 EDID_DAT_LCD
EDID_DAT_LCD <37>
S

Q17
BSS138_SOT23
UMA@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 9 of 47
5 4 3 2 1
 5 4 3 2 1

+VCCP
2

D13 +2.5VS
D D
@ CH751H-40_SC76 U14H
1 1

+VCCP H22 1 2
VCC_SYNC C306
R221 +2.5VS AC14 0.1U_0402_16V4Z
VTT0
AB14 VTT1 VCCTX_LVDS0 B30 +2.5VS
@ 10_0402_5% W14 C30
VTT2 VCCTX_LVDS1 +1.5VS_PCIE R57
V14 A30
2

VTT3 VCCTX_LVDS2 0_0805_5%

T14
R14
VTT4
VTT5 VCC3G0 AB41 W=40 mils 2 1 +1.5VS

10U_1206_6.3V6M

10U_1206_6.3V6M
P14 VTT6 VCC3G1 AJ41
+1.5VS

220U_D2_4VM
N14 VTT7 VCC3G2 L41 1
M14 VTT8 VCC3G3 N41 1 1

C108
L14 R41 +
VTT9 VCC3G4
2

+2.5VS

C107

C105

0.1U_0402_16V4Z
AD13 VTT10 VCC3G5 V41
220U_D2_4VM

D12 AC13 Y41

VTT11 VCC3G6 2 2 2
AB13 VTT12 1
@ CH751H-40_SC76 1 AA13 AC33 +1.5VS_3GPLL
VTT13 VCCA_3GPLL

C99
Y13 G41 +2.5VS
1 1

VTT14 VCCA_3GBG
C91

+ W13 H41
VTT15 VSSA_3GBG 2 +1.5VS_DPLLA +1.5VS_DPLLB
V13 VTT16
R220 +3VS U13 L4 FBM-11-160808-601-T_0603 L16 L5
2 VTT17 +2.5VS_CRTDAC
T13 VTT18 VCCA_CRTDAC0 E21 1 2 +2.5VS 1 2 +1.5VS 1 2 +1.5VS

2200P_0402_50V7K
@ 10_0402_5% R13 F21 FBM-L10-160808-301-T_0603 FBM-L10-160808-301-T_0603
VTT19 VCCA_CRTDAC1

0.1U_0402_16V4Z

330U_D2E_2.5VM

UMA@ C300

0.1U_0402_16V4Z

330U_D2E_2.5VM

UMA@ C100
0.1U_0402_16V4Z
N13 G21 close pin G41
2

VTT20 VSSA_CRTDAC2
M13 VTT21 1 1 1 1
L13 VTT22 1 1

C72

C71

C82

C101
+ +
AB12 VTT23 VCCA_DPLLA B26 +1.5VS_DPLLA CRTDAC: Route caps within
AA12 VTT24 VCCA_DPLLB C39 +1.5VS_DPLLB
Y12 VTT25 VCCA_HPLL AF1 +1.5VS_HPLL
2 2 250mil of Alviso. Route FB
W12 2 2 2 2
VTT26 within 3" of Calistoga
V12 VTT27
U12 VTT28 VCCA_LVDS A38 +2.5VS
T12 VTT29 VSSA_LVDS B39
C
R12 VTT30 C
P12 +2.5VS
VTT31
N12 AF2
M12
VTT32
VTT33
P O W E R VCCA_MPLL +1.5VS_MPLL
+3VS_TVDACA +3VS_TVDACA +3VS_TVDACA +3VS

0.01U_0402_16V7K
4.7U_0805_10V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z
L12 VTT34 VCCA_TVBG H20 +3VS_TVBG
R11 G20 R206
VTT35 VSSA_TVBG
1 1 P11 VTT36 2 1
C24

C50

2200P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K
N11 1 1 0_0603_5%
VTT37

C304

C102

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
M11 VTT38 VCCA_TVDACA0 E19 +3VS_TVDACA
R10 VTT39 VCCA_TVDACA1 F19 1 1 1 1 1 1
2 2
P10 VTT40 VCCA_TVDACB0 C20 +3VS_TVDACA 2 2

C55

C54

C58

C45

C46
C297
N10 VTT41 VCCA_TVDACB1 D20
M10 VTT42 VCCA_TVDACC0 E20 +3VS_TVDACA 2 2 2 2 2 2
P9 VTT43 VCCA_TVDACC1 F20
N9 VTT44
M9 VTT45 close pin A38
R8 VTT46 VCCD_HMPLL0 AH1 +1.5VS
P8 VTT47 VCCD_HMPLL1 AH2
N8 VTT48
M8 +3VS_TVBG +3VS
VTT49 R205
P7 VTT50 VCCD_LVDS0 A28
N7 VTT51 VCCD_LVDS1 B28 2 1
M7 C28 0_0805_5%
VTT52 VCCD_LVDS2

2200P_0402_50V7K

0.1U_0402_16V4Z
R6 VTT53
P6 VTT54 VCCD_TVDAC D21 +1.5VS_TVDAC 1 1
M6 VTT55 VCCDQ_TVDAC H19

C49
MCH_A6 A6 VTT56

C63
0.47U_0603_10V7K

R5 VTT57 VCCHV0 A23 +3VS 2 2

P5 VTT58 VCCHV1 B23
0.1U_0402_16V4Z

10U_1206_6.3V6M

1 N5 VTT59 VCCHV2 B25

C296

M5 VTT60 1 1
P4 VTT61 VCCAUX0 AK31
N4 VTT62 VCCAUX1 AF31
2
C302

C298

M4 VTT63 VCCAUX2 AE31

2 2
R3 VTT64 VCCAUX3 AC31
B P3 AL30 B
N3
VTT65
VTT66
VCCAUX4
VCCAUX5 AK30 PCI-E/MEM/PSB PLL decoupling
0.22U_0603_10V7K

M3 VTT67 VCCAUX6 AJ30

R2 AH30 +1.5VS
VTT68 VCCAUX7
P2 VTT69 VCCAUX8 AG30
+1.5VS_3GPLL +1.5VS +1.5VS_TVDAC +1.5VS
0.1U_0402_16V4Z

1 M2 AF30 R56 R213

VTT70 VCCAUX9
C94

MCH_D2 D2 AE30 0_0603_5% 0_0603_5%

VTT71 VCCAUX10
AB1 VTT72 VCCAUX11 AD30 1 2 1 2 1
0.22U_0603_10V7K

2200P_0402_50V7K
0.1U_0402_16V4Z

10U_1206_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R1 AC30
MCH_AB1

2 VTT73 VCCAUX12
C299

1 P1 VTT74 VCCAUX13 AG29

C12

N1 VTT75 VCCAUX14 AF29 1 1 1 1 1 1

2
0.47U_0603_10V7K

M1 VTT76 VCCAUX15 AE29

C97

C98

C67

C37
C104

C301
VCCAUX16 AD29
2
1 VCCAUX17 AC29
2 2 2 2 2 2
C10

VCCAUX18 AG28
VCCAUX19 AF28
AE28 @ @
2 VCCAUX20
VCCAUX21 AH22
VCCAUX22 AJ21
AG14 VCCAUX32 VCCAUX23 AH21
AF14 VCCAUX33 VCCAUX24 AJ20
AE14 VCCAUX34 VCCAUX25 AH20
Y14 VCCAUX35 VCCAUX26 AH19
+1.5VS_MPLL R16 +1.5VS_HPLL R17
AF13 VCCAUX36 VCCAUX27 P19
AE13 P16 0_0603_5% 0_0603_5%
+1.5VS VCCAUX37 VCCAUX28
AF12 VCCAUX38 VCCAUX29 AH15 45mA Max. 2 1 +1.5VS 45mA Max. 2 1 +1.5VS
AE12 VCCAUX39 VCCAUX30 P15

0.1U_0402_16V4Z

10U_1206_6.3V6M

0.1U_0402_16V4Z

10U_1206_6.3V6M
AD12 VCCAUX40 VCCAUX31 AH14

1 1 1 1
CALISTOGA_FCBGA1466~D

C13

C14
C8

C9
UMA@
2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
Size Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: P, 21, 2006 Sheet 10 of 47
5 4 3 2 1
 5 4 3 2 1

Strap Pin Table

CFG[3:17] have internal pull up

U14F CFG[19:18] have internal pull down

+VCCP +1.5VS +VCCP U14G +1.8V

AD27 VCC_NCTF0 VCCAUX_NCTF0 AG27 AA33 VCC0 VCC_SM0 AU41 011 = 667MT/s FSB
AC27 AF27 W33 AT41 MCH_AT41 CFG[2:0] 001 = 533MT/s FSB
VCC_NCTF1 VCCAUX_NCTF1 VCC1 VCC_SM1 MCH_AM41
AB27 VCC_NCTF2 VCCAUX_NCTF2 AG26 P33 VCC2 VCC_SM2 AM41
AA27 VCC_NCTF3 VCCAUX_NCTF3 AF26 N33 VCC3 VCC_SM3 AU40 0 = DMI x 2

0.47U_0603_10V7K

0.47U_0603_10V7K
Y27 VCC_NCTF4 VCCAUX_NCTF4 AG25 L33 VCC4 VCC_SM4 BA34 CFG5 1 = DMI x 4 *(Default)
W27 VCC_NCTF5 VCCAUX_NCTF5 AF25 J33 VCC5 VCC_SM5 AY34
V27 VCC_NCTF6 VCCAUX_NCTF6 AG24 AA32 VCC6 VCC_SM6 AW34 1 1 0 = Reserved

C106
D D
U27 VCC_NCTF7 VCCAUX_NCTF7 AF24 Y32 VCC7 VCC_SM7 AV34 CFG7 1 = Mobile Yonah CPU*(Default)

C103
T27 VCC_NCTF8 VCCAUX_NCTF8 AG23 W32 VCC8 VCC_SM8 AU34
0.22U_0603_10V7K

0.22U_0603_10V7K

0.22U_0603_10V7K

R27 VCC_NCTF9 VCCAUX_NCTF9 AF23 V32 VCC9 VCC_SM9 AT34

2 2 0 = Lane Reversal Enable
AD26 VCC_NCTF10 VCCAUX_NCTF10 AG22 P32 VCC10 VCC_SM10 AR34 CFG9 1 = Normal Operation (Default)*
1 1 1 AC26 VCC_NCTF11 VCCAUX_NCTF11 AF22 N32 VCC11 VCC_SM11 BA30
AB26 VCC_NCTF12 VCCAUX_NCTF12 AG21 M32 VCC12 VCC_SM12 AY30
C69

C61

C25

AA26 VCC_NCTF13 VCCAUX_NCTF13 AF21 L32 VCC13 VCC_SM13 AW30 CFG6 0 = Reserved
Y26 VCC_NCTF14 VCCAUX_NCTF14 AG20 J32 VCC14 VCC_SM14 AV30
2 2 2
W26 VCC_NCTF15 VCCAUX_NCTF15 AF20 AA31 VCC15 VCC_SM15 AU30 PSB 4X CLK Enable 1 = Calistoga *
V26 VCC_NCTF16 VCCAUX_NCTF16 AG19 W31 VCC16 VCC_SM16 AT30
U26 VCC_NCTF17 VCCAUX_NCTF17 AF19 V31 VCC17 VCC_SM17 AR30 Place near pin AT41 & AM41
T26 VCC_NCTF18 VCCAUX_NCTF18 R19 T31 VCC18 VCC_SM18 AP30 00 = Reserved
R26 VCC_NCTF19 VCCAUX_NCTF19 AG18 R31 VCC19 VCC_SM19 AN30 CFG[13:12] 01 = XOR Mode Enabled
AD25 VCC_NCTF20 VCCAUX_NCTF20 AF18 P31 VCC20 VCC_SM20 AM30 10 = All Z Mode Enabled
AC25 VCC_NCTF21 VCCAUX_NCTF21 R18 N31 VCC21 VCC_SM21 AM29 11 = Normal Operation *(Default)
AB25 VCC_NCTF22 VCCAUX_NCTF22 AG17 M31 VCC22 VCC_SM22 AL29
AA25 VCC_NCTF23 VCCAUX_NCTF23 AF17 AA30 VCC23 VCC_SM23 AK29 0 = Dynamic ODT Disabled
Y25 VCC_NCTF24 VCCAUX_NCTF24 AE17 Y30 VCC24 VCC_SM24 AJ29 CFG16 1 = Dynamic ODT Enabled *(Default)
W25 VCC_NCTF25 VCCAUX_NCTF25 AD17 W30 VCC25 VCC_SM25 AH29

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
V25 VCC_NCTF26 VCCAUX_NCTF26 AB17 V30 VCC26 VCC_SM26 AJ28 10 = 1.05V*(Default)
U25 VCC_NCTF27 VCCAUX_NCTF27 AA17 U30 VCC27 VCC_SM27 AH28 CFG10 CFG18 01 = 1.5V
1U_0603_10V4Z
10U_1206_6.3V6M

10U_1206_6.3V6M

T25 W17 T30 AJ27

P O W E R
VCC_NCTF28 VCCAUX_NCTF28 VCC28 VCC_SM28 1 1 1 1
R25 VCC_NCTF29 VCCAUX_NCTF29 V17 R30 VCC29 VCC_SM29 AH27 0 = Normal Operation * (Default)

C21

C20

C86

C47
1 1 1 AD24 VCC_NCTF30 VCCAUX_NCTF30 T17 P30 VCC30 VCC_SM30 BA26 CFG19 1 = DMI Lane Reversal Enable
AC24 VCC_NCTF31 VCCAUX_NCTF31 R17 N30 VCC31 VCC_SM31 AY26
2 2 2 2
C48

C95

C31

AB24 VCC_NCTF32 VCCAUX_NCTF32 AG16 M30 VCC32 P O W E R VCC_SM32 AW26 0 = No SDVO Device Present *
2 2 2
AA24 VCC_NCTF33 VCCAUX_NCTF33 AF16 L30 VCC33 VCC_SM33 AV26 (Default)
Y24 VCC_NCTF34 VCCAUX_NCTF34 AE16 AA29 VCC34 VCC_SM34 AU26 SDVO_CTRLDATA
W24 VCC_NCTF35 VCCAUX_NCTF35 AD16 Y29 VCC35 VCC_SM35 AT26 1 = SDVO Device Present
V24 VCC_NCTF36 VCCAUX_NCTF36 AC16 W29 VCC36 VCC_SM36 AR26
U24 VCC_NCTF37 VCCAUX_NCTF37 AB16 V29 VCC37 VCC_SM37 AJ26
C
T24 VCC_NCTF38 VCCAUX_NCTF38 AA16 U29 VCC38 VCC_SM38 AH26 0 = Only PCIE or SDVO is C
R24 VCC_NCTF39 VCCAUX_NCTF39 Y16 R29 VCC39 VCC_SM39 AJ25 CFG20 operational. *(Default)
AD23 VCC_NCTF40 VCCAUX_NCTF40 W16 P29 VCC40 VCC_SM40 AH25
V23 VCC_NCTF41 VCCAUX_NCTF41 V16 M29 VCC41 VCC_SM41 AJ24 (PCIE/SDVO select) 1 = PCIE/SDVO are operating
U23 U16 L29 AH24
T23
VCC_NCTF42 VCCAUX_NCTF42
T16 AB28
VCC42 VCC_SM42
BA23 simu.
VCC_NCTF43 VCCAUX_NCTF43 VCC43 VCC_SM43
R23 VCC_NCTF44 VCCAUX_NCTF44 R16 AA28 VCC44 VCC_SM44 AJ23

0.47U_0603_10V7K
220U_D2_4VM

AD22 VCC_NCTF45 VCCAUX_NCTF45 AG15 Y28 VCC45 VCC_SM45 BA22

V22 VCC_NCTF46 VCCAUX_NCTF46 AF15 V28 VCC46 VCC_SM46 AY22
1 U22 VCC_NCTF47 VCCAUX_NCTF47 AE15 U28 VCC47 VCC_SM47 AW22 1
T22 VCC_NCTF48 VCCAUX_NCTF48 AD15 T28 VCC48 VCC_SM48 AV22

C27
+ R22 AC15 R28 AU22
VCC_NCTF49 VCCAUX_NCTF49 VCC49 VCC_SM49
C18

AD21 VCC_NCTF50 VCCAUX_NCTF50 AB15 P28 VCC50 VCC_SM50 AT22

2 R32
V21 VCC_NCTF51 VCCAUX_NCTF51 AA15 N28 VCC51 VCC_SM51 AR22 <7> CFG5 1 2 @ 2.2K_0402_5%
2
U21 VCC_NCTF52 VCCAUX_NCTF52 Y15 M28 VCC52 VCC_SM52 AP22
T21 W15 L28 AK22 R40 1 2 @ 2.2K_0402_5%
VCC_NCTF53 VCCAUX_NCTF53 VCC53 VCC_SM53 <7> CFG7
R21 VCC_NCTF54 VCCAUX_NCTF54 V15 P27 VCC54 VCC_SM54 AJ22
AD20 U15 N27 AK21 R37 1 2 @ 2.2K_0402_5%
VCC_NCTF55 VCCAUX_NCTF55 VCC55 VCC_SM55 <7> CFG9
V20 VCC_NCTF56 VCCAUX_NCTF56 T15 M27 VCC56 VCC_SM56 AK20 Place near pin BA23
U20 R15 L27 BA19 R35 1 2 @ 2.2K_0402_5%
VCC_NCTF57 VCCAUX_NCTF57 VCC57 VCC_SM57 <7> CFG11
T20 VCC_NCTF58 P26 VCC58 VCC_SM58 AY19

@ 220U_D2_4M_R45
10U_1206_6.3V6M

10U_1206_6.3V6M
R20 N26 AW19 R34 1 2 @ 2.2K_0402_5%
VCC_NCTF59 VCC59 VCC_SM59 <7> CFG12
AD19 VCC_NCTF60 VSS_NCTF0 AE27 L26 VCC60 VCC_SM60 AV19 1
V19 AE26 N25 AU19 1 1 R38 1 2 @ 2.2K_0402_5%
VCC_NCTF61 VSS_NCTF1 VCC61 VCC_SM61 + <7> CFG13
U19 VCC_NCTF62 VSS_NCTF2 AE25 M25 VCC62 VCC_SM62 AT19

C44

C78

C59
@ 220U_D2_4VM

T19 AE24 L25 AR19 R33 1 2 @ 2.2K_0402_5%

VCC_NCTF63 VSS_NCTF3 VCC63 VCC_SM63 <7> CFG16
1 AD18 VCC_NCTF64 VSS_NCTF4 AE23 P24 VCC64 VCC_SM64 AP19
2 2 2
AC18 VCC_NCTF65 VSS_NCTF5 AE22 N24 VCC65 VCC_SM65 AK19
+ AB18 AE21 M24 AJ19
VCC_NCTF66 VSS_NCTF6 VCC66 VCC_SM66
C79

AA18 VCC_NCTF67 VSS_NCTF7 AE20 AB23 VCC67 VCC_SM67 AJ18

Y18 VCC_NCTF68 VSS_NCTF8 AE19 AA23 VCC68 VCC_SM68 AJ17
2
W18 VCC_NCTF69 VSS_NCTF9 AE18 Y23 VCC69 VCC_SM69 AH17
V18 VCC_NCTF70 VSS_NCTF10 AC17 P23 VCC70 VCC_SM70 AJ16
B
U18 Y17 N23 AH16 +3VS B
VCC_NCTF71 VSS_NCTF11 VCC71 VCC_SM71
T18 VCC_NCTF72 VSS_NCTF12 U17 M23 VCC72 VCC_SM72 BA15
L23 VCC73 VCC_SM73 AY15
+VCCP

0.47U_0603_10V7K
AC22 AW15 R48 1 2 @ 1K_0402_5%
+1.8V VCC74 VCC_SM74 <7> CFG18
M19 AB22 AV15 R50 1 2 @ 1K_0402_5%
VCC100 VCC75 VCC_SM75 <7> CFG19
L19 AR6 Y22 AU15 1 R51 1 2 @ 1K_0402_5%
VCC101 VCC_SM100 VCC76 VCC_SM76 <7> CFG20
N18 VCC102 VCC_SM101 AP6 W22 VCC77 VCC_SM77 AT15

C93
M18 VCC103 VCC_SM102 AN6 P22 VCC78 VCC_SM78 AR15
L18 VCC104 VCC_SM103 AL6 N22 VCC79 VCC_SM79 AJ15
2
P17 VCC105 VCC_SM104 AK6 M22 VCC80 VCC_SM80 AJ14
N17 VCC106 VCC_SM105 AJ6 L22 VCC81 VCC_SM81 AJ13
M17 VCC107 VCC_SM106 AV1 AC21 VCC82 VCC_SM82 AH13
N16 VCC108 VCC_SM107 AJ1 AA21 VCC83 VCC_SM83 AK12
M16 VCC109 W21 VCC84 VCC_SM84 AJ12
0.47U_0603_10V7K

0.47U_0603_10V7K

L16 VCC110 N21 VCC85 VCC_SM85 AH12

M21 VCC86 VCC_SM86 AG12 Place near pin BA15
1 1 L21 VCC87 VCC_SM87 AK11
CALISTOGA_FCBGA1466~D AC20 BA8
VCC88 VCC_SM88
C15

C17

UMA@ AB20 VCC89 VCC_SM89 AY8

Y20 VCC90 VCC_SM90 AW8
2 2
W20 VCC91 VCC_SM91 AV8
P20 VCC92 VCC_SM92 AT8
N20 VCC93 VCC_SM93 AR8
M20 VCC94 VCC_SM94 AP8
L20 VCC95 VCC_SM95 BA6
AB19 VCC96 VCC_SM96 AY6
Place near pin AV1 & AJ1 AA19 VCC97 VCC_SM97 AW6
Y19 VCC98 VCC_SM98 AV6
N19 VCC99 VCC_SM99 AT6

CALISTOGA_FCBGA1466~D
A A
UMA@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 11 of 47
5 4 3 2 1
 5 4 3 2 1

U14I U14J
AC41 VSS0 VSS100 AE34 AN21 VSS200 VSS280 AG10
AA41 VSS1 VSS101 AC34 AL21 VSS201 VSS281 AC10
W41 VSS2 VSS102 C34 AB21 VSS202 VSS282 W10
T41 VSS3 VSS103 AW33 Y21 VSS203 VSS283 U10
P41 VSS4 VSS104 AV33 P21 VSS204 VSS284 BA9
M41 VSS5 VSS105 AR33 K21 VSS205 VSS285 AW9
D D
J41 VSS6 VSS106 AE33 J21 VSS206 VSS286 AR9
F41 VSS7 VSS107 AB33 H21 VSS207 VSS287 AH9
AV40 VSS8 VSS108 Y33 C21 VSS208 VSS288 AB9
AP40 VSS9 VSS109 V33 AW20 VSS209 VSS289 Y9
AN40 VSS10 VSS110 T33 AR20 VSS210 VSS290 R9
AK40 VSS11 VSS111 R33 AM20 VSS211 VSS292 G9
AJ40 VSS12 VSS112 M33 AA20 VSS212 VSS291 E9
AH40 VSS13 VSS113 H33 K20 VSS213 VSS293 A9
AG40 VSS14 VSS114 G33 B20 VSS214 VSS294 AG8
AF40 VSS15 VSS115 F33 A20 VSS215 VSS295 AD8
AE40 VSS16 VSS116 D33 AN19 VSS216 VSS296 AA8
B40 VSS17 VSS117 B33 AC19 VSS217 VSS297 U8
AY39 VSS18 VSS118 AH32 W19 VSS218 VSS298 K8
AW39 VSS19 VSS119 AG32 K19 VSS219 VSS299 C8
AV39 VSS20 VSS120 AF32 G19 VSS220 VSS300 BA7
AR39 VSS21 VSS121 AE32 C19 VSS221 VSS301 AV7
AN39 VSS22 VSS122 AC32 AH18 VSS222 VSS302 AP7
AJ39 VSS23 VSS123 AB32 P18 VSS223 VSS303 AL7
AC39 VSS24 VSS124 G32 H18 VSS224 VSS304 AJ7
AB39 VSS25 VSS125 B32 D18 VSS225 VSS305 AH7
AA39 VSS26 VSS126 AY31 A18 VSS226 VSS306 AF7
Y39 VSS27 VSS127 AV31 AY17 VSS227 VSS307 AC7
W39 VSS28 VSS128 AN31 AR17 VSS228 VSS308 R7
V39 AJ31 AP17 G7
T39
VSS29
VSS30
VSS129
VSS130 AG31 AM17
VSS229
VSS230
P O W E R VSS309
VSS310 D7
R39 VSS31 VSS131 AB31 AK17 VSS231 VSS311 AG6
P39 VSS32 VSS132 Y31 AV16 VSS232 VSS312 AD6
N39 VSS33 VSS133 AB30 AN16 VSS233 VSS313 AB6
M39 E30 AL16 Y6
L39
VSS34
VSS35
P O W E R VSS134
VSS135 AT29 J16
VSS234
VSS235
VSS314
VSS315 U6
J39 VSS36 VSS136 AN29 F16 VSS236 VSS316 N6
H39 VSS37 VSS137 AB29 C16 VSS237 VSS317 K6
C C
G39 VSS38 VSS138 T29 AN15 VSS238 VSS318 H6
F39 VSS39 VSS139 N29 AM15 VSS239 VSS319 B6
D39 VSS40 VSS140 K29 AK15 VSS240 VSS320 AV5
AT38 VSS41 VSS141 G29 N15 VSS241 VSS321 AF5
AM38 VSS42 VSS142 E29 M15 VSS242 VSS322 AD5
AH38 VSS43 VSS143 C29 L15 VSS243 VSS323 AY4
AG38 VSS44 VSS144 B29 B15 VSS244 VSS324 AR4
AF38 VSS45 VSS145 A29 A15 VSS245 VSS325 AP4
AE38 VSS46 VSS146 BA28 BA14 VSS246 VSS326 AL4
C38 VSS47 VSS147 AW28 AT14 VSS247 VSS327 AJ4
AK37 VSS48 VSS148 AU28 AK14 VSS248 VSS328 Y4
AH37 VSS49 VSS149 AP28 AD14 VSS249 VSS329 U4
AB37 VSS50 VSS150 AM28 AA14 VSS250 VSS330 R4
AA37 VSS51 VSS151 AD28 U14 VSS251 VSS331 J4
Y37 VSS52 VSS152 AC28 K14 VSS252 VSS332 F4
W37 VSS53 VSS153 W28 H14 VSS253 VSS333 C4
V37 VSS54 VSS154 J28 E14 VSS254 VSS334 AY3
T37 VSS55 VSS155 E28 AV13 VSS255 VSS335 AW3
R37 VSS56 VSS156 AP27 AR13 VSS256 VSS336 AV3
P37 VSS57 VSS157 AM27 AN13 VSS257 VSS337 AL3
N37 VSS58 VSS158 AK27 AM13 VSS258 VSS338 AH3
M37 VSS59 VSS159 J27 AL13 VSS259 VSS339 AG3
L37 VSS60 VSS160 G27 AG13 VSS260 VSS340 AF3
J37 VSS61 VSS161 F27 P13 VSS261 VSS341 AD3
H37 VSS62 VSS162 C27 F13 VSS262 VSS342 AC3
G37 VSS63 VSS163 B27 D13 VSS265 VSS343 AA3
F37 VSS64 VSS164 AN26 B13 VSS264 VSS344 G3
D37 VSS65 VSS165 M26 AY12 VSS263 VSS345 AT2
AY36 VSS66 VSS166 K26 AC12 VSS266 VSS346 AR2
AW36 VSS67 VSS167 F26 K12 VSS267 VSS347 AP2
AN36 VSS68 VSS168 D26 H12 VSS268 VSS348 AK2
AH36 VSS69 VSS169 AK25 E12 VSS269 VSS349 AJ2
B B
AG36 VSS70 VSS170 P25 AD11 VSS270 VSS350 AD2
AF36 VSS71 VSS171 K25 AA11 VSS271 VSS351 AB2
AE36 VSS72 VSS172 H25 Y11 VSS272 VSS352 Y2
AC36 VSS73 VSS173 E25 J11 VSS273 VSS353 U2
C36 VSS74 VSS174 D25 D11 VSS274 VSS354 T2
B36 VSS75 VSS175 A25 B11 VSS275 VSS355 N2
BA35 VSS76 VSS176 BA24 AV10 VSS276 VSS356 J2
AV35 VSS77 VSS177 AU24 AP10 VSS277 VSS357 H2
AR35 VSS78 VSS178 AL24 AL10 VSS278 VSS358 F2
AH35 VSS79 VSS179 AW23 AJ10 VSS279 VSS359 C2
AB35 VSS80 VSS180 AT23 VSS360 AL1
AA35 VSS81 VSS181 AN23
Y35 AM23 CALISTOGA_FCBGA1466~D
VSS82 VSS182
W35 VSS83 VSS183 AH23 UMA@
V35 VSS84 VSS184 AC23
T35 VSS85 VSS185 W23
R35 VSS86 VSS186 K23
P35 VSS87 VSS187 J23
N35 VSS88 VSS188 F23
M35 VSS89 VSS189 C23
L35 VSS90 VSS190 AA22
J35 VSS91 VSS191 K22
H35 VSS92 VSS192 G22
G35 VSS93 VSS193 F22
F35 VSS94 VSS194 E22
D35 VSS95 VSS195 D22
AN34 VSS96 VSS196 A22
AK34 VSS97 VSS197 BA21
AG34 VSS98 VSS198 AV21
AF34 VSS99 VSS199 AR21

CALISTOGA_FCBGA1466~D
A A
UMA@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 12 of 47
5 4 3 2 1
 5 4 3 2 1

Layout Note: +1.8V +1.8V

+DDR_MCH_REF
<8> DDR_A_DQS#[0..7]
trace width and +DDR_MCH_REF1
+DDR_MCH_REF1 <14>
spacing is 20/20.
<8> DDR_A_D[0..63] JP3

2.2U_0805_16V4Z

0.1U_0402_16V4Z
1 VREF VSS 2
3 4 DDR_A_D6 1 1
<8> DDR_A_DM[0..7] +1.8V VSS DQ4

C145

C134
DDR_A_D4 5 6 DDR_A_D0
DDR_A_D1 DQ0 DQ5
<8> DDR_A_DQS[0..7] 7 DQ1 VSS 8
9 10 DDR_A_DM0
VSS DM0

1
DDR_A_DQS#0 2 2
<8> DDR_A_MA[0..13] 11 DQS0# VSS 12
R86 DDR_A_DQS0 13 14 DDR_A_D5
DQS0 DQ6 DDR_A_D7
15 VSS DQ7 16
100_0402_1% DDR_A_D2 17 18
D DDR_A_D3 DQ2 VSS DDR_A_D13 D
19 20

2
+DDR_MCH_REF1 DQ3 DQ12 DDR_A_D12
<14> +DDR_MCH_REF1 21 VSS DQ13 22

0.1U_0402_16V4Z
DDR_A_D8 23 24
DQ8 VSS

1
Layout Note: DDR_A_D14 25 26 DDR_A_DM1
R87 DQ9 DM1
1 27 VSS VSS 28
Place near JP41 DDR_A_DQS#1 29 30 M_CLK_DDR0
M_CLK_DDR0 <7>
DQS1# CK0

C149
100_0402_1% DDR_A_DQS1 31 32 M_CLK_DDR#0
DQS1 CK0# M_CLK_DDR#0 <7>
33 34

2
2 DDR_A_D9 VSS VSS DDR_A_D11
35 DQ10 DQ14 36
DDR_A_D15 37 38 DDR_A_D10
DQ11 DQ15
39 VSS VSS 40

+1.8V 41 42
DDR_A_D16 VSS VSS DDR_A_D20
43 DQ16 DQ20 44
DDR_A_D17 45 46 DDR_A_D21
DQ17 DQ21
47 VSS VSS 48
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_A_DQS#2 49 50
DQS2# NC PM_EXTTS#0 <7,14>
1 1 1 1 1 1 1 1 1 DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2
C89

C87

C28

C92

C30

C85

C57

C43

C83
53 VSS VSS 54
DDR_A_D18 55 56 DDR_A_D23
DDR_A_D19 DQ18 DQ22 DDR_A_D22
57 DQ19 DQ23 58
2 2 2 2 2 2 2 2 2
59 VSS VSS 60
DDR_A_D29 61 62 DDR_A_D28
DDR_A_D24 DQ24 DQ28 DDR_A_D25
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
EC_P80_DATA DM3 DQS3# DDR_A_DQS3
<14,33> EC_P80_DATA 69 NC DQS3 70
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D31
DDR_A_D27 DQ26 DQ30 DDR_A_D30
75 DQ27 DQ31 76
77 VSS VSS 78
C DDR_CKE0_DIMMA DDR_CKE1_DIMMA C
<7> DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA <7>
81 VDD VDD 82
EC_P80_CLK 83 84
<14,33> EC_P80_CLK NC NC/A15
DDR_A_BS#2 85 86
<8> DDR_A_BS#2 BA2 NC/A14
Layout Note: DDR_A_MA12
87 VDD VDD 88
DDR_A_MA11
89 A12 A11 90
Place one cap close to every 2 pullup DDR_A_MA9 91 92 DDR_A_MA7
DDR_A_MA8 A9 A7 DDR_A_MA6
resistors terminated to +0.9VS 93 A8 A6 94
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1
A10/AP BA1 DDR_A_BS#1 <8>
DDR_A_BS#0 107 108 DDR_A_RAS#
<8> DDR_A_BS#0 BA0 RAS# DDR_A_RAS# <8>
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
+0.9VS <8> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7>
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
<8> DDR_A_CAS# CAS# ODT0 M_ODT0 <7>
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
<7> DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

<7> M_ODT1 M_ODT1 119 120

NC/ODT1 NC
121 VSS VSS 122
1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_A_D37 123 124 DDR_A_D39
DDR_A_D36 DQ32 DQ36 DDR_A_D38
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
C74

C66

C60

C51

C42

C34

C40

C53

C64

C77

C39

C70

C33

133 134 DDR_A_D34

DDR_A_D35 VSS DQ38 DDR_A_D33
135 DQ34 DQ39 136
DDR_A_D32 137 138
DQ35 VSS DDR_A_D45
139 VSS DQ44 140
DDR_A_D40 141 142 DDR_A_D43
B DDR_A_D44 DQ40 DQ45 B
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_A_D41 151 152 DDR_A_D47
DDR_A_D46 DQ42 DQ46 DDR_A_D42
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D49 157 158 DDR_A_D52
+0.9VS DDR_A_D48 DQ48 DQ52 DDR_A_D53
Layout Note: 159 DQ49 DQ53 160
Pla ce these resistor 161 VSS VSS 162
RP1 RP2 163 164 M_CLK_DDR1
closely JP41,all NC,TEST CK1 M_CLK_DDR1 <7>
DDR_A_WE# 1 8 8 1 DDR_A_RAS# 165 166 M_CLK_DDR#1
VSS CK1# M_CLK_DDR#1 <7>
DDR_A_CAS# 2 7 7 2 DDR_CS0_DIMMA# trace length Max=1.5" DDR_A_DQS#6 167 168
DDR_CS1_DIMMA# M_ODT0 DDR_A_DQS6 DQS6# VSS DDR_A_DM6
3 6 6 3 169 DQS6 DM6 170
M_ODT1 4 5 5 4 DDR_A_MA13 171 172
DDR_A_D54 VSS VSS DDR_A_D51
173 DQ50 DQ54 174
56_0804_8P4R_5% 56_0804_8P4R_5% DDR_A_D50 175 176 DDR_A_D55
DQ51 DQ55
177 VSS VSS 178
RP6 DDR_A_D61 179 180 DDR_A_D57
56_0402_5% DDR_A_BS#1 DDR_A_D60 DQ56 DQ60 DDR_A_D56
5 4 181 DQ57 DQ61 182
DDR_A_BS#0 R39 1 2 6 3 DDR_A_MA0 183 184
DDR_A_MA2 DDR_A_DM7 VSS VSS DDR_A_DQS#7
7 2 185 DM7 DQS7# 186
DDR_A_MA10 R43 1 2 8 1 DDR_A_MA4 187 188 DDR_A_DQS7
56_0402_5% DDR_A_D59 VSS DQS7
189 DQ58 VSS 190
56_0804_8P4R_5% DDR_A_D58 191 192 DDR_A_D62
DQ59 DQ62 DDR_A_D63
193 VSS DQ63 194
RP7 RP9 CLK_SMBDATA 195 196
<14,15> CLK_SMBDATA SDA VSS
DDR_A_MA1 4 5 5 4 DDR_A_MA6 CLK_SMBCLK 197 198
<14,15> CLK_SMBCLK SCL SA0
DDR_A_MA3 3 6 6 3 DDR_A_MA7 199 200
+3VS VDDSPD SA1
DDR_A_MA5 2 7 7 2 DDR_A_MA11

1
10K_0402_5%

10K_0402_5%
DDR_A_MA8 1 8 8 1 DDR_CKE1_DIMMA 1
C7 FOX_ASOA426-M2RN-7F

R13

R15
A 56_0804_8P4R_5% 56_0804_8P4R_5% A
ME@
0.1U_0402_16V4Z
RP10 2
SO-DIMM A

2
DDR_A_MA9 4 5
DDR_A_MA12 3 6
DDR_A_BS#2 2 7
DDR_CKE0_DIMMA 1 8 Top side
56_0804_8P4R_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 13 of 47
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V
<8> DDR_B_DQS#[0..7]

<8> DDR_B_D[0..63]
+DDR_MCH_REF1
+DDR_MCH_REF1 <13>
<8> DDR_B_DM[0..7] JP4

2.2U_0805_16V4Z

0.1U_0402_16V4Z
<8> DDR_B_DQS[0..7] 1 VREF VSS 2
3 4 DDR_B_D5 1 1
DDR_B_D0 VSS DQ4 DDR_B_D4
<8> DDR_B_MA[0..13] 5 DQ0 DQ5 6

C146

C135
DDR_B_D1 7 8
DQ1 VSS DDR_B_DM0
9 VSS DM0 10
DDR_B_DQS#0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7
15 VSS DQ7 16
D DDR_B_D2 D
17 DQ2 VSS 18
Layout Note: DDR_B_D3 19 20 DDR_B_D12
DQ3 DQ12 DDR_B_D13
21 VSS DQ13 22
Place near JP42 DDR_B_D8 23 24
DDR_B_D9 DQ8 VSS DDR_B_DM1
25 DQ9 DM1 26
27 VSS VSS 28
DDR_B_DQS#1 29 30 M_CLK_DDR3
DQS1# CK0 M_CLK_DDR3 <7>
DDR_B_DQS1 31 32 M_CLK_DDR#3
DQS1 CK0# M_CLK_DDR#3 <7>
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
+1.8V 39 40
VSS VSS

41 VSS VSS 42
2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_B_D17 43 44 DDR_B_D21
DDR_B_D20 DQ16 DQ20 DDR_B_D16
1 1 1 1 1 1 1 1 1 45 DQ17 DQ21 46
C29

C23

C90

C96

C22

C68

C75

C88

C32
47 VSS VSS 48
DDR_B_DQS#2 49 50
DQS2# NC PM_EXTTS#0 <7,13>
DDR_B_DQS2 51 52 DDR_B_DM2
2 2 2 2 2 2 2 2 2 DQS2 DM2
53 VSS VSS 54
DDR_B_D18 55 56 DDR_B_D22
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_B_D28 61 62 DDR_B_D26
DDR_B_D25 DQ24 DQ28 DDR_B_D24
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
EC_P80_DATA DM3 DQS3# DDR_B_DQS3
<13,33> EC_P80_DATA 69 NC DQS3 70
71 VSS VSS 72
DDR_B_D30 73 74 DDR_B_D29
DDR_B_D31 DQ26 DQ30 DDR_B_D27
75 DQ27 DQ31 76
C C
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
<7> DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB <7>
81 VDD VDD 82
Layout Note: EC_P80_CLK 83 84
<13,33> EC_P80_CLK NC NC/A15
DDR_B_BS#2 85 86
Place one cap close to every 2 pullup <8> DDR_B_BS#2 BA2 NC/A14
87 VDD VDD 88
DDR_B_MA12 89 90 DDR_B_MA11
resistors terminated to +0.9VS DDR_B_MA9 A12 A11 DDR_B_MA7
91 A9 A7 92
DDR_B_MA8 93 94 DDR_B_MA6
A8 A6
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS#1
+0.9VS A10/AP BA1 DDR_B_BS#1 <8>
DDR_B_BS#0 107 108 DDR_B_RAS#
<8> DDR_B_BS#0 BA0 RAS# DDR_B_RAS# <8>
DDR_B_WE# 109 110 DDR_CS2_DIMMB#
<8> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <7>
111 VDD VDD 112
DDR_B_CAS# 113 114 M_ODT2
<8> DDR_B_CAS# CAS# ODT0 M_ODT2 <7>
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_CS3_DIMMB# 115 116 DDR_B_MA13

<7> DDR_CS3_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
1 1 1 1 1 1 1 1 1 1 1 1 1 M_ODT3 119 120
<7> M_ODT3 NC/ODT1 NC
121 VSS VSS 122
DDR_B_D32 123 124 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
125 DQ33 DQ37 126
2 2 2 2 2 2 2 2 2 2 2 2 2
127 VSS VSS 128
C73

C80

C76

C35

C41

C56

C81

C62

C52

C84

C65

C38

C36

DDR_B_DQS#4 129 130 DDR_B_DM4

DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_B_D39
DDR_B_D34 VSS DQ38 DDR_B_D38
135 DQ34 DQ39 136
DDR_B_D35 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
B DDR_B_D40 DDR_B_D45 B
141 DQ40 DQ45 142
DDR_B_D41 143 144
DQ41 VSS DDR_B_DQS#5
145 VSS DQS5# 146
DDR_B_DM5 147 148 DDR_B_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
Layout Note: 159 DQ49 DQ53 160
Pla ce these resistor 161 VSS VSS 162
+0.9VS 163 164 M_CLK_DDR2
closely JP42,all NC,TEST CK1 M_CLK_DDR2 <7>
165 166 M_CLK_DDR#2
DDR_B_DQS#6 VSS CK1# M_CLK_DDR#2 <7>
RP3 RP4 trace length Max=1.5" 167 DQS6# VSS 168
DDR_B_CAS# 8 1 4 5 DDR_B_MA13 DDR_B_DQS6 169 170 DDR_B_DM6
DDR_B_WE# M_ODT2 DQS6 DM6
7 2 3 6 171 VSS VSS 172
DDR_CS3_DIMMB# 6 3 2 7 DDR_CS2_DIMMB# DDR_B_D51 173 174 DDR_B_D54
M_ODT3 DDR_B_RAS# DDR_B_D50 DQ50 DQ54 DDR_B_D55
5 4 1 8 175 DQ51 DQ55 176
177 VSS VSS 178
56_0804_8P4R_5% 56_0804_8P4R_5% DDR_B_D56 179 180 DDR_B_D60
DDR_B_D61 DQ56 DQ60 DDR_B_D57
181 DQ57 DQ61 182
RP5 183 184
DDR_B_BS#1 DDR_B_DM7 VSS VSS DDR_B_DQS#7
4 5 185 DM7 DQS7# 186
DDR_B_BS#0 R44 1 2 3 6 DDR_B_MA0 187 188 DDR_B_DQS7
56_0402_5% DDR_B_MA2 DDR_B_D59 VSS DQS7
2 7 189 DQ58 VSS 190
DDR_B_MA10 R41 1 2 1 8 DDR_B_MA4 DDR_B_D58 191 192 DDR_B_D62
DQ59 DQ62 DDR_B_D63
193 VSS DQ63 194
56_0804_8P4R_5% CLK_SMBDATA 195 196
<13,15> CLK_SMBDATA SDA VSS
CLK_SMBCLK 197 198 R12
<13,15> CLK_SMBCLK SCL SAO
RP8 RP11 199 200 1 2 +3VS
+3VS VDDSPD SA1
DDR_B_MA1 5 4 4 5 DDR_B_MA7

1
10K_0402_5%
DDR_B_MA3 6 3 3 6 DDR_B_MA11 1 10K_0402_5%

R14
A DDR_B_MA5 DDR_B_MA6 C6 P-TWO_A5692B-A0G16-P A
7 2 2 7
DDR_B_MA9 8 1 1 8 DDR_CKE3_DIMMB ME@
0.1U_0402_16V4Z
56_0804_8P4R_5% 56_0804_8P4R_5% 2 SO-DIMM B

2
RP12
DDR_CKE2_DIMMB 8 1
DDR_B_BS#2 7 2
DDR_B_MA12
DDR_B_MA8
6 3
Security Classification Compal Secret Data Compal Electronics, Inc.
5 4 Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

56_0804_8P4R_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 14 of 47
5 4 3 2 1
 5 4 3 2 1

FSLC FSLB FSLA CPU SRC PCI +3VS +CK_VDD_MAIN1

CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz
+3VS 1 2
R428 R419 R429 0_0805_5% 1 1 1 1 1 1 1
0 0 1 133 100 33.3 C227 C218 C219 C432 C222 C233 C449
2.2K_0402_5% 2.2K_0402_5%
Q29 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2N7002_SOT23 2 2 2 2 2 2 2
0 1 1 166 100 33.3
CLK_SMBDATA

S
<21,28> ICH_SMBDATA 1 3
Table : ICS954306 +CK_VDD_MAIN2

G
2
D D
FSB Frequency Selet: +3VS 1 2 1 2 +CK_VDD_REF C446 2 1 33P_0402_50V8J
+3VS R331 0_0805_5% 1 1 1 R330

1
C413 C458 C457 1_0805_1%
Stuff CLK_Ra CLK_Rb CLK_Rc 1 2 +CK_VDD_48 Y2

2
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R427 CLK_XTAL_IN 14.31818MHZ_20P_6X1430004201

G
CPU Driven 2 2 2 2.2_0805_1%

2
CLK_SMBCLK CLK_XTAL_OUT
*(Default) No Stuff CLK_Rd CLK_Re CLK_Rf<21,28> ICH_SMBCLK 1 3
C448
2 1
33P_0402_50V8J

S
2N7002_SOT23 L17
Stuff CLK_Rd CLK_Re CLK_Rf Q28
533MHz U29 1 2 +3VS
+CK_VDD_MAIN1
1 1 FBM-L10-160808-301-T_0603
No Stuff CLK_Ra CLK_Rb CLK_Rc C450 C451 Place crystal within
1 VDDSRC VDDA 7 500 mils of CK410
49 0.1U_0402_16V4Z 10U_0805_10V4Z
VDDSRC 2 2
Stuff CLK_Rd CLK_Rf 54 8
65
VDDSRC
VDDSRC
GNDA Place near U4
667MHz Place these components
No Stuff CLK_Ra CLK_Rb CLK_Rc 25 H_STP_PCI#
PCI_SRC_STOP# H_STP_PCI# <21>
30
CLK_Re 36
VDDPCI
VDDPCI CPU_STOP# 24 H_STP_CPU#
H_STP_CPU# <21>
near each pin within 40
+VCCP
12 VDDCPU MCH_BCLK CLK_MCH_BCLK
mils.
CPUCLKT1LP 11 1 2 CLK_MCH_BCLK <7>
1 2 +CK_VDD_REF 18 R424 0_0402_5%
C452 0.1U_0402_16V4Z VDDREF MCH_BCLK# 1 CLK_MCH_BCLK#
CPUCLKC1LP 10 2 CLK_MCH_BCLK# <7>
2

1 2 +CK_VDD_48 40 R423 0_0402_5% CLK_CPU_BCLK 2 1

@ R349 C422 0.1U_0402_16V4Z VDD48 R434 @ 49.9_0402_1%
56_0402_5% 14 CPU_BCLK 1 2 CLK_CPU_BCLK CLK_CPU_BCLK# 2 1
CPUCLKT0LP CLK_CPU_BCLK <4>
R353 CLK_Rd CLK_XTAL_IN 20 R426 0_0402_5% R433 @ 49.9_0402_1%
8.2K_0402_5% X1 CPU_BCLK# 1 CLK_CPU_BCLK#
13 2 CLK_CPU_BCLK# <4>
1

FSA 2 CPUCLKC0LP R425 0_0402_5% CLK_MCH_BCLK 2

1 1 2 MCH_CLKSEL0 <7> 1
C CLK_XTAL_OUT R432 @ 49.9_0402_1% C
19 X2
1 2 R326 6 CLK_MCH_BCLK# 2 1
<5> CPU_BSEL0 CPUCLKT2_ITP/SRCCLKT10LP
R332 1K_0402_5% R364 R431 @ 49.9_0402_1%
0_0402_5% <21> CLK_48M_ICH CLK_48M_ICH 2 1 FSA 41 5
USB_48MHz/FSLA CPUCLKC2_ITP/SRCCLKC10LP
1

CLK_Ra 33_0402_5%
R323 FSB 45 FSLB/TEST_MODE/24Mhz CLK_MCH_SSCDREFCLK
SRCCLKT9LP 3 1 2
@ 1K_0402_5% <21> CLK_14M_ICH CLK_14M_ICH 2 1 CLKREF1 23 R345 @ 49.9_0402_1%
R412 33_0402_5% REF0/FSLC/TEST_SEL CLK_MCH_SSCDREFCLK#
2 1 2
2

SRCCLKC9LP R344 @ 49.9_0402_1%

33_0402_5% 2 1 R381 PCI_MINI 34 72 CLK_PCIE_MCARD 1 2
<26> CLK_PCI_1394 PCICLK4/FCTSEL1 CLKREQ9# R341 @ 49.9_0402_1%
+VCCP 33_0402_5% 2 1 R387 PCI_EC 33 70 CLK_PCIE_MCARD#1 2
<33> CLK_PCI_LPC SEL_48M/PCICLK3 SRCCLKT8LP R340 @ 49.9_0402_1%
<24> CLK_PCI_PCM 33_0402_5% 2 1 R388 PCI_PCM 32 69 CLK_MCH_3GPLL 1 2
SEL_24M/PCICLK2 SRCCLKC8LP
2

R398 @ 49.9_0402_1%
R123 15_0402_5% 2 1 R404 PCI_LAN 27 71 CLK_MCH_3GPLL# 1 2
<27> CLK_PCI_LAN SEL_PCI6/PCICLK1 CLKREQ8#
15_0402_5% 2 1 R395 R409 @ 49.9_0402_1%
<32> CLK_PCI_DB
@ 1K_0402_5% 66 PCIE_SATA 1 2 CLK_PCIE_SATA CLK_PCIE_VGA 1 2
SRCCLKT7LP CLK_PCIE_SATA <20>
15_0402_5% 2 1 R415 CLK_CODEC 22 R414 0_0402_5% R343 @ 49.9_0402_1%
<29> CLK_14M_CODEC
1

FSB 15_0402_5% 2 SEL_PCI5/REF1 PCIE_SATA# CLK_PCIE_SATA# CLK_PCIE_VGA#

1 2 MCH_CLKSEL1 <7> <32> CLK_14M_SIO 1 R145 SRCCLKC7LP 67 1 2 CLK_PCIE_SATA# <20> 1 2
R417 0_0402_5% R342 @ 49.9_0402_1%
1 2 R122 <7> CLK_MCH_DREFCLK CLK_MCH_DREFCLK 1 2 MCH_DREFCLK 43 38 SATAREQ# CLK_PCIE_ICH 1 2
<5> CPU_BSEL1 DOTT_96MHz/27MHz_Nonspread
CLKREQ7#/48Mhz_1 SATAREQ# <21>
R121 1K_0402_5% R362 UMA@ 33_0402_5% R385 @ 49.9_0402_1%
0_0402_5% <7> CLK_MCH_DREFCLK# CLK_MCH_DREFCLK#1 2 MCH_DREFCLK# 44 63 CLK_PCIE_ICH# 1 2
DOTC_96MHz/27MHz_spread SRCCLKT6LP
1

CLK_Rb R361 UMA@ 33_0402_5% R392 @ 49.9_0402_1%

@ R120 64 CLK_MCH_DREFCLK 1 2
CLK_PCI_ICH SRCCLKC6LP
<19> CLK_PCI_ICH 2 R372 1 PCI_ICH 37 ITP_EN/PCICLK_F0
R347 @ 49.9_0402_1%
0_0402_5% 33_0402_5% 62 CLK_MCH_DREFCLK#1 2
CLKREQ6# R346 @ 49.9_0402_1%
CLK_Re
2

CLK_ENABLE# 39 60 MCH_3GPLL 1 2 CLK_MCH_3GPLL CLK_PCIE_SATA 1 2

<45> CLK_ENABLE# VTT_PWRGD#/PD SRCCLKT5LP CLK_MCH_3GPLL <7>
R399 0_0402_5% R413 @ 49.9_0402_1%
B MCH_3GPLL# 1 CLK_MCH_3GPLL# CLK_PCIE_SATA# 1 B
SRCCLKC5LP 61 2 CLK_MCH_3GPLL# <7> 2
+VCCP R410 0_0402_5% R416 @ 49.9_0402_1%
<13,14> CLK_SMBCLK CLK_SMBCLK 16 29 CLKREQ5# 2 1 MCH_CLKREQ#
SMBCLK CLKREQ5#/PCICLK6 MCH_CLKREQ# <7>
R394 0_0402_5%
2

58 PCIE_ICH 1 2 CLK_PCIE_ICH
SRCCLKT4LP CLK_PCIE_ICH <21>
R383 R386 0_0402_5%
CLK_SMBDATA 17 59 PCIE_ICH# 1 2 CLK_PCIE_ICH#
<13,14> CLK_SMBDATA SMBDAT SRCCLKC4LP CLK_PCIE_ICH# <21>
R396 @ 1K_0402_5% R393 0_0402_5%
8.2K_0402_5% 57
1

CLKREF1 2 CLKREQ4#
1 1 2 MCH_CLKSEL2 <7>
1 2 CLKIREF 9 55
R407 R430 0_0402_5% GND SRCCLKT3LP
<5> CPU_BSEL2 1 2
R397 1K_0402_5% 4 56
0_0402_5% GNDSRC SRCCLKC3LP
1

CLK_Rc +3VS +3VS +3VS +3VS

15 GNDCPU CLKREQ3#/PCICLK5 28
@ R390
ITP PCI6 PCI5 21 52 PCIE_MCARD 1 2 CLK_PCIE_MCARD SATAREQ# 2 1 +3VS
GNDREF SRCCLKT2LP CLK_PCIE_MCARD <28>
0_0402_5% R356 0_0402_5% R366 @ 10K_0402_5%
1

CLK_Rf 31 53 PCIE_MCARD#1 2 CLK_PCIE_MCARD#

CLK_PCIE_MCARD# <28>
2

R363 R368 R382 R406 GNDPCI SRCCLKC2LP R355 0_0402_5%

35 26 CLKREQ_MCARD#
GNDPCI CLKREQ2# CLKREQ_MCARD# <28>
@ 10K_0402_5% 10K_0402_5% @ 10K_0402_5% @ 10K_0402_5%
42 50 PCIE_VGA 1 2 CLK_PCIE_VGA CLKREQ_MCARD# 2 1
CLK_PCIE_VGA <18>
2

CLK_ENABLE# PCI_ICH PCI_LAN CLK_CODEC GND48 SRCCLKT1LP R358 VGA@ 0_0402_5% R140 @ 10K_0402_5%
68 51 PCIE_VGA# 1 2 CLK_PCIE_VGA#
GNDSRC SRCCLKC1LP CLK_PCIE_VGA# <18>
1

R357 VGA@ 0_0402_5%

R352 R367 R389 R405 46
CLKREQ1#
@ 10K_0402_5% @ 10K_0402_5% 10K_0402_5% 10K_0402_5% 47 SSCDREFCLK 1 2 CLK_MCH_SSCDREFCLK
LCD100/96/SRC0_TLP CLK_MCH_SSCDREFCLK <7>
R360 UMA@ 0_0402_5%
2

+3VS 48 SSCDREFCLK#1 2 CLK_MCH_SSCDREFCLK#

LCD100/96/SRC0_CLP CLK_MCH_SSCDREFCLK# <7>
R359 UMA@ 0_0402_5%
A A
1

PCI_MINI = FCTSEL1
R374 PCI_PME=SEL_PCI6 ICS9LPR325AKLFT_MLF72
FCTSEL1
@ 10K_0402_5% PIN43 PIN44 PIN47 PIN48
(PIN34) PCI_LAN PIN27
2

PCI_MINI
0 CLKREQ5 Security Classification Compal Secret Data Compal Electronics, Inc.
1

0 DOT96T DOT96C 96/100M_T 96/100M_C

R373 1 PCICLK6 2005/10/06 2006/10/06 Title
Issued Date Deciphered Date
10K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
1 27Mout 27MSSout SRCT0 SRCC0 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 15 of 47
5 4 3 2 1
 A B C D E F G H

1 1

+LCDVDD +5VALW

+LCDVDD +3VS

2
R196 R201 Q14

100_0402_1% 100K_0402_5%

S
1 3
AO3413_SOT23

1 2

1
D

G
2
2N7002_SOT23 0.047U_0402_16V4Z
2
Q15 G
S 1 1 1 1

3
C291 C288 C289
C290

1
4.7U_0805_10V4Z 4.7U_0805_10V4Z
Q16 2 2 2 2
DTC124EK_SC59

<9> GMCH_LVDDEN 2 R203 1 2 0.1U_0402_16V4Z

UMA@ 0_0402_5%

2 2

3
B+ INVPWR_B+ +3VS
0.1U_0603_50V4Z
L14 1 2 0_0805_5% 2 1 C294

2
R202
@ L15 1 2 0_0805_5% 2 1
C295 4.7K_0402_5%
68P_0402_50V8K D9

1
CH751H-40_SC76
JP40 1 2 DISPOFF#
<33> BKOFF# DISPOFF#
1
2 <33> ENBKL
D10
<33> INVT_PWM 3
DISPOFF# @ CH751H-40_SC76
4
<33> DAC_BRIG 5 <9> GMCH_ENBKL 2 R52 1 1 2
3 UMA@ 0_0402_5% 3
INVPWR_B+ 6

2
7 R204
MOLEX_53780-0790 <18> G7X_ENBKL 2 R89 1 UMA@ 100K_0402_5%
VGA@ 0_0402_5%

1
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 16 of 47
A B C D E F G H
 A B C D E

TV-OUT Conn.

<18> CARD_LUMA 2 1 LUMA <36>

R60 VGA@ 0_0402_5%

<18> CARD_CRMA 2 1 CRMA <36>

R59 VGA@ 0_0402_5%

<18> CARD_COMP 2 1 COMP <36>

150_0603_1%
1 R61 VGA@ 0_0402_5% 1

1
150_0603_1%

150_0603_1%
1

1
R5
R4

R3
<9> TV_LUMA 2 1
R224 UMA@ 0_0402_5%
2 1 @
<9> TV_CRMA

2
R225 UMA@ 0_0402_5% @ @

2
<9> TV_COMPS 2 1
R223 UMA@ 0_0402_5%

Pop when with internal graphics

CRT Conn.
VGA@
2 1 R 1 2
<18> CARD_VGA_R RED <36>
R64 0_0402_5% L1 0_0603_5%
VGA@
2 1 G 1 2
<18> CARD_VGA_G GREEN <36>
R66 0_0402_5% L2 0_0603_5%
VGA@
2 1 B 1 2
<18> CARD_VGA_B BLUE <36>

150_0603_1%

82P_0402_50V8J

82P_0402_50V8J

82P_0402_50V8J
R68 0_0402_5% L3 0_0603_5%

1
150_0603_1%

150_0603_1%
1 1 1

1
R8
R6

R7

C3

C1

C2
UMA@
2 @ 2 2 2 2
<9> CRT_R 2 1

2
R63 0_0402_5% @ @

2
UMA@ @ @ @
<9> CRT_G 2 1
R65 0_0402_5%
UMA@
<9> CRT_B 2 1
R67 0_0402_5%

Pop when with internal graphics

+3VS +2.5VS +3VS

1

R197 R198 R199 R200

0_0402_5% 0_0402_5% 0_0402_5%0_0402_5%
VGA@ UMA@ UMA@ VGA@
2

+3VS
+3VS
1

R9 R10
2.2K_0402_5% 2.2K_0402_5%
2
G

Q1
2

2 VGA@1 3 1 2N7002_SOT23
<18> CARD_DDCDATA VGA_DDC_DAT <36>
R80 10_0402_5%
S

<18> CARD_DDCCLK 2
2
G

R79 VGA@ 0_0402_5%

2 1 Q2
3 UMA@ R2 @ 0_0402_5% 3
3 1 2N7002_SOT23 VGA_DDC_CLK <36>
DDCDA
S

<9> 3VDDCDA 1 2
R76 0_0402_5%
UMA@ 2 1
1 2 DDC CL +5VS R11 @ 0_0402_5%
<9> 3VDDCCL
R75 0_0402_5%
1

1
0.1U_0402_16V4Z R1
1K_0402_5%
C5
2
2
5

U1
VGA@
P

OE#

2 1 HSYNC 2 4
<18> CARD_HSYNC A Y JVGA_HS <36>
R82 0_0402_5%
G

VGA@
2 1 VSYNC +5VS 74AHCT1G125GW_SOT353-5
<18> CARD_VSYNC
3

R81 0_0402_5%
0.1U_0402_16V4Z

1
<9> CRT_HSYNC 1 UMA@ 2
R78 39_0402_5%
C4
5

2
<9> CRT_VSYNC 1 UMA@ 2 U2
R77 39_0402_5%
P

OE#

2 A Y 4 JVGA_VS <36>
Pop when with internal graphics
G

74AHCT1G125GW_SOT353-5
3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 17 of 47
A B C D E
 5 4 3 2 1

D D
MAX. 4.06A @ 1.8V
MAX. 130mA @ 2.5V
MAX. 655mA @ 3.3V

PEG_M_TXP[0..15]
PEG_M_TXP[0..15] <9>
PEG_M_TXN[0..15]
PEG_M_TXN[0..15] <9>

PEG_RXP[0..15]
PEG_RXP[0:15] <9>
JP7 JP8
1 41 1 41 PEG_RXN[0..15]
1 41 1 41 PEG_RXN[0:15] <9>
PEG_M_TXP1 2 42 PEG_RXP1 PEG_M_TXP0 2 42 PEG_RXP0
PEG_M_TXN1 2 42 PEG_RXN1 PEG_M_TXN0 2 42 PEG_RXN0
3 3 43 43 3 3 43 43
4 4 44 44 4 4 44 44
PEG_M_TXP3 5 45 PEG_RXP3 PEG_M_TXP2 5 45 PEG_RXP2
PEG_M_TXN3 5 45 PEG_RXN3 PEG_M_TXN2 5 45 PEG_RXN2
6 6 46 46 6 6 46 46
7 7 47 47 7 7 47 47
PEG_M_TXP5 8 48 PEG_RXP5 PEG_M_TXP4 8 48 PEG_RXP4
PEG_M_TXN5 8 48 PEG_RXN5 PEG_M_TXN4 8 48 PEG_RXN4
9 9 49 49 9 9 49 49
10 10 50 50 10 10 50 50
PEG_M_TXP7 11 51 PEG_RXP7 PEG_M_TXP6 11 51 PEG_RXP6
PEG_M_TXN7 11 51 PEG_RXN7 PEG_M_TXN6 11 51 PEG_RXN6
12 12 52 52 12 12 52 52
13 13 53 53 13 13 53 53
C PEG_M_TXP9 PEG_RXP9 PEG_M_TXP8 PEG_RXP8 C
14 14 54 54 14 14 54 54
PEG_M_TXN9 15 55 PEG_RXN9 PEG_M_TXN8 15 55 PEG_RXN8
15 55 15 55
16 16 56 56 16 16 56 56
PEG_M_TXP11 17 57 PEG_RXP11 PEG_M_TXP10 17 57 PEG_RXP10 +5VS +2.5VS
PEG_M_TXN11 17 57 PEG_RXN11 PEG_M_TXN10 17 57 PEG_RXN10
18 18 58 58 18 18 58 58
19 19 59 59 19 19 59 59

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
PEG_M_TXP13 20 60 PEG_RXP13 PEG_M_TXP12 20 60 PEG_RXP12
PEG_M_TXN13 20 60 PEG_RXN13 PEG_M_TXN12 20 60 PEG_RXN12
21 21 61 61 21 21 61 61
22 22 62 62 22 22 62 62 2 2 2 2

C244

C240

C112

C113
PEG_M_TXP15 23 63 PEG_RXP15 PEG_M_TXP14 23 63 PEG_RXP14
PEG_M_TXN15 23 63 PEG_RXN15 PEG_M_TXN14 23 63 PEG_RXN14
24 24 64 64 24 24 64 64
25 25 65 65 25 25 65 65
+1.8VS SUSP# 1 1 1 1
+3VS 26 26 66 66 +5VS <15> CLK_PCIE_VGA 26 26 66 66 SUSP# <24,26,33,34,35,43,44>
+1.5VS 27 67 27 67 G7X_THER_ALERT#
27 67 <15> CLK_PCIE_VGA# 27 67 G7X_THER_ALERT# <21>
28 68 28 68 VGA@ VGA@ VGA@ VGA@
28 68 28 68
29 29 69 69 <17> CARD_DDCCLK 29 29 69 69
+2.5VS 30 70 30 70
30 70 <17> CARD_DDCDATA 30 70 G7X_ENBKL <16>
31 31 71 71 31 31 71 71 PLTRST_VGA# <19>
32 32 72 72 <17> CARD_VSYNC 32 32 72 72
33 73 B+ 33 73
33 73 33 73
34 34 74 74 <17> CARD_HSYNC 34 34 74 74
35 35 75 75 35 35 75 75
36 76 36 76 +3VS
36 76 <17> CARD_VGA_R 36 76 CARD_COMP <17>
37 37 77 77 37 37 77 77
38 38 78 78 <17> CARD_VGA_G 38 38 78 78 CARD_LUMA <17>

0.047U_0402_16V4Z

0.047U_0402_16V4Z
39 39 79 79 39 39 79 79
40 40 80 80 <17> CARD_VGA_B 40 40 80 80 CARD_CRMA <17>
ACES_88363-08001 ACES_88363-08001 1 1

C110

C111
B 2 2 B

VGA@ VGA@

A A

Title
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size
SCHEMATIC, M/B LA-3111P
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B
Custom 401408
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: , 21, 2006 Sheet 18 of 47
5 4 3 2 1
 5 4 3 2 1

D D

+3VS

R271 1 2 8.2K_0402_5% PCI_DEVSEL#

R268 1 2 8.2K_0402_5% PCI_STOP#

R269 1 2 8.2K_0402_5% PCI_TRDY#

R263 1 2 8.2K_0402_5% PCI_FRAME# <24,26,27,32> PCI_AD[0..31] U3B

PCI_AD0 E18 D7 PCI_REQ0#
AD0 REQ0# PCI_REQ0# <26>
R273 1 2 8.2K_0402_5% PCI_PLOCK# PCI_AD1 C18 E7 PCI_GNT0#
AD1 GNT0# PCI_GNT0# <26>
PCI_AD2 A16 C16 PCI_REQ1#
R287 1 2 8.2K_0402_5% PCI _IRDY# PCI_AD3 F18
AD2 PCI REQ1#
D16
PCI_AD4 AD3 GNT1# PCI_REQ2#
E16 AD4 REQ2# C17 PCI_REQ2# <24>
R274 1 2 8.2K_0402_5% PCI_SERR# PCI_AD5 A18 D17 PCI_GNT2#
AD5 GNT2# PCI_GNT2# <24>
PCI_AD6 E17 E13 PCI_REQ3#
AD6 REQ3# PCI_REQ3# <27>
R276 1 2 8.2K_0402_5% PCI_PERR# PCI_AD7 A17 F13 PCI_GNT3#
AD7 GNT3# PCI_GNT3# <27>
PCI_AD8 A15 A13 PCI_REQ4#
R272 1 PCI_REQ4# PCI_AD9 AD8 REQ4# / GPIO22 +3VS
2 8.2K_0402_5% C14 AD9 GNT4# / GPIO48 A14
PCI_AD10 E14 C8 PCI_REQ5#
R270 1 AD10 GPIO1 / REQ5#
2 8.2K_0402_5% PCI_REQ3# PCI_AD11 D14 AD11 GPIO17 / GNT5# D8

5
PCI_AD12 B12 U21
PCI_AD13 AD12 PCI_CBE#0 PCI_PCIRST#
C13 B15 1

P
AD13 C/BE0# PCI_CBE#0 <24,26,27,32> B
PCI_AD14 G15 C12 PCI_CBE#1 4 PCI_RST#
AD14 C/BE1# PCI_CBE#1 <24,26,27,32> Y PCI_RST# <21,24,25,26,27,32,33>
PCI_AD15 G13 D12 PCI_CBE#2 2
AD15 C/BE2# PCI_CBE#2 <24,26,27,32> A

G
PCI_AD16 E12 C15 PCI_CBE#3
AD16 C/BE3# PCI_CBE#3 <24,26,27,32>
PCI_AD17 C11 TC7SH08FUF_SSOP5

3
PCI_AD18 AD17 PCI _IRDY#
D11 AD18 IRDY# A7 PCI_IRDY# <24,26,27>
C PCI_AD19 PCI_PAR C
A11 AD19 PAR E10 PCI_PAR <24,26,27>
PCI_AD20 A10 B18 PCI_PCIRST# 2 1
PCI_AD21 AD20 PCIRST# PCI_DEVSEL# R257 @ 0_0402_5%
F11 AD21 DEVSEL# A12 PCI_DEVSEL# <24,26,27>
+3VS PCI_AD22 F10 C9 PCI_PERR#
AD22 PERR# PCI_PERR# <24,26,27> +3VS
PCI_AD23 E9 E11 PCI_PLOCK#
PCI_AD24 AD23 PLOCK# PCI_SERR# R236
D9 AD24 SERR# B10 PCI_SERR# <24,26,27>
R298 1 2 8.2K_0402_5% PCI_PIRQA# PCI_AD25 B9 F15 PCI_STOP# 2 1
AD25 STOP# PCI_STOP# <24,26,27> PLTRST_VGA# <18>

5
PCI_AD26 A8 F14 PCI_TRDY# U18 0_0402_5%
AD26 TRDY# PCI_TRDY# <24,26,27,32>
R300 1 2 8.2K_0402_5% PCI_PIRQB# PCI_AD27 A6 F16 PCI_FRAME# PCI_PLTRST# 1

P
AD27 FRAME# PCI_FRAME# <24,26,27,32> B
PCI_AD28 C7 4 PLT_RST#
AD28 Y PLT_RST# <7,23,28>
R294 1 2 8.2K_0402_5% PCI_PIRQC# PCI_AD29 B6 C26 PCI_PLTRST# 2
AD29 PLTRST# A

G
PCI_AD30 E6 A9 CLK_PCI_ICH
AD30 PCICLK CLK_PCI_ICH <15>
R291 1 2 8.2K_0402_5% PCI_PIRQD# PCI_AD31 D6 B19 PCI_PME# TC7SH08FUF_SSOP5
PCI_PME# <33>

3
AD31 PME#
R283 1 2 8.2K_0402_5% PCI_PIRQE#

R290 1 2 8.2K_0402_5% PCI_PIRQF# PCI_PIRQA# A3

Interrupt I/F G8 PCI_PIRQE# 2 1
<24> PCI_PIRQA# PIRQA# GPIO2 / PIRQE# PCI_PIRQE#
PCI_PIRQB# B4 F7 PCI_PIRQF# R235 @ 0_0402_5%
PCI_PIRQB# PIRQB# GPIO3 / PIRQF# PCI_PIRQF# <27>
R279 1 2 8.2K_0402_5% PCI_PIRQG# PCI_PIRQC# C5 F8 PCI_PIRQG#
PIRQC# GPIO4 / PIRQG# PCI_PIRQG# <26>
PCI_PIRQD# B5 G7 PCI_PIRQH#
PIRQD# GPIO5 / PIRQH# PCI_PIRQH# <26>
R284 1 2 8.2K_0402_5% PCI_PIRQH#

R286 1 2 8.2K_0402_5% PCI_REQ0# AE5

MISC AE9
RSVD[1] RSVD[6]
AD5 RSVD[2] RSVD[7] AG8
R264 1 2 8.2K_0402_5% PCI_REQ1# AG4 AH8
RSVD[3] RSVD[8]
AH4 RSVD[4] RSVD[9] F21
R261 1 2 8.2K_0402_5% PCI_REQ2# AD9 AH20
RSVD[5] MCH_SYNC# MCH_ICH_SYNC# <7>
R282 1 2 8.2K_0402_5% PCI_REQ5# Place closely pin A9
ICH7_BGA652~D

CLK_PCI_ICH
B B

2
R277

@ 10_0402_5%

1
1
C364

@ 8.2P_0402_50V
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 19 of 47
5 4 3 2 1
 5 4 3 2 1

C195
18P_0402_50V8J
2 1 ICH_RTCX1

10M_0402_5%
1
Y1

R109
2 NC IN 1
32.768KHZ_12.5P_1TJS125BJ2A251
3 NC OUT 4
U3A
LPC_AD[0..3] <32,33>

2
C196

RTC
18P_0402_50V8J AB1 AA6 LPC_AD0
ICH_RTCX2 RTXC1 LAD0 LPC_AD1
2 1 AB2 RTCX2 LAD1 AB5
D LPC_AD2 D
LAD2 AC4
+RTCVCC R293 1 2 ICH_RTCRST# AA3 Y6 LPC_AD3
RTCRST# LAD3

LPC
20K_0402_5%
ICH_INTVRMEN W4 AC3 LPC_DRQ0#
INTVRMEN LDRQ0# LPC_DRQ#0 <32>
J1 SM_INTRUDER# Y5 AA5
INTRUDER# LDRQ1# / GPIO23
1 2
3MM AB3 LPC_FRAME#
+RTCVCC LFRAME# LPC_FRAME# <32,33>
W1 EE_CS
Y1 EE_SHCLK 2 1 R250 10K_0402_5% +3VS
C392 Y2 AE22 GATEA20
EE_DOUT A20GATE GATEA20 <33>

LAN
1U_0603_10V4Z W3 AH28 H_A20M#
EE_DIN A20M# H_A20M# <4>
1

CPU
1 2
R288 V3 AG27 H_CPUSLP_R# 2 @ 1 R233 0_0402_5%
LAN_CLK CPUSLP# H_CPUSLP# <4,7>
1M_0402_5% U3 AF24 DPRSLP# 2 1 R243 0_0402_5%
LAN_RSTSYNC TP1 / DPRSTP# H_DPRSTP# <4,45>
AH25 H_DPSLP#
H_DPSLP# <4>
2

SM_INTRUDER# TP2 / DPSLP# 56_0402_5% +VCCP

U5 LAN_RXD0 2 1
V4 AG26 H_FERR# R234
LAN_RXD1 FERR# H_FERR# <4>
T5 LAN_RXD2
AG24 H_PW RGOOD
+RTCVCC GPIO49 / CPUPWRGD H_PWRGOOD <4>
U7 LAN_TXD0
V6 AG22 H_IGNNE#
LAN_TXD1 IGNNE# H_IGNNE# <4>
C389@ V7 AG21
LAN_TXD2 INIT3_3V#
2 1 1 R310 2 INIT# AF22 H_INIT#
H_INIT# <4>
1

@ 10_0402_5% R311 AF25 H_INTR

INTR H_INTR <4>
R296 10P_0402_25V8K 33_0402_5%
+VCCP

AC-97/AZALIA
1 2 ICH_AC_BITCLK_R U1 2 1 R251 10K_0402_5%
<28> ICH_BITCLK_MDC ACZ_BCLK +3VS
332K_0402_1% 1 2 ICH_AC_SYNC_R R6 AG23 KB_RST#
<28> ICH_SYNC_MDC ACZ_SYNC RCIN# KB_RST# <33>
R281 33_0402_5%
2

1
1 2 ICH_AC_RST_R# R5 AF23 H_SMI#
<28> ICH_RST_MDC# ACZ_RST# SMI# H_SMI# <4>
ICH_INTVRMEN R314 33_0402_5% AH24 H_NMI R245
NMI H_NMI <4>
ICH_AC_SDIN0 T2
C <29> ICH_AC_SDIN0 ACZ_SDIN0 C
ICH_AC_SDIN1 T3 AH22 H_STPCLK# 56_0402_5%
<28> ICH_AC_SDIN1 ACZ_SDIN1 STPCLK# H_STPCLK# <4>
T1

2
ACZ_SDIN2 THRMTRIP_ICH#
THERMTRIP# AF26 1 R237 2 H_THERMTRIP# <4,7>
1 2 ICH_AC_SDOUT_R T4 24.9_0402_1%
<28> ICH_SDOUT_MDC ACZ_SDOUT
R315 33_0402_5%
AH17 PD_A0
DA0 PD_A0 <23>
SATA_LED# AF18 AE17 PD_A1
<37> SATA_LED# SATALED# DA1 PD_A1 <23>
AF17 PD_A2
DA2 PD_A2 <23>
PSATA_IRX_DTX_N0_C AF3 AE16 PD_CS#1
<23> PSATA_IRX_DTX_N0_C SATA0RXN DCS1# PD_CS#1 <23>
PSATA_IRX_DTX_P0_C AE3 AD16 PD_CS#3
<23> PSATA_IRX_DTX_P0_C SATA0RXP DCS3# PD_CS#3 <23>
PSATA_ITX_DRX_N0_C AG2 SATA0TXN

SATA
PSATA_ITX_DRX_P0_C AH2 SATA0TXP PD_D0
DD0 AB15
AF7 AE14 PD_D1
SATA2RXN DD1 PD_D2
AE7 SATA2RXP DD2 AG13
AG6 AF13 PD_D3
SATA2TXN DD3 PD_D4
AH6 SATA2TXP DD4 AD14
AC13 PD_D5
CLK_PCIE_SATA# DD5 PD_D6
<15> CLK_PCIE_SATA# AF1 SATA_CLKN DD6 AD12
CLK_PCIE_SATA AE1 AC12 PD_D7
<15> CLK_PCIE_SATA SATA_CLKP DD7
AE12 PD_D8
R275 DD8 PD_D9
AH10 SATARBIASN DD9 AF12
1 2 AG10 AB13 PD_D10
+3VS SATARBIASP DD10 PD_D11
DD11 AC14
24.9_0402_1% AF14 PD_D12
DD12 PD_D13
DD13 AH13
PD_D14
4.7K_0402_5% 2 1 R266 PD _IORDY PD _IORDY AG16
IDE DD14 AH14
AC15 PD_D15
<23> PD_IORDY IORDY DD15
8.2K_0402_5% 2 1 R265 PD_IRQ PD_IRQ AH16
<23> PD_IRQ IDEIRQ
10K_0402_5% 2 1 R259 SATA_LED# PD_DACK# AF16
<23> PD_DACK# DDACK#
PD_IOW# AH15 AE15 PD_DREQ
B <23> PD_IOW# DIOW# DDREQ PD_DREQ <23> B
PD_IOR# AF15
<23> PD_IOR# DIOR#

ICH7_BGA652~D

PD_D[0..15]
PD_D[0..15] <23>
PSATA_ITX_DRX_N0 1 2 PSATA_ITX_DRX_N0_C
<23> PSATA_ITX_DRX_N0
C387 3900P_0402_50V7K

PSATA_ITX_DRX_P0 1 2 PSATA_ITX_DRX_P0_C
<23> PSATA_ITX_DRX_P0
C388 3900P_0402_50V7K

BATT1.1

+RTCVCC
Close to U7

R114
+ BATT1 -
1 2 1 2
<29> ICH_SDOUT_AUDIO 1 2 ICH_AC_SDOUT_R W=20mils
R299 33_0402_5% 2 100_0603_1%
D3
C203
1 2 +CHGRTC ML1220T13RE
<29> ICH_SYNC_AUDIO 1 2 ICH_AC_SYNC_R 0.1U_0402_16V4Z 45@
R280 33_0402_5% 1
RB751V_SOD323

<29> ICH_RST_AUDIO# 1 2 ICH_AC_RST_R#

A R313 33_0402_5% A

<29> ICH_BITCLK_AUDIO 1 2 ICH_AC_BITCLK_R

1 R312 33_0402_5%

@ C390
27P_0402_50V8J
2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 20 of 47
5 4 3 2 1
 5 4 3 2 1

+3VS Place closely pin B2 Place closely pin AC1

CLK_48M_ICH CLK_14M_ICH
+3VALW +3VALW

1
10K_0402_5%
R253 1 2 SIRQ R305 R308

1
2

2
8.2K_0402_5% R256 R247 @ 10_0402_5% @ 10_0402_5%
R258 1 2 PCI_CLKRUN# R239 R241

2
2.2K_0402_5% 2.2K_0402_5% U3C
10K_0402_5% 10K_0402_5% 10K_0402_5% 1 1

2
R254 1 2G7X_THER_ALERT# <15,28> ICH_SMBCLK ICH_SMBCLK C22 AF19 C384 C391

1
D ICH_SMBDATA SMBCLK GPIO21 / SATA0GP D
<15,28> ICH_SMBDATA B22 SMBDATA GPIO19 / SATA1GP AH18 SB_INT_FLASH_SEL

SMB
SATA
GPIO
LINKALERT# A26 AH19 @ 4.7P_0402_50V8C @ 4.7P_0402_50V8C
ICH_SMLINK0 LINKALERT# GPIO36 / SATA2GP 2 2
B25 SMLINK0 GPIO37 / SATA3GP AE19 1 R260 2
ICH_SMLINK1 A25 100_0402_5%
SMLINK1
+3VALW +3VALW
R232 AC1 CLK_14M_ICH +3VALW
CLK14 CLK_14M_ICH <15>

Clocks
10K_0402_5% 1 2 I CH_RI# A28 B2 CLK_48M_ICH
RI# CLK48 CLK_48M_ICH <15>
R242 1 2 LINKALERT# 8.2K_0402_5%

5
SB_SPKR A19 U37
<29> SB_SPKR SPKR
150_0402_5% PAD T41 SUS_STAT# A27 C20 ICH_SUSCLK T44 PAD SLP_S4# 1

P
R248 1 SUS_STAT# SUSCLK B
2 ITP_DBRESET# <4> ITP_DBRESET#
ITP_DBRESET# A22 SYS_RST# Y 4 PM_SLP_S5# PM_SLP_S5# <33>

SYS
B24 SLP_S3# SLP_S5# 2
SLP_S3# SLP_S3# <33> A

G
10K_0402_5% PM_BMBUSY# AB18 D23 SLP_S4#
R246 1 <7> PM_BMBUSY# GPIO0 / BM_BUSY# SLP_S4#
2 OCP# F22 SLP_S5# TC7SH08FUF_SSOP5

3
OCP# SLP_S5#
<4> OCP# B23 GPIO11 / SMBALERT#
10K_0402_5% AA4 ICH_POK R295
PWROK ICH_POK <7,33>

POWER MGT
R304 1 2 SPI_MISO <15> H_STP_PCI#
H_STP_PCI# AC20 GPIO18 / STPPCI# 1 2 10K_0402_5%

GPIO
H_STP_CPU# AF21 AC22 1 2 DPRSLPVR
<15> H_STP_CPU# GPIO20 / STPCPU# GPIO16 / DPRSLPVR DPRSLPVR <7,45>
10K_0402_5% R90 100_0402_5%
R285 1 2 SPI_CS# <23> IDERST_CD#
IDERST_CD# A21 GPIO26 TP0 / BATLOW# C21 ICH_LOW_BAT#

B21 C23 PBTN_OUT#

GPIO27 PWRBTN# PBTN_OUT# <33>
E23 GPIO28
C19 PCI_RST#
LAN_RST# PCI_RST# <19,24,25,26,27,32,33>
1K_0402_5% PCI_CLKRUN# AG18
<24,26,27,33> PCI_CLKRUN# GPIO32 / CLKRUN# EC_RSMRST#
R255 1 2 ICH_PCIE_WAKE# Y4
RSMRST# EC_RSMRST# <33>
AC19 R297 10K_0402_5%
8.2K_0402_5% GPIO33 / AZ_DOCK_EN#
U2 GPIO34 / AZ_DOCK_RST# 1 2
R252 2 1 ICH_LOW_BAT#
10K_0402_5% ICH_PCIE_WAKE# F20 E20 EC_SCI#
<28> ICH_PCIE_WAKE# WAKE# GPIO9 EC_SCI# <33>
R240 1 2 WL_ON SIRQ AH21 A20
C <24,26,32,33> SIRQ SERIRQ GPIO10 ACIN <33,39> C
EC_THERM# AF20 F19 DPRSLPVR 2 1
<33> EC_THERM# THRM# GPIO12
10K_0402_5% E19 EC_LID_OUT# R91
GPIO13 EC_LID_OUT# <33>
R292 1 2 SPI_MOSI VGATE AD22 R4 @ 100K_0402_5%
<45> VGATE VRMPWRGD GPIO14
E22 CPUSB# T42 PAD
GPIO15 WL_ON
GPIO24 R3
AC21 D20 EC_FLASH#
G7X_THER_ALERT# AC18
GPIO6 GPIO GPIO25
AD21 SATAREQ#
EC_FLASH# <34>
<18> G7X_THER_ALERT# GPIO7 GPIO35 / SATAREQ# SATAREQ# <15>
EC_SMI# E21 AD20
<33> EC_SMI# GPIO8 GPIO38
AE20 KILL_MDC# KILL_MDC# <28>
GPIO39
ICH7_BGA652~D Need update symbol

U3D
F26 V26 DMI_RXN0
PERn1 DMI0RXN DMI_RXN0 <7>
F25 V25 DMI_RXP0
PERp1 DMI0RXP DMI_RXP0 <7>

DIRECT MEDIA INTERFACE

E28 U28 DMI_TXN0
PETn1 DMI0TXN DMI_TXN0 <7>
E27 U27 DMI_TXP0
PETp1 DMI0TXP DMI_TXP0 <7>
PCIE_RXN2 H26 Y26 DMI_RXN1
<28> PCIE_RXN2 PERn2 DMI1RXN DMI_RXN1 <7>
PCIE_RXP2 H25 Y25 DMI_RXP1
<28> PCIE_RXP2 PERp2 DMI1RXP DMI_RXP1 <7>
<28> PCIE_TXN2 0.1U_0402_16V4Z 2 1 C328 PCIE_C_TXN2 G28 W28 DMI_TXN1
PETn2 DMI1TXN DMI_TXN1 <7>
<28> PCIE_TXP2 0.1U_0402_16V4Z 2 1 C329 PCIE_C_TXP2 G27 W27 DMI_TXP1
PETp2 DMI1TXP DMI_TXP1 <7>

PCI-EXPRESS
K26 AB26 DMI_RXN2
PERn3 DMI2RXN DMI_RXN2 <7>
K25 AB25 DMI_RXP2
PERp3 DMI2RXP DMI_RXP2 <7>
J28 AA28 DMI_TXN2
PETn3 DMI2TXN DMI_TXN2 <7>
J27 AA27 DMI_TXP2
PETp3 DMI2TXP DMI_TXP2 <7>
M26 AD25 DMI_RXN3
B PERn4 DMI3RXN DMI_RXN3 <7> B
M25 AD24 DMI_RXP3
PERp4 DMI3RXP DMI_RXP3 <7>
L28 AC28 DMI_TXN3
PETn4 DMI3TXN DMI_TXN3 <7>
L27 AC27 DMI_TXP3
PETp4 DMI3TXP DMI_TXP3 <7>
P26 AE28 CLK_PCIE_ICH#
PERn5 DMI_CLKN CLK_PCIE_ICH# <15>
P25 AE27 CLK_PCIE_ICH
PERp5 DMI_CLKP CLK_PCIE_ICH <15>
N28 PETn5
N27 C25 R238 24.9_0402_1% Within 500 mils
PETp5 DMI_ZCOMP DMI_IRCOMP
DMI_IRCOMP D25 1 2 +1.5VS
T25 RP15
PERn6 USB20_N0 USB_OC#4
T24 PERp6 USBP0N F1 USB20_N0 <31> 4 5 +3VALW
R28 F2 USB20_P0 USB_OC#2 3 6
PETn6 USBP0P USB20_P0 <31>
R27 G4 USB20_N1 USB_OC#3 2 7
PETp6 USBP1N USB20_N1 <28>
G3 USB20_P1 USB_OC#1 1 8
USBP1P USB20_P1 <28>
R2 H1 USB20_N2
SPI_CLK USBP2N USB20_N2 <37>
SPI_CS# P6 H2 USB20_P2 10K_1206_8P4R_5%
SPI_CS# SPI USBP2P USB20_P2 <37>
P1 J4 USB20_N3
SPI_ARB USBP3N USB20_N3 <36>
J3 USB20_P3
USBP3P USB20_P3 <36>
SPI_MOSI P5 K1 USB20_N4 RP16
SPI_MOSI USBP4N USB20_N4 <37>
SPI_MISO P2 K2 USB20_P4 USB_OC#0 4 5
SPI_MISO USBP4P USB20_P4 <37> +3VALW
L4 USB20_N5 USB_OC#5 3 6
USBP5N USB20_N5 <36>
L5 USB20_P5 USB_OC#6 2 7
USBP5P USB20_P5 <36>
USB_OC#0 D3 M1 USB20_N6 USB_OC#7 1 8
<31> USB_OC#0 OC0# USBP6N USB20_N6 <37>
USB_OC#1 C4 M2 USB20_P6
USB_OC#2 D5
OC1# USB USBP6P
N4
USB20_P6 <37>
10K_1206_8P4R_5%
<37> USB_OC#2 OC2# USBP7N
USB_OC#3 D4 N3
USB_OC#4 OC3# USBP7P
<37> USB_OC#4 E5 OC4#
USB_OC#5 C3 R307 22.6_0402_1%
USB_OC#6 OC5# / GPIO29 USBRBIAS
<37> USB_OC#6 A2 OC6# / GPIO30 USBRBIAS# D2 1 2
USB_OC#7 B3 D1
OC7# / GPIO31 USBRBIAS
Within 500 mils
A ICH7_BGA652~D A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 21 of 47
5 4 3 2 1
 5 4 3 2 1

+VCCP
U3F U3E
A4 VSS[0] VSS[98] P28
ICH_V5REF_RUN G10 L11 0.1U_0402_16V4Z A23 R1
V5REF[1] Vcc1_05[1] VSS[1] VSS[99]
Vcc1_05[2] L12 B1 VSS[2] VSS[100] R11
AD17 V5REF[2] Vcc1_05[3] L14 1 B8 VSS[3] VSS[101] R12
Vcc1_05[4] L16 1 1 B11 VSS[4] VSS[102] R13
+1.5VS ICH_V5REF_SUS F6 L17 C363 C357 + C351 B14 R14
V5REF_Sus Vcc1_05[5] VSS[5] VSS[103]
Vcc1_05[6] L18 B17 VSS[6] VSS[104] R15
D 0.1U_0402_16V4Z 220U_D2_4VM D
AA22 Vcc1_5_B[1] Vcc1_05[7] M11 B20 VSS[7] VSS[105] R16
2 2 2
1 AA23 Vcc1_5_B[2] Vcc1_05[8] M18 B26 VSS[8] VSS[106] R17
+5VS +3VS

220U_D2_4VM
1 1 1 AB22 Vcc1_5_B[3] Vcc1_05[9] P11 B28 VSS[9] VSS[107] R18
+ C335 C340 C332 AB23 P18 C2 T6
Vcc1_5_B[4] Vcc1_05[10] VSS[10] VSS[108]

C327
AC23 T11 1U_0603_10V4Z C6 T12
Vcc1_5_B[5] Vcc1_05[11] VSS[11] VSS[109]
1

AC24 Vcc1_5_B[6] Vcc1_05[12] T18 C27 VSS[12] VSS[110] T13

R278 D15 2 2 2 2
AC25 Vcc1_5_B[7] Vcc1_05[13] U11 D10 VSS[13] VSS[111] T14
AC26 Vcc1_5_B[8] Vcc1_05[14] U18 D13 VSS[14] VSS[112] T15
100_0402_5% CH751H-40_SC76 0.1U_0402_16V4Z 0.1U_0402_16V4Z AD26 V11 D18 T16
Vcc1_5_B[9] Vcc1_05[15] VSS[15] VSS[113]
AD27 V12 D21 T17
2

Vcc1_5_B[10] Vcc1_05[16] VSS[16] VSS[114]

AD28 Vcc1_5_B[11] Vcc1_05[17] V14 D24 VSS[17] VSS[115] U4
ICH_V5REF_RUN Place closely pin D26 V16 E1 U12
Vcc1_5_B[12] Vcc1_05[18] VSS[18] VSS[116]
1 1 D27 Vcc1_5_B[13] Vcc1_05[19] V17 E2 VSS[19] VSS[117] U13
C362 C361 D28,T28,AD28. D28 V18 E4 U14
Vcc1_5_B[14] Vcc1_05[20] VSS[21] VSS[118]
E24 Vcc1_5_B[15] E8 VSS[22] VSS[119] U15
0.1U_0402_16V4Z 0.1U_0402_16V4Z E25 U6 +3VS E15 U16
2 2 Vcc1_5_B[16] Vcc3_3 / VccHDA VSS[23] VSS[120]
E26 Vcc1_5_B[17] 1 F3 VSS[24] VSS[121] U17
F23 R7 +VCCP C356 F4 U24
Vcc1_5_B[18] VccSus3_3/VccSusHDA +3VALW VSS[25] VSS[122]
F24 Vcc1_5_B[19] F5 VSS[26] VSS[123] U25
G22 AE23 C354 0.1U_0402_16V4Z F12 U26
Vcc1_5_B[20] V_CPU_IO[1] 2 VSS[27] VSS[124]
G23 Vcc1_5_B[21] V_CPU_IO[2] AE26 1 2 F27 VSS[28] VSS[125] V2
H22 Vcc1_5_B[22] V_CPU_IO[3] AH26 F28 VSS[29] VSS[126] V13
+5VALW +3VALW H23 0.1U_0402_16V4Z G1 V15
Vcc1_5_B[23] VSS[30] VSS[127]
J22 Vcc1_5_B[24] Vcc3_3[3] AA7 +3VS 1 2 G2 VSS[31] VSS[128] V24
J23 Vcc1_5_B[25] Vcc3_3[4] AB12 G5 VSS[32] VSS[129] V27
1

K22 AB20 1 C353 G6 V28

R289 D16 Vcc1_5_B[26] Vcc3_3[5] C359 0.1U_0402_16V4Z VSS[33] VSS[130]
K23 Vcc1_5_B[27] Vcc3_3[6] AC16 G9 VSS[34] VSS[131] W6
L22 Vcc1_5_B[28] Vcc3_3[7] AD13 1 2 G14 VSS[35] VSS[132] W24
10_0402_5% CH751H-40_SC76 L23 AD18 0.1U_0402_16V4Z G18 W25
Vcc1_5_B[29] Vcc3_3[8] 2 C358 VSS[36] VSS[133]
M22 AG12 G21 W26
2

ICH_V5REF_SUS Vcc1_5_B[30] Vcc3_3[9] 4.7U_0805_10V4Z VSS[37] VSS[134]

M23 Vcc1_5_B[31] Vcc3_3[10] AG15 G24 VSS[38] VSS[135] Y3
N22 Vcc1_5_B[32] Vcc3_3[11] AG19 G25 VSS[39] VSS[136] Y24
C C
1 N23 Vcc1_5_B[33] G26 VSS[40] VSS[137] Y27
C371 P22 A5 +3VS H3 Y28
Vcc1_5_B[34] Vcc3_3[12] VSS[41] VSS[138]

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
P23 Vcc1_5_B[35] Vcc3_3[13] B13 H4 VSS[42] VSS[139] AA1
0.1U_0402_16V4Z R22 B16 1 1 1 H5 AA24
2 Vcc1_5_B[36] Vcc3_3[14] VSS[43] VSS[140]
R23 Vcc1_5_B[37] Vcc3_3[15] B7 H24 VSS[44] VSS[141] AA25

C368

C350

C337
R24 Vcc1_5_B[38] Vcc3_3[16] C10 H27 VSS[45] VSS[142] AA26
R25 Vcc1_5_B[39] Vcc3_3[17] D15 H28 VSS[46] VSS[143] AB4
2 2 2
R26 Vcc1_5_B[40] Vcc3_3[18] F9 J1 VSS[47] VSS[144] AB6
+3VS T22 G11 J2 AB11
Vcc1_5_B[41] Vcc3_3[19] VSS[48] VSS[145]
T23 Vcc1_5_B[42] Vcc3_3[20] G12 J5 VSS[49] VSS[146] AB14
T26 Vcc1_5_B[43] Vcc3_3[21] G16 J24 VSS[50] VSS[147] AB16
T27 Vcc1_5_B[44] J25 VSS[51] VSS[148] AB19
1 T28 Vcc1_5_B[45] VccRTC W5 +RTCVCC J26 VSS[52] VSS[149] AB21
C352 U22 K24 AB24
Vcc1_5_B[46] VSS[53] VSS[150]

0.1U_0402_16V4Z

0.1U_0402_16V4Z
U23 Vcc1_5_B[47] VccSus3_3[1] P7 +3VALW K27 VSS[54] VSS[151] AB27
0.1U_0402_16V4Z V22 1 1 1 1 K28 AB28
2 Vcc1_5_B[48] VSS[55] VSS[152]

C369

C370
V23 A24 C386 C376 L13 AC2
Vcc1_5_B[49] VccSus3_3[2] VSS[56] VSS[153]
W22 Vcc1_5_B[50] VccSus3_3[3] C24 L15 VSS[57] VSS[154] AC5
W23 D19 0.1U_0402_16V4Z 0.1U_0402_16V4Z L24 AC9
Vcc1_5_B[51] VccSus3_3[4] 2 2 2 2 VSS[58] VSS[155]
Y22 Vcc1_5_B[52] VccSus3_3[5] D22 L25 VSS[59] VSS[156] AC11
Place closely pin AG28 within 100mlis. Y23 Vcc1_5_B[53] VccSus3_3[6] G19 L26 VSS[60] VSS[157] AD1
M3 VSS[61] VSS[158] AD3
+1.5VS +1.5VS_DMIPLLR +1.5VS_DMIPLL
B27 Vcc3_3[1] VccSus3_3[7] K3 +3VALW M4 VSS[62] VSS[159] AD4
R229 R230 K4 1 1 M5 AD7
VccSus3_3[8] VSS[63] VSS[160]
0.01U_0402_16V7K

1 2 1 2 +1.5VS_DMIPLL AG28 K5 C367 C377 M12 AD8

VccDMIPLL VccSus3_3[9] VSS[64] VSS[161]
10U_0805_10V4Z

VccSus3_3[10] K6 M13 VSS[65] VSS[162] AD11

0.5_0805_1% 0_0805_5% 1 1 AB7 L1 0.1U_0402_16V4Z 0.1U_0402_16V4Z M14 AD15
+1.5VS Vcc1_5_A[1] VccSus3_3[11] 2 2 VSS[66] VSS[163]
C330

AC6 Vcc1_5_A[2] VccSus3_3[12] L2 M15 VSS[67] VSS[164] AD19

C338

AC7 Vcc1_5_A[3] VccSus3_3[13] L3 M16 VSS[68] VSS[165] AD23

1 AD6 Vcc1_5_A[4] VccSus3_3[14] L6 M17 VSS[69] VSS[166] AE2
2 2 C373 AE6 Vcc1_5_A[5] VccSus3_3[15] L7 M24 VSS[70] VSS[167] AE4
AF5 Vcc1_5_A[6] VccSus3_3[16] M6 M27 VSS[71] VSS[168] AE8
B 0.1U_0402_16V4Z B
AF6 Vcc1_5_A[7] VccSus3_3[17] M7 M28 VSS[72] VSS[169] AE11
2
AG5 Vcc1_5_A[8] VccSus3_3[18] N7 N1 VSS[73] VSS[170] AE13
AH5 Vcc1_5_A[9] N2 VSS[74] VSS[171] AE18
Vcc1_5_A[19] AB17 +1.5VS N5 VSS[75] VSS[172] AE21
+1.5VS Place closely pin AG5. AD2 VccSATAPLL Vcc1_5_A[20] AC17 N6 VSS[76] VSS[173] AE24
0.1U_0402_16V4Z

N11 VSS[77] VSS[174] AE25

+3VS AH11 Vcc3_3[2] Vcc1_5_A[21] T7 N12 VSS[78] VSS[175] AF2
0.1U_0402_16V4Z

1 Vcc1_5_A[22] F17 N13 VSS[79] VSS[176] AF4

C375

1 +1.5VS AB10 Vcc1_5_A[10] Vcc1_5_A[23] G17 N14 VSS[80] VSS[177] AF8

AB9 Vcc1_5_A[11] N15 VSS[81] VSS[178] AF11
C355

1 AC10 Vcc1_5_A[12] Vcc1_5_A[24] AB8 1 2 N16 VSS[82] VSS[179] AF27

2 C365 AD10 Vcc1_5_A[13] Vcc1_5_A[25] AC8 N17 VSS[83] VSS[180] AF28
2 C348 0.1U_0402_16V4Z
AE10 Vcc1_5_A[14] N18 VSS[84] VSS[181] AG1
1U_0603_10V4Z AF10 K7 ICH_K7 PAD T46 N24 AG3
2 Vcc1_5_A[15] VccSus1_05[1] VSS[85] VSS[182]
AF9 Vcc1_5_A[16] N25 VSS[86] VSS[183] AG7
AG9 C28 ICH_C28 PAD T15 N26 AG11
Vcc1_5_A[17] VccSus1_05[2] ICH_G20 VSS[87] VSS[184]
AH9 Vcc1_5_A[18] VccSus1_05[3] G20 PAD T43 P3 VSS[88] VSS[185] AG14
P4 VSS[89] VSS[186] AG17
+3VALW Place closely pin AG9. E3 VccSus3_3[19] Vcc1_5_A[26] A1 +1.5VS P12 VSS[90] VSS[187] AG20
1 Vcc1_5_A[27] H6 P13 VSS[91] VSS[188] AG25
C372 C1 H7 1 P14 AH1
+1.5VS VccUSBPLL Vcc1_5_A[28] VSS[92] VSS[189]
1 J6 C360 P15 AH3
0.1U_0402_16V4Z C366 ICH_AA2 Vcc1_5_A[29] VSS[93] VSS[190]
T47 PAD AA2 VccSus1_05/VccLAN1_05[1] Vcc1_5_A[30] J7 P16 VSS[94] VSS[191] AH7
2 ICH_ Y7 0.1U_0402_16V4Z
T45 PAD Y7 VccSus1_05/VccLAN1_05[2] P17 VSS[95] VSS[192] AH12
0.1U_0402_16V4Z 2
P24 VSS[96] VSS[193] AH23
2
V5 VccSus3_3/VccLAN3_3[1] P27 VSS[97] VSS[194] AH27
V1 VccSus3_3/VccLAN3_3[2]
W2 ICH7_BGA652~D
VccSus3_3/VccLAN3_3[3]
+3VS 1 2 W7 VccSus3_3/VccLAN3_3[4]
R497 0_0402_5%
1 ICH7_BGA652~D
C349
A A
0.1U_0402_16V4Z
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 22 of 47
5 4 3 2 1
 5 4 3 2 1

D JP9 D

1 GND
PSATA_ITX_DRX_P0 2
<20> PSATA_ITX_DRX_P0 A+
PSATA_ITX_DRX_N0 3
<20> PSATA_ITX_DRX_N0 A-
4 GND
2 1 PSATA_IRX_DTX_N0 5
<20> PSATA_IRX_DTX_N0_C B-
C230 3900P_0402_50V7K 6 B+
7 GND
2 1 PSATA_IRX_DTX_P0
<20> PSATA_IRX_DTX_P0_C
C234 3900P_0402_50V7K
8 V33
9 V33
+3VS 1 2 10 V33
R151 @ 0_0805_5% 11 +5VS +3VS
GND
12 GND

1000P_0402_50V7K
22U_1206_6.3V6M

22U_1206_6.3V6M
13 0.1U_0402_16V4Z @ 0.1U_0402_16V4Z
GND

1000P_0402_50V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z
+5VS 1 2 14 V5
R170 0_0805_5% 15 1 1 1 1 1 1 1 1 1 1
V5

C266

C257

C258

C252

C246

C245
16 V5
17 C256 C271 C247 C251
GND
18 Reserved 2 2 2 2 2 2 2 2 2 2
19 GND
20 1U_0603_10V4Z @ 1U_0603_10V4Z
V12 @ @
21 V12
22 Pleace near HD CONN @
V12
Pleace near HD CONN
ALLTO_C16630-122A4-L_RV

C
Main SATA +5V Default C

PD_D[0..15]
PD_D[0..15] <20>
PD_A[0..2]
PD_A[0..2] <20>

JP10
<29> INT_CD_L 1 1 2 2 INT_CD_R <29>
<29> CD_AGND 3 3 4 4
R262 1 2@ 0_0402_5% 5 6 PD_D8
<21> IDERST_CD# 5 6
R267 1 2 33_0402_5% PD_D7 7 8 PD_D9
<7,19,28> PLT_RST# 7 8
PD_D6 9 10 PD_D10
PD_D5 9 10 PD_D11
11 11 12 12
B PD_D4 PD_D12 B
13 13 14 14
PD_D3 15 16 PD_D13
PD_D2 15 16 PD_D14
17 17 18 18
PD_D1 19 20 PD_D15
+3VS PD_D0 19 20 PD_DREQ
21 21 22 22 PD_DREQ <20>
23 24 PD_IOR#
23 24 PD_IOR# <20>
1

PD_IOW# 25 26
<20> PD_IOW# 25 26
PD _IORDY 27 28 PD_DACK#
<20> PD_IORDY 27 28 PD_DACK# <20>
R249 PD_IRQ 29 30
<20> PD_IRQ 29 30
10K_0402_5% PD_A1 31 32 PDIAG# 1 2
PD_A0 31 32 PD_A2 R244 100K_0402_5% +5VS
33 34
2

PD_CS#1 33 34 PD_CS#3 +5VS

<20> PD_CS#1 35 35 36 36 PD_CS#3 <20>
ODD_LED# 37 38
<37> ODD_LED# 37 38
39 39 40 40
+5VS 41 41 42 42 +5VS
43 43 44 44 2 1 1 1
45 46 C347 0.1U_0402_16V4Z
PRI_CSEL 45 46 C344 C336
47 47 48 48
49 50 1U_0603_10V4Z 10U_0805_10V4Z
49 50
2

2 2
OCTEK_CDR-50DY1G
R231 ME@
470_0402_5%
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 23 of 47
5 4 3 2 1
 A B C D E

CARD_S1_A[0..25] +3VS
CARD_S1_A[0..25] <25> +S1_VCC
+3VS
CARD_S1_D[0..15] C431 C438 C454
CARD_S1_D[0..15] <25>
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
PCI_AD[0..31] 1 1 1 1 1 1 1 1 1 1 1
PCI_AD[0..31] <19,26,27,32>
C400 C456
Power on RESET# 4.7U_0805_10V4Z C402 C436
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 +3VS 2 2 2 2 2 2 2
Reset# Here C455 C445 C404
4 +3VS 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C421 4
0.1U_0402_16V4Z
<25> VPPD0
VCC <25> VPPD1 1 2
<25> VCCD0#
C403
<25> VCCD1#
0.1U_0402_16V4Z
ENE CB1410 just have one vcc plane internal,
if want S3 wake-up function(PME#),then at S3

126

138
122
102
CLK

74
73

72
71

44
18

90

86
50
30
14

63
U28 status must keep all Vcc +3V. That is different

VCCI
VCCD1#
VCCD0#

VPPD1
VPPD0

VCCP0
VCCP1

VCCSK0
VCCSK1

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
with TI 1410 and O2-Micro 6912, just keep the
VCCI pin +3V, the other vcc can use +3VS.
SUSPEND# >1ms PCI_AD31 3 144 CARD_S1_D10
PCI_AD30 AD31 CAD31/D10 CARD_S1_D9
4 AD30 CAD30/D9 142
PCI_AD29 5 141 CARD_S1_D1
PCI_AD28 AD29 CAD29/D1 CARD_S1_D8
7 AD28 CAD28/D8 140
PCIRST# PCI_AD27 8 139 CARD_S1_D0
PCI_AD26 AD27 CAD27/D0 CARD_S1_A0
9 AD26 CAD26/A0 129
PCI_AD25 10 128 CARD_S1_A1
PCI_AD24 AD25 CAD25/A1 CARD_S1_A2
11 AD24 CAD24/A2 127
PCI_AD23 15 124 CARD_S1_A3
PCI_AD22 AD23 CAD23/A3 CARD_S1_A4
16 AD22 CAD22/A4 121
PCI_AD21 17 120 CARD_S1_A5
PCI_AD20 AD21 CAD21/A5 CARD_S1_A6
19 AD20 CAD20/A6 118
PCI_AD19 23 116 CARD_S1_A25
PCI_AD18 AD19 CAD19/A25 CARD_S1_A7
24 AD18 CAD18/A7 115
PCI_AD17 25 113 CARD_S1_A24
3 PCI_AD16 AD17 CAD17/A24 CARD_S1_A17 3
26 AD16 CAD16/A17 98
PCI_AD15 38 96 CARD_S1_IOWR#
AD15 CAD15/IOWR# CARD_S1_IOWR# <25>
PCI_AD14 39 97 CARD_S1_A9
Entry S3 PCI_AD13
PCI_AD12
40
AD14
AD13
CAD14/A9
CAD13/IORD# 93 CARD_S1_IORD#
CARD_S1_A11
CARD_S1_IORD# <25>
>1ms PCI_AD11
41
43
AD12 CAD12/A11 95
92 CARD_S1_OE#
AD11 CAD11/OE# CARD_S1_OE# <25>
PCI_AD10 45 91 CARD_S1_CE2#
AD10 CAD10/CE2# CARD_S1_CE2# <25>
PCI_AD9 46 89 CARD_S1_A10
PCI_AD8 AD9 CAD9/A10 CARD_S1_D15
47 AD8 CAD8/D15 87
PCI_AD7 49 85 CARD_S1_D7
PCI_AD6 AD7 CAD7/D7 CARD_S1_D13
SUSPEND# 51 AD6 CAD6/D13 82
PCI_AD5 52 83 CARD_S1_D6
PCI_AD4 AD5 CAD5/D6 CARD_S1_D12
53 AD4 CAD4/D12 80
PCI_AD3 54 81 CARD_S1_D5
PCI_AD2 AD3 CAD3/D5 CARD_S1_D11
55 AD2 CAD2/D11 77
PCI_AD1 CARD_S1_D4
PCI_AD0
56
57
AD1 PQFP 144 CAD1/D4 79
76 CARD_S1_D3
AD0 CAD0/D3
PCIRST#
PCI_CBE#3 12
22.2 X 22.2 X 1.60 125 CARD_S1_REG#
<19,26,27,32> PCI_CBE#3 C/BE3# CC/BE3#/REG# CARD_S1_REG# <25>
PCI_CBE#2 27 112 CARD_S1_A12
<19,26,27,32> PCI_CBE#2 C/BE2# CC/BE2#/A12
PCI_CBE#1 CARD_S1_A8
SUSPEND# will gate the PCIRST# or <19,26,27,32> PCI_CBE#1
PCI_CBE#0
37
48
C/BE1# CC/BE1#/A8 99
88 CARD_S1_CE1#
<19,26,27,32> PCI_CBE#0 C/BE0# CC/BE0#/CE1# CARD_S1_CE1# <25>
GRST#, so need S3 wake up function,
PCI_RST# 20 119 CARD_S1_RST
SUSPEND# must be LOW ahead the PCIRST# <19,21,25,26,27,32,33> PCI_RST#
<19,26,27,32> PCI_FRAME# 28
RST# CRST#/RESET
111 CARD_S1_A23
CARD_S1_RST <25>
FRAME# CFRAME#/A23 CARD_S1_A15
about 1ms. <19,26,27> PCI_IRDY# 29 IRDY# CIRDY#/A15 110
31 109 CARD_S1_A22
<19,26,27,32> PCI_TRDY# TRDY# CTRDY#/A22
32 107 CARD_S1_A21
<19,26,27> PCI_DEVSEL# DEVSEL# CDEVSEL#/A21
33 105 CARD_S1_A20
2 <19,26,27> PCI_STOP# STOP# CSTOP#/A20 2
34 104 CARD_S1_A14
<19,26,27> PCI_PERR# PERR# CPERR#/A14
35 133 CARD_S1_WAIT#
<19,26,27> PCI_SERR# SERR# CSERR#/WAIT# CARD_S1_WAIT# <25>
36 101 CARD_S1_A13
<19,26,27> PCI_PAR PAR CPAR/A13
1 2 1 123 CARD_S1_INPACK#
+3VS <19> PCI_REQ2# REQ# CREQ#/INPACK# CARD_S1_INPACK# <25>
R318 10K_0402_5% 2 106 CARD_S1_WE#
<19> PCI_GNT2# GNT# CGNT#/WE# CARD_S1_WE# <25>
CLK_PCI_PCM CLK_PCI_PCM 21 108 CARD_A16_CLK 1 2 CARD_S1_A16
<15> CLK_PCI_PCM PCLK CCLK/A16 R420 33_0402_5%
1

59 135 CARD_S1_BVD1
<33> CB_PME# RI_OUT#/PME# CSTSCHG/BVD1 CARD_S1_BVD1 <25>
R379 1 2 70 136 CARD_S1_WP
<18,26,33,34,35,43,44> SUSP# SUSPEND# CCLKRUN#/WP CARD_S1_WP <25>
33_0402_5% @ D17
@ RB751V_SOD323 PCI_AD20 1 2 PCI_PCM_ID 13 103 CARD_S1_A19
R408 100_0402_5% IDSEL CBLOCK#/A19
2

1 PCI_PIRQA# 60 132 CARD_S1_RDY#

<19> PCI_PIRQA# MFUNC0 CINT#/READY CARD_S1_RDY# <25>
Note: MF0 -- MF6 must 61 MFUNC1
C429 64 62 PCM_SPK#
10P_0402_25V8K@ refer the data sheet for MFUNC2 SPKOUT CARD_S1_BVD2
PCM_SPK# <29>
<21,26,32,33> SIRQ 65 MFUNC3 CAUDIO/BVD2 134 CARD_S1_BVD2 <25>
2 design. 67 MFUNC4
68 137 CARD_S1_CD2#
MFUNC5 CCD2#/CD2# CARD_S1_CD2# <25>
RSVD/D14
RSVD/A18

69 75 CARD_S1_CD1#
RSVD/D2

<21,26,27,33> PCI_CLKRUN# MFUNC6 CCD1#/CD1# CARD_S1_CD1# <25>

117 CARD_S1_VS2
CVS2/VS2# CARD_S1_VS2 <25>
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

66 131 CARD_S1_VS1
<19,21,25,26,27,32,33> PCI_RST# VCC/GRST# CVS1/VS1# CARD_S1_VS1 <25>

CB1410_LQFP144
6
22
42
58
78
94
114
130

84
100
143

CARD_S1_D2
CARD_S1_A18
CARD_S1_D14
1 1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
PROPRIETARY NOTE Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 24 of 47
A B C D E
 A B C D E

PCMCIA Power Controller

CARD_S1_A[0..25]
<24> CARD_S1_A[0..25] CARD_S1_D[0..15]
<24> CARD_S1_D[0..15]
JP11
+S1_VCC
1 GND GND 35
CARD_S1_D3 2 36 CARD_S1_CD1#
CARD_S1_D4 D3 CD1# CARD_S1_D11 CARD_S1_CD1# <24>
1 3 D4 D11 37
U5 CARD_S1_D5 4 38 CARD_S1_D12
C210 CARD_S1_D6 D5 D12 CARD_S1_D13
VCC 13 5 D6 D13 39
1 12 0.1U_0402_16V4Z CARD_S1_D7 6 40 CARD_S1_D14 1
VCC 2 CARD_S1_CE1# D7 D14 CARD_S1_D15
9 12V VCC 11 <24> CARD_S1_CE1# 7 CE1# D15 41
+S1_VPP CARD_S1_A10 8 42 CARD_S1_CE2#
CARD_S1_OE# A10 CE2# CARD_S1_VS1 CARD_S1_CE2# <24>
<24> CARD_S1_OE# 9 OE# VS1# 43 CARD_S1_VS1 <24>
+5VS CARD_S1_A11 10 44 CARD_S1_IORD#
+5VS CARD_S1_A9 A11 IORD# CARD_S1_IOWR# CARD_S1_IORD# <24>
1 11 A9 IOWR# 45 CARD_S1_IOWR# <24>
10 CARD_S1_A8 12 46 CARD_S1_A17
VPP C209 CARD_S1_A13 A8 A17 CARD_S1_A18
1 1 13 A13 A18 47
C197 5 0.1U_0402_16V4Z CARD_S1_A14 14 48 CARD_S1_A19
C193 5V 2 CARD_S1_WE# A14 A19 CARD_S1_A20
6 5V <24> CARD_S1_WE# 15 WE# A20 49
10U_1206_10V4Z 0.1U_0402_16V4Z CARD_S1_RDY# 16 50 CARD_S1_A21
2 2 <24> CARD_S1_RDY# IREQ# A21
VCCD0 1 VCCD0# <24> +S1_VCC 17 VCC VCC 51 +S1_VCC
VCCD1 2 VCCD1# <24> +S1_VPP 18 VPP1 VPP2 52 +S1_VPP
+3VS 15 CARD_S1_A16 19 53 CARD_S1_A22
VPPD0 VPPD0 <24> A16 A22
14 CARD_S1_A15 20 54 CARD_S1_A23
+3VS VPPD1 VPPD1 <24> A15 A23
CARD_S1_A12 21 55 CARD_S1_A24
CARD_S1_A7 A12 A24 CARD_S1_A25
3 3.3V 22 A7 A25 56
1 1 4 8 CARD_S1_A6 23 57 CARD_S1_VS2
3.3V OC A6 VS2# CARD_S1_VS2 <24>

SHDN
C198 CARD_S1_A5 24 58 CARD_S1_RST

GND
C194 CARD_S1_A4 A5 RESET CARD_S1_WAIT# CARD_S1_RST <24>
25 A4 WAIT# 59 CARD_S1_WAIT# <24>
10U_1206_10V4Z 0.1U_0402_16V4Z CARD_S1_A3 26 60 CARD_S1_INPACK#
2 2 CP-2211_SSOP16 CARD_S1_A2 A3 INPACK# CARD_S1_REG# CARD_S1_INPACK# <24>
27 61

16
CARD_S1_A1 A2 REG# CARD_S1_BVD2 CARD_S1_REG# <24>
28 A1 SPKR# 62 CARD_S1_BVD2 <24>
CARD_S1_A0 29 63 CARD_S1_BVD1
CARD_S1_D0 A0 STSCHG# CARD_S1_D8 CARD_S1_BVD1 <24>
30 D0 D8 64
PCI_RST# CARD_S1_D1 31 65 CARD_S1_D9
PCI_RST# <19,21,24,26,27,32,33> D1 D9
CARD_S1_D2 32 66 CARD_S1_D10
CARD_S1_WP D2 D10 CARD_S1_CD2#
<24> CARD_S1_WP 33 IOIS16# CD2# 67 CARD_S1_CD2# <24>
34 GND GND 68
2 +S1_VPP 2
69 GND GND 77
70 78 +S1_VCC
GND GND
1 71 GND GND 79
1 2 72 GND GND 80
C215 73 81 1 1 1
C241 4.7U_0805_10V4Z C243 GND GND
74 GND GND 82
2 C239 C216
1U_0805_25V4Z 75 GND GND 83
2 1 0.1U_0402_16V4Z C238
76 GND GND 84
0.01U_0402_16V7K 2 2 2
87 GND GND 89
88 90 10U_1206_10V4Z 0.01U_0402_16V7K
GND GND
FOX_WZ21131-G2-P4_LT
ME@

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 25 of 47
A B C D E
 5 4 3 2 1

+3VS
SD,MMC,MS,XD muti-function pin define
MDIO SD Card MMC Card MS Card XD Card
U34
<19,24,27,32> PCI_AD[0..31] PIN Name PIN Name PIN Name PIN Name PIN Name

10U_0805_4VAM
0.01U_0402_16V7K
PCI_AD31 125 10 1 1
PCI_AD30 AD31 VCC_PCI3V
126 AD30 VCC_PCI3V 20 MDIO00 SDCD# MMCCD# XDCD0#

C468

C506
PCI_AD29 127 27
PCI_AD28 AD29 VCC_PCI3V
1 32 MDIO01 MSCD# XDCD1#
PCI_AD27
PCI_AD26
2
3
AD28
AD27 R5C832 VCC_PCI3V
VCC_PCI3V 41
128
2 2 +3VS
MDIO02 XDCE#
PCI_AD25 AD26 VCC_PCI3V
5 AD25
PCI_AD24 6 61 MDIO03 SDWP# XDR/B#
PCI_AD23 AD24 VCC_RIN
9 AD23

0.1U_0402_16V4Z

10U_0805_4VAM
0.01U_0402_16V7K

0.01U_0402_16V7K
PCI_AD22 11 16 MDIO04 SDPWR0 MMCPWR MSWR XDPWR
PCI_AD21 AD22 VCC_ROUT
12 AD21 VCC_ROUT 34 1 1 1 1
D PCI_AD20 D
14 AD20 VCC_ROUT 64 MDIO05 SDPWR1 XDWP#

C515

C507

C489

C522
0.47U_0603_16V4Z

0.47U_0603_16V4Z
0.01U_0402_16V7K

0.01U_0402_16V7K
PCI_AD19 15 114 1 1 1 1
PCI_AD18 AD19 VCC_ROUT
17 AD18 VCC_ROUT 120
2 2 2 2
MDIO06 SDLED# MMCLED# MSLED# XDLED#

C464

C460

C491

C516
PCI_AD17 18
PCI_AD16 AD17
19 AD16 VCC_3V 67 +3VS 2 2 2 2
MDIO07 MSEXTCK
PCI_AD15 36 AD15

10U_0805_4VAM
0.01U_0402_16V7K
PCI_AD14 37 86 1 1 MDIO08 SDCCMD MMCCMD MSBS XDWE#
PCI_AD13 AD14 VCC_MD3V
38 AD13

C486

C505
PCI_AD12 39 98 +3V_PHY MDIO09 SDCCLK MMCCLK MSCCLK XDRE#
PCI_AD11 AD12 AVCC_PHY3V
40 AD11 AVCC_PHY3V 106
PCI_AD10 2 2
42 AD10 AVCC_PHY3V 110 MDIO10 SDCDAT0 MMCDAT MSCDAT0 XDCDAT0
PCI_AD9 43 112
PCI_AD8 AD9 AVCC_PHY3V
44 AD8 MDIO11 SDCDAT1 MSCDAT1 XDCDAT1
PCI_AD7 46 113 IEEE1394_TPBIAS0
PCI_AD6 AD7 TPBIAS0 +3V_PHY
47 AD6 MDIO12 SDCDAT2 MSCDAT2 XDCDAT2
PCI_AD5 48 109 IEEE1394_TPAP0 L18
PCI_AD4 AD5 TPAP0 IEEE1394_TPAN0
49 AD4 TPAN0 108 +3VS 1 2 MDIO13 SDCDAT3 MSCDAT3 XDCDAT3
PCI_AD3 50 AD3

0.1U_0402_16V4Z

0.1U_0402_16V4Z
22U_0805_6.3V6M

1000P_0402_50V7K

1000P_0402_50V7K
PCI_AD2 51 105 IEEE1394_TPBP0 BLM21A601SPT_0805 MDIO14 XDCDAT4
PCI_AD1 AD2 TPBP0 IEEE1394_TPBN0
52 AD1 TPBN0 104
PCI_AD0 53 1 1 1 1 1 MDIO15 XDCDAT5
AD0 SDCD#_XDCD0#
MDIO00 80 SDCD#_XDCD0# <37>

C465

C470

C469

C466

C467
79 MSCD#_XDCD1 MDIO16 XDCDAT6
MDIO01 MSCD#_XDCD1 <37>
PCI_CBE#3 7 78 XD_CE#
<19,24,27,32> PCI_CBE#3 C/BE3# MDIO02 XD_CE# <37> 2 2 2 2 2
PCI_CBE#2 21 77 SDWP#_XDRB# MDIO17 XDCDAT7
<19,24,27,32> PCI_CBE#2 C/BE2# MDIO03 SDWP#_XDRB# <37>
PCI_CBE#1 35 76 SDPWR0_MSPWR_XDPWR
<19,24,27,32> PCI_CBE#1 C/BE1# MDIO04
PCI_CBE#0 45 75 XDWP# MDIO18 XDCLE
<19,24,27,32> PCI_CBE#0 C/BE0# MDIO05 XDWP# <37>
74 3IN1_LED#
MDIO06 3IN1_LED# <37>
73 TP_MSEXTCK MDIO19 XDALE
PCI_PAR MDIO07 SDCMD_MSBS
<19,24,27> PCI_PAR 33 PAR MDIO08 88 SDCMD_MSBS <37>
PCI_FRAME# 23 84 SDCLK_MSCLK
<19,24,27,32> PCI_FRAME# FRAME# MDIO09 SDCLK_MSCLK <37>
PCI_TRDY# 25 82 SDDATA0_MSDATA0
C <19,24,27,32> PCI_TRDY#
PCI_IR DY# 24
TRDY# MDIO10
81 SDDATA1_MSDATA1
SDDATA0_MSDATA0 <37> Function set pin define C
<19,24,27> PCI_IRDY# IRDY# MDIO11
PCI_STOP# 29 93 SDDATA2_MSDATA2 UDIO3 UDIO4 MSEN XDEN Function
<19,24,27> PCI_STOP# STOP# MDIO12
PCI_DEVSEL# 26 90 SDDATA3_MSDATA3
<19,24,27> PCI_DEVSEL# DEVSEL# MDIO13 SDDATA3_MSDATA3 <37>
PCI_AD22 1 2 CBS_IDSEL 8 91 XDD4 Pull-up Pull-up Pull-up Pull-up Enable
IDSEL MDIO14 XDD4 <37>
R455 100_0402_5% PCI_PERR# 30 89 XDD5 SD,XD,MS,MMC Card
<19,24,27> PCI_PERR# PERR# MDIO15 XDD5 <37>
PCI_SERR# 31 92 XDD6
<19,24,27> PCI_SERR# SERR# MDIO16 XDD6 <37>
87 XDD7
MDIO17 XDD7 <37> +3VS
85 XDCLE
MDIO18 XDCLE <37>
PCI_REQ0# 124 83 XDALE
<19> PCI_REQ0# REQ# MDIO19 XDALE <37>
PCI_GNT0# 123
<19> PCI_GNT0# GNT#
58 MSEN MSEN R474 1 2 10K_0402_5%
MSEN XDEN U DIO3 R468 10K_0402_5%
55 Layout Note: Place close to R5C832 Layout Note: Place close to R5C832 1 2
XDEN U DIO4 R475 10K_0402_5%
<15> CLK_PCI_1394 121 PCICLK and Shield GND for SDCLK_MSCLK and Shield GND for SD_CLK 1 2
119 94 R5C832XI U DIO5 R473 1 2 100K_0402_5%
<19,21,24,25,27,32,33> PCI_RST# PCIRST# XI
CBS_GRST# 71 95 R5C832XO 1 2
R436 1 GBRST# XO XDEN
2@ 10K_0402_5% 117 CLKRUN#
C471 R472 1 2 10K_0402_5%
70 96 0.01U_0402_16V7K
R435 1 PME# FIL0
<21,24,27,33> PCI_CLKRUN# 2 0_0402_5% REXT 101 C481
R5_PME# 100 1 2 R5C832XI
<33> R5_PME# VREF

10K_0603_1%
0.01U_0402_16V7K
<19> PCI_PIRQG# 115 INTA#

2
116 72 SIRQ 2 16P_0603_50V8J
<19> PCI_PIRQH# INTB# UDIO0/SERIRQ# SIRQ <21,24,32,33>

2
R441
60 TP_UDIO1 X2 Solve MS Duo Adaptor short problem
UDIO1 PAD T49

C461
56 TP_UDIO2
UDIO2 PAD T48
1 2 69 65 U DIO3 24.576MHz_16P_1BG24576CKIA
+3VS HWSPND# UDIO3 1
R464 10K_0402_5% 66 59 U DIO4 C473

1
TEST UDIO4 U DIO5 R5C832XO R490 2
UDIO5 57 1 2 1 0_0402_5%
<18,24,33,34,35,43,44> SUSP# 1 2
R463 @ 0_0402_5% 111 4 16P_0603_50V8J @ Q33
AGND GND SDDATA1_MSDATA1 SD_MSDATA1
3 2N7002_SOT23

S
107 AGND GND 13 1 SD_MSDATA1 <37>
103 22 R491 2 1 0_0402_5%
AGND GND
102 AGND GND 28
99 54 Layout Note: Shield GND for @ Q35

G
2
B AGND GND +VCC_4IN1 SDDATA2_MSDATA2 B
32N7002_SOT23 SD_MSDATA2

S
GND 62 CBS_CCLK_INTERNAL and CBS_CCLK 1 SD_MSDATA2 <37>
GND 63 1 2
97 68 R453 0_0805_5%
NC GND +VCC_4IN1

0.1U_0402_16V4Z
10U_1206_6.3V6M

118

G
2
GND

S
GND 122 1 1 1 3 +VCC_4IN1_XD
+5VS
C521

C437
@ Q31
R5C832_TQFP128~D 1 2 2N7002_SOT23

G
2
2 2 R456 @ 10K_0402_5%
1 2
Layout Note: Place close to R5C832 R452 @ 10K_0402_5%

1
D D
SDCD#_XDCD0# 2 XDCD# 2
270P_0402_50V7K

G G
1

5.1K_0603_1%

1 S S

3
C453

@ Q34 @ Q32
R421

2N7002_SOT23 2N7002_SOT23
2
2

CLK_PCI_1394 Z3008 40mil

1

2
56.2_0603_1%

56.2_0603_1%

+VCC_4IN1
4.7P_0402_50V8C10_0402_5%

+3VS U35
R444

R439

R440

+3VS 3 1
@ SDPWR0_MSPWR_XDPWR VIN VOUT D22
4 VIN/CE VOUT 5
100K_0402_5%

1U_0603_10V4Z

150K_0402_5%
MSCD#_XDCD1 2
2

1
1

1
0.1U_0402_16V4Z
2 1 1 XDCD#
GND XDCD# <37>
R462

C517

R483
JP13 SDCD#_XDCD0# 3
2 IEEE1394_TPBN0 1 5 1 RT9701CB_SOT25
A IEEE1394_TPBP0 TPB- GND DAN202U_SC70 A
2 TPB+ GND 6
2
C463

C494

IEEE1394_TPAN0 3 7
2

2
IEEE1394_TPAP0 TPA- GND
4 TPA+ GND 8
1 @ CBS_GRST# 2
SUYIN_020115FB004S512ZL
0.33U_0603_16V4Z
0.01U_0402_16V7K

ME@
2

2
56.2_0603_1%

56.2_0603_1%

1
Layout Note: Shield GND for
2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
R437

R438

C459

C462

C493 IEEE1394_TPA and TPB

1U_0603_10V6K 2005/10/06 2006/10/06 Title
2 Issued Date Deciphered Date
SCHEMATIC, M/B LA-3111P
1

1 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
IEEE1394_TPBIAS0 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 26 of 47
5 4 3 2 1
 5 4 3 2 1

+3VALW +3VS
+3V_LAN

1
R498 R499
0_0603_5% 0_0603_5% GIGA@ 2SB1188_SC62

3
@
U24 R403 C385

2
2 1 CTRL12 1 +1.2V_LAN
+3V_LAN

3
1U_0603_10V4Z
Q21

2
CTRL25 1
8100CL 5.6K_0603_1% 1
100@ 100@ +2.5V_LAN
1
Q27 GIGA@ +

2
D 2SB1188_SC62 C374 C379 D

1 22U_A_4VM GIGA@ 0.1U_0402_16V4Z

2 2
1
+
C433 C393
22U_A_4VM 0.1U_0402_16V4Z
2 2
PCI_AD[0..31]
<19,24,26,32> PCI_AD[0..31] R400 1 2 3.6K_0402_5% +3V_LAN
U24 U31
PCI_AD0 104 108 LAN_EEDO 4 5 1
PCI_AD1 AD0 EEDO LAN_EEDI DO GND
103 AD1 AUX/EEDI 109 3 DI NC 6
PCI_AD2 102 111 LAN_EECLK 2 7 C410 0.1U_0402_16V4Z
PCI_AD3 AD2 EESK LAN_EECS SK NC
98 AD3 EECS 106 1 CS VCC 8 +3V_LAN
PCI_AD4 2
97 AD4
PCI_AD5 96 117 ACTIVITY# AT93C46-10SU-2.7_SO8
AD5 LED0 ACTIVITY# <37>
PCI_AD6 95 115 LINK_10_100#
AD6 LED1 LINK_10_100# <37>
PCI_AD7 93 114
PCI_AD8 AD7 LED2
90 AD8 NC/LED3 113
PCI_AD9 89
PCI_AD10 AD9 TXD+/MDI0+ 25MHZ_16P_XSL025000FK1H
87 AD10 TXD+/MDI0+ 1
PCI_AD11 86 2 TXD-/MDI0- Y3
PCI_AD12 AD11 TXD-/MDI0- RXIN+/MDI1+ LAN_X1 LAN_X2
85 AD12 RXIN+/MDI1+ 5 2 1
PCI_AD13 83 6 RXIN-/MDI1-
PCI_AD14 AD13 RXIN-/MDI1-
82 AD14
PCI_AD15 79 14 NC/MDI2+ 1 1
PCI_AD16 AD15 NC/MDI2+ NC/MDI2-
59 AD16 NC/MDI2- 15
PCI_AD17 58 18 NC/MDI3+ C442 C443
PCI_AD18 AD17 NC/MDI3+ NC/MDI3- 27P_0402_50V8J 27P_0402_50V8J +2.5V_LAN
57 AD18 NC/MDI3- 19
PCI_AD19 2 2 U23
55 AD19
PCI_AD20 53 121 LAN_X1
PCI_AD21 AD20 X1 LAN_X2
50 AD21 X2 122
C PCI_AD22 TXD+/MDI0+ MDO0+ C
49 AD22 12 TD4- MX4- 13 MDO0+ <37>
PCI_AD23 47 105 R319 1 2 1K_0402_5% C398 GIGA@ 0.01U_0402_16V7K TXD-/MDI0- 11 14 MDO0-
PCI I/F

AD23 LWAKE +3VS TD4+ MX4+ MDO0- <37>

PCI_AD24 43 23 ISOLATE# R317 1 2 15K_0402_5% 2 1 10 15 MCT0 2 1 R348 RJ45_PR
AD24 ISOLATE# TCT4 MCT4 RJ45_PR <37>
PCI_AD25 42 127 RTSET R403 1 2 2.49K_0603_1% 75_0402_5%
PCI_AD26 AD25 RTSET 5.6K for 8100CL GIGA@ RXIN+/MDI1+ MDO1+
40 AD26 NC/SMBCLK 72 9 TD3- MX3- 16 MDO1+ <37>
PCI_AD27 39 74 2.49K for 8110S(B) C396 GIGA@ 0.01U_0402_16V7K RXIN-/MDI1- 8 17 MDO1-
AD27 NC/SMBDATA TD3+ MX3+ MDO1- <37>
PCI_AD28 37 2 1 7 18 MCT1 2 1 R325
PCI_AD29 AD28 TCT3 MCT3 75_0402_5%
36 AD29 NC/M66EN 88
PCI_AD30 34 GIGA@ 0.1U_0402_16V4Z NC/MDI2+ 6 19 MDO2+
AD30 TD2- MX2- MDO2+ <37>
PCI_AD31 33 10 +AVDDH 1 1 1 R418 2 GIGA@ 0_0805_5% +3V_LAN C418 GIGA@ 0.01U_0402_16V7K NC/MDI2- 5 20 MDO2-
AD31 NC/AVDDH TD2+ MX2+ MDO2- <37>
120 C441 2 1 4 21 2 1 R320
PCI_CBE#0 AVDDH C420 TCT2 MCT2 GIGA@ 75_0402_5%
<19,24,26,32> PCI_CBE#0 92 C/BE#0
PCI_CBE#1 77 11 2 1 0_0402_5% GIGA@ 0.1U_0402_16V4Z NC/MDI3+ 3 22 MDO3+
<19,24,26,32> PCI_CBE#1 C/BE#1 NC/HSDAC+ 2 2 TD1- MX1- MDO3+ <37>
PCI_CBE#2 60 123 R354 GIGA@ C408 GIGA@ 0.01U_0402_16V7K NC/MDI3- 2 23 MDO3-
<19,24,26,32> PCI_CBE#2 C/BE#2 NC/HG TD1+ MX1+ MDO3- <37>
PCI_CBE#3 44 124 2 1 1 24 2 1 R322
<19,24,26,32> PCI_CBE#3 C/BE#3 NC/LG2 TCT1 MCT1
126 DVDD_A 1 2 +1.2V_LAN GIGA@ 75_0402_5%
PCI_AD17 VDD12A
1 2 LAN_IDSEL 46 IDSEL 1
R302 100_0402_5% R301 GIGA@ 0.5u_24HST1041A-2
76 GIGA@ 0_0402_5%
LAN I/F

<19,24,26> PCI_PAR PAR

<19,24,26,32> PCI_FRAME# 61 FRAME# NC/VSS 9
2
<19,24,26> PCI_IRDY# 63 IRDY# NC/VSS 13
67 C378
<19,24,26,32> PCI_TRDY# TRDY#
68 GIGA@ 0.1U_0402_16V4Z U22
<19,24,26> PCI_DEVSEL# DEVSEL#
<19,24,26> PCI_STOP# 69 STOP# NC/GND 22
48 TXD+/MDI0+ 8 9 MDO0+
NC/GND TXD-/MDI0- TD- TX- MDO0-
<19,24,26> PCI_PERR# 70 PERR# NC/GND 62 7 TD+ TX+ 10
75 73 6 11 MCT0
<19,24,26> PCI_SERR# SERR# NC/GND CT CT
NC/GND 112
<19> PCI_REQ3# 30 REQ# NC/GND 118
29 1 2 0.1U_0402_16V4Z 3 14 MCT1
<19> PCI_GNT3# GNT# C401 RXIN+/MDI1+ CT CT MDO1+
2 RD- RX- 15
<19> PCI_PIRQF# 25 RXIN-/MDI1- 1 16 MDO1- R324
B INTA# CTRL25 RD+ RX+ GIGA@ 49.9_0402_1% C412 B
CTRL25 8
31 NC/MDI3+ 2 1
<33> LAN_PME# PME#
125 CTRL12 NS0013_16P 2 1
CTRL12 100@ NC/MDI3- 2
19,21,24,25,26,32,33> PCI_RST# 27 RST# 1
26 +3V_LAN R321
CLK_PCI_LAN VDD33 GIGA@ 49.9_0402_1% GIGA@ 0.01U_0402_16V7K
<15> CLK_PCI_LAN 28 CLK VDD33 41 1 1 1 1 1
<21,24,26,33> PCI_CLKRUN# 65 CLKRUN# VDD33 56
71 C394 C381 C406 C440 C423 R333
VDD33 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z GIGA@ 49.9_0402_1% C415
VDD33 84
2 2 2 2 2 NC/MDI2+ 2
VDD33 94 1
VDD33 107 12
4 NC/MDI2- 2 1
GND/VSS R329
17 GND/VSS
128 GIGA@ 49.9_0402_1% GIGA@ 0.01U_0402_16V7K
GND/VSS AVDDL R422 1
AVDDL 3 2 +3V_LAN
7 1 1 1 100@ 0_0805_5% R380
AVDDL 49.9_0402_1% C430
21 GND/VSSPST AVDDL 20
38 16 C409 C425 C428 GIGA@ 0_0805_5% TXD+/MDI0+ 2 1
GND/VSSPST AVDDL 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +DVDD R376 1
51 GND/VSSPST 2 +2.5V_LAN 2 1
2 2 2 TXD-/MDI0-
66 GND/VSSPST 2 1
CLK_PCI_LAN 81 32 +DVDD R303 1 2 +1.2V_LAN R375
GND/VSSPST VDD12 GIGA@ 0_0805_5% 49.9_0402_1% 0.01U_0402_16V7K
91 GND/VSSPST VDD12 54 1 1 1 1
1

101 GND/VSSPST VDD12 78

119 99 C405 C427 C395 C382 0_0805_5%
R316 GND/VSSPST VDD12 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R306 R369
1 2 +2.5V_LAN
@ 10_0402_5% 2 2 2 2 100@ 49.9_0402_1% C424
35 24 +1.2V_LAN RXIN+/MDI1+ 2 1
2

GND NC/VDD12
Power

1 52 GND NC/VDD12 45 2 2 2 2 2 2 1
80 64 GIGA@ C380 C383 GIGA@ C439 C444 C407 RXIN-/MDI1- 2 1
C397 GND NC/VDD12 GIGA@ R365
100 GND NC/VDD12 110
@ 10P_0402_50V8J 116 GIGA@ 0.1U_0402_16V4Z GIGA@ 0.1U_0402_16V4Z 49.9_0402_1% 0.01U_0402_16V7K
2 NC/VDD12 1 1 1 1 1
A 0.1U_0402_16V4Z 0.1U_0402_16V4Z A
12 V_12P R350 1 2 0.1U_0402_16V4Z
NC
1 100@ 0_0402_5%
+2.5V_LAN
near LAN controller
RTL8110SBL_LQFP128 C414 R351 1 2 +AVDDH
GIGA@ GIGA@ 0_0402_5%
0.1U_0402_16V4Z
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 27 of 47
5 4 3 2 1
 A B C D E

Mini-Express Card(Slot 1-WLAN)

JP16
<21> ICH_PCIE_WAKE# 1 1 2 2 +3VS
BT_AVTIVE R479 2 1 @ 0_0402_5% 3 4
WLAN_AVTIVE R480 2 @ 0_0402_5% 3 4
1 5 5 6 6 +1.5VS

0.1U_0402_16V4Z
1 1
<15> CLKREQ_MCARD# 7 7 8 8

0.1U_0402_16V4Z
9 9 10 10 1

C498
CLK_PCIE_MCARD# 11 12 1
<15> CLK_PCIE_MCARD# 11 12

C499
CLK_PCIE_MCARD 13 14
<15> CLK_PCIE_MCARD 13 14
15 15 16 16
2
17 17 18 18
2
19 19 20 20 RF_OFF# <33>
21 22 PLT_RST#
21 22 PLT_RST# <7,19,23>
<21> PCIE_RXN2 23 23 24 24 +3VALW
<21> PCIE_RXP2 25 25 26 26
27 27 28 28
29 30 ICH_SMBCLK ICH_SMBCLK <15,21>
29 30 ICH_SMBDATA
<21> PCIE_TXN2 31 31 32 32 ICH_SMBDATA <15,21>
<21> PCIE_TXP2 33 33 34 34
35 35 36 36
37 37 38 38
39 39 40 40
41 41 42 42
43 44 W IRELESS_LED# WIRELESS_LED# <37>
43 44
45 45 46 46
47 47 48 48
49 49 50 50
51 51 52 52

53 GND1 GND2 54

FOX_AS0B226-S56N-7F

2 2
+3VALW
MDC CONN. C495

1
1 2
R495 JP17
10K_0402_1%
1U_0805_25V4Z
1 2

2
GND1 RES0
<20> ICH_SDOUT_MDC 3 IAC_SDATA_OUT RES1 4
5 GND2 3.3V 6 +3VALW
AZ _SYNC 7 8
<20> ICH_SYNC_MDC IAC_SYNC GND3
<20> ICH_AC_SDIN1 R107 1 2 AZ_SDIN3 9 10
R496 2 IAC_SDATA_IN GND4
<20> ICH_RST_MDC# 133_0402_5% 11 IAC_RESET# IAC_BITCLK 12 ICH_BITCLK_MDC <20>
@ 0_0402_5%
D23
2

GND
GND
GND
GND
GND
GND
1
<21> KILL_MDC# 3
ACES_88018-124G

13
14
15
16
17
18
DAP202U_SOT323

Connector for MDC Rev1.5

+5VS
1

3 3
R108
10K_0402_1%
1 2

RF_OFF

<33> RF_OFF# 2 Q9 BT MODULE CONN

DTC124EK_SC59

+3VS Q22 +3VS_BT

C164
3

3 1 2 1
AO3413_SOT23
0.1U_0402_16V4Z
BTONLED
G

<37> BTONLED
2

JP38
1

1 1
2 2
<21> USB20_N1 USB20_N1 3
USB20_P1 3
<21> USB20_P1 4 4
Q23 2 BTON_LED 5
DTC124EK_SC59 BT_AVTIVE 5
6 6
WLAN_AVTIVE 7 7
1

8 8
9
3

R309 GND1
10 GND2
10K_0402_5%
MOLEX_53780-0870
2

4 4
ME@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 28 of 47
A B C D E
 A B C D E

+VDDA

1
R153
10K_0402_1%
AC97 Codec
28.7K for Module Design (VDDA = 4.702)

2
2 1C255
+5VS +5VAMP
(output = 250 mA)

1
C263 1U_0603_10V4Z U33
1
<33> BEEP# 2 1 1
R168
2 L22 1 2 60mil 4 VIN VOUT 5 40mil +VDDA
1

1 R159 KC FBM-L11-201209-221LMAT_0805

2
C477 560_0402_5% 10K_0402_1% L21 1 2 2 6 1 4.85V
1U_0603_10V4Z C487 1U_0603_10V4Z KC FBM-L11-201209-221LMAT_0805 DELAY SENSE or ADJ
1 1

2
@ 0.1U_0402_10V6K 1 2MONO_IN1 2 1 MONO_IN C490 7 1 R449 C478
2 R158 20K_0402_5% ERROR CNOISE 150K_0603_1% 10U_0805_10V4Z
R167 10U_0805_10V4Z C482 2
8 3 1

1
2 2 10U_1206_16V4Z SD GND C476
C253 1 2

1
R160 C SI9182DH-AD_MSOP8

1
<24> PCM_SPK# 2 1 1 2 2 Q12 10K_0402_5%
B 2SC2411K_SC59 2
1
C472 560_0402_5% E R450

3
1U_0603_10V4Z 0.1U_0402_16V4Z 51K_0603_1%
@ 0.1U_0402_10V6K

2
2
C254
R161
<21> SB_SPKR 2 1 1 2
1

1
560_0402_5% D4
1U_0603_10V4Z R171
@ 10K_0402_5% RB751V_SOD323
2

+VDDC

R176
+AVDD_AC97
1 2 +3VS
2 FBM-L10-160808-301-T_0603 2

1 1 1
C496 C503 C497
L11
1 2 0.1U_0402_16V4Z 10U_0805_10V4Z
+VDDA 2 2 2
FBM-L10-160808-301-T_0603 1 1 1
C264 C282 0.1U_0402_16V4Z
C277 0.1U_0402_16V4Z
10U_0805_10V4Z 0.1U_0402_16V4Z

25
38
42
46
34

9
2 2 2 U11
+AVDD_AC97

AVDD1
AVDD2
AVDD3
AVDD4
AVDD5

DVDD1

DVDD2
2
R494 14 AUX_L SURR_L 35 R500 1 2@ 0_0402_5% 250_LINE_OUTL
2.49K_0402_1%
15 36 R501 1 2@ 0_0402_5% 250_LINE_OUTR
AUX_R SURR_R

1
R166 1 2 40.2K_0402_1% 16 37
<37> JACK_PLUG SENSE_A MONO_OUT

+AVDD_AC97 1 2 17 SENSE_B HP_OUT_L 39 HP_L <30>

R484 2.49K_0402_1%
23 LINE_IN_L HP_OUT_R 41 HP_R <30>
1 2 C267 1 2 27P_0402_50V8J
24 R174 33_0402_5%
R157 20K_0402_5% CD_R_L LINE_IN_R ICH_BITCLK_AUDIO
<23> INT_CD_L 2 1 BIT_CLK 6 ICH_BITCLK_AUDIO <20>
R156 2 1 20K_0402_5% C261 1 2 1U_0402_6.3V4Z CD_RC_L 18
R155 20K_0402_5% CD_L 250_SDIN R173 1 ICH_AC_SDIN0
2 1 SDATA_IN 8 2 33_0402_5% ICH_AC_SDIN0 <20>
R154 2 1 20K_0402_5% CD_R_R C260 1 2 1U_0402_6.3V4Z C D_RC_R 20
<23> INT_CD_R CD_R
2 250_XTL_IN 1 2CLK_14M_CODEC CLK_14M_CODEC <15>
CD_GNA C479 1 1U_0603_10V4Z CD_GNDA XTL_IN R175 @ 0_0402_5%
2 19 CD_GND_REF
3 CD_AGND R447 2 CD_GNA 3
<23> CD_AGND 1

1
10K_0402_5% MIC 1 2 C_MIC 21 1
<30> MIC MIC1
C480 1U_0603_10V4Z @ R177 0_0402_5% R169
1

C274 +AVDD_AC97
1 2 22 MIC2 GPIO 3 2 1
R448 C523 1U_0603_10V4Z 22P_0402_50V8J
MDC_RC_SPK 10K_0402_5% 2
1 2 13 29 @

2
PHONE VREFOUT_LI

2
10K_0402_5% @ C262 0.1U_0402_16V4Z 33
MONO_IN VREFOUT_CL R457
12
2

PC_BEEP
1M_0402_5%
+3VS R458 1 2 47K_0402_5% 28 @
VREFOUT_MIC +AUD_VREF
R459 1 2 0_0402_5% 11
<20> ICH_RST_AUDIO#

1
RESET#
VREF 27
<20> ICH_SYNC_AUDIO 10 SYNC 1 1
32 C268 C492
LFE_OUT 0.1U_0402_16V4Z 1U_0603_10V4Z
<20> ICH_SDOUT_AUDIO 5 SDATA_OUT CENTER_OUT 31
2 2

R487
1 2 47 43 250_LINE_OUTL C509 1 2 4.7U_0805_10V4Z LINE_OUTL
<30,33> EAPD EAPD LINE_OUT_L LINE_OUTL <30>
FBM-L10-160808-301-T_0603 45 250_LINE_OUTR
LINE_OUT_R
48 SPDIF_OUT
C508 1 2 4.7U_0805_10V4Z LINE_OUTR LINE_OUTR <30>
AVSS1 26
4 40 250_LINE_OUTL 1 2
DVSS1 AVSS2 C280 @ 1000P_0402_50V7K
7 DVSS2 AVSS3 44
30 250_LINE_OUTR 1 2
AVSS4 C281 @ 1000P_0402_50V7K
AD1986A_CSP48 +AUD_VREF

1 2
R152 0_0603_5%
1
10mil 1
4 4
1 2 C275 C272
R451 0_0603_5% 1U_0603_10V4Z 0.1U_0402_16V4Z
@ 2 2 @

1 2
R187 0_0603_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

GND GNDA THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 29 of 47
A B C D E
 A B C D E

1 1

+5VAMP +5VAMP W=40mil

0.1U_0402_16V4Z +3VS
1

R732 1 1
10K_0402_5% C504

2
@ C502
4.7U_0805_10V4Z R183 C511 0.1U_0402_16V4Z
2

VOLMAX 2 2
10K_0402_5% 1 2
1

U36

1
R454 10 1 MUTE R730 JP20
VDD MUTE AMP_OFF#
0_0402_5% 15 VDD SHUTDOWN# 2 1 2 @ 0_0402_5% EAPD SPKL+O
1
SPKL-O
SPKL- L23 SPKL-O SPKR+O 2
9 1 2 0_0603_5%
2

VOL_AMP LOUT- SPKR-O 3

<33> VOL_AMP 7 VOLUME 4
16 SPKR- L24 1 2 0_0603_5% SPKR-O
VOLMAX ROUT- ACES_85204-0400
8 VOLMAX 1 1 1 1
11 SPKL+ L20 1 2 0_0603_5% SPKL+O C163 C162 C168 C167 ME@
BTL# LOUT+
1 2 13 SE/BTL#
R467 0_0402_5% 14 SPKR+ L8 1 2 0_0603_5% SPKR+O @ 47P_0402_50V8J @ 47P_0402_50V8J @ 47P_0402_50V8J
LINE_OUTL LEFT_2 R165 1 L IN ROUT+ 2 2 2 2
<29> LINE_OUTL 1 2 2 10K_0402_5% 6 LIN-
C259 0_0603_5% 3 @ 47P_0402_50V8J
LINE_OUTR RIGHT_2 R162 1 RIN-
<29> LINE_OUTR 1 2 2 10K_0402_5% RIN
GND 5
C265 0_0603_5% 4 12
BYPASS GND
1
2 APA2068KAI-TRL_SOP16 2
C488 +AUD_VREF
4.7U_0805_10V4Z
2

1
MIC IN
+3VS R445 @ R446
2.2K_0402_5% 2.2K_0402_5%
L19

2
1

1 2 FBM-11-160808-601-T_0603 LINE_IN_L-1
<29> MIC LINE_IN_L-1 <37>
R729 INT_MIC
INT_MIC <37>
10K_0402_5%
2

D20 1 1
EAPD# 2
1 MUTE C474 C475
1

3 47P_0402_50V8J 47P_0402_50V8J
<33> EC_MUTE

1
2 2 @
@DAN202U_SC70 R733
2 1 10K_0402_5%
EAPD 2 Q703 R485 0_0402_5% @
<29,33> EAPD
DTC124EK_SC59

2
3

3 3

HEADPHONE
C270
100U_D2_6.3VM R181 47_0402_5%
SPKL+_C 1 INTSPK_CL+ PL

+
<29> HP_L 1 2 2 1 2 PL <37>
L10 FBM-11-160808-601-T_0603

JACK_PLUG
JACK_PLUG <29,37>
C269 R179 47_0402_5%
SPKR+_C 1 INTSPK_CR+ 1 PR
+

<29> HP_R 1 2 2 2 PR <37>

L9 FBM-11-160808-601-T_0603

1
100U_D2_6.3VM R180 R178 1 1
C279 C278

1
47P_0402_50V8J 47P_0402_50V8J C
1K_0402_5% 1K_0402_5% 2 Q701
2 2 B 2SC2411K_SC59

2
E

1
C
EAPD# 1 2 2 Q702
R727 1K_0402_5% B 2SC2411K_SC59
E

3
1 2
R728 1K_0402_5%

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 30 of 47
A B C D E
 USB Port +USB_VCCA

+5VS 1000P_0402_50V7K
1
1 1 1 1
C174 + C161 C160 C534 C535
+USB_VCCA 150U_D_6.3VM 0.1U_0402_16V4Z
U25
2 2 2 2 2
1 GND OUT 8
C411 0.1U_0402_16V4Z 2 7
IN OUT 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 1 3 IN OUT 6
<35,37> SYSON# SYSON# 4 5
EN# FLG USB_OC#0 <21> JP21
G528_SO8 1 VCC
<21> USB20_N0 2 D-
1 <21> USB20_P0 3 D+
C417 1 1 4 GND

2
@ 1000P_0402_50V7K
D14 C321 C322 5
2 @ PSOT24C_SOT23 @ 10P_0402_50V8J @10P_0402_50V8J GND1
6 GND2
2 2
7 GND3
8 GND4

1
For EMI SUYIN_020173MR004G565ZR
ME@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 31 of 47
 5 4 3 2 1

D D

INT_KBD CONN.( TYPE "D" KB)

CP1
KSI[0..7] KSI1 1 8
KSI[0..7] <33>
KSI7 2 7
KSI6 3 6
KSO[0..16] KSO9 4 5
KSO[0..16] <33>
100P_1206_8P4C_50V8 +3VALW
CP2
Power BTN
KSI4 1 8

1
KSI5 2 7
KSO0 3 6 R118
KSI2 4 5 100K_0402_5%
JP26
KSI1 1 100P_1206_8P4C_50V8

2
KSI7 1
2 CP3
KSI6 2 KSI3 1
3 3 8
KSO9 4 KSO5 2 7 D2
KSI4 4 KSO1 3 ON/OFF
5 5 6 2 ON/OFF# <33>
KSI5 6 KSI0 4 5 ON/OFFBTN# 1
C KSO0 6 <37> ON/OFFBTN# 51ON# C
7 7 3 51ON# <39>
KSI2 8 100P_1206_8P4C_50V8
KSI3 8 +3VALW DAN202U_SC70
9 CP4
KSO5 9 KSO2 1 Q10
10 10 8
KSO1 11 KSO4 2 7 2 1
11

1
KSI0 12 KSO7 3 6 SW1 @ 0_0603_5% DTC124EK_SC59
1
12

1
KSO2 13 KSO8 4 5 2 1 R113 D1
KSO4 13 SW @ 0_0603_5% 4.7K_0402_5%
14 14 RLZ20A_LL34
KSO7 15 100P_1206_8P4C_50V8
KSO8 15 2 C205
16 CP6

2
KSO6 16 KSO6 1 EC_ON 1000P_0402_50V7K
17 17 8 <33> EC_ON 2
KSO3 18 KSO3 2 7
KSO12 18 KSO123
19 19 6
KSO13 20 KSO134 5
KSO14 20
21

3
KSO11 21 100P_1206_8P4C_50V8
22 22
KSO10 23 CP5
KSO15 23 KSO141
24 24 8
KSO112 7
ACES_85202-2405 KSO103 6
KSO154 5

100P_1206_8P4C_50V8

B B

JP33 JP43
1 1 PCI_CBE#0 FOR PORT 80 DEBUG PORT EC DEBUG PORT
1
2 2
+5VS FOR LPC SIO DEBUG PORT 1
2 2 PCI_AD6
PCI_CBE#0 <19,24,26,27>
PCI_AD6 <19,24,26,27>
3 +3VS 3 PCI_AD4
3 3 PCI_AD4 <19,24,26,27>
4 4 PCI_AD2
4 4 PCI_AD2 <19,24,26,27>
5 5 PCI_AD0
5 5 PCI_AD0 <19,24,26,27>
6 6 PCI_AD1
6 CLK_14M_SIO <15> LPC_AD[0..3] 6 PCI_AD1 <19,24,26,27>
7 LPC_AD0 7 PCI_AD3
7 LPC_AD[0..3] <20,33> 7 PCI_AD3 <19,24,26,27>
8 LPC_AD1 8 PCI_AD5 JP22
8 8 PCI_AD5 <19,24,26,27>
9 LPC_AD2 9 PCI_AD7 +5VALW 1
9 9 PCI_AD7 <19,24,26,27> 1
LPC_AD3 PCI_AD8
10 10
LPC_FRAME# 10 10
PCI_CBE#1
PCI_AD8 <19,24,26,27> <33> EC_TX 2 2 P80_DATA
11 11
12 LPC_DRQ#0
LPC_FRAME# <20,33>
R391 11 11
12 PCI_CBE#2
PCI_CBE#1 <19,24,26,27> <33> EC_RX 3
4
3 P80_CLK
12 LPC_DRQ#0 <20> 12 PCI_CBE#2 <19,24,26,27> 4
13 PCI_RST# 10K_0402_5% 13 PCI_CBE#3
13 PCI_RST# <19,21,24,25,26,27,33> 13 PCI_CBE#3 <19,24,26,27>
14 2 1 14 ACES_85205-0400
14 14
15 15 CLK_PCI_DB <15> 15 15 CLK_PCI_DB <15> ME@
16 SIRQ 16 +5VS
16 SIRQ <21,24,26,33> 16
17 17 17 17 PCI_RST# <19,21,24,25,26,27,33>
18 18 18 18 PCI_FRAME# <19,24,26,27>
19 19 19 19 PCI_TRDY# <19,24,26,27>
20 20 PCI_AD9
20 20 PCI_AD9 <19,24,26,27>
ACES_85201-2005 ACES_85201-2005

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 32 of 47
5 4 3 2 1
 5 4 3 2 1

+3VALW
Analog Board ID definition,
Please see page 3.
L6 +EC_AVCC
1 2 +3VALW +3VALW
+3VALW +EC_AVCC
FBM-11-160808-601-T_0603 2 1
C212 1 1 1 1 1 1
C211

0.1U_0402_16V4Z
C231

0.1U_0402_16V4Z
C447

0.1U_0402_16V4Z
C248

0.1U_0402_16V4Z
C220

1000P_0402_50V7K
C237

1000P_0402_50V7K
C201
0.1U_0402_16V4Z

2
1000P_0402_50V7K
1 ECAGND 2 R492 R119
1 2
2 2 2 2 2 2 Ra
L7 FBM-11-160808-601-T_0603 100K_0402_1% 100K_0402_1%
@

1
ADP_ID BRD_ID
D D
1 1

1
C524 C208

105
127
141
0.1U_0402_16V4Z R493 R115 Rb

11
26
37

75

0.1U_0402_16V4Z
U6 2 1 ECAGND 0_0402_5% 33K_0402_5%
BATT_TEMP C202 0.01U_0402_16V7K @ 2 @ 2
1 71

VCC/ EC VCC
VCC / EC VCC
VCC / EC VCC
VCC / EC VCC

EC_AVCC / AVCC
VCC
VCC
<20> GATEA20 GA20/ GPIO00/GA20 BATTEMP/AD0/GPIO38 BATT_TEMP <40>
2 72 BATT_OVP
<20> KB_RST# BATT_OVP <41>

2
KBRST#/GPIO01/KBRST# BATT OVP/AD1/GPIO39 ADP_ID
<21,24,26,32> SIRQ 3 SERIRQ ADP_I/AD2/GPIO3A 73 ADP_ID <39>
5 74 BRD_ID
<20,32> LPC_FRAME# LPC_FRAME# / LFRAME# AD BID0/AD3/GPIO3B
LPC_AD3 6
<20,32> LPC_AD3 LPC AD3/LAD3
LPC_AD2 9 AD INtput or GPI
<20,32> LPC_AD2 LPC AD2/LAD2
LPC_AD1 10 Host +3VALW
<20,32> LPC_AD1 LPC AD1/LAD1 INTERFACE
LPC_AD0 12
<20,32> LPC_AD0 LPC AD0/LAD0
14 76 DAC_BRIG
<15> CLK_PCI_LPC CLK_PCI_EC/PCICLK DAC_BRIG/DA0/GPIO3D DAC_BRIG <16>
15 PWR 78 EN_FAN1
<19,21,24,25,26,27,32> PCI_RST# PCIRST# EN DFAN1/DA1/GPIO3D EN_FAN1 <4>

2
2 1 2 1 1 2 EC_RST# 42 79 IREF
+3VALW EC RST#/ ECRST# IREF2/DA2 IREF <41>
R143@ 10_0402_5% R112 47K_0402_5% EC_SCI# 24 80 1 2 R125 Ra
<21> EC_SCI# EC SCI#/SCI#/GPIO0E EN DFAN2/DA3/ GPIO3F VOL_AMP <30>
C232 R3361 2 44 R486 0_0402_5% 100K_0402_1%
<21,24,26,27> PCI_CLKRUN# PM_CLKRUN#/ CLKRUN# DA output or GPO
@ 22P_0402_50V8J 2 @ 0_0402_5% 15W@
C200 FAN/PWM

1
0.1U_0402_16V4Z 25 INVT_PWM MB_ID
INVT_PWM/GPIO0F/PWM1 INVT_PWM <16>
KSI0 63 27 BEEP#
KSI0/GPIO30 BEEP#/GPIO10/PWM2 BEEP# <29>

2
1 KSI1 AMP_MUTE#
64 KSI1/GPIO31 OUT BEEP/GPIO12/PWM3 30 AMP_MUTE# <37>
+3VALW KSI2 65 31 ACOFF R126 Rb
KSI2/GPI032 ACOFF/GPIO18/PWM4 ACOFF <39,41>
KSI3 66 32 FAN_SPEED1 0_0402_5%
KSI3/GPIO33 FAN SPEED1/GPIO14/FANFB1 FAN_SPEED1 <4>
KSI4 67 33 MB_ID 14W@
KSI4/GPIO34 FAN SPEED2/GPIO15/FANFB2
2

KSI5 68

1
R134 KSI6 KSI5/GPI035
69 KSI6/GPIO36
10K_0402_5% KSI7 70 91 EC_P80_CLK
KSI7/GPIO37 PSCLK1 EC_P80_CLK <13,14>
key Matrix 92 EC_P80_DATA
PSDAT1 EC_P80_DATA <13,14>
KSO0 47 scan 93
1

KSO1 KSO0/GPIO20 PS2 interface PSCLK2

<24> CB_PME# 1 2 48 KSO1/GPIO21 PSDAT2 94 EAPD <29,30>
C R131 @ 0_0402_5% KSO2 TP_CLK C
49 KSO2/GPIO22 PSCLK3 95 TP_CLK <37>
1 2 EC_PME# KSO3 50 96 TP_DATA
<26> R5_PME# KSO3/GPIO23 PSDAT3 TP_DATA <37>
R141 @ 0_0402_5% KSO4 51
KSO5 KSO4/GPIO24 ADB0
<27> LAN_PME# 1 2 52 KSO5/GPIO25 ADB0/D0 125
R138 0_0402_5% KSO6 53 126 ADB1
KSO7 KSO6/GPIO26 ADB1/D1 ADB2
<19> PCI_PME# 1 2 54 KSO7/GPIO27 ADB2/D2 128
R127 0_0402_5% KSO8 55 Data 130 ADB3
KSO[0..15] KSO9 KSO8/GPIO28 BUS ADB3/ D3 ADB4 +3VS
56 KSO9/GPIO29 ADB4/D4 131
+3VS <32> KSO[0..15] KSO10 57 132 ADB5 KBA[0..19]
RP13 KSI[0..7] KSO11 KSO10/GPIO2A ADB5/D5 ADB6 <34> KBA[0..19] EC_P80_CLK 1
58 KSO11/GPIO2B ADB6/D6 133 2
1 8 AMP_MUTE# <32> KSI[0..7] KSO12 59 134 ADB7 ADB[0..7] R402 @ 4.7K_0402_5%
KSO12/GPIO2C ADB7/D7 <34> ADB[0..7]
2 7 VOL_UP# KSO13 60 KSO13/GPIO2D KBA0/A0 111 KBA0 EC_P80_DATA 1 2
3 6 VOL_DOWN# KSO14 61 KSO14/GPIO2E KBA1/A1 112 KBA1 R411 @ 4.7K_0402_5%
4 5 MEDIA# KSO15 62 KSO15/GPIO2F KBA2/A2 113 KBA2 EC_MUTE 1 2
10K_1206_8P4R_5% KSO16 89 114 KBA3 R128 @ 10K_0402_5%
+3VALW KSO17 EC URXD/KSO16/GPIO48 KBA3/A3 KBA4
90 EC UTXD/KSO17/GPIO49 KBA4/A4 115
RP14 116 KBA5
KBA5/A5 KBA6
1 8 KBA6/A6 117
2 7 FR D# EC_SMB_DA2 88 Address 118 KBA7
<4> EC_SMB_DA2 EC SMD2/ GPIO47/SDA2 KBA7/A7 +5VS
3 6 EC_SMB_CK2 87 BUS 119 KBA8
<4> EC_SMB_CK2 EC SMC2/GPIO46/SCL2 KBA8/A8
4 5 FSEL# EC_SMB_DA1 86 SM BUS 120 KBA9
<34,40> EC_SMB_DA1 EC SMD1/GPIO44/SDA1 KBA9/A9
100K_1206_8P4R_5% EC_SMB_CK1 85 121 KBA10 TP_CLK 1 2
<34,40> EC_SMB_CK1 EC SMC1/GPIO44/SCL1 KBA10/A10 4.7K_0402_5%
122 KBA11 R142
+5VALW KBA11/A11 KBA12 TP_DATA 1
KBA12/A12 123 2
EC_TX34 124 KBA13 R146 4.7K_0402_5%
<32> EC_TX PCM_SPK#/EMAIL_LED#/ GPIO16 KBA13/A13
1 2 EC_SMB_CK1 EC_RX35 110 KBA14
<32> EC_RX SB_SPKR/PWR_SUSP_LED#/ GPIO17 KBA14/A14
R130 4.7K_0402_5% 38 109 KBA15
<37> PWR_LED# PWRLED#/ GPIO19 KBA15/A15 +3VALW
1 2 EC_SMB_DA1 40 108 KBA16
<37> NUM_LED# NUMLED#/ GPIO1A KBA16/A16
R133 4.7K_0402_5% CHARGE_LED0# 99 107 KBA17
<37> CHARGE_LED0# BATT CHGI LED#/ E51CS# KBA17/A17
CHARGE_LED1# 101 106 KBA18 KBA1 1 2
<37> CHARGE_LED1# BATT LOW LED#/ E51MR0 KBA18/A18
+3VS CAPS_LED# 100 98 KBA19 R147 @1K_0402_5%
<37> CAPS_LED# CAPS LED#/ E51TMR1 KBA19/A19
B SUSP_LED# 102 KBA4 1 2 B
<37> SUSP_LED# ARROW LED#/ E51 INT0
1 2 EC_SMB_CK2 SYSON 104 84 R148 @ 1K_0402_5%
<35,43> SYSON SYSON/GPIO56/ E51 INT1 SELIO2#/ GPIO43 ENBKL <16>
R135 4.7K_0402_5% 97 MEDIA# KBA5 1 2
SELIO#/ GPIO50 MEDIA# <37>
1 2 EC_SMB_DA2 4 135 FR D# R149 @ 1K_0402_5%
<21> EC_RSMRST# EC_RSMRST#/ GPIO02 FRD#/RD# FRD# <34>
R139 4.7K_0402_5% 1 1 BKOFF# 7 136 FW R#
<16> BKOFF# BKOFF#/GPIO03 FWR#/WR# FWR# <34>
C226 C223 8 144 FSEL#
<21> SLP_S3# PM SLP S3#/GPIO04 FSEL#/SELMEM# FSEL# <34>
EC_LID_OUT# 16
<21> EC_LID_OUT# EC LID OUT#/GPIO06
@ 100P_0402_50V8J @ 100P_0402_50V8J PM_SLP_S5# 17 41 EC_ON
2 2 <21> PM_SLP_S5# PM SLP S05#/ GPIO07 EC ON/ GPIO1B EC_ON <32>
EC_SMI# 18 43 CRY1 1 R150 2 CRY2
<21> EC_SMI# EC SMI#/GPIO08 AC IN/ GPIO1C ACIN <21,39>
PM_SLP_S5# R4011 2@ 0_0402_5% 19 29 EC_THERM# @ 20M_0603_5%
EC SWI#/GPIO09 ECTHERM#/GPIO11 EC_THERM# <21>
LID_SWITCH# 20 36
<36> LID_SWITCH# LID SW#/ GPIO0A ONOFF/GPIO18 ON/OFF# <32>
SUSP# 21 45 ICH_POK
<18,24,26,34,35,43,44> SUSP# SUSP#/GPIO0B PCMRST#/GPIO1E ICH_POK <7,21>
PBTN_OUT# 22 46
<21> PBTN_OUT# PBTN_OUT#/GPIO0C WL OFF#/GPIO1F RF_OFF# <28>
EC_PME# 23 EC PME#/GPIO0D
ALI/MH#/GPIO40 81 EC_MUTE <30>
82 FSTCHG
FSTCHG/GPIO41 FSTCHG <41>
83 VR_ON
VR ON/ GPIO42 VR_ON <45>
137 VOL_UP# 1 1
GPIO57/GPIO57 VOL_UP# <37>
CRY1 140 142 VOL_DOWN# C250 C249
XCLKO GPIO58/GPIO58 VOL_DOWN# <37>

4
AGND

CRY2 138 143 KILL_SW#

GND
GND
GND
GND
GND
GND

XCLKI GPIO59/GPIO59 KILL_SW# <36>

10P_0402_50V8J

10P_0402_50V8J
OUT
IN
2 2
KB910L_LQFP144
139
129
103
13
28
39

77

NC

NC
ECAGND

3
A X1 32.768KHZ_12.5P_1TJS125BJ2A251 A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 33 of 47
5 4 3 2 1
 +5VALW
+5VALW

1
C199
1 2 0.1U_0402_16V4Z R116
100K_0402_1%

U4

2
8 VCC A0 1
7 WP A1 2
<33,40> EC_SMB_CK1 6 SCL A2 3
<33,40> EC_SMB_DA1 5 SDA GND 4

AT24C16AN-10SU-2.7_SO8~N
+3VALW +3VALW

1
C501
R117

1
1 2 R442 100K_0402_1%
100K_0402_1%
SUSP# <18,24,26,33,35,43,44>
0.1U_0402_16V4Z

2
U32

2
G
5
TC7SH32FU_SSOP5

2
2 1 3
P
I0 EC_FLASH# <21>
FWE# 4

S
O
I1 1
G
Q30
2N7002_SOT23
3

+3VALW
FWR# <33>

U26 R337

5
@TC7SH32FU_SSOP5 @ 100K_0402_5%
R339 2 INT_FLASH_EN# 1 2

P
INT_FSEL# 1 I0
2 4 O
1 FSEL#
I1 FSEL# <33>

G
@ 22_0402_5%

3
1 2
R338 0_0402_5%

Reserve R177, if U12A is single gate.

KBA[0..19]
<33> KBA[0..19]
ADB[0..7]
1MB Flash ROM
<33> ADB[0..7]
+3VALW
U30

KBA0 21 31
KBA1 A0 VCC0
20 A1 VCC1 30 1
KBA2 19 C416
KBA3 A2
18 A3
KBA4 17 25 ADB0 0.1U_0402_16V4Z
KBA5 A4 D0 ADB1 2
16 A5 D1 26
KBA6 15 27 ADB2
KBA7 A6 D2 ADB3
14 A7 D3 28
KBA8 8 32 ADB4
KBA9 A8 D4 ADB5
7 A9 D5 33
KBA10 36 34 ADB6
KBA11 A10 D6 ADB7
6 A11 D7 35
KBA12 5
KBA13 A12
4 A13
KBA14 3 10 RESET# 1 2 +3VALW
KBA15 A14 RP# R443
2 A15 NC 11
KBA16 1 12 100K_0402_1%
KBA17 A16 READY/BUSY#
40 A17 NC0 29
KBA18 13 38
KBA19 A18 NC1
37 A19
INT_FSEL# 22
FR D# CE#
<33> FRD# 24 OE# GND0 23
FWE# 9 39
WE# GND1

SST39VF080-70-4C-EIE_TSOP40~N

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 34 of 47
 A B C D E F G H I J

+5VALW

1
R92
+5VALW to +5VS Transfer
1 47K_0402_5% 1

2
+5VALW +5VS SYSON#
<31,37> SYSON#

1
U27 0.1U_0402_16V4Z D
8 D S 1 <33,43> SYSON 2
C435 1 7 2 G Q6
+VSB 10U_0805_10V4Z D S 2N7002_SOT23
6 3 1 1 S

3
D S
5 D G 4
C426 C419

1
2 SI4800DY_SO8 10U_0805_10V4Z
R384 2 2 +5VALW
22K_0402_5%

1
2
RUNON R334
2 2
1 10K_0402_5%

1
D C434

2
SUSP 2 0.1U_0603_25V7K SUSP
<44> SUSP
G

1
Q26 2 D
S

3
2N7002_SOT23 2
<18,24,26,33,34,43,44> SUSP#
G Q24
S 2N7002_SOT23

3
3 3

+3VALW to +3VS Transfer

+3VALW
+3VS
U7 0.1U_0402_16V4Z
8 D S 1
1 7 D S 2
+VSB C236 6 3
D S 1 1
10U_0805_10V4Z 5 4 C229 C225
4 D G 4

1
2 SI4800DY_SO8 10U_0805_10V4Z
R136 2 2
33K_0402_5%

2
R132 1 2 RUNON +5VS +1.8VS +0.9VS
@ 0_0402_5%
1

1
D C224
SUSP 2 0.1U_0603_25V7K R335 R58 R106
G
Q11 S 2 470_0402_5% 470_0402_5% 470_0402_5%
3
2N7002_SOT23

1 2

1 2

1 2
D D D
5 5
2 SUSP 2 SUSP 2 SUSP
G G G
S Q25 S Q3 S Q8

3
2N7002_SOT23 2N7002_SOT23 2N7002_SOT23

+1.8V to +1.8VS Transfer +1.8V +3VS +2.5VS

+1.8V

1
+1.8VS VGA@
U17 0.1U_0402_16V4Z R228 R731 R105
8 D S 1
1 7 2 470_0402_5% 470_0402_5% 470_0402_5%
6 +VSB D S 6
C313 6 3 1 1

1 2

1 2

1 2
VGA@ D S C131 C133
5 D G 4 D D D
10U_0805_10V4Z VGA@
2

2 SI4800DY_SO8 10U_0805_10V4Z 2 SYSON# 2 SUSP 2 SUSP

R227 VGA@ 2 2 G G G
47K_0402_5% S Q5 S Q704 S Q7

3
VGA@ 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23
1

R129 1 2 RUNON
@ 0_0402_5%
1
1

D C312
SUSP 2 0.1U_0603_25V7K
G VGA@
Q20 S 2
3

7 2N7002_SOT23 7
VGA@

8
Security Classification Compal Secret Data Compal Electronics, Inc. 8
Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 35 of 47
A B C D E F G H I J
 5 4 3 2 1

D
CMOS Camera Conn D

+5VS

2 1
C292 C293
@ 0.1U_0402_10V6K
4.7U_0603_6.3V6M 1 2
VGA I/O PORT Connector JP42
1 1
<21> USB20_N3 USB20_N3 2 1 2
JP6 USB20_P3 R488 2 0_0603_5% 2
<21> USB20_P3 1 3 3
VGA_DDC_DAT 1 2 R489 0_0603_5% 4
<17> VGA_DDC_DAT VGA_DDC_CLK 1 2 CRMA 4
<17> VGA_DDC_CLK 3 3 4 4 CRMA <17> 5 5
JVGA_HS 5 6 6
<17> JVGA_HS JVGA_VS 5 6 LUMA GND1
<17> JVGA_VS 7 7 8 8 LUMA <17> 7 GND2
9 9 10 10
RED 11 12 COMP ACES_88266-05001
<17> RED 11 12 COMP <17>
13 13 14 14 ME@
GREEN 15 16 +3VS
<17> GREEN 15 16
17 17 18 18 +5VS
BLUE 19 20
<17> BLUE 19 20
ACES_87216-2012
ME@

C C

Finger Print board

For EMI

1
D21
PSOT24C_SOT23
@
JP37

3
USB20_P5 4
<21> USB20_P5 4
USB20_N5 3
<21> USB20_N5 3
2 2
+3VS 1 1
ACES_85201-0405
LID Switch 2 1
C315 C314
@ 0.1U_0402_10V6K
4.7U_0603_6.3V6M 1 2

+3VALW
+3VALW 1 2
R195 0_0402_5%
2

1
2

R193 R481
47K_0402_5% 100K_0402_5%
VDD

D19
1

1 OUTPUT 3 1 2 LID_SWITCH# <33>

C286 RB751V_SOD323
B 0.1U_0402_16V4Z B
1
GND

2 C287
U13 10P_0402_25V8K
1

A3212ELHLT-T_SOT23W-3 Kill Switch

+3VS
SW2
1 2 3 3
R188 10K_0402_5%
<33> KILL_SW# 2 2
KILL_SW#
1 1

1BS003-1211L_3P

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 36 of 47
5 4 3 2 1
 5 4 3 2 1

4 in 1 Card Reader UMA LCD/PANEL Conn.

+VCC_4IN1_XD +VCC_4IN1 (60 MIL) JP5
JP12 +LCDVDD 1 2 +3VS
1 2 EDID_CLK_LCD
41 XD-VCC SD-VCC 15 3 3 4 4 EDID_CLK_LCD <9>
9 5 6 EDID_DAT_LCD
MS-VCC 5 6 EDID_DAT_LCD <9>
SDDATA0_MSDATA0 33 R461 22_0402_5% 7 8
<26> SDDATA0_MSDATA0 XD-D0 7 8
SD_MSDATA1 34 4 IN 1 CONN 16 SDCLK 1 2 SDCLK_MSCLK LVDSAC+ 9 10 LVDSBC+
<26> SD_MSDATA1 XD-D1 SD_CLK <9> LVDSAC+ 9 10 LVDSBC+ <9>
SD_MSDATA2 35 19 SDDATA0_MSDATA0 LVDSAC- 11 12 LVDSBC-
<26> SD_MSDATA2 XD-D2 SD-DAT0 SDDATA0_MSDATA0 <26> <9> LVDSAC- 11 12 LVDSBC- <9>
SDDATA3_MSDATA3 36 20 SD_MSDATA1 13 14
D <26> SDDATA3_MSDATA3 XD-D3 SD-DAT1 SD_MSDATA1 <26> 13 14 D
XDD4 37 11 SD_MSDATA2 LVDSA2+ 15 16 LVDSB2+
<26> XDD4 XD-D4 SD-DAT2 SD_MSDATA2 <26> <9> LVDSA2+ 15 16 LVDSB2+ <9>
XDD5 38 12 SDDATA3_MSDATA3 LVDSA2- 17 18 LVDSB2-
<26> XDD5 XD-D5 SD-DAT3 SDDATA3_MSDATA3 <26> <9> LVDSA2- 17 18 LVDSB2- <9>
XDD6 39 13 SDCMD_MSBS 19 20
<26> XDD6 XD-D6 SD-CMD SDCMD_MSBS <26> 19 20
XDD7 40 21 SDCD#_XDCD0# <9> LVDSA1+ LVDSA1+ 21 22 LVDSB1+
<26> XDD7 XD-D7 SD-CD-SW SDCD#_XDCD0# <26> 21 22 LVDSB1+ <9>
22 LVDSA1- 23 24 LVDSB1-
SD-CD-COM <9> LVDSA1- 23 24 LVDSB1- <9>
SDCMD_MSBS 30 43 SDWP#_XDRB# 25 26
<26> SDCMD_MSBS XD-WE SD-WP-SW SDWP#_XDRB# <26> 25 26
XDWP# 31 44 LVDSA0+ 27 28 LVDSB0+
<26> XDWP# XD-WP SD-WP-COM <9> LVDSA0+ 27 28 LVDSB0+ <9>
XDALE 29 R460 22_0402_5% LVDSA0- 29 30 LVDSB0-
<26> XDALE XD-ALE <9> LVDSA0- 29 30 LVDSB0- <9>
XDCD# 23 8 MSCLK 1 2 SDCLK_MSCLK
<26> XDCD# XD-CD MS-SCLK SDCLK_MSCLK <26>
SDWP#_XDRB# 25 4 SDDATA0_MSDATA0 31 32
<26> SDWP#_XDRB# XD-R/B MS-DATA0 SDDATA0_MSDATA0 <26> GNDGND
SDCLK_MSCLK 26 3 SD_MSDATA1
XD-RE MS-DATA1 SD_MSDATA1 <26>
XD_CE# 27 5 SD_MSDATA2 ME@ ACES_88107-30001
<26> XD_CE# XD-CE MS-DATA2 SD_MSDATA2 <26>
XDCLE 28 7 SDDATA3_MSDATA3
<26> XDCLE XD-CLE MS-DATA3 SDDATA3_MSDATA3 <26>
6 MSCD#_XDCD1
MS-INS MSCD#_XDCD1 <26>
32 2 SDCMD_MSBS
XD-GND MS-BS SDCMD_MSBS <26>
24 XD-GND SD-GND 14
18 N.C. SD-GND 17
42 N.C. MS-GND 1
10
45 SHIELD GND
MS-GND Audio Jack/USB Conn.
46 SHIELD GND
TAITW_R012-210-LR +USB_VCCB
JP27
1 1
2 2
<21> USB20_N2 USB20_N2 3
USB20_P2 3
<21> USB20_P2 4 4
5 5
USB20_P4 6
PWR ON/OFF SW & LED <21>
<21>
USB20_P4
USB20_N4
USB20_N4 7
6
7
8 8
C C
+USB_VCCC 9 9
+3VALW +3VS USB20_P6 10
<21> USB20_P6 10
<21> USB20_N6 USB20_N6 11
JP29 11
12
Lan1 Conn. 1 1 1 2 C527 PR
470P_0402_50V8J <30> PR
PR
JACK_PLUG
13
12
13
2 2 2 <29> JACK_PLUG 14 14
C525 @68P_0402_50V8K 3 1 2 C528 JACK_PLUG PL 15
<33> AMP_MUTE# 3 470P_0402_50V8J <30> PL 15
JP41 4 16
<33> VOL_UP# 4 16
<27> ACTIVITY# 1 2 10mil 10 Green LED- <33> VOL_DOWN# 5 5 1 2 C529 PL 17 17
R327 @300_0402_5% 6 470P_0402_50V8J 18
<33> MEDIA# 6 INT_MIC 18
9 7 LINE_IN_L-1 19
+3VALW Green LED+ 7 <30> LINE_IN_L-1 19
ON/OFFBTN# 8 1 2 C530 20
MDO3- <32> ON/OFFBTN# 8 0.1U_0402_25V4K 20
<27> MDO3- 1 PR4- <33> PWR_LED# 9 9
DRIVE_LED# 10 1 2 C531 ACES_87213-2000
MDO3+ 10 0.1U_0402_25V4K ME@
<27> MDO3+ 2 PR4+ 11 11
<33> NUM_LED# 12 12 1 2 C532
MDO1- 3 13 0.1U_0402_25V4K
<27> MDO1- PR2- <33> CAPS_LED# 13
14 14 1 2 C533
MDO2- 4 0.1U_0402_25V4K
<27> MDO2- PR3- ACES_85202-1405
MDO2+ 5 ME@
<27> MDO2+ PR3+
MDO1+ 6
<27> MDO1+ PR2+ +3VS MIC1
MDO0- 7 INT_MIC 1
<27> MDO0- PR1-
SHLD2 14 2

5
MDO0+ 8 U20
<27> MDO0+ PR1+
13 ODD_LED# 1 WM-64PCY_2P

P
SHLD1 <23> ODD_LED# B
1 210mil 12 4 DRIVE_LED# 45@
<27> LINK_10_100# Yellow LED- Y
R328 @300_0402_5% SATA_LED# 2
<20> SATA_LED# A

G
+3VALW 11 Yellow LED+ TC7SH08FUF_SSOP5 +5VS

3
B
2 1 FOX_JM74113-P2101-7F +USB_VCCB B
C526 @68P_0402_50V8K ME@ U9
C399 1 8
RJ45_PR 0.1U_0402_16V4Z LANGND C483 0.1U_0402_16V4Z GND OUT
<27> RJ45_PR 1 2 2 IN OUT 7
1 1 2 1 3 IN OUT 6
1000P_1206_2KV7K SYSON# 4 5
C191 C192
4.7U_0805_10V4Z
Front LEDs <31,35> SYSON# EN#
G528_SO8
FLG USB_OC#2 <21>
USB_OC#4 <21>
2 2 1
+3VS C500
D6 @ 1000P_0402_50V7K
<28> WIRELESS_LED# 2 1 1 2
R190 200_0402_5% 2
HT-110UYG-CT_YEL/GRN
D7
<28> BTONLED 2 1 1 2
R194 200_0402_5% +5VS
HT-110UYG-CT_YEL/GRN +USB_VCCC
D18 U10
<26> 3IN1_LED# 2 1 1 2 1 GND OUT 8
R476 200_0402_5% C276 0.1U_0402_16V4Z 2 7
HT-110UYG-CT_YEL/GRN IN OUT
2 1 3 IN OUT 6
<31,35> SYSON# SYSON# 4 5 1 2
EN# FLG R172 0_0402_5% USB_OC#6 <21>
+3VALW G528_SO8
SUSP_LED# D8
<33> SUSP_LED# 2 1 1 2
R191 200_0402_5%
T/P Board HT-110UYG-CT_YEL/GRN
1
C273
@ 1000P_0402_50V7K
D5
CHARGE0 2
<33> CHARGE_LED0# 1 2 2
+5VS R192 200_0402_5%
A A
1
JP28
1 2 CHARGE1 3
1 <33> CHARGE_LED1#
R189 200_0402_5%
2
3 AMBER_LED# HT-210UD/UYG_AMB/GRN
4
5 TP_DATA <33>
6 TP_CLK <33> Security Classification Compal Secret Data Compal Electronics, Inc.
ACES_85201-0605 Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
SCHEMATIC, M/B LA-3111P Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401408
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 37 of 47
5 4 3 2 1
 A B C D E F G H I J

1 1

2 2

3 3

4 4

5 5
CF6 CF9 CF11 CF10 CF12 CF2 CF1 CF4 CF3 CF5
1 1 1 1 1 1 1 1 1 1

CF7 CF8 CF13 CF14

1 1 1 1

FM3 FM1 FM4 FM2

1 1 1 1

H1 H2 H3 H4 H5 H6 H7 H8 H9 H10
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
6 6
1

1
H11 H12 H13 H14 H15 H17 H18 H19 H20
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

1
7 H21 H22 H23 H24 H25 H26 H27 H28 7
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

8
Security Classification Compal Secret Data Compal Electronics, Inc. 8
Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 38 of 47
A B C D E F G H I J
 A B C D

PR213 ACIN BATT ONLY

10K_0402_1%
1 2
Precharge detector Precharge detector
+3VALWP ADP_ID <33>

@820P_0603_50V7K
Min. typ. Max. Min. typ. Max.

2
0.1U_0402_16V7K
H-->L 14.589V 14.84V 15.243V H-->L 6.138V 6.214V 6.359V

1
PC154

PC185
PJP1
@ JST_B5B-EH-A(LF)(SN) @ PD20 L-->H 15.562V 15.97V 16.388V L-->H 7.196V 7.349V 7.505V

2
V-PORT-0603-220 M-V05_0603 VIN
1 1

1
2 PF1 PL2
1
2 12A_65V_451012MRL ADPIN FBMA-L18-453215-900LMA90T_1812 PR2 1

3 2 1 1 2 1K_1206_5%
3

10_1206_5%
1 2

1
100P_0402_50V8J
560P_0402_50V7K
4 4

PR1
100P_0402_50V8J

560P_0402_50V7K
PQ1

1
5 PD2 PR3 TP0610K-T1-E3_SOT23
5

PC1

PC2

PC3

PC4
RLS4148_LLDS2 1K_1206_5%
VS 2 1 1 2 3 1

12

RLZ24B_LL34
PD1
PR4
1K_1206_5%
1 2

100K_0402_5%

100K_0402_5%
2

1
PR8

PR6

PR7
1K_1206_5%

2
PR175 PC131 1 2
10K_0402_1% 0.01U_0402_25V7K
1 2 1 2

2
VS
PR5
VIN 1M_0402_1%
1 2

10K_0402_1%

100K_0402_5%
1

1
84.5K_0402_1%
1

VS

PR9

PR13
1
PR10

PR11
10K_0402_5%
1 2

1 2
PR12 ACIN <21,33>
2

2 22K_0402_1% PU1A 2 2

1 2 3 <33,41> ACOFF
P

+ PACIN
O 1 PACIN <41>
0.047U_0402_16V7K

20K_0402_1%

2 - B+
1

G
0.1U_0402_16V7K

RLZ4.3B_LL34

10K_0402_1%
PQ2 2

3
1

1
PR14

LM393DT_SO8 DTC115EUA_SC70
4
PC5

PC6

PR15
PD3
Vin Detector
2

PQ3
2

3
PR16 DTC115EUA_SC70
2

2
10K_0402_1%
2 1 RTCVREF
3.3V High 18.764 17.901 17.063
Low 17.745 16.9 16.03 VL
PR17
2.2M_0402_5%
2 1

VIN

RLS4148_LLDS2

499K_0402_1%
1
2

PR18
PD4

100K_0402_1%
1
VS

PR19
PD5

2
RLS4148_LLDS2

1 1
2 1
3.3V BATT+ VS

33_1206_5%
PD6

8
RTCVREF

PR20
RB715F_SOT323
<40,42> MAINPWON 2 5

P
3 3

PU2 PQ4 +
1 7 O

0.01U_0402_25V7K
191K_0402_1%

499K_0402_1%
PR22 G920AT24U_SOT89 PR23 TP0610K-T1-E3_SOT23 PR276 <41> ACON 3 6

2
-

1
PR21 560_0603_5% 200_0805_5% 33_1206_5%

PC7
PR24

PR25
1000P_0402_50V7K
560_0603_5%
1 2 1 2 3 2 2 1 CHGRTCP 3 1 2 1 PR271

4
OUT IN

1
0.22U_1206_25V7K

200K_0402_1% PU1B
1

PC9
4.7U_0805_6.3V6K

0.1U_0603_25V7K
PC10
1U_0805_25V4Z

+CHGRTC <41> PRECHG 2 1 LM393DT_SO8

2
1

GND
PC11

100K_0402_5%

PRG++ 2

2
1

PC8
0.1U_0603_25V7K
PR26

PC12

PC13
2

1
2

2
PR27
2

22K_0402_1% PQ5
1 2 PR28 RHU002N06_SOT323 PR29
<32> 51ON#

1
PJ1 34K_0402_1% D 47K_0402_5%
PAD-OPEN 3x3m PJ2 PAD-OPEN 3x3m
2 1 2 2 1
+1.5VSP 1 2 +1.5VS 1 2 +1.8V
RTCVREF G PACIN <41>
+1.8VP

1
S

3
66.5K_0402_1%
1
(6A,240mils ,Via NO.=12) (6A,240mils ,Via NO.= 12)

PR30
PJ3 PJ4 2 +5VALWP
PAD-OPEN 3x3m PAD-OPEN 3x3m @
+5VALWP 1 2 +5VALW +0.9VSP 1 2 +0.9VS

2
PQ6

3
DTC115EUA_SC70
(5A,200mils ,Via NO.= 10) (0.3A,40mils ,Via NO.= 2)
4 PJ6 PJ11 4

PAD-OPEN 3x3m PAD-OPEN 3x3m

+3VALWP 1 2 +3VALW +2.5VSP 1 2 +2.5VS

(4.5A,180mils ,Via NO.= 9)

PJ7 PJ8 Security Classification Compal Secret Data Compal Electronics, Inc.
PAD-OPEN 3x3m PAD-OPEN 3x3m 2005/10/06 2006/10/06 Title
Issued Date Deciphered Date
1 2 1 2
+1.05VSP +VCCP +VSBP +VSB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 401408 B
(5A,200mils ,Via NO.= 10) (0.3A,40mils ,Via NO.= 2) MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 39 of 47
A B C D
 A B C D

@ PJP2 PF2 BATT++ PL3

ALLTO_C103D6-10701-L 12A_65V_451012MRL FBMA-L18-453215-900LMA90T_1812
PH1 under CPU botten side :
BATT_S1 BATT+
1 1 PR177
2 1
PR178
1 2 CPU thermal protection at 85 degree C

0.01U_0402_25V7K
1000P_0603_50V7K

1000P_0603_50V7K
1K_0402_1% 47K_0402_5%
2 ALI/NIMH# 1 2 1 2
Recovery at 70 degree C
2 +3VALWP

PC15
3 AB/I VS
3

1
PC14

PC16
4 TS_A
4 EC_SMDA
5

2
5

1
VL

0.1U_0603_25V7K
1K_0402_1%
1 6 EC_SMCA 1

2
6 VL

PR176
7 7

PC17
8.66K_0402_1%

150K_0402_1%
1

2
100_0402_1%

100_0402_1%

2
1

1
PR31

PR32
PR35

PR33
PR34
ALI/MH# 1 442K_0603_1%
2

1
PR36

2
6.49K_0402_1% PR37

8
1 2 47K_0603_1%
+3VALWP
1 2 3

P
+
O 1
MAINPWON <39,42>

1K_0402_1%
TM_REF1 2 -

G
100K_0603_1%_TH11-4H104FT
PU3A

1
PR38
LM393DT_SO8

4
PH1
1000P_0402_50V7K
2

1U_0603_6.3V6M
BATT_TEMP <33>

2
1

PC18

PC19
PR39
EC_SMB_DA1 <33,34>
2 150K_0402_1%
1 VL

2
EC_SMB_CK1 <33,34>

150K_0402_1%
1
PR40
2 2

2
PQ7
TP0610K-T1-E3_SOT23 VS
B+ 3 1 +VSBP
0.22U_1206_25V7K

0.1U_0603_25V7K
1

8
100K_0402_5%

1
PR41

PC20

PC21 5

P
+
O 7
6
2

G
PR42 PU3B
2

22K_0402_1% LM393DT_SO8

4
VL 1 2
100K_0402_5%
2
PR43

3 3

PR44
1

0_0402_5% D
1 2 2
<42> SPOK G
0.1U_0402_16V7K

S PQ8
3
1

PC22

RHU002N06_SOT323
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 40 of 47
A B C D
 A B C D E

65W PR45=0.02_2512_1% PR54=30K_0402_1% Iadp=0~3.125A

90W PR45=0.15_2512_1% PR54=28.7K_0402_1% Iadp=0~4.3A Fosc=14100/Rt=14100/47=300KHz PJ12
PAD-OPEN 3x3m
Charger
1 2

P2 PR45
B+ PQ11 PQ39
PQ9 PQ10 0.02_2512_1% AO4407_SO8 AO4407_SO8
AO4407_SO8 AO4407_SO8 1 8 8 1
8 1 1 8 1 4 2 7 7 2
PL4
VIN 7
6
2
3
2
3
7
6 2 3 FBMA-L11-322513-201LMA40T_1210 CHG_B+ 3 6
5
6
5
3

5 5 1 2

4.7U_1206_25V6K

4
200K_0402_1%

2200P_0402_50V7K
0.1U_0603_25V7K

4.7U_1206_25V6K

0.1U_0603_25V7K

BATT+
1 PR272 1

4
1
PR48 100K_0402_1%

1
PC27

PR46

PC23

PC24
47K_0402_1% 1 2

1
PC25

PC26
P2 1 2
VIN
1

47K_0402_5%

1
10K_0402_1%

10K_0402_1%
PR47

PR273
PR50
1

0_0603_5%
2

PR49
PQ12 PU4

32
DTA144EUA_SC70 MB39A126PFV-ER_SSOP24

1
47K
1 -INC2 +INC2 24 ACOFF#
47K

3
2
1
2 PR51 PC28 PR52

2
47K
10K_0402_1% 4700P_0402_25V7K 100K_0402_1% 2
47K

1
MB39A126 1 2 1 2 2 1 2 23
OUTC2 GND

1
PC29 4 PQ13
0.22U_0603_16V7K AO4407_SO8
3 22 CS 1 2
1

+INE2 CS
1

DTA144EUA_SC70
PC30 2ACOFF ACOFF <33,39>

PQ41
0.1U_0603_25V7K 2

10K_0402_1%

30K_0402_1%
0.01U_0402_25V7K
4 -INE2 VCC 21 1 2 PRECHG <39>

5
6
7
8
1

PC31

PR53

PR54
2 PQ14

3
5 20 DTC115EUA_SC70 PQ40

3
ACOK OUT PC32 DTC115EUA_SC70
2

0.1U_0603_25V7K
2

2
PQ15

LXCHRG
6 19 1 2
3

VREF VH
1

150K_0402_1%

0.22U_0603_16V7K
DTC115EUA_SC70
PR55
1

1
D PC33 PL5 PR56
7 18
ACIN XACOK VIN

BATT+
2 PR57 PC34 PR58 10U_LF919AS-100M-P3_4.5A_20% 0.02_2512_1%
G 1K_0402_1% 2200P_0402_50V7K 56.2K_0402_1% 1 2 1 4
2

2 MB39A1261 2
S 2 1 2 8 17 1 2
3

-INE1 RT

1
47K_0402_5%

EC31QS04

EC31QS04
PQ16 2 3

PD10

PD11
RHU002N06_SOT323

10U_1206_25VAK

10U_1206_25VAK

10U_1206_25VAK
PR59
9 +INE1 -INE3 16
PR60 PR61 PR62 PC35

1
PC36

PC37

PC38
IREF 133K_0402_1%
<33> 10K_0402_1% 33K_0402_1% 1500P_0603_50V7K

2
1 2 2 1 10 15 MB39A126 1 21 2

2
OUTC1 FB123
1

2
100K_0402_1%

0.01U_0402_25V7K

2
1

PC39

G 11 14
SEL CTL

47K_0402_5%
PR63

S PQ17 PC40
3

1
RHU002N06_SOT323 10P_0402_50V8J
2

PR64
12 -INC1 +INC1 13 1 2

0_0402_5%
2

PR65

2
PD12
RLS4148_LLDS2
ACOFF# 1 2 2

PR66
22K_0402_1% +3VALWP
<39> PACIN 1 2 PC41
47K_0402_5%

CS 47P_0402_50V8J
1

IREF=0.932*Icharge 1 2
PR67

IREF=0.466~3.1V
<39> ACON
2

3 3
2
LI-3S :13.05V----BATT-OVP=1.45V
1

CC=3.3A
PQ18
BATT-OVP=0.111*BATT+ (100K/(100K+133K))*3.1V=1.33V
3

DTC115EUA_SC70

<33> FSTCHG
2
BATT+
1.33/(20*0.02)=3.33A

499K_0402_1% 340K_0402_1%
1
PQ19 VS
3

PR68
DTC115EUA_SC70

0.01U_0402_25V7K

2
CP Point=3.06A

PC42

1
5V*(10K/(30.9k+10k))=1.222V

PR69
2
1.222V/(20*0.02)=3.06A

2
8
5

P
+
VS <33> BATT_OVP 7 0
- 6
G

105K_0402_1%
1

0.01U_0402_25V7K
PU12B
4

1
PR72
PU12A LM358DR_SO8
Charge voltage
8

PC43
LM358DR_SO8
+ 3 3S CC-CV MODE : 12.6V
P

2
1

2
0
4
- 2 SEL is L 4
G
4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 41 of 47
A B C D E
 A B C D

B+

PL6
FBMA-L11-322513-201LMA40T_1210

PC45 PC46
1

0.1U_0603_25V7K 0.1U_0603_25V7K

2
1 2 BST5B BST3B 1 2
PJ13
1 JUMP_43X79 B+++ 1

MAX8743_B+

SI4800BDY-T1-E3_SO8
1 1 2 2 2200P_0402_50V7K VL

8
7
6
5
10U_1206_25VAK
PD13

1
CHP202UPT_SOT323-3 PJ14

D
D
D
D
1

2
PC48

0_0603_5%
PQ21
JUMP_43X79
MAX8743_B+
PC47

PR74

SI4800BDY-T1-E3_SO8
2200P_0402_50V7K
MAX8743_B+ 1 1 2 2

0.1U_0402_16V7K
47_0402_5%

10U_1206_25VAK
2

5
6
7
8
S
S
S

4.7_1206_5%

4.7_1206_5%

PR75

1
PR76

PR77

PC49
PR78

D
D
D
D
1
2
3
4

PC50

PC51

PQ20
0_0603_5%

2
5HG 1 2 DH5

2
2

G
S
S
S
LX5

SI4810BDY-T1-E3_SO8
@

4
3
2
1
8
7
6
5

2
PC52

0.1U_0603_25V7K
1U_0805_25V4Z

0_0603_5%
PR79
VL 3HG

D
D
D
D
PQ29
LX3

2
2VREF_1999
4.7UH_PCMC063T-4R7MN_5.5A_20%

5
6
7
8
4.7U_0805_6.3V6K

1 PC55

SI4810BDY-T1-E3_SO8
1
G
S
S
S

1U_0805_16V7K

365K_0402_1% 200K_0402_1%

215K_0402_1% 200K_0402_1%

D
D
D
D
1

2
PC53

PR80

PR81
1
2
3
4

PQ30
BST3A

PC54

G
S
S
S
0_0603_5%
DL5

PR82
2 1

4
3
2
1
2

18

20

13

17

2
PL7

PR83

4.7UH_PCMC063T-4R7MN_5.5A_20%
BST5A 14

V+
LD05

TON

VCC

1
BST5

PR84
2
ILIM3 5 2

16 DL3
DH5
+5VALWP
1

2
15

1
LX5
19 DL5 ILIM5 11

PL8
21 OUT5
9 PU6 28
FB5 BST3
150U_V_6.3VM_R18

10.2K_0402_1%

1 26 DH3
N.C.MAX8734AEEI+_QSOP28 DH3
2

24

1
DL3
150U_V_6.3VM_R18

PR85

6 SHDN# LX3 27
VS 4 22
1 1 ON5 OUT3
1 2 3 ON3
PC186

PC56

+ + PR86 7
1

@ 0_0402_5% FB3
12 SKIP# PGOOD 2 +3VALWP
2 2 2VREF_19998

PRO#
LDO3
PZD1 PR88

GND
REF
2

2
0_0402_5%

0_0402_5% @ 3.57K_0402_1%
@ RLZ5.1B_LL34 47K_0402_5% PR89
PR87

PR90
1 2 1 2 10_0402_5%2

150U_V_6.3VM_R18
23

25

10
0.047U_0603_16V7K

0.22U_0603_16V7K
1

14.7U_0805_6.3V6K
100K_0402_5%
1

1
2

PC59

PC58
+
PR91

PC57

2
PC60

0_0402_5%
<40> SPOK
2

2
2

PR92

2
1

PR93
PR94
+5V Ipeak = 6.66A ~ 10A 47K_0402_5%
1 2
0.047U_0603_16V7K

3 3

1
1

PC61
2

+3.3V Ipeak = 6.66A ~ 10A

MAINPWON <39,40>
1U_0603_6.3V6M
1

PC62
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 42 of 47
A B C D
 5 4 3 2 1

D D

PJ15
JUMP_43X79
1 OZ813_B+
1 2 2
PF5 PL9
@ 7A_24VDC_429007.WRML FBMA-L11-322513-201LMA40T_1210
2 1 1 2 B+
+3VALWP

10U_1206_25VAK
SI4800BDY-T1-E3_SO8

1
1K_0402_1%

PC63
1.8VS2N

8
7
6
5
1.8VS2P

PR261

D
D
D
D

2
PQ22
PR262
@ 0_0402_5%
1 2 @

G
S
S
S
PR269 PL10
+5VALWP 0_0402_5% 3.3UH_PCMC063T-3R3MN_6A_20%

1
2
3
4
PR266 DH_1.8V_1 1 DH_1.8V_2
0_0402_5% 1.8VSET
2 1 2 +1.8VP OCP=6A

220U_D2_4VM_R15
2 1 LX_1.8V

1
<33,35> SYSON

51_0402_1%
1

8
7
6
5
0.01U_0402_25V7K

PR95
PC65
1

0.1U_0603_25V7K
PC184

PC66
1000P_0402_50V7K PR97 PR98 +

D
D
D
D
2
100K_0402_1% 22K_0402_1%

2
1
PQ23 1 2 1 2
2

PC67
SI4810BDY-T1-E3_SO8 PC68

G
S
S
S
PU7 6800P_0402_25V7K

25

24
23
22
21
20
19

DL_1.8V
2
C 1.8VS2P 1 2 C

1
2
3
4
2

2
22_0402_1%

1K_0402_1%

CS2P
GNDA

CS2N
VSET2

PGD2
LX2
HDR2
PR99

PR100
@
RB751V-40TE17_SOD323-2

4700P_0402_25V7K
PD16 1.8VS2N
PR101 1 18 BST_1.8V 1 2

1
ON/SKIP2 BST2

1
PC69
22P_0402_50V8J

PC70
0_0402_5% 2 17
DREF VIN LDR2
2 1 3 VREF VDDP 16 +5VALWP
4 15

2
TSET GDNP

1
0.022U_0402_16V7K

0.1U_0603_25V7K

5 VDDA LDR1 14
2
24K_0402_1%

100K_0402_1%
6 13 PC71 +5VALWP
ON/SKIP1 BST1
1

0.01U_0402_25V7K
PR103

PC72

PC73

PC74
1U_0603_6.3V6M
1U_0805_16V7K
OZ813LN_QFN24

2
PR104

PC75
PJ18

VSET1

PGD1

HDR1
CS1N
CS1P
JUMP_43X79
2

LX1
PD17 1 2 2
1

2.2U_0603_6.3V6K
PR105 BST_1.05V1 2
1

@ 75K_0402_1% PF6

7
8
9
10
11
12

1
RB751V-40TE17_SOD323-2 @ 7A_24VDC_429007.WRML

PC156
PC76 2 1 OZ813_B+

0_0402_5%
0.1U_0603_25V7K

2
1.8VSET

PR263

2
DH_1.05V_1 PL11
150K_0402_1%

3.3UH_PCMC063T-3R3MN_6A_20%
2

1.05SET @ LX1.05V 1 2 +1.05VSP OCP=6A

1
2

61.9K_0402_1%
PR106

51_0402_1%
0_0402_5%
PR172

1.05VS1P

DL_1.05V

PR270

PR107

220U_D2_4VM_R15
PC77 1
1000P_0402_50V7K 1.05VS1N
1

PC78
PR108 PR109 +
1

5
6
7
8

SI4800BDY-T1-E3_SO8
100K_0402_1% 29.4K_0402_1%

2
10U_1206_25VAK
1 2 1 2

D
D
D
D
1

1
2

1K_0402_1%
PC80

DH_1.05V_2
PR264

PC79
B 5600P_0402_25V7K B

PQ24
1.05VS1P 2 1

2
G
S
S
S
PR179
2

4
3
2
1
100K_0402_1% @

4700P_0402_25V7K
2 1 1.05VS1N
<18,24,26,33,34,35,44> SUSP#
0.1U_0402_16V7K
1

1
PC81
22P_0402_50V8J

PC82
+3VALWP
PC132

5
6
7
8

SI4810BDY-T1-E3_SO8
2

2
D
D
D
D
PQ31
G
S
S
S
4
3
2
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: G, 21, 2006 Sheet 43 of 47
5 4 3 2 1
 5 4 3 2 1

PJ16
JUMP_43X79
1 1 2 2

PF7
D PL12 D
@ 7A_24VDC_429007.WRML
B+ 1 2 2 1

10U_1206_25VAK
FBMA-L11-322513-201LMA40T_1210
PHASE_VCCPP

PC83
PR265
10K_0402_1% UG_VCCPP
1 2 PR110

2
1 2 1 2

0_0603_5% PC85 0.1U_0402_16V7K

+5VS

1
BOOT_VCCPP
PR111
@4.7_0603_5%

5
6
7
8
17

16

15

14

13
PU8 PQ26

D
D
D
D
2
1 PR1122 6269_VCC

PHASE
GND

PGOOD

UG

BOOT
4.7_0603_5%

G
S
S
S
1 VIN PVCC 12 1 2 PC86
SI4800BDY-T1-E3_SO8

4
3
2
1
2.2U_0603_6.3V6K
OCP=6A
6269_VCC 2 11 LG_VCCPP PL13
VCC LG 3.3UH_PCMC063T-3R3MN_6A_20%
1 2 +1.5VSP
PR113

1
1 2 3 FCCM PGND 10 1

5
6
7
8
PC87
2.2U_0603_6.3V6K 0_0402_5% PQ27 + PC88

D
D
D
D
PR114
C
2 SI4810BDY-T1-E3_SO8 220U_D2_4VM_R15 C
1 2 4 9 ISEN_VCCPP
1 2
<18,24,26,33,34,35,43> SUSP# EN ISEN PR115 2

COMP

G
S
S
S
8.66K_0402_1%

FSET
47K_0402_5%
1

VO
FB

4
3
2
1
PC89
0.01U_0402_25V7K
2

8
ISL6269CRZ-T_QFN16

1
22P_0402_50V8J
1

PR117
PR116 PC90
PC91

49.9K_0402_1% 0.01U_0402_25V7K

2
2

2
1
57.6K_0402_1%
PC92
6800P_0402_25V7K
2 PR118
1 2

4.53K_0402_1%

1
PR119
3K_0402_1%
+1.8VP

B +3VS B
2

1
PJ9

1
+5VS JUMP_43X118
1

2
PJ10
1

JUMP_43X79

2
1

PC93 PU9
1 6 +3VALWP
2

1U_0603_6.3V6M VIN VCNTL

2

2 GND NC 5

1
6

1
PU10 PC94 3 7 PC95
PC96 22U_1206_6.3V6M VREF NC 1U_0603_6.3V6M
5
VCNTL

2
VIN 22U_1206_6.3V6M PR120
7 4 8
2

POK 1K_0402_1% VOUT NC

VOUT 4
PR121 9

2
TP
VOUT 3 +2.5VSP
33K_0402_1% 1
1

1 2 8 2 APL5331KAC-TRL_SO8
EN FB
1

,26,33,34,35,43> SUSP#
22U_1206_6.3V6M

PR122 + PC98 PR123 RHU002N06_SOT323

GND

+0.9VSP

1
PQ28 D
PC97

9 PC99 @ 150U_D_6.3VM 100K_0402_1%

2

VIN
1

1
2.15K_0402_1% 2 1 2
2

1
PC100 2 <35> SUSP G PR124 PC101
1

0.01U_0402_25V7K S 1K_0402_1% 0.1U_0402_16V7K PC102

2

2
1

APL5912-KAC-TRL_SO8 22U_1206_6.3V6M

2
1

0.01U_0402_25V7K PC103
0.1U_0402_16V7K
2

PR125
1K_0402_1%
A A
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: G, 21, 2006 Sheet 44 of 47
5 4 3 2 1
 5 4 3 2 1

+5VS
PJ17
PAD-OPEN 3x3m
1 2
CPU_B+ B+
PR214 PL14
5VS12 1 FBM-L11-322513-201LMAT_1210
2 1 2 1

0.01U_0402_25V7K
0_1206_5%

2200P_0402_50V7K
0.1U_0603_25V7K
PR215 PF8 1

100U_25V_M
PC157
10_0402_5% @ 7A_24VDC_429007.WRML

1
10U_1206_25VAK

10U_1206_25VAK

10U_1206_25VAK

PC158
+

200K_0402_5%

PC159

PC160

PC161

PC162

PC163
2

2
2 PR216 1

2
D D

2
PC164 2

2
2.2U_0603_6.3V6K

2
13K_0402_5%
PC165

1
PR217
1U_0603_6.3V6M

SI7682DP-T1-E3_SO8
PU11

1
NTC

PQ32
100K_0402_5% V CC 19 25
PR218 Vcc VDD 0.22U_0603_16V7K 4
1 2 6 8 PR220
THRM TON 2.2_0402_5% PC166
PR219 0_0402_5% 2 1 31 30 BST1_CPU 1 2 BSTM1_CPU 1 2
<5> CPU_VID0 D0 BST1 +CPU_CORE
PR274

3
2
1
PR221 0_0402_5% 2 1 32 29 DH1__CPU 10_0402_5%2 PL15
<5> CPU_VID1 D1 DH1 P_0.36H_ETQP4LR36WFC_24A_20%
PR222 0_0402_5% 2 1 33 28 LX1__CPU 2 1 +CPU_CORE
<5> CPU_VID2 D2 LX1

6.8_1206_5%

2.1K_0603_1%
PR223 0_0402_5% 2 1 34 26 DL1__CPU
<5> CPU_VID3 D3 DL1

5
6
7
8

5
6
7
8

2
PR224

PR226
PR225 0_0402_5% 2 1 35 27
<5> CPU_VID4 D4 PGND1

IRF8113PBF_SO8

IRF8113PBF_SO8
PR227 0_0402_5% 2 1 36 18
<5> CPU_VID5

2
D5 GND

1
PQ33

PQ34

10_0402_5%
PR230

PR229
PR228 0_0402_5% 1 2 37 17 CSP1__CPU 4 4 3.48K_0402_1% PR231 NTC
<5> CPU_VID6 D6 CSP1

470P_0603_50V7K
PC167
1 2 1 2

DL1__CPU
PR2322 71.5K_0402_1%
1 7 16 CSN1_CPU
TIME CSN1 <5>
10KB_0603_5%_ERTJ1VR103J VCCSENSE

2
2 1 9 12 FB_CPU

3
2
1

3
2
1
470P_0402_50V8J PC168 CCV FB PC169
1 2 11 10 C CI_CPU 0.22U_0603_16V7K
C REF CCI C
1 2
PR233 499_0402_1% 1 2 PC170 0.22U_0603_16V7K 39 21 DH2_CPU
<7,21> DPRSLPVR DPRSLPVR DH2

100_0402_5%
PR234 0_0402_5% 1 2 40 20 BST2_CPU
<4,20> H_DPRSTP# DPRSTP BST2

PR235
1 2 3 22 LX2_CPU PR237 0_0402_5%
<5> H_PSI# PSI LX2
PR236 0_0402_5% 1 2
+3VS 2 24 DL2__CPU

1
PWRGD DL2 PR238 3K_0603_1% PC171 0.022U_0402_16V7K

2.2_0402_5%
1 23 1 2 1 2 CPU_VCC_SENSE
CLKEN PGND2
10K_0402_1%

PR239
2

2
2K_0402_1%

38 14 CSP2_CPU PR242 3.65K_0402_1% PR243

SHDN CSP2
PR240

PR241

1 2 1100_0402_5%
2

4700P_0402_25V7K
5 15 CSN2__CPU

1
PR244 VRHOT CSN2 PR245 PR246

PC172
0_0402_5% 4 13 NTC @ 3K_0603_1% @ 3K_0603_1%
1

POUT GNDS
1 2 1 2 1 2

BSTM2_CPU
<21> VGATE

1
PR247
10_0402_5%2 PR248 PC173
<15> CLK_ENABLE# MAX8770GTL+_TQFN40 20K_0402_1% 470P_0402_50V8J

2
PR249 1 2 1 2
<33> VR_ON 10_0402_5%2 PC174
1000P_0402_50V7K
1
2

CPU_B+
10K_0402_5%

0.22U_0603_16V7K
1
+3VS
PR250

PC175
1

56_0402_5%

PR251

2200P_0402_50V7K
PR252

10U_1206_25VAK

10U_1206_25VAK

10U_1206_25VAK

0.1U_0603_25V7K
100_0402_5%
1

1
PC176

PC177
@ PR253
1

SI7682DP-T1-E3_SO8

PC178

PC179

PC180
B @ 0_0402_5% B
2

1 2 VSSENSE
29.6

2
<4> H_PROCHOT# <5> VSSENSE PR275

PQ35
PR254 0_0402_5%
1

10K_0402_5% 1 2 4
+3VS 1 2 PR255
10_0402_5%
0.1U_0402_16V7K
2
10K_0402_1%

PC181

3
2
1
1

2 1
PR267

PL16

6.8_1206_5%
P_0.36H_ETQP4LR36WFC_24A_20%

5
6
7
8
2

5
6
7
8

PR256
@ CLK_ENABLE# <15>

IRF8113PBF_SO8
PR268
1

1
D

2.1K_0603_1%
IRF8113PBF_SO8
@ 0_0402_5%

2
PQ36

PR257
VGATE 1 2 2 PQ38

PQ37
G @ 2N7002-7-F_SOT23-3 4

470P_0603_50V7K
DL2__CPU
S 4
3

2
1

PC182
PR258 PR259 NTC

3
2
1
3.48K_0402_1% 10KB_0603_5%_ERTJ1VR103J

3
2
1

2
1 2 1 2

1 2

A PR260 0_0402_5% PC183 0.22U_0603_16V7K A

1 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/10/06 Deciphered Date 2006/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-3111P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401408 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 45 of 47
5 4 3 2 1
 A B C D E

Version change list (P.I.R. List) Page 1 of 1

Item Fixed Issue/Reason for change Rev. PG# Modify List B.Ver# Phase
1 B Test Add U37(TC7SH08FUF) 1
Implement S4 0.2 21 1. Connect U37 pin1(SLP_S4#) ,pin2(SLP_S5#) to U3(SB)
1
2. Connect U37 pin4(PM_SLP_S5#) to U6(EC) pin17
3. Del R482"

2 Change ICH7M GPIO pin control 0.2 21 Change G7X_THER_ALERT# net from U3 (ICH7M) pin AD20
(GPIO 38) to pinAC18 (GPIO7)

3 SD/XD card can't work/Reverse solve MS Duo short solution 0.2 26 Add a D22(DAN202U),R490,R491
1. Connect D22 pin3 to MSCD#_XDCD0
2. Connect D22 pin2 to MSCD#_XDCD1
3. Connect D22 pin1 to JP12 pin23(XDCD#)
4. Connect R490 pin2 to SDDATA1_MSDATA1
5. Connect R490 pin1 to SD_MSDATA1
6. Connect R491 pin2 to SDDATA2_MSDATA2
7. Connect R491 pin1 to SD_MSDATA2
Change R456,Q33,Q35 to no stuff

2 2
4 Set amplifier gain 0.2 30 Connect U36 pin 7 to R486 pin 2

5 Add ADP_ID 0.2 33 1. Connect R401 pin1 to PR213 pin2

6 Support wake on Ring/Disable MDC function 0.2 28 1. Change JP17 pin6 from +3VS to +3VALW
2. Add R495,D23
3. Connect D23 pin1/2 to ICH_RST_MDC#
4. Connect D23 pin3 to ICH7M GPIO

7 HD Audio design change 0.2 29 1. Change line out from pin 35/36 to pin 43/45
2. Add R494 and connect R494 pin 1 to R166 pin 2
3. Connect R494 pin 2 to +AVDD_AC97
4. Add C527/C528/C529/C530 for EMI

8 VCCLAN3_3 power plant change 0.2 22 Connect U3(ICH7M) pin V5/V1/W2/W7 to +3VS

9 Reverse +3VS for Lan power 0.2 27 1. Add R498,R499

3 2. Connect R498 pin1 to +3VS and Connect R499 pin 1 to +3VALW 3
3. Connect R498/R499 pin 2 to +3V_LAN

10 Finger print connector change 0.2 27 Change JP37 from ACES_85201-0605 to ACES_85201-0405

11 Change KB910L GPIO pin control 0.2 33 Change SUSP_LED# from U3 (KB910L) pin 35 to pin 102

C Test
12 EMI solution 0.3 31/37 Add C531,C532,C533,C534,C535

13 Solve HP bo issue 0.3 30 1. Add Q701,Q702,R727,R728

2. Add Q703,R729 to change EAPD phase
3. Connect EAPD# to R727,R728

14 Solve Speaker bo issue solution 0.3 30 1. Connect EAPD to EC pin 94

2. Change EC_Mute sequence to solve this issue

4 4

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-3111P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401408 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 46 of 47
A B C D E
 A B C D E

Version change list (P.I.R. List) Page 1 of 1

Item Fixed Issue Rev. PG# Modify List B.Ver# Phase

1 EMI brd band question 0.1 39 1.add PC185 1

1 45 2.add gate resistor;PR274,PR275

3.change value that PR220,PR239
4.ad snubber circuit that PR224,PC167,PR256,PC182

2 CPU Core question 0.1 45 1.add PR267,PR268,PR38

3 1.change value for PR83,PR84

Regulator +5VALWP/+3VALWP OCP design point 0.1 42

Battery and MOSFET protect function 0.1 41 1.addPR272,PR273,PQ39,PQ40,PQ41

4
39 2.addPR271

2 2

3 3

4 4

Compal Electronics, Inc.

Title
SCHEMATIC, M/B LA-3111P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
401408 B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: , 21, 2006 Sheet 47 of 47
A B C D E