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1.1 MOTIVATION
With overall communication of private and secret information over the machine
systems then again the Internet, there is dependably a plausibility of risk to
information privacy, information honesty and, likewise information accessibility.
Information encryption keeps up information secrecy, trustworthiness and validation.
Data has happened to the most imperative stakes in developing interest of need to
store significance of occasions in regular life. Messages need to be secured from
unapproved gathering. Encipherment is one of the security systems to secure data
from community. Encryption shrouds the first substance of a message in order to
make it mixed up to anybody, with the exception of the individual who has the
extraordinary information to peruse it.
In the past cryptography implies just encryption and decoding utilizing mystery keys,
these days it is characterized in diverse components like topsy-turvy-key
encipherment (public-key cryptography) and symmetric-key encipherment (called as
privet-key cryptography). The general population key calculation is intricate and has
high reckoning time. Private Key calculations include stand out key, both for
encryption and unscrambling while, open key calculations include two keys, one for
encryption and an alternate for decoding. There were numerous cryptographic
algorithms proposed, for example, Data Encryption Standard (DES), 2-DES, 3-DES,
the Advanced Encryption Standard, Elliptic Curve Cryptography, and different
calculations. Numerous examiners and programmers are continually attempting to
break these calculations utilizing beast constrain and side channel assaults. A few
strikes were effective as it was the situation for the Data Encryption Standard in
1993.
Design optimization is being done by using Finite State Machine. Data path and
control unit are designed for both cipher and decipher block, after that respective data
path and control unit are integrated using structural modeling style of Verilog.
Xilinx_ISE_14.2 software is being used for the purpose of simulating and optimizing
the synthesizable Verilog code.
This software allows us to take our design from design entry through Xilinx device
programming. The ISE project navigator processes our design through various steps
in the ISE design flow.
Design Entry
Synthesis
Implementation
Simulation and verification
Device Configuration
The Test-bench waveform containing the signals can be used to simulate the modules
used in our project in the Xilinx ISE simulator.
1.5 ORGANISATION
This thesis is organized as follows:
Chapter 3 describes the AES algorithm in details. The four encryption stages are
presented: Byte Substitution, Shift Rows, Mix Column and lastly Add Round Key and
inverse part of all four blocks. It also describes the details of Cipher and Decipher
block.
In Chapter6, Synthesis has done for Spartan-3 FPGA and Area and clocking results are
captured
There are numerous angles to security and numerous provisions, extending from safe
trade and installments to private correspondences and ensuring passwords. One vital
perspective for safe interchanges is that of cryptography, which the fundamental center
of this subject is. At the same time it is paramount to notice that when cryptography is
fundamental for safe interchanges, it is not independent from anyone else sufficient.
The onlooker is exhorted, then, that the themes secured in this part just portray the first
of numerous steps important for important security in any count of situations.
Cryptography then ensures information from theft or change, as well as be utilized for
client confirmation. There are, when all is said in done, three sorts of cryptographic
plans ordinarily used to achieve these objectives: mystery key (or symmetric)
cryptography, open-key (or unbalanced) cryptography, and hash works, each of which
is depicted beneath. In all instances, the introductory decoded information is alluded to
as plain-text. It is encoded into figure content, which will thus (ordinarily) be decoded
into utilizable plain-text.
2.3.3 HASHING
In hashing, an altered-length message condensation is made out of a variable-length
message. The condensation is typically much more modest than the message. To be
valuable, both the message and the review be sent to Ashu. Hashing is utilized to give
check values, which were examined prior in connection to give information
respectability.
There are many cryptographic algorithms using GF among them, the AES algorithm
uses the GF (28). The data byte can be characterized using a polynomial representation
of GF (28).
DES was the fruit of a research project performed by International Business Machines
(IBM) Corporation in the later parts of 1960s which give rise to a cipher called as
LUCIFER. In the earlier parts of 1970s it was decided to commercialize LUCIFER
and a quantity of significant
Modifications were added. IBM wasnt alone on this ship of modifications as they
asked technical help from the National Security Agency (NSA) (other outside experts
were aboard but it is probable that, from a technical point of view, the NSA was the
chief backer). The changed variety of LUCIFER was presented as a suggestion for the
novel national encryption standard demanded by the National Bureau of Standards
(NBS). It was lastly accepted in 1977 as the Data Encryption Standard (DES) (FIPS
PUB 46).
3.1 INTRODUCTION
The Advanced Encryption Standard is a determination for the purpose of encryption of
automated information built by the National Institute of Standards and Technology of
U.S. in 2001. AES is focused around the Rijndael figure created by Joan Daemen and
Vincent Rijmen (two Belgian cryptographers), who proposed a suggestion to NIST
throughout the AES determination process. Rijndael is a group of figures with
distinctive key and piece sizes. For AES, NIST chose three parts of the Rijndael family,
each with a piece size of 128 bits, yet three distinctive key lengths: 128, 192 and 256
bits. AES has been received by the U.S. government and is currently utilized around the
world. It succeeds the Data Encryption Standard (DES), which was distributed in 1977.
The algorithm depicted by AES is a symmetric-key calculation, importance the same
key is utilized for the purpose of encryption and decryption of the information.
3.2 HISTORY
The prior ciphers might be broken without hardly lifting a finger on advanced
processing frameworks. The DES calculation was softened up 1998 utilizing a
framework that cost about $250,000. It was additionally unreasonably moderate in
programming for it was made for middle-1970's equipment and doesnt process
effective programming code. Then again, Triple DES has three times the same number
of iterations as DES and is relatively sluggish. And also, the 64 bit square size of triple
DES besides DES isnt extremely effective also is faulty concerning security.
What was obliged was a fresh out of the box new encryption algorithm that might be
impervious to the majority of the identified attacks. NIST needed someone to assist the
making of another algorithm. Nonetheless, in view of the discussion that ran with the
DES standard, and the ages of a few limbs of the U.S. government having a go at all
that they could to upset sending of protected cryptography this was liable to increase
solid distrust. The issue remained was, NIST would really have liked to help make
another fantastic encryption standard yet they couldn't get included specifically.
Tragically they were truly the main ones with the specialized notoriety and assets to the
lead the exertion. As opposed to outlining or serving to outline a figure, what they did
The above matrix in fig 3.3 is the state matrix whos each element is of one byte
data.
We need to be interested with how this framework is influenced in every one iteration.
For this specific adjust every byte is linked into another 8 bits in the accompanying
way: the left-hand side 4 bits of the half word is utilized to determine a specific row of
the s-box and the right-hand side 4 bits tags a specific column. For instance, the 8 bits
{95} (wavy sections speak to hex values in FIPS PUB 197) chooses line nine segment
five that eventually comes out to hold the quantity {2a}, which is utilized to modify the
state matrix.
The very initial row (i.e. row 0th) of the state matrix isnt modified.
The 2nd row is left shifted by 1 byte in a round path.
The 3rd row is left shifted by 2 bytes in a round path.
The fourth row is left shifted by 3 bytes in a round path.
The Inverse Shift Rows conversion (called as Inv Shift Rows) performs these round
movements in the inverse heading for each of the last three columns (the first column
was unchanged in any situation). This process may not seem to do abundant yet in the
event that you contemplate how the bytes are requested inside state then it could be
Every component of the item framework is the entirety of results of components of one
line and one segment. For this situation the unique augmentations & multiplication are
achieved in GF (28). The Mix Columns change of a solitary segment j (0 _ j _ 3) of
state could be communicated as: Where x means multiplication over the finite field GF
(28).
The key is duplicated into the initial four expressions of the stretched key. The rest of
the stretched key is packed in 4 words at once. Each one included word w[i] hinge on
the promptly going before word, w[i 1], and the expression 4 places back w[ i 4]. In
3 out of 4 cases, upfront XOR is utilized. For a statement whose location in the w
exhibit is a numerous of four, a more random capacity is utilized.
RotWord just rotates the word data by a one-byte round left movement. This
implies that a data word [a0, a1, a2, a3] is changed into [a1, a2, a3, a0]
SubWord substitutes every bytes of the word using byte substitution method,
utilizing the S-box portrayed prior.
The consequence of above processes is bitwise XORed with round constant,
known as Rcon[j].
4.1 OVERVIEW
In this chapter, a hardware model for implementing the AES128 algorithm is
introduced. The model is implemented using the Verilog hardware description
language. This chapter covers the design and implementation issues of the AES128
algorithm. The hardware model developed in this chapter is synthesizable. This means
that the model provides a cycle-by-cycle RTL description of the circuit that a logic
synthesis tool can convert to an optimized gate-level netlist.
The modeling process utilized in this project is the bottom-up approach. This means
that the leaf components in the design hierarchy were developed first and the higher-
level modules were constructed by instantiating their subcomponents and connecting
them with the internal signals. All the modules in the design hierarchy were modeled in
behavioral style, but the root module consisted of data flow modeling as well to
implement the four major cipher transformations.
AES Engine FSM has following states. Each state processing as follows:-
4.2.1.2 PRE_RND
In this state, it generates a rnd_req signal to another FSM, which does the AES round
operations such as Substitution, Shift & Mix column and Add round key operations. It
transits to the MIDRND_INT state. In this state Rnd_cnt vector assigns to zero value.
It takes single clock signal to transits.
4.2.1.3 MID_RND_INIT
In this state, it waits for the rnd_cmpltd signal from the State Operations FSM. After
receiving rnd_cmpltd signal, it transits to the MID_RND_RUN state. It asserts rnd_req
signal along with Rnd_cnt vector to increment. It checks for the Rnd_cnt to less than 9
and if it reaches 9, state transits to the FINAL_RND state.
4.2.1.4 MID_RND_RUN
In this round, it waits for the rnd_cmpltd signal and when it received, state changes to
the MID_RND_INIT state.
4.2.1.5 FINAL_RND
In this round, it waits for the rnd_cmpltd signal and when it received, state changes to
the CIPHER_OU_VAL state.
4.2.1.6 CIPHER_OUT_VAL
In this state puts a ase encrypted data on aes_cipher_data out bus along with asserting
aes_cipher_out_val signal.
6.1 Overview
A primary objective of this project was to develop a synthesizable model for the
AES128 encryption algorithm. Synthesis is the process of converting the register
transfer level (RTL) representation of a design into an optimized gate-level netlist. This
is a major step in ASIC design flow that takes an RTL model closer to a low-level
hardware implementation.
Synthesis consists of three main steps. The first step is the Translation, which
involves converting the RTL description of a design into a non-optimized intermediate
representation that is used by the synthesis tool. The second step is the logic
optimization, which optimizes the internal representation by removing redundant logic
and performing Boolean logic optimizations. The third step is called technology
mapping & optimization which maps the internal representation to an optimized gate
level representation using the technology library cells based on design constraints.[3]
In this chapter, we describe how the Xilinx Ise tool was utilized to synthesize the
verified AES128 model, by using a script that was developed to perform the synthesis
based on certain constraints. The script generates several reports about the synthesis
outcome including timing and area estimates. Synthesis report is as shown in Fig 6.1.1.
8.1 APPENDIX-A
8.1.1.1 AES_engine.v
/*------------------------------------------------------------------------------------------
* Module_name : aes_engine.v
*--------------------------------------------------------------------------------------------
`timescale 1 ns/ 1 ps
//---------------------------------------------------------------------------------------------
// directives
module aes_engine (
);
//-----------------------------------------------------------
reg nxt_round_valid ;
reg round_valid ;
reg nxt_cipher_valid_out ;
reg aes_abort_latch ;
wire s_box_comp_done ;
reg aes_abort_done ;
reg round_completed ;
//-------------------------------------------------------------
if (!reset_n) begin
end
else begin
if (aes_abort_done) begin
end
else begin
end
end
end
//--------------------------------------------------------------
// STATE MACHINE
always @* begin
nxt_aes_state = aes_state ;
nxt_aes_eng_data = aes_eng_data ;
nxt_aes_eng_key = aes_eng_key ;
nxt_round_valid = 'd0 ;
nxt_round_cnt = round_cnt ;
aes_abort_done = 'd0 ;
nxt_cipher_valid_out = 'd0 ;
nxt_cipher_data_op = cipher_data_op ;
case (aes_state)
ENG_IDLE: begin
if (aes_abort) begin
nxt_aes_state = ENG_IDLE ;
nxt_aes_eng_key = 'd0 ;
nxt_aes_state = 'd0 ;
nxt_round_cnt = 'd0 ;
end
nxt_aes_eng_data = aes_core_data ;
nxt_aes_eng_key = aes_core_key ;
nxt_round_cnt = 'd0 ;
nxt_aes_state = AES_INIT ;
end
end
AES_INIT: begin
nxt_aes_state = ABORT ;
end
else begin
nxt_round_valid = 1'b1 ;
nxt_aes_state = ENG_PREL_ROUND ;
end
end
ENG_PREL_ROUND: begin
nxt_aes_state = ABORT;
end
nxt_aes_state = MID_ROUND_INIT ;
nxt_aes_eng_data = nxt_updated_plain_data ;
end
end
MID_ROUND_INIT: begin
nxt_aes_state = ABORT ;
end
else begin
nxt_round_valid = 1'b1 ;
nxt_aes_state = MID_ROUND_RUN ;
end
end
MID_ROUND_RUN: begin
nxt_aes_state = ABORT;
end
nxt_aes_state = ENG_FINAL_ROUND ;
nxt_aes_eng_data = nxt_updated_plain_data ;
nxt_round_valid = 1'b1 ;
nxt_round_cnt = 'd10 ;
end
nxt_aes_state = MID_ROUND_INIT ;
nxt_aes_eng_data = nxt_updated_plain_data ;
end
end
ENG_FINAL_ROUND: begin
end
nxt_aes_state = CIPHER_OUT_VAL ;
nxt_cipher_valid_out = 1'b1 ;
nxt_cipher_data_op = nxt_updated_plain_data ;
end
end
CIPHER_OUT_VAL: begin
nxt_aes_state = ENG_IDLE ;
nxt_round_cnt = 'd0 ;
end
ABORT : begin
aes_abort_done = 1'b1 ;
nxt_aes_state = ENG_IDLE;
end
endcase
end
//-----------------------------------------------------------------------------
if (!reset_n) begin
end
else begin
end
end
end
//--------------------------------------------------------------------
// ROUND MANIPULATER
// --------------------------------------------------------------------
if (!reset_n) begin
end
else begin
end
end
// STATE MACHINE
always @* begin
nxt_round_map_state = round_map_state ;
key_req = 1'b0;
round_completed = 1'b0;
s_box_req_0 = 1'b0;
s_box_req_1 = 1'b0;
s_box_req_2 = 1'b0;
s_box_req_3 = 1'b0;
s_box_req_4 = 1'b0;
s_box_req_5 = 1'b0;
s_box_req_6 = 1'b0;
s_box_req_7 = 1'b0;
s_box_req_8 = 1'b0;
s_box_req_9 = 1'b0;
s_box_req_10 = 1'b0;
s_box_req_11 = 1'b0;
s_box_req_12 = 1'b0;
s_box_req_13 = 1'b0;
s_box_req_14 = 1'b0;
s_box_req_15 = 1'b0;
s_box_in_0 = 'h0 ;
s_box_in_2 = 'h0 ;
s_box_in_3 = 'h0 ;
s_box_in_4 = 'h0 ;
s_box_in_5 = 'h0 ;
s_box_in_6 = 'h0 ;
s_box_in_7 = 'h0 ;
s_box_in_8 = 'h0 ;
s_box_in_9 = 'h0 ;
s_box_in_10 = 'h0 ;
s_box_in_11 = 'h0 ;
s_box_in_12 = 'h0 ;
s_box_in_13 = 'h0 ;
s_box_in_14 = 'h0 ;
s_box_in_15 = 'h0 ;
nxt_int_round_data = int_round_data;
nxt_key_input_data = key_input_data;
case (round_map_state)
ROUND_IDLE: begin
nxt_round_map_state = PRE_ROUND ;
end
nxt_round_map_state = S_BOX_SUBST;
s_box_req_0 = 1'b1;
s_box_in_0 = aes_eng_data[127:120];
s_box_in_1 = aes_eng_data[119:112];
s_box_req_2 = 1'b1;
s_box_in_2 = aes_eng_data[111:104];
s_box_req_3 = 1'b1;
s_box_in_3 = aes_eng_data[103:96];
s_box_req_4 = 1'b1;
s_box_in_4 = aes_eng_data[95:88];
s_box_req_5 = 1'b1;
s_box_in_5 = aes_eng_data[87:80];
s_box_req_6 = 1'b1;
s_box_in_6 = aes_eng_data[79:72];
s_box_req_7 = 1'b1;
s_box_in_7 = aes_eng_data[71:64];
s_box_req_8 = 1'b1;
s_box_in_8 = aes_eng_data[63:56];
s_box_req_9 = 1'b1;
s_box_in_9 = aes_eng_data[55:48];
s_box_req_10 = 1'b1;
s_box_in_10 = aes_eng_data[47:40];
s_box_req_11 = 1'b1;
s_box_in_11 = aes_eng_data[39:32];
s_box_req_12 = 1'b1;
s_box_in_12 = aes_eng_data[31:24];
s_box_req_13 = 1'b1;
s_box_in_13 = aes_eng_data[23:16];
s_box_req_14 = 1'b1;
s_box_req_15 = 1'b1;
end
end
PRE_ROUND: begin
nxt_round_map_state = ADD_ROUND_KEY ;
nxt_key_input_data = aes_eng_data ;
key_req = 1'b1;
end
S_BOX_SUBST: begin
if (s_box_comp_done) begin
nxt_round_map_state = SHIFT_AND_MIX_COL;
end
end
SHIFT_AND_MIX_COL: begin
nxt_round_map_state = ADD_ROUND_KEY ;
key_req = 1'b1;
end
ADD_ROUND_KEY: begin
if (key_ack) begin
round_completed = 1'b1;
nxt_round_map_state = ROUND_IDLE ;
end
end
end
//----------------------------------------------------------------------------
always @* begin
nxt_updated_plain_data = key_input_data;
if (key_ack) begin
nxt_updated_plain_data [47 :40 ] = key_input_data [47 :40 ] ^ key_data [47 :40 ] ; // A10 +
K10
nxt_updated_plain_data [39 :32 ] = key_input_data [39 :32 ] ^ key_data [39 :32 ] ; // A11 +
K11
nxt_updated_plain_data [23 :16 ] = key_input_data [23 :16 ] ^ key_data [23 :16 ] ; // A13 +
K13
end
end
//-----------------------------------------------------------------------------
// ROW_0 = NO SHIFT
//
//
always @* begin
//colomn_0
//column_1
//column_2
//column_3
end
//-------------------------------------------------------------
// MIX COLUMN
// +-----+-----+------+------+
// +-----+-----+------+------+
// +-----+-----+------+------+
// +-----+-----+------+------+
// +-----+-----+------+------+
//
always @* begin
// column-0
column_data [127:120] =
column_data [119:112] =
column_data [111:104] =
column_data [103:96] =
// column-1
column_data [95:88] =
column_data [87:80] =
column_data [79:72] =
column_data [71:64] =
// column-2
column_data [63:56] =
// column-3
(shifted_data [7 :0 ] ) ; // mul by 1
(shifted_data [7 : 0] ) ; // mul by 1
column_data [7 :0] =
end
//-----------------------------------------------------------------------------------------
// MULTIPLYING by 2 and 3
//-----------------------------------------------------------------------------------------
// MULTIPLY BY 2
assign shift_data_by2 [95 :88 ] = (shifted_data [95 ] == 1'b1 ) ? ((shifted_data [95 :88 ] << 1) ^
8'h1B) : (shifted_data[95 :88 ] << 1) ;
assign shift_data_by2 [87 :80 ] = (shifted_data [87 ] == 1'b1 ) ? ((shifted_data [87 :80 ] << 1) ^
8'h1B) : (shifted_data[87 :80 ] << 1) ;
assign shift_data_by2 [79 :72 ] = (shifted_data [79 ] == 1'b1 ) ? ((shifted_data [79 :72 ] << 1) ^
8'h1B) : (shifted_data[79 :72 ] << 1) ;
assign shift_data_by2 [71 :64 ] = (shifted_data [71 ] == 1'b1 ) ? ((shifted_data [71 :64 ] << 1) ^
8'h1B) : (shifted_data[71 :64 ] << 1) ;
assign shift_data_by2 [63 :56 ] = (shifted_data [63 ] == 1'b1 ) ? ((shifted_data [63 :56 ] << 1) ^
8'h1B) : (shifted_data[63 :56 ] << 1) ;
assign shift_data_by2 [55 :48 ] = (shifted_data [55 ] == 1'b1 ) ? ((shifted_data [55 :48 ] << 1) ^
8'h1B) : (shifted_data[55 :48 ] << 1) ;
assign shift_data_by2 [47 :40 ] = (shifted_data [47 ] == 1'b1 ) ? ((shifted_data [47 :40 ] << 1) ^
8'h1B) : (shifted_data[47 :40 ] << 1) ;
assign shift_data_by2 [39 :32 ] = (shifted_data [39 ] == 1'b1 ) ? ((shifted_data [39 :32 ] << 1) ^
8'h1B) : (shifted_data[39 :32 ] << 1) ;
assign shift_data_by2 [31 :24 ] = (shifted_data [31 ] == 1'b1 ) ? ((shifted_data [31 :24 ] << 1) ^
8'h1B) : (shifted_data[31 :24 ] << 1) ;
// MULTIPLY BY 3
assign shift_data_by3 [95 :88 ] = shift_data_by2 [95 :88 ] ^ shifted_data [95 :88 ];
assign shift_data_by3 [87 :80 ] = shift_data_by2 [87 :80 ] ^ shifted_data [87 :80 ];
assign shift_data_by3 [79 :72 ] = shift_data_by2 [79 :72 ] ^ shifted_data [79 :72 ];
assign shift_data_by3 [71 :64 ] = shift_data_by2 [71 :64 ] ^ shifted_data [71 :64 ];
assign shift_data_by3 [63 :56 ] = shift_data_by2 [63 :56 ] ^ shifted_data [63 :56 ];
assign shift_data_by3 [55 :48 ] = shift_data_by2 [55 :48 ] ^ shifted_data [55 :48 ];
assign shift_data_by3 [47 :40 ] = shift_data_by2 [47 :40 ] ^ shifted_data [47 :40 ];
assign shift_data_by3 [39 :32 ] = shift_data_by2 [39 :32 ] ^ shifted_data [39 :32 ];
assign shift_data_by3 [31 :24 ] = shift_data_by2 [31 :24 ] ^ shifted_data [31 :24 ];
assign shift_data_by3 [23 :16 ] = shift_data_by2 [23 :16 ] ^ shifted_data [23 :16 ];
endmodule