UNIT 1

DIGITAL SYSTEM DESIGN

AUTOMATION
TOPICS

Abstraction Levels

System Level Design Flow

RTL Design Flow

VHDL

VHDL Initiation

Existing Languages

VHDL Requirements
ABSTRACTION
LEVELS
ABSTRACTION LEVELS
Level Components Representation
Behavioral Algorithms, FSMs Algorithmic representation
of system functions
System Processors, memories, Interconnection of major
(architectural) functional subsystems functional units
Register Transfer Registers, adders, Data movement and
(dataflow) comparators, ALUs, transformation and required
counters, controllers, sequential control
bus
Gate (logic level) Gates, flip-flops Implementation of register
level components using
gates and flip-flops
Transistor Transistors, resistors, Implementation of gats and
capacitors flip-flops using transistors,
capacitors, and resistors
HARDWARE/SOFTWARE DESIGN FLOW
DESIGN METHODOLOGY

Uses VHDL to describe the system being designed and
the testbench used to verify the design

Uses a software simulator tool to simulate the design to
verify its functionality and timing

Uses a software synthesis tool to create the logic
described

Uses a software place-and-route tool to map the
synthesized logic to the target PLD and to generate a
timing model and a configuration file

Uses a PLD to physically implement the design

Uses the information in configuration file to program
the PLD
RTL DESIGN FLOW
SIMULATION
COMPILATION AND SYNTHESIS
COMPILATION AND SYNTHESIS

Analysis

Analyze the design and create a uniform format for
all parts of the design

Checks the syntax and semantics of the input VHDL
code

Generic Hardware Generation

Generates a set of Boolean expressions or a netlist of
basic gates
COMPILATION AND SYNTHESIS

Logic Optimization

Responsible for reducing expressions with constant
input, removing redundant logic expressions, two
level minimization, and multi-level minimization
that includes logic sharing

Output is in form of Boolean expressions, tabular
logic representations, or primitive gate netlists

Binding

Decides exactly what logic elements and cells are
needed based on the target hardware

Routing and Placement

Decides on the placement of cells of the target
hardware
VHDL INITIATION

Early 70’s: Initial Discussions

Late ‘70s: Definition of requirements

Summer 1981:

USDoD sponsored a workshop on HDLs at Woods
Hole, Massachusetts.

It was arranged by USIDA.

1983:

USDoD established requirements for a standard
VHSIC Hardware Description Language (VHDL),
based on the recommendations of the “Woods Hole”
workshop.

Contract of development was awarded to IBM,
Intermetrics, and Texas Instruments.

Under the restrictions of USITAR
VHDL INITIATION

Early ’84

VHDL 2.0 that allows concurrent statements only
was released

December 1984:

VHDL 6.0 was released

Mid ’85:

USITAR restrictions were lifted from VHDL and its
related software

VHDL 7.2 LRM copyright was transferred to IEEE
for further development and standardization.

May 1987:

IEEE 1076 / A VHDL LRM was released.
VHDL INITIATION

Late ‘87:

Version B of the LRM was developed and approved by
REVCOM (a committee of the IEEE Standards
Board).

December 1987:

VHDL 1076-1987 formally became the IEEE
standard HDL.

Mid ’88:

Increasing support by CAE manufacturers

1990:

Efforts for defining the new version of VHDL was
started by a team of volunteers working under the
IEEE DASC (Design Automation Standards
Committee).
VHDL INITIATION

Late ’91:

Revision---add extensions to lang.reference

October 1992:

A new VHDL referred to as VHDL ’93 was completed
and released for review. After minor modifications,
this new version was approved by the VHDL
balloting group members and became the new VHDL
language standard.

Mid ’94:

Standardization work for the present VHDL
standard (formally referred to as VHDL 1076-1993)
was completed.

1999:

VHDL-AMS (Analog- and Mixed-Signal) extension
EXISTING LANGUAGES

AHPL

CDL

CONLAN

IDL

ISPS

TEGAS

TI-HDL

ZEUS
EXISTING LANGUAGES

AHPL (A Hardware Programming Language)

Developed at the University of Arizona.

Tool for teaching computer organization.

An HDL for describing hardware at the dataflow
level of abstraction.

Uses an implicit clock for synchronizing assignments
of data.

Does not provide support for describing asynchronous
circuits.

The language descriptions consist of interacting
concurrent modules.

Hierarchy of modules is not supported.
EXISTING LANGUAGES

AHPL (A Hardware Programming Language)

Fix data types (restricted to bits, vectors of bits, and
arrays of bits).

Procedures or functions are only allowed in the
context of combinational logic units.

Delay and constraints are not allowed.

Assignment of values to busses and registers all
occur at the same time without delay, since they are
synchronized with an implicit clock.
EXISTING LANGUAGES

CDL (Computer Design Language)

Developed for instruction in digital systems.

A dataflow language.

Does not support design hierarchy.

Microstatements are used to transfer data into
registers.

Conditional microstatements use if-then-else
constructs and can be nested.
EXISTING LANGUAGES

CONLAN (Consensus Language)

Created in an attempt to establish a standard HDL.

Consists of a family of languages for describing
hardware at various levels of abstraction.

All operations are executed concurrently.

It allows hierarchical description of hardware but has
limited external use.
EXISTING LANGUAGES

IDL (Interactive Design Language)

Used only by IBM.

Originally designed for automatic generation of PLA
structures, but it was later extended to cover more
general circuit descriptions.

Designs in hierarchy of structures.

This language is primarily a concurrent HDL.
EXISTING LANGUAGES

ISPS (Instruction Set Processor Specification)

Developed at Carnegie Mellon University.

Based on ISP notation.

Designed for hardware simulation, design
automation, and automatic generation of machine-
relative software (compiler-compilers)

Used to describe the Mancester University Mark-1
computer

A very high-level behavioral language

Timing control is limited.
EXISTING LANGUAGES

TEGAS (Test Generation and Simulation)

A system for test generation and simulation.

It is only structural.

Digital hardware can be described hierarchically.

Detailed timing specification can be specified.
EXISTING LANGUAGES

TI-HDL (Texas Instruments HDL)

A multilevel language for the design and description
of hardware.

Allows hierarchical specification of hardware

Supports description of synchronous, asynchronous,
and combinational logic circuits.

Behavioral descriptions are sequential and
softwarelike, and they use if-then-else, case, for, and
while constructs for program flow control.

Has fixed data types with no provision for adding
user-defined types.
EXISTING LANGUAGES

ZEUS

A non-procedural language

It supports design hierarchy and allows definition of
systems by their functionality or their structural
arrangements.

Timing is at the clock level, and there are no
provisions for gate delay specification or detailed
timing constraints.

Provides a close link to physical layout.
VHDL REQUIREMENTS

General features

Support for design hierarchy

Library support

Sequential statement

Generic design

Type declaration and usage

Use of subprograms

Timing control

Structural specification
SOURCE

VHDL Modular Design and Synthesis of Cores
and Systems, Zainalabedin Navabi, Mc-Graw-
Hill Companies, 2007