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    Instrucciones Z80

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    Instrucciones Z80

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
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    11 views16 pages

    Sgs 8400

    Uploaded by

    Jonathan Rangel
    Instrucciones Z80

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
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    of 16
    Z80 CPU Central Process Unit f= The instruction sel contains 158 inetructions. The 78 instructions of the BOBDA are included as a subsot; 8080A and 280" goltware compatibility Is maintained. = GMHz, 6MHz, AMHz and 2.5 MHz clocks for the 280H, 780B, 2308 and 230 CPU resull in rapid instruction execution with, consequent high data throughput. = The extensive instruction sol includes string, bit, byle, and word operations, Block ‘searches and block transiers together with indexed and relative feddressing result in the most powerlul dala handling capabilities in the microcomputer industry. = The 280 microprocessors and associated family of peripheral controllers are linked by a vectored interrupt system. This oe “78400 tem may be daisy-chained to allow finplementation of @ priority interrupt schome. Little, it any, additional logic is required lor daisy-chaining. Duplicate sets of both general-purpose ‘and flag registers are provided, easing the desicn and operation of system sullware Through single contoxt sialehing, background-loreground programming, ‘and single-level interrupt processing. In ‘addition, two 16-bit index registers facilitate program processing of tables and arrays: ‘There are three modes of high speed Interrupt processing: 8080 similar, non- 20 peripheral device, and 280 Family peripheral with or without daisy chain, ‘On-chip dynamic memory refresh counter, LTA | HALL | Figure 1. Logie Functions meme BREED AS ipuwo | oes? General Description ‘The 280, 280A, 2808 and 280H CPUs are third-generation single-chip microprocessors with exceptional computetional power. They 3c higher systom throughput and more efficient memory utiliztion than comparable second-and third-generation microprocessors. The internal registers contain 208 bits of read/write memory that are accessible to the programmer. These registers include two sets of six general- [purpose registers which may be used Individually as either Bit registers or as 16-bit register pairs. In addition, there are two sets of accumulator and flag registers. A group of "Exchange" instructions makes either set of main or allerate resisters, accessible to the programmer. The alternate set eilows operation in ioreground. ? pe Figure 2 Pin Configuration background mode or it may be reserved for very fast interrupt response The 280 also contains a Stack Pointer, Program Counter, two index registers, & Refresh register (Counter), and an Inteztupt register The CPU is easy to incorporate into e aystem since it requires only a single +8 V power source. All output signals ave fully decoded ‘and timed to control standard memory oF peripheral circuits, and itis supported by an extensive family of peripheral controllers. The internal block diagram (Figure 3) shows the primary functions of the 280 processors. Subsequent text provides more detatl on the 780 VO contcoller family, registers, = instruction set, interrupts and daisy caaining, ‘and CPU timing. Figure 2s. Chip Carer Pin Configuration General Description (Continued) beara KI sn am ere a = oP LE ett aoe Figure 9. CPU Block Diagram 80 Microprocessor Family ‘The 280, 280A, 200B end 280H ricroprocestor Is the central element of comprehensive microprocessor product family. This family works together in most plications with minimum requirements for ‘edditional logic, facilitating the design of efficent and cost-effective microcomputer bose systems, Five components to provide extensive support for the 280 microprocessor. These 1 The CTC (Couter/Timer Circult) features four programmable 8-bit counter/timers, ‘each of which has an 8-bit prescaler. Each of the four channels may be configurated to operate in either coun or timer mode. 1 The PIO (Parallel InpuvOutput) operates in both data-byte V/O transfer mode (with handshaking) and in bit mode (without handshaking). The PIO may be sonfigured to interlace with standard parallel periperal devices such as printers, tape punches, and keyboards the DMA (Direct Memory Access) provides dual port data transfer sperations and the ability to teminate data transfer as a result of a pattern match, ‘= The SIO (Serial Input/Output) controller offers two channele. It i capable of perating in a variety of programmable medes for both synchronous and agynchronous communication, including Bi-Synch and SDLC. = The DART (Dual Asynchronous Receiver/Transmitter) device provides low cost asynchronous serial communication. thas two channels and a full modem control interface, ee NAN he vam! | EE || ZB400, | Hat lik ti 780 CPU Registers Figure 4 shows three groups of registers within the Z80 CPU. The firet group consists of duplicate sets of B-bit registers: @ principal set and an alternate set (designated by’ Iprimel, e.g., A’). Both sets consist of the Accumulator Regier, the Flag Register, ‘and six general-purpose registers. Transler of data between these duplicate sets of registers is accomplished by use of “Exchange” instructiors. The result is faster response to interrupts and easy, efficient implementation of such versatile programming techniques as background: foreground data processing. The second set of registers consists of six registers with assigned functions. These are the I (Interrupt Register), the R (Refresh Register), the IX end IY (Index Registers), the SP (Stack Pointer), and the PC (Program Counter) ‘The third group consists of two interrupt status flip-flops, plus and additional pair of flip-flops which assits in Identifying the interrupt mode at any particular time. Table 1 provides further information on these registers. Fig. 4. CPU Regist CPU Registers (Continued) Teal Slee Gia Temata ‘Accumulator (@ Shares an opaansor the raul of an apeaton Flag 8 See eatrection Se General Purpose 8 Can be used separaily ar asa 16 roger with C General Purpose 8 See B, show, General Purpose 8 Can bo used separ or a @ 6. reise with E. Genecal Purpose 8 See, shove Gonsral Purpose 8 Cam bo used separaay or ap LE nagar wh Gonoral Purpose 8 SeeH, abow. Note:The (8.0), DB, and (H.L) seis are combina as flows: B-High byte Clow bye Dokigh bye E—Low bro HOHign byte LEow te 1 Inert Reiter 8 Screrupper eights memary adv or vectored tcrt pros p Felrch Reger 8 ——_rovides uerugarer dysnie memory eefreh, Lower seven bt are futomaticly nemecnted sou al sok ae ploud om the ars bus ‘Eitna each insecon itch cyele raze me « Index Resiter 16 se fe indenod adres. ty Tedex Fegiter 18 Same a8 1, abowr ‘Stack Pointer 16 Hold adden fhe top of sho stack. Sov Push or Pop i nt Program Counter 1 Hold are of as instruction, IF, Inerrpt Enable FipFlape Seto roa to india ierupt satus (see Figure Inde oterrust Mode ‘o-Flogs Relat Interrupt node ees Figure ‘Table 1. CPU Registers Hh, ey L Sai i } neg SS Interrupts: General Operation The CPU accepis two interrupt input signals: NMI and INT. The NM is ¢ non maskable interrupt and has the highest Prionty. INT is @ lower priority int:cupt {and it requires thet inferrupts be enabled in Software in order to operat. INT can be connected to multiple peripheral devices in @ ‘ited OR configuration, ‘The 780 has @ single response modo for interrupt service for the non.mesiable interrupt. The maskable interrupt, INT, has three progremmable response modes aveilabe. These aro 1 Modis 0 — similar with the 6080 microprocessor © Mode 1 — Peripheral Interrupt servico, for use with non-6080/280 ayers. 1 Mode 2— a vectored interrupt scheme, usvelly daisy chained, for use with 220 Family and compatible peripheral devices. Tho CPU services inerrapts by sampling the NMI and INT signals ot the sing edge Othe last clock of an trucrion. Further interrupt service procewsing depends upon the type of inerrape that wee ceteciea Details on sntersupt responses ere shown in the CPU Timing Section. Non-Maskable Interrupt (NFA). The nor: maskable interrupt cannot be disabled by rogram control and therefore will be accepted at all times by the CPU. NMI is usually reserved for servicing only the highest priority type inlezrupte, such as that for orderly shut-down after power failure has been detected, ter recognition of the NMI signal (providing BUSREO is act active), the CPU jumps to restart location 0066H. Normelly, software starting at this address contains the Interrupt service routin Maskable Interrupt (INT). Regardless of the interrupt mode set by the user, the 220 response to a maskable interrupt input follows @ common timing cycle. After the Interrupt has been detected by the CPU (provided that interrupts are enabled and BUSREO is not active) « special interrupt processing cycle begins, This is « special fetch (MI) cycle in which IORQ becomes _ active rather than MREO, as in. normal MT ceyele. In addition, this special MI oycle is automatically extended by two WAT? sttes, to allow for the time required to acknowledge the interrupt request ‘Mode 0 Interrupt Operation. This mode is similar to the 8080 microprocessor interrupt service procedures. The interrupting device places an instruction on the data bus. This is normally a Restart Instruction, which will initiate @ call to the selected one of ei! restart locations in page zero of memory. Unlike the 8060, the 280 CPU responds to the Call instruction with only one interrupt acknowledge cycle followed by two Temory read cycles. Mode | Interrupt Operation. Mode 1 __ operation is very similar to that for the NM ‘The principal difference is that the Mode 1 Interrupt has a restart location of 0038H only. Mode 2 Interrupt Operation. This interrupt ode has been designed to utilize most effectively the capabilities of the 80 microprocessor and its associated peripheral family. The interrupting peripheral device selects the starting address of the interrupt service routine. It does this by placing an B-bit vector on the data bus during the interrupt acknowledge cycle. The CPU forms a pointer using this byte as the lower 8-bits and the contents of the I register as the upper 8-bits. This points to an entry ina table of addresses for interrupt service routines. The CPU then jumps to the routine at that eddress. This flexibility in selecting the interrupt service routine address allows the periphral device to use several different types of service routines. These routines may be located at any available location ia memory. Since the interrupting device supplies the low-order byte of the 2-byte vector, bit 0 (Aa) must be a zero. Interrupt Priority (Daisy Chaining and Nested Interrupts). Tho interrupt pricrity of each peripheral device Is determined by its physical location within a daisy-chain Interrupts: General Operation (Continued) configuration. Each device in the chain has Srinterrapt enable input line (IE) and an Shlerupt enable output line (IEO), which ta {ed io the next lower prionty device. The ita doves in the daisy chain as ts TEL input hardwired toa High level. The frst Gevice hes highes! pricaty, while each Suoceding device has a corresponding lower Peony. This arrengement permits the CPU B select the highest print interrup! from Several simultaneously interrupting ripheral. the interrupting device disables tt IEO linet the noxt lower priority periphecal unt it as been serviced. After servicing, ts {EO tine is talsed, allowing lower priory peripherals to demand interrupt servicing ‘The 260 CBU wil nest (queue) any pending interupla of intrrupte received While selected peripheral is being Interrupt Enable/Disable Operation. Two flip-flops, IFF, and IFF;, referred to in the register description are used to signal the CPU interrupt status. Operation of the two flip-flops Is described in Table 2. For more deta, refer to the 280 CPU Technical Mansel. Di intructon ° FB ieesuetion 1 WDALininuction © + TFF,~Pasty fag ID ALRimairucton + + BF;~Pasty fag Aeon TV oF, =F) (onesie eserupt INfaiesbie ReTNiprraction REIFF at =e ‘oman of an RAT ‘Table 2, State of Flip-Flops WF | A Instruction Sot 8-Bit Load Group The 280 microprocessor has one of the © 16-bit arithmetic operations most powerful and versatile Instruction sets available in any 8:bit microprocessor. It ees ere ane includes such unique operations as a block Bit set, reset, and tost operations a move for fast, efficient deta transiors withing um t = memory or between memory and I/O. It also if : me allows operations on ary bitin any location Calls, returns, and restarts 7 x aS igen © Input and output a : a: The following is a summary of the 280 Input and output operations : gt Instruction sot and shows the assembly A variety of addressing modes are ee 2 language mnemonic, the operation, the flag implemented to permit efficient and fast data ae be slats, and gives comments on each transfer between various registers, memory Baa. Bat. ft E instruction. The 280 CBU Technical Manual locations, and inpuoutput devices. These and 280 CPU Programming Manuel contain addressing modes include: wor mane significantly more deals fer programming Immediate . os © Immediate extended : Meas Gees eae cess atime «8 ow © Modified page zero rea The instructions are divided into the Shee at iene ee lative wares cans seers es Wipe «oso © BLbit loads arma a © it oad a - eaea te © Exchanges, block transfers, and searches © Resister eta © Bbit arithmetic and logic operations Ll a dle PELIT wee a GF © Generel-purpose arithmetic and CPU a meee ‘ ee control 0 Be oxmres Wing 238 KAY | 16-Bit Load Group | Eechange, Block Transfer. Block Search Groups { oo — fees | . a co | fee ee eee Ane a | ioe geme 2 +H tape cee ee i foee ene WH Mme ee ee ee ND ee Dw ummm 2 4 & / ' 1 100 OE AY i og oot ee : pve Goneral-Purpose Arithmetic and CPU Control Groups ee ee wwe Anker pee eves wor a Sale rans : soba i0 mt o-o oe sou toe a eda Cy "ea, mt ugg] pf sume aa Urals snows Seca imap 2 2 8 meh Mbeas Sates oy ee oa a _ ot 00 to toxoxrrco Pam sre MB 2 a8 ese emma rd : ge 162it Arithmetic Group ves ae ny aa fhe momemc Fexaxves go: «oe ae nome. nF im none teense: GBM a 6 8 gan Bit Set. Reset and Test Group nicex-a) tani opie o rete teat Be erm ciation dct Ge Jump Grup (Continued) Input and Output Grup [ " Orhan, Te at tet sree ors, feat tea eat — Srecies 8 tv Cetera Srey Crd Set Commas rene Shee 8 atone Spee Creme seme Comme ws, 2B Nemdamiene Naw eked eee nm 22 on awdon ky poo rene oneness name a a8 | . oc NOTES ype ne semen nb lan sre oe 7 Sarees Tina 20 rPaxeeix ome a gett ENE Smet . uaeR soit son pikxee sk nome a 2 cwto= kr Shae + 2 SBA, Call and Return Group coum. Sees nomen 2 pew chim ee ge a oso” ieee eee ae een Sa ee om Bs! na axxeae yeep 2 » geen wR, Trt rts mmm 1 oe | reaxxea x nm 2 6m oetem Rete Wewrdeon See ces ccc. 1 oma Bene Ais = ee 9 Mime! 2 3 a a , RP GREP Fahy { 28400 z PLEGEGS . Rimmiprmanmemmtvs Srabat — Srmbat Operon Sm se tag $= Lu eNaB a te ent, Theta ncn ring the rent oo F Eto. 82 teen ote operon corn by Hetp evo tog Pony Pastor” + Ten hag snared bythe operon Fi rte rmetecctsiex 9 —etagurvan'r wept Sh lg wih pty of boa wn i fog wetby he opto. eee es fas cant «X Tee hay "coteae™ SRESPECN Wo cuban, fv = YP agai nadia toh veer Taw tenitlespaton ween, B= 0k She operon MautwSis i Biielccrion Fv Ti Be fag tesedexodra w he partrt 5 ‘the result of the operation produced an overtlow, the operation. es aan eacicrabore”” —¢— AnyotelinoCPU regis, B.C, D. EH, Hateary ag Rinse toes tom Aneta brat atari mode Fererepens Shred lore part ecto x RSEENSRTS ue prow ope: Ao fn baton rat areing maces Fesconetttot Sed ra nto nan Whe hep nconuncionwihihe 4 ngene te twotndar inert. Stl ade namcton DRA oproperivcor RK Reeah cou. athe roulimoycedBeD ir lowing 8 inrange < 0,25 > [Eicesessacon mm oprnde hn irtange e055 > pe 80 ros cc Eimtnc tag. C= Lato conten zcdaced 1 cary tre the MSB of the operand o result Pin Descriptions -Ays. Address Bus (output, active High, eR) AG Ag form a 16-bi address bus. {The Address Bus provides the address for pemory data bus exchanges (up to 64K (=) aod for VO device exchanges. BUSKGR. Bus Acknowledge (output, active vw). Bus Acknowledge indicates to'the Squesting device that the CPU address bus, ‘dala bus, and control signels MREO, IORQ, #5, and WA have entered their high impedance states. The external circuitry can row control these lines. BUSREQ. Bus Request (input, active Low) Bus Request has a higher priority than NMI jis always recogaized at the end of the front machine cycle. BUSREO forces the COU address bus, data bus, and control Signsls MREO, TORO, RO, and WR to go to STigh-impedance sale go thet other devices Gen control these lines. BUSREO is normally wite-ORed and requires an external pullup {or these applications. Extended BUSREQ periods due to extensive DMA operations can provent the CPU from properly refreshing Eynamic RAMS. DyDy. Dato Bus (inputvoutput, active High, 2ale). Dey constitute an B-bit direciionel data bus, used tor data ‘changes with memory and 1/0. HALT. Hott Stole (output, active Low). HALT tndlcetes that the CPU has executed a Halt {nslcuction and is awaiting either a non- mashable or @ maskable interrupt (with the Trask enabled) belore operation can resume ‘While halted, the CPU executes NOPs to raintain memory relresh, INT. Interrupt Request (input, ective Low). Interrupt Request Is generated by UO devices, The CPU honors a recuest at the tnd ef the current instruction ifthe internal Scltware-controlled interrupt ensble flip-flop GFF) is enabled. INT is normally wire-ORed tnd requires an external pullup for these ‘applications. (ORG, Inpui/Qutout Request (output, active Low, 3-state). IORQ indicates that the lower half of the address bus holds a velid /O address fer an /O road or write operation, TORO is also generated concurrently with MT uring an interrupt acknowledge cycle to indicate that an interrupt response vector ‘can be placed on the data bus. MI. Mochine Cycle One (cutput, active Low). MI, together with MREO, indicates that the current machine oycle is the opcode fs Gyele of an instruction execution. Ml, fecether with TORQ, indicates an interrupt scinowledge cycle FREQ, Memory Request (output, active Low, State). MRE indicates that the adiiress bus holds a valid address for a remory read or memory write operation, NMI. Non-Maskable Interrupt (input ‘negative edge-triggered). NMI has ¢ higher prority than INT. NMI is always recognized ithe end of the current instruction, Independent of the status of the interrupt Grable flip-flop, and automatically forces the CPU to restart at location O066H BD. Read (output, active Low, 3state). RD indicates thatthe CPU wants to rerd data from memory or en U/O device. Tio addressed VO device or memory should us sigal to gate data ono the CPU eta RESET. Reset (input, active Low). RESET Intializes the CPU a follows: it resets the inerrupt enable flip-flop, cleers the PC and Registers band Ry and sete the interrupt talus to Mode 0. During reset timo, the address and data bus go to high {impedance state, and all control output signals go to the inactive state. Note that RESET must be active for a rrinimum of three fall clock cycles before the qesot operation is complete. HESH. Feiresh (output, ective Low). RFSH, together with MREO, indicates that the lower seven bits ofthe syatem’s address bus can be tsed as a rfresh address to the system's gynemic memories. WAIT. Wait (input, active Low). WATT irdicetes to the CPU that the addressed nemory of UO devices are not ready for a Gata warster. The CPU continues fo enter a Wit sate es long as this signal is active. Extended WATT periods can prevent the CPU trom relreshing dymamie memory properly. ‘WR. Write (cutput, active Low, 3-state). WR indicates that the CPU data bus holds valid date to be stored at the idressed memory oF V/O location, Se (parang | | i ib A bod CPU Timing The 280 CPU executes instructions by proceeding through a specific sequence of operations: = Memory read or write = UO device read or write m= Interrupt acknowledge The baste clock perled is referred to as a T time or cycle, and three or more T cycles make up a machine cycle (MI, M2 or M3 for instance). Machine cycles can be extended either by the CPU autonatically inserting fone or more Wait states or by the insertion cof one or more Wait states by the user. Instruction Opcode Fetch. The CPU places the contents of the Program Counter (PC) on the address bus at the start of the cycle (Figure 5). Approximately one-half clock gycle later, MREQ goes active, When active, RD indicates that the memory data can be enabled onto the CPU data bus. The CPU samples the WATT input with the falling edge of clock state T>. During clock states T; and T, of an MI cycle dynamic RAM relrech can occur while the CPU starts decoding and executing the instruction. When the Refresh Control signal becomes active, refreshing of dynamic memory can take place. i swrwmasal TX NOTE: Ty Wace aed vin ecm or sw ane Svs, Figure 5, Instruction Opcode Fateh CPU Timing (Continued) Memory Read or Write Gyclos. Figure 6 ie be timing of menor tad ere ies ther than an opoodte fateh (Ml) cycle. ‘Fhe MREO and RD signals function exaclly dni the fetch cycle, In'a memory write cycle, MRED also becomes active when the address bus is stable. The WE line is active ‘when the data bus is stable, so that it can be tly as an R/W pulse to most Figuee 6, Memory Read or Write Cycles iis gil i ot a CPU Timing (Continued) }¢PU Timing (Continued) Imput of Output Cycles. Figure 7 shows the This extra Wait state allows suificient time for | Interrupt Request/Acknowledge Cycle. The During this MI cycle, IORO becomes active timing for an'VO seed or VOwrite oparetion. an VO port to decode the address from the; CBU samples the interrupt signal with the (instead of MREQ) to indicate thet the intr During VO operations, the CPU port address lines. rising edge of the last clock eyele at the end rupting davice can place an B-bit vector on automatically inserts single Wait state (T,) of eny instruction (Figure 8). When an the dala bus. The CPU autometically adds mers 8 accepted, specie Mi cycle tne Wait aes fo this ool | generate: =2! eae ee ee EE 2) Tee Wa crit amc mr by CPU Figure 8. Interrupt Request/Acknowledge Cycle Figure 7. Input or Output Cycles (CPU Timing (Continued) Non-Maskable Interrupt Request Cycle. NMI is sampled at the same time as the maskable interrupt Input INT but has higher priority and cannot be disabled under Software control. The subsequent timing is similar to that oi a normal instruction fetch except that data put on the bus by the smemory is ignored: The CPU ineteed executes a restart (RST) operation and jumps to the NMI service routine located at address 066 (Figure 9). “Anse To cic “hee pe ecu oer than he inne eae he ck eye Petes Teast Figure 8, Non-Maskable Interupt Request Operation CPU Timing (Continued) Bus Reqeust/Acknowledge Cycle. The CPU felon BUSREO wih te stg eg of te BE lock period of any machine cycle ‘sare 10), U BUSREO is active, the CPU_ (Ss addzeas, data, and MBEG, TORO, Bl i 78400 oT VLE ‘and Wi lines to a high-impedance state with the sising edge of the next clock pulse. At that time, any external device can take control of these lines, usually to transfer data tween, memory and V/O devices. Ty Anca lack cyte sed by equating dance Figure 10. 2Bus Request/Acknowledge Cycle (Ze400, eevee " # aS itt CPU Timing (Continued) AC Characteristics ‘AC Characteristics _ Halt Acknowledge Cycle. When the CPU properly accept it. As long as RESET } Zatco_TauooR—Zatoos Zao receives an Halt insruction, ftexecutes NOP Femains active, the address and data buses Min Max Min ‘Max Min Mex Min Max fates untl either on INT or NMI input is float, and the contral outputs are inactive. Nuster___Symbol_ Parameter tos) (os) (cs) (os) (ns) (am) _(ox)_(os), received, When in the Halt state, the Once FESET goes inactive, three internal T ere Clock Cyclo Time oS foronre alee aa ‘umes nova pee oeee RESET fe Sen enenir ny ee oo in mo mw seh wees ao the best opeade a Weel Clock Pale With Low) 199 m0 110 20m 6 20 83 HO Reset Cycle, RESET must be active for at fetch wil be to location 0000 (Figure 12). | 4 te Clock Fal Ts ~ @- = P- w least three clock eycles for the CPU to | __s—ne Clock Rie Tine —___»—_» 2 10 @ TACHA) Clock Tt Adres Valid Delay us 0 9 — © 7 THA(MREQ) Address Valid to MEO 4 Delay 125" — 65" — 35) mt a a @ —TECIMRED Clock tte WREQ # Delay a te) ap @TACHOMREOH Clock to NEG 1 Deby im &- nm © baaad 10 twitch —NIREO Pale Width gk) —— 170° —10-——s8__45-— 8 @ : i TwiREG! REC Pulao Wieth (Low) en en Eo [8 FaCKRON Glock to RD | Detar eS

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