Professional Documents
Culture Documents
SOCKET-775
Note:
D D
Do not include the schematic
when create netlist.
Host Bus
AGP BUS
AGP SLOT DDR SDRAM
SiS648FX DIMM1
VGA AGP BUS SIS661 DIMM2
PCI Slot 1
C C
MuTIOL 1G
PCI Slot 2
LAN PHY
PCI Slot 3
AC'97
LAN
Audio Codec
SiS964
IDE 1
IDE 2
Back Panel Front Panel
B
KEYBOARD PS/2 B
SATAX2 USB 0
/MOUSE LPC Bus USB 4
USB 1 USB 5
FAN 1 USB 2 USB 6
FAN CONTROL USB 3 USB 7
FAN 2 VOLTAGE MONITOR
A A
648M06 B
Date: Wednesday, March 16, 2005 Sheet 1 of 41
5 4 3 2 1
5 4 3 2 1
CPUPWRGD
CPURST_
VRMPWRGD
D D
&
PWOK
CPUPWRGD
NBPWRGD CPURST_
ATX
Power SiS648FX
NBRST_
PSON_ SiS661FX
C C
AGP 8X SLOT
SiS963/SiS963L
SBPWRGD PCI Slot 1
PCI Slot 2
NBRST_ PCI Slot 3
PCIRST_
Front Panel
PSON_
IDE CONN 1
B RSTSW_ SIORST_ B
IDE CONN 2
PWRBTN_
PWRBTN_
SIORST_ SIORST_
Super IO Media
Interface
A A
TECHNOLOGY COPR.
Title
Reset Map
Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 2 of 41
5 4 3 2 1
14.318MHz
CPU
D D
CPUCLK0 100/133/200 MHz
100/133/200 MHz
CPUCLK1
66 MHz AGP 8x
133 MHz
DIMM 1-2
ZCLK0
66 MHz SiS648FX FWDSDCLK0 DDRCLK
AGPCLK0
CLOCK GENERATOR
C C
33 MHz
96XPCLK
133 MHz
ZCLK1
48 MHz
UCLK48M
REFCLK
33 MHz
PCI Slot 1-3
SiS964
PCICLK1-3
B B
AUDIO_CLK
32.768KHz
AC'97
24.576MHz/NC
48 MHz
SIO48M Super I/O
A A
TECHNOLOGY COPR.
Title
Clock Distribution
Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 3 of 41
5 4 3 2 1
5 4 3 2 1
DDR 2 DIMMS:
ATX VCC3
ATX SPS
12V > 2.5V
REGULATOR
VCC2.5_MEM
> 2.5V +/-100mv
P/S S3AUXSW- 6.00A
SB5V
5
V 5
3
.
+
1
-
1 +
1
> REGULATOR
S V 3 2 2
V V V 2
D B VCC2.5_MEM D
V
DDR_VTT_STR DDR VTT
MPGA478
1.25V
+12V CORE_CPU_SYS VCCP > REGULATOR > 1.25V
> VRD 10 > 1.1V~1.85V 70A 2A
VCC_VID
> MIC5258 VCCVID
> 1.2V 30mA
VCC3 SIS963L
SIS648FX
VCC3_DUAL
> VCC3:
5V_DUAL VCC3: VCC1.8V > 3.3V
PWRG_ATX
> 3.3V
108mA
1.8V
1389.5mA
VCC1.8V
>
VCC3 VCCP VCC1.8V
> VCC3_DUAL VDDQ: SB3V
> VCC3_DUAL 1.8V
VCC2.5_MEM SB1.8V
VCC3 VCC1.8V
AIC1084
> 2.5V
501.3mA
1.8V
10mA
VCC3
CLK_GEN
> 3.3V
300mA
VCCP
VCC5_DUAL
5V_SYS > SUPER I/O
VCC5_DUAL
VCC3_DUAL > 5V
VCC3
VCC5 >
PCI PER SLOT:
3.3V 7.6A
> VCC3_DUAL
PWRG_ATX
> 5V
SB5V VCC5_DUAL
VCC3_DUAL > PS2 KB/MS POWER
+12V VCC5A
VCC3
AIC1084
> AGP
VCC3
>
A5V 70mA
3.3V 10mA
+12V
>
VCC5
>
A
VCC3_DUAL
> A
>
TECHNOLOGY COPR.
Title
Power Delivery Map
Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 4 of 41
5 4 3 2 1
5 4 3 2 1
HAJ[31..3]
9 HAJ[31..3]
HDJ[63..0]
HDJ[63..0] 9
U11A
HAJ3 L5 D2
2 OF 7 HAJ4 A03# ADS# HADSJ 9
U11B P6 A04# BNR# C2 HBNRJ 9
HAJ5 M5 D4
HAJ6 A05# HIT# HITJ 9
L4 A06# RSP# H4 R255
HDJ0 B4 G16 HDJ32 HAJ7 M4 G8
HDJ1 D00# D32# HDJ33 HAJ8 A07# BPRI# HBPRIJ 9 TP_EDRDYJ
C5 D01# D33# E15 R4 A08# DBSY# B2 HDBSYJ 9
D HDJ2 A4 E16 HDJ34 HAJ9 T5 C1 D
HDJ3 D02# D34# HDJ35 HAJ10 A09# DRDY# HDRDYJ 9
C6 D03# D35# G18 U6 A10# HITM# E4 HITMJ 9 20
HDJ4 A5 G17 HDJ36 HAJ11 T4 AB2 HIERRJ
HDJ5 D04# D36# HDJ37 HAJ12 A11# IERR# R0603
B6 D05# D37# F17 U5 A12# INIT# P3 INITJ 14,31
HDJ6 B7 F18 HDJ38 HAJ13 U4 C3 +/-5%
HDJ7 D06# D38# HDJ39 HAJ14 A13# LOCK# HLOCKJ 9
A7 D07# D39# E18 V5 A14# TRDY# E3 HTRDYJ 9
HDJ8 A10 E19 HDJ40 HAJ15 V4 AD3
HDJ9 D08# D40# HDJ41 HAJ16 A15# BINIT#
A11 D09# D41# F20 W5 A16# DEFER# G7 HDEFERJ 9
HDJ10 B10 E21 HDJ42 N4 F2 TP_EDRDYJ
HDJ11 D10# D42# HDJ43 9 HREQJ[4..0] RSVD1 EDRDY#
C11 D11# D43# F21 P5 RSVD2 MCERR# AB3
HDJ12 D8 G21 HDJ44 HREQJ0 K4 GTLREF voltage should be 0.67*FSB_VTT
HDJ13 D12# D44# HDJ45 HREQJ1 REQ0# 12 mils width, 15 mils spacing
B12 D13# D45# E22 J5 REQ1# AP0# U2
HDJ14 C12 D22 HDJ46 HREQJ2 M6 U3 divider should be within 1.5" of the GTLREF pin
HDJ15 D14# D46# HDJ47 HREQJ3 REQ2# AP1# caps should be placed near CPU pin
D11 D15# D47# G22 K6 REQ3#
HDBIJ0 A8 D19 HDBIJ2 HREQJ4 J6 F3 HBR0J
9 HDBIJ0 DBI0# DBI2# HDBIJ2 9 REQ4# BR0# HBR0J 9
C8 G20 R6 G3 TESTHI_8
9 HDSTBNJ0 DSTBN0# DSTBN2# HDSTBNJ2 9 HAJ[31..3] 9 HADSTBJ0 ADSTB0# TESTHI08 VTT_OUT_RIGHT
B9 G19 G5 G4 TESTHI_9
9 HDSTBPJ0 DSTBP0# DSTBP2# HDSTBPJ2 9 9 HAJ[31..3] PCREQ# TESTHI09
H5 TESTHI_10
HDJ16 HDJ48 HAJ17 TESTHI10
G9 D16# D48# D20 AB6 A17#
HDJ17 F8 D17 HDJ49 HAJ18 W6 J16 TP_DPJ0 TP3 1) PLACE THOSE CIRCUITS R264
HDJ18 D17# D49# HDJ50 HAJ19 A18# DP0# TP_DPJ1 TP4 < 1.5" FROM THE BALL 100
F9 D18# D50# A14 Y6 A19# DP1# H15
HDJ19 E9 C15 HDJ51 HAJ20 Y4 H16 TP_DPJ2 TP2 2) THE 220PF CAPS HAS TO +/-1%
HDJ20 D19# D51# HDJ52 HAJ21 A20# DP2# TP_DPJ3 TP1 BE CLOSED TO THE BALL R0603
D7 D20# D52# C14 AA4 A21# DP3# J17
HDJ21 E10 B15 HDJ53 HAJ22 AD6 AS POSSIBLE.
HDJ22 D21# D53# HDJ54 HAJ23 A22# HGTLREF
D10 D22# D54# C18 AA5 A23# GTLREF H1
HDJ23 F11 B16 HDJ55 HAJ24 AB5
HDJ24 D23# D55# HDJ56 HAJ25 A24# C315 C317 R265
F12 D24# D56# A17 AC5 A25# RESET# G23 HCPURSTJ 9
HDJ25 HDJ57 HAJ26 1uF 220pF 210
C
HDJ26
D13
E13
D25#
D26#
D57#
D58#
B18
C21 HDJ58 HAJ27
AB4
AF5
A26#
A27# RS0# B3 HRSJ0 9
* 10V, Y5V, +80%/-20% * 50V, X7R, +/-10% +/-1%
C
TECHNOLOGY COPR.
Y1 CPU_BOOT R288 680 R0603 +/-5% VID5
BOOTSELECT LL_ID0 Title
LL_ID0 V2 LL_ID0 7
AA2 R287 62 R0603 +/-5% Dummy RSVD_AK6 Clock Distribution
LL_ID1
Document Number Rev
CPU Prescott_Socket_LGA775_Rev0.5
648M06 B
Date: Wednesday, March 16, 2005 Sheet 5 of 41
5 4 3 2 1
5 4 3 2 1
FSB_VTT
U11D 4 OF 7
HTCK AE1 A29
HTDI TCK VTT1 +12V VCC3
AD1 TDI VTT2 B25
HTDO AF1 B29
HTMS TDO VTT3
AC1 TMS VTT4 B30
HTRSTJ AG1 C29 VTT_OUT_RIGHT
TRST# VTT5 R142 R141 R146
VTT6 A26
B27 10K 249 110
HBPM0J VTT7 +/-5% +/-1% +/-1% C328
AJ2 BPM0# VTT8 C28
HBPM1J
HBPM2J
AJ1
AD2
BPM1# VTT9 A25
A28
R0603 R0603 R0603
* 1uF
10V, Y5V, +80%/-20%
D
HBPM3J BPM2# VTT10 C0603
AG2 BPM3# VTT11 A27
HBPM4J AF2 C30 Q22
HBPM5J BPM4# VTT12
AG3 BPM5# VTT13 A30
C25 GTLREF_SEL G
VTT14 2N7002
11,13 NBRST- AC2 DBR# VTT15 C26
VTT16 C27 S
AK3 B26 TESTHI_0
ITPCLKOUT0 VTT17 5 TESTHI_0
AJ3 ITPCLKOUT1 VTT18 D27
D28 C193 R144
FSBSEL0 VTT19
A
17
17
BSEL0
BSEL1
FSBSEL1
G29
H30
BSEL0
BSEL1
VTT20
VTT21
D25
D26
* 0.1uF
16V, Y5V, +80%/-20%
62
+/-1% A
G30 B28 C0603 R0603
BSEL2 VTT22
VTT23 D29
R138 D30
1K VTT24
VTTPWRGD AM6 VTTPWRGD 7
+/-1%
R0603 AA1 VTT_OUT_RIGHT VTT_OUT_RIGHT
Place at CPU end of route
Dummy VTT_OUT1 VTT_OUT_LEFT
VTT_OUT2 J1 VTT_OUT_LEFT
VTT_SEL F27
*
41 C0603 C0603 C0603 C0603
GND1 37
C293 R210 8 35 1nF Dummy Dummy Dummy Dummy
6.8nF 10nF 1K OFS GND2 C0603
* 25V, X7R, +/-10% +/-1% GND3
GND4
40
19 50V, X7R, +/-10% Close to VRD Controller
C0603 R0603 9 12 Dummy
R217 TCOMP GND5
GND6 7
VCC5
ISL6561
R211
20K 33.2K R209
R0603 +/-1% 3.9K
+/-5% R0603 +/-5%
B Dummy 47Kohm R0603 B
VTTPWRGD
6 VTTPWRGD
VTT_OUT_LEFT
FB
R280
R300 680
SB5V +12V 20K nearby PWM VTT_OUT_LEFT SB5V +/-5%
+/-5% R0603
R0603
R292 Dummy R257
D
D
R299 4.7K 10K
4.7K +/-5% Q41 R284 +/-5% Q37
+/-5% R0603 2.74K R0603
R0603 Dummy G 2N7002 +/-1% G
C
C
S
S
+/-5% MMBT3904 Q38
C
E
R0603 Dummy
C323
E
Dummy
*
A 1uF A
C0603
10V, Y5V, +80%/-20%
FOXCONN PCEG
Title
Voltage Regulator Down 10.1
Size Document Number Rev
Custom 648M06 B
*
VIN_PWM L16 Choke Coil 1.2uH 12V_POWER
Dummy
C180 C182 EC15
C144
12V_POWER R81 4.7 * 0.1uF
16V, Y5V, +80%/-20% * 4.7uF
16V, Y5V, +80%/-20%
* 1800uF
16V, +/-20%
*
+/-5% Q20 C0603 C1206 CE50D100H300
D
R0805
0.1uF
R52 4.7 BOOT1 C0603 R175 15K R0603 +/-1% Phase1_L 7
+/-5% R147 0 16V, X7R, +/-10% G C260
R0805 +/-5% AOD412 0.1uF
D R0805
L34
* C0603 D
S
C132 R149 10K 16V, X7R, +/-10%
*
1uF +/-5%
* 16V, Y5V, +80%/-20% R0603 R172 Max Current-119A
VCCP
D
C0603 2.2
Q24 Q23 +/-5% Choke Coil 0.6uH
Thermal Current-101A
R0805
R152 0 G G
+/-5% AOD412 AOD412 C244
R0805 1nF
*
S
50V, X7R, +/-10%
C0805
14
U6
C143
BOOT1 11 12 VIN_PWM
VCC
PVCC
*
13 +/-5% C106 C110 EC9
D
PHASE1
PWM1 1 4
R0805
0.1uF
Q5
* 0.1uF
16V, Y5V, +80%/-20% * 4.7uF
16V, Y5V, +80%/-20%
* 1800uF
16V, +/-20%
PWM1 LGATE1 BOOT2 C0603 C0603 C1206 CE50D100H300 R198 15K R0603 +/-1% Phase2_L 7
BOOT2 10 9 R45 0 16V, X7R, +/-10% G C270
BOOT2 UGATE2 +/-5% 0.1uF
8 R0805 AOD412
L18
* C0603
S
PHASE2
PGND
*
PWM2 2 7 +/-5% VCCP
PWM2 LGATE2 R0603 R190
D
ISL6614A 2.2
3
S
50V, X7R, +/-10%
7 PWM1 PWM1 C0805
7 PWM2 PWM2
C136
VIN_PWM
12V_POWER R56 4.7
+/-5%
* Q4 C108 C112 EC8
D
U8
R0805
0.1uF * 0.1uF
16V, Y5V, +80%/-20% * 4.7uF
16V, Y5V, +80%/-20%
* 1800uF
16V, +/-20%
R88 4.7 7 2 C0603 C0603 C1206 CE50D100H300 R174 15K R0603 +/-1%
PVCC BOOT Phase3_L 7
+/-5% R54 0 16V, X7R, +/-10% G C259
*
S
7 PWM3 3 8 R50 10K 16V, X7R, +/-10%
*
PWM PHASE +/-5% VCCP
4 5 R0603 R171
D
R57 GND LGATE 2.2
499K ISL6612 Q8 Q11 +/-5% Choke Coil 0.6uH
+/-1% R0805 VCCP VCCP
R0603 R77 0 G G
Dummy +/-5% AOD412 AOD412 C243
R0805 1nF C499 C494
*
S
Close to U26 50V, X7R, +/-10%
C0805
* 100uF
2V, +30%/-20%
* 100uF
2V, +30%/-20%
B ctdh16 ctdh16 B
C130
VIN_PWM
12V_POWER R47 4.7 Dummy Dummy
*
U5
R0805
0.1uF * 0.1uF
16V, Y5V, +80%/-20% * 4.7uF
16V, Y5V, +80%/-20%
* 1800uF
16V, +/-20%
R61 4.7 Dummy 7 2 C0603 C0603 C1206 CE50D100H300 R197 15K R0603 +/-1%
PVCC BOOT Phase4_L 7
+/-5% R46 0 Dummy 16V, X7R, +/-10% G Dummy Dummy Dummy Dummy C275
*
*
PWM PHASE Dummy +/-5% Dummy VCCP
4 5 R0603 Q13 Q10 R187
D
GND LGATE D
R76 2.2 12V_POWER
499K ISL6612 +/-5% Choke Coil 0.6uH
+/-1% Dummy R0805 Dummy
R0603 R73 0 Dummy G G Dummy
Dummy +/-5% C263 C149
4
R0805 AOD412 AOD412 1nF 0.1uF
* *
S
Close to U27 Dummy Dummy 50V, X7R, +/-10% 16V, Y5V, +80%/-20%
C0805 C0603
Dummy Dummy ATX12V_2X2
VCCP FOR EMI ISSUE CN3
VCCP
3
A A
EC17 EC13 EC16 EC12 EC14 EC18
*
EC20
560uF *
EC21
560uF *
EC19
560uF *
EC22
560uF *
EC30
560uF
* 1800uF
6.3V, +/-20%
* 1800uF
6.3V, +/-20%
* 820uF *
2.5V, +/-20%
1800uF
6.3V, +/-20%
* 820uF
2.5V, +/-20%
* 1800uF
6.3V, +/-20%
4V, +/-20% 4V, +/-20% 4V, +/-20% 4V, +/-20% 4V, +/-20% CE35D80H200 CE35D80H200 CE35D80H130 CE35D80H200 CE35D80H130 CE35D80H200
CE35D80H200 CE35D80H200 CE35D80H200 CE35D80H200 CE35D80H200 TECHNOLOGY COPR.
Title
Put under CPU Heat-Sink Output CAP
0.8V~1.55V/ 119A
Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 8 of 41
5 4 3 2 1
8 7 6 5 4 3 2 1
AAD[0..31]
AAD[0..31] 19
CP1 X_COPPER VCC3
SBA-[0..7]
SBA-[0..7] 19
A1XAVDD L27
AC-BE[0..3]
AC-BE[0..3] 19
DUMMY * FB L0603 80 Ohm
HDBIJ[0..3] C209
5 HDBIJ[0..3] ST[0..2] 10nF
HDJ[0..63] ST[0..2] 19 * 25V, Y5V, +80%/-20%
C1XAVSS
C1XAVDD
C4XAVSS
C4XAVDD
HVREF
HPCOMP
HNCOMP
ST0
ST1
ST2
AAD0
AAD1
AAD2
AAD3
AAD4
AAD5
AAD6
AAD7
AAD8
AAD9
AAD10
AAD11
AAD12
AAD13
AAD14
AAD15
AAD16
AAD17
AAD18
AAD19
AAD20
AAD21
AAD22
AAD23
AAD24
AAD25
AAD26
AAD27
AAD28
AAD29
AAD30
AAD31
SBA-7
SBA-6
SBA-5
SBA-4
SBA-3
SBA-2
SBA-1
SBA-0
5 HDJ[0..63] ADSTBF[0..1] C0603 CP2 X_COPPER
ADSTBF[0..1] 19
ADSTBS[0..1] A1XAVSS L26
5 HAJ[31..3]
HAJ[31..3] ADSTBS[0..1] 19
DUMMY * FB L0603 80 Ohm
D HREQJ[4..0] FSB_VTT
D
5 HREQJ[4..0] R159
AK34
AK35
AA26
AL36
AJ36
W26
U26
R26
D22
C22
B22
L20
W4
W6
G3
G4
G6
U2
U4
R2
R3
R4
N2
R6
H4
H5
D2
HNCOMP
B6
B5
Y5
V2
V4
V5
P2
K2
K4
E2
E3
E4
B2
E6
B3
F7
T4
T5
F2
F4
F5
L3
L4
L6
J2
J3
J4
J6
U12A
C1XAVSS
C4XAVSS
HVREF0
HVREF1
HVREF2
HVREF3
HVREF4
HCOMP_P
ST0
ST1
ST2
AAD0
AAD1
AAD2
AAD3
AAD4
AAD5
AAD6
AAD7
AAD8
AAD9
AAD10
AAD11
AAD12
AAD13
AAD14
AAD15
AAD16
AAD17
AAD18
AAD19
AAD20
AAD21
AAD22
AAD23
AAD24
AAD25
AAD26
AAD27
AAD28
AAD29
AAD30
AAD31
SBA7
SBA6
SBA5
SBA4
SBA3
SBA2
SBA1
SBA0
C1XAVDD
C4XAVDD
HCOMP_N
HCOMPVREF_N
CPUCLK1 AC-BE3 14
17 CPUCLK1 AJ31 CPUCLK AC/BE3# K5
CPUCLK-1 AJ33 M5 AC-BE2 R0603
17 CPUCLK-1 CPUCLK# AC/BE2# AC-BE1 +/-1%
AC/BE1# P4
HLOCKJ T33 U6 AC-BE0 R49 change from 100 to 120
5 HLOCKJ HDEFERJ HLOCK# AC/BE0#
5 HDEFERJ T35 DEFER# R158
5 HTRDYJ
5 HCPURSTJ
14 CPUPWRGD_NB
5 HBPRIJ
HTRDYJ
HCPURSTJ
CPUPWRGD_NB
HBPRIJ
HBR0J
V32
B23
F22
R34
U31
HTRDY#
CPURST#
CPUPWRGD
BPRI#
AGP AREQ#
AGNT#
AFRAME#
AIRDY#
C6
E8
N6
M4
N4
AREQ
AGNT
AFRAME
AIRDY
ATRDY
19
19
19
19
19
120
HPCOMP
DBI3#
DBI2#
DBI1#
DBI0#
HAJ3
HD9#
HD8#
HD7#
HD6#
HD5#
HD4#
HD3#
HD2#
HD1#
HD0#
AA34 HA3#
VCCP A4XAVDD L31
648C DUMMY * FB L0603 80 Ohm
SIS648 C208
C24
E23
B24
D23
D25
F24
C26
B25
B26
D27
D26
E27
B27
D28
C28
B28
E29
F28
B29
C30
B30
B31
C32
D29
C33
B33
B35
D32
B34
E31
D31
D33
D35
G31
C35
F33
E33
D34
E35
F32
J34
G34
H35
F35
J33
J31
G35
H33
J35
K32
N33
K33
L31
L33
K35
L35
M35
M33
P32
P33
L34
N34
N35
P35
F26
B32
E34
R31
R143 10nF
619 * 25V, Y5V, +80%/-20%
+/-1% FSB_VTT C0603 CP4 X_COPPER
HDJ63
HDJ62
HDJ61
HDJ60
HDJ59
HDJ58
HDJ57
HDJ56
HDJ55
HDJ54
HDJ53
HDJ52
HDJ51
HDJ50
HDJ49
HDJ48
HDJ47
HDJ46
HDJ45
HDJ44
HDJ43
HDJ42
HDJ41
HDJ40
HDJ39
HDJ38
HDJ37
HDJ36
HDJ35
HDJ34
HDJ33
HDJ32
HDJ31
HDJ30
HDJ29
HDJ28
HDJ27
HDJ26
HDJ25
HDJ24
HDJ23
HDJ22
HDJ21
HDJ20
HDJ19
HDJ18
HDJ17
HDJ16
HDJ15
HDJ14
HDJ13
HDJ12
HDJ11
HDJ10
HDJ9
HDJ8
HDJ7
HDJ6
HDJ5
HDJ4
HDJ3
HDJ2
HDJ1
HDJ0
R0603
HDBIJ3
HDBIJ2
HDBIJ1
HDBIJ0
A4XAVSS L28
*
D
*
DQM3 AP24 DQM3
DQS3 AR25 DQS3/CSB3# 10pF
MD32
MD33
AN21 MD32
AP20 MD33
CKE0 AP4
AT3
CKE0
CKE1
* R188
4.7K C0603
VCC2.5_MEM MD34 CKE1 CKE2 +/-5% 50V, NPO, +/-5%
AN20 MD34 CKE2 AR3
MD35 AL18 MD35 AP3 CKE3 R0603
MD36 CKE3 Dummy VCC3
AM21 MD36 CKE4 AR2
C358 C356 MD37 AR21 MD37 AN4 CP9 X_COPPER
0.1uF 0.1uF MD38 CKE5
* 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% MD39
AL19 MD38 S3AUXSW# AP2 S3AUXSW- 37 DDRAVDD L46
C0603 C0603 DQM4
AM19 MD39
AL20 DQM4 DUMMY * FB L0603 80 Ohm
Dummy Dummy DQS4 AR20 DQS4/CSB4# C286
MD40 0.1uF
MD41
AL15 MD40
AL14 MD41
R218 * 16V, Y5V, +80%/-20%
MD42 AN15 MD42 AL21 FWDSDCLKO C0603 CP10 X_COPPER
C379 C355 MD43 FWDSDCLKO FWDSDCLKO 18
AR15 MD43
B * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
MD44
MD45
AN16 MD44
AM15 MD45
DRAMTEST AL22 22
DDRAVSS L45
DUMMY * FB L0603 80 Ohm
B
C0603 C0603 MD46 AN14 MD46 R0603 VCC2.5_MEM
R238
Dummy MD47 AL13 MD47 +/-5%
DQM5 AP16 DQM5 AL35 DLLAVDD DDRCOMN
DQS5 DLLAVDD
AR16 DQS5/CSB5#
C353 C359 MD48 AM13 MD48 AL34 DLLAVSS VCC3
0.1uF 0.1uF MD49 DLLAVSS 40.2 CP11 X_COPPER
* 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% MD50
AL12 MD49
AL11 MD50 R0603
C0603 C0603 MD51 DDRAVDD +/-1% DLLAVDD L44
Dummy Dummy MD52
AR12 MD51
AP14 MD52
DDRAVDD AM35
DUMMY * FB L0603 80 Ohm
MD53 AR14 MD53 AN36 DDRAVSS C281
MD54 DDRAVSS
AN13 SIS648 0.1uF
C351 C403 MD55 MD54
AP12 MD55 R237
* 16V, Y5V, +80%/-20%
0.1uF 0.1uF DQM6 C0603 CP12 X_COPPER
* 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% DQS6
AN12 DQM6
AR13 DQS6/CSB6# DDRVREFA AF16 DDRVREFA DDRCOMP
C0603 C0603 MD56 DDRVREFB DLLAVSS L43
Dummy MD57
AL10 MD56
AR11 MD57
DDRVREFB AF23
40.2
DUMMY * FB L0603 80 Ohm
MD58 AM9 MD58 AP1
MD59 TRAP2 R0603
AR9 MD59
C340 C366 MD60 AM11 MD60 AR8 DDRCOMP +/-1%
0.1uF 0.1uF MD61 DDRCOMP_P DDRCOMN
* 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% MD62
AN11 MD61
AP10 MD62
DDRCOMP_N AP8
A A
TECHNOLOGY COPR.
Title
661FX-2 DDR
Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 10 of 41
8 7 6 5 4 3 2 1
ROUT GOUT BOUT
** **
150 13 ZSTB-1 ZSTB1# HSYNC 33 R160 LSYNC
VSYNC B11 VSYNC 20 5 6
ZAD0 AH5 CSYNC 7 8
ZAD1 ZAD0 100 R156
AK2 ZAD1 VGPIO0 E13 DDC1CLK 20
ZAD2 AJ4 C11 100 R161 RSYNC R157 4.7K DUMMY
DDC1DATA 20
*
ZVREF ZAD3 ZAD2 VGPIO1
AJ6 ZAD3
ZAD4 AH2 ZAD4
* R214
51.1
C295
0.1uF
ZAD5
ZAD6
AH4 ZAD5 INT#A C10 INT-A 13,19,24,25
* 16V, Y5V, +80%/-20% ZAD7
AG3
AG6
ZAD6
ZAD7
C0603 ZAD8 AF4 D12 CSYNC
ZAD9 ZAD8 CSYNC RSYNC NBPWRGD C288 0.1uF C0603 16V, Y5V, +80%/-20%
AG2 E12
HyperZip
**
ZAD10 ZAD9 RSYNC LSYNC
AF5 ZAD10 LSYNC D11
ZAD11 AG4 AUXOK C284 0.1uF C0603 16V, Y5V, +80%/-20%
ZAD12 ZAD11
AD2 ZAD12
ZAD13 AE6 E15 VCOMP
ZAD14 ZAD13 VCOMP VRSET
AE2 D15
C ZAD15 AE4
ZAD14
ZAD15
VRSET
VVBWN E14 VVBWN C
ZAD16 AL3 ZAD16 DACAVDD
DACAVDD1 D13
ZVREF AK4 C12 DACAVSS
ZVREF DACAVSS1 CP13 X_COPPER VCC3
VCC3 CP15 X_COPPER ZCMP_N AD5 D14 DACAVDD
ZCMP_P ZCOMP_N DACAVDD2 DACAVSS DCLKAVDD L33
L38
* Z4XAVDD
AD4 ZCOMP_P DACAVSS2 C13
C212 DUMMY * FB L0603 80 Ohm
DUMMY FB L0603 80 Ohm DCLKAVDD 0.1uF
C283 Z1XAVDD AN1 Z1XAVDD
DCLKAVDD
DCLKAVSS
B15
C15 DCLKAVSS * 16V, Y5V, +80%/-20% CP14 X_COPPER
TESTMODE2
TESTMODE1
TESTMODE0
0.1uF Z1XAVSS C0603
* 16V, Y5V, +80%/-20% CP17 X_COPPER
AM2 Z1XAVSS ECLKAVDD DCLKAVSS L29
B14
*
PCIRST#
ECLKAVDD
ENTEST
PWROK
DLLEN#
C0603 Z4XAVDD ECLKAVSS DUMMY FB L0603 80 Ohm
AUXOK
AL2 C14
TRAP1
TRAP0
L36 Z4XAVSS Z4XAVSS Z4XAVDD ECLKAVSS
DUMMY * FB L0603 80 Ohm
AL1 Z4XAVSS
SIS648
AN2
AM4
AN3
F9
D10
C9
B9
B10
E10
D9
CP16 X_COPPER VCC3
648C
ECLKAVDD L32
38 NBPWRGD
6,13 NBRST- NBPWRGD C210 DUMMY * FB L0603 80 Ohm
AUXOK ENTEST 0.1uF
14,40 AUXOK * 16V, Y5V, +80%/-20% CP18 X_COPPER
C0603
ECLKAVSS L30
VCC3 CP39 X_COPPER DUMMY * FB L0603 80 Ohm
B L39
DUMMY* FB L0603 80 Ohm
Z1XAVDD B
C277
0.1uF
CP40 X_COPPER * 16V, Y5V, +80%/-20%
C0603
L41 Z1XAVSS VRSET
DUMMY* FB L0603 80 Ohm VVBWN C201 0.1uF C0603 16V, Y5V, +80%/-20%
* *
VCC1.8V
VCOMP C200 0.1uF C0603 16V, Y5V, +80%/-20%
VCC1.8V
CP19 X_COPPER
* R148
130
DACAVDD L25
R177 56 ZCMP_N C493 C492 DUMMY * FB L0603 80 Ohm
*
+/-5%
R0603
Put the cap bottom side
A A
TECHNOLOGY COPR.
Title
661FX-3 VGA & MUTIOL
Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 11 of 41
8 7 6 5 4 3 2 1
VCC1.8V
648C
AC24
AD13
AD15
AD17
AD19
AD21
AD23
AD24
AA24
AB13
AA13
AA12
SB3V SB1.8V
W13
W24
AM3
W11
W12
AM5
AG1
AH3
AD3
M17
AK3
AE1
C17
C18
C19
C20
C21
D17
D18
D19
D20
D21
N13
N14
N16
N18
N19
N20
N21
N22
N23
N24
R24
U24
N15
R13
U13
AF3
N17
A17
A18
A19
A20
A21
B17
B18
B19
B20
B21
E17
E18
E19
E20
E21
P13
P24
V13
V24
Y13
Y24
Y11
Y12
F17
F18
F19
F20
F21
T13
T24
AJ1
L17
D4
D5
SB1.8V
U12D C504 C503
IVDD, AUX_IVDD 1.8V
* 1uF
* 0.1uF
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
VDDZ
NC1
NC2
NC3
VDD3.3
VDD3.3
VDD3.3
IVDD
IVDD
IVDD
IVDD
IVDD
PVDD
IVDD
PVDD
IVDD
IVDD
IVDD
IVDD
PVDD
PVDD
IVDD
PVDD
PVDD
IVDD
IVDD
PVDD
PVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
PVDD
IVDD
IVDD
IVDD
L25 AB12 10V, Y5V, +80%/-20% 16V, Y5V, +80%/-20%
VTT AUX_IVDD C0603 C0603
L26 VTT AUX3.3 AC12 SB3V
M18 Bottom Bottom
VTT
M19 VTT VDDQ AA1 VDDQ
M20 VTT VDDQ AA2
M21 VTT VDDQ AA3
M22 AA4
D M23
M24
VTT
VTT
VTT
VDDQ
VDDQ
VDDQ
AA5
AA6 D
M25 VTT VDDQ AB1
M26 VTT VDDQ AB2
N25 VTT VDDQ AB3
P25 VTT VDDQ AB4
R25 VTT VDDQ AB5
T25 AB6 FSB_VTT VCC1.8V
VTT VDDQ
U25 VTT VDDQ AC1
V25 VTT VDDQ AC2
W25 AC3 C188 C207 C265 C261
VTT VDDQ
VCC2.5_MEM
Y25
AA25
VTT
VTT
VDDQ
VDDQ
AC4
AC5
* 1uF
10V, Y5V, +80%/-20% * 1uF
10V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
AC6 C0603 C0603 C0603 C0603
VDDQ
AL7 VDDM
AL8 VDDM VDDQ L11
AL9 VDDM VDDQ L12
AM6 VDDM VDDQ L13
AM7 M11 C214 C187 C506 C264
VDDM VDDQ
AM8
AN5
VDDM
VDDM
VDDQ
VDDQ
M12
M13
* 1uF
10V, Y5V, +80%/-20% * 10uF
10V, Y5V, +80%/-20% * 1uF
10V, Y5V, +80%/-20% * 10uF
10V, Y5V, +80%/-20%
AN6 M14 C0603 C1206 C0603 C1206
VDDM VDDQ Dummy Bottom Dummy
AN7 VDDM VDDQ M15
AN8 VDDM VDDQ M16
AP5 VDDM VDDQ N11
AP6 VDDM VDDQ N12
AP7 VDDM VDDQ P12
AR4 VDDM VDDQ R12
AR5 VDDM VDDQ T12
AR6 VDDM VDDQ U12
AR7 VDDM VDDQ V12
AT4 VDDM
AT5 VDDM IVDD B16 VCC1.8V
AT6 VDDM IVDD C16
AT7 D16 VCC2.5_MEM
AB25
AC25
VDDM
SIS648
VDDM
Power IVDD
IVDD
IVDD
E16
F15
C343 C380 C344
VDDM
AD12
AD25
VDDM
VDDM
NC4
NC5
E11
F11
* 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 1uF
10V, Y5V, +80%/-20%
AE11 F13 C0603 C0603 C0603
VDDM NC6 Dummy Dummy
AE12 VDDM NC7 AL33
C AE13
AE14
AE15
VDDM
VDDM
NC8
NC9
AM34
A9
A3
C
VDDM VSS C291 C298
AE16 VDDM VSS A5
AE17
AE18
VDDM
VDDM
VSS
VSS
C1
C3
* 1uF
10V, Y5V, +80%/-20% * 10uF
10V, Y5V, +80%/-20%
AE19 C5 C0603 C1206
VDDM VSS Dummy
AE20 VDDM VSS E1
AE21 VDDM VSS E5
AE22 VDDM VSS E7
AE23 VDDM VSS E9
AE24 VDDM VSS F3
AE25 VDDM VSS G1
AE26 VDDM VSS G5
AF11 VDDM VSS H3
AF12 VDDM VSS J1
AF25 VDDM VSS J5
AF26 K3 VDDQ
VDDM VSS
VSS L1
AB24 PVDDM VSS L5
AC13 M3 C247 C246
PVDDM VSS
AD14
AD16
PVDDM
PVDDM
VSS
VSS
N1
N5
* 1uF
10V, Y5V, +80%/-20% * 1uF
10V, Y5V, +80%/-20%
AD18 P3 C0603 C0603
PVDDM VSS
AD20 PVDDM VSS R1
AD22 PVDDM VSS R5
VSS T3
P14 VSS VSS U1
P15 U5 C248 C251
VSS VSS
P16
P17
VSS
VSS
VSS
VSS
V3
W1
* 1uF
10V, Y5V, +80%/-20% * 10uF
10V, Y5V, +80%/-20%
P18 W5 C0603 C1206
VSS VSS Dummy
P19 VSS VSS Y3
P20 VSS
P21 VSS VSS AE5
P22 VSS VSS AG5
P23 VSS VSS AJ5
R14 VSS VSS AL5
R15 VSS
R16 A22 Place these capacitors under 660 solder side
VSS VSS
R17 VSS VSS A24
R18 A26 VCC1.8V VDDQ VCC2.5_MEM
VSS VSS
R19 A28
B R20
R21
VSS
VSS
VSS
VSS
VSS
VSS
A30
A32 C505 C498 C500 C497 C511 C509 B
R22
R23
VSS
VSS
VSS
VSS
A34
C23
* 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
T14 C25 C0603 C0603 C0603 C0603 C0603 C0603
VSS VSS Bottom Bottom Bottom Bottom Bottom Bottom
T15 VSS VSS C27
T16 VSS VSS C29
T17 VSS VSS C31
T18 VSS VSS C34
T19 C36 C495 C501 C496 C508
VSS VSS
T20
T21
VSS
VSS
VSS
VSS
E22
E24
* 0.1uF
16V, Y5V, +80%/-20% * 10uF
10V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
T22 E26 C0603 C1206 C0603 C0603
VSS VSS Bottom Bottom Bottom Bottom
T23 VSS VSS E28
U14 VSS VSS E30
U15 VSS VSS E32
U16 VSS VSS E36
U17 VSS VSS F34
U18 VSS VSS G32
U19 VSS VSS G36
U20 VSS VSS H34
U21 VSS VSS J32
U22 J36 FSB_VTT FSB_VTT FSB_VTT FSB_VTT FSB_VTT
VSS VSS
U23 VSS VSS K34
V14 VSS VSS L32
V15 L36 C526 C527 C528 C529 C530
VSS VSS
V16
V17
VSS
VSS
VSS
VSS
M34
N32
* 4.7uF * 4.7uF * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
V18 N36 C0805 C0805 C0603 C0603 C0603
VSS VSS 10V, Y5V, +80%/-20% 10V, Y5V, +80%/-20% Bottom Bottom Bottom
V19 VSS VSS P34
V20 R32 Bottom Bottom
VSS VSS
V21 VSS
V22 VSS VSS T34
V23 VSS VSS U32
W14 VSS VSS U36
W15 V34 VCC1.8V VCC1.8V VCC2.5_MEM
VSS VSS
W16 VSS VSS W32
W17 VSS VSS W36
W18 Y34 C531 C532 C533
VSS VSS
W19
W20
VSS
VSS
VSS
VSS
AA32
AA36
* 4.7uF * 4.7uF * 10uF
10V, Y5V, +80%/-20%
W21 AB34 C0805 C0805 C1206
VSS VSS 10V, Y5V, +80%/-20% 10V, Y5V, +80%/-20% Bottom
A W22
W23
VSS
VSS
Bottom Bottom A
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC32
AC36
AD34
AE32
AE36
AF34
AM10
AM12
AM14
AM16
AM18
AM20
AM22
AM24
AM26
AM28
AM30
AP9
AP11
AP13
AP15
AP17
AP19
AP21
AP23
AP25
AP27
AP29
AP31
AP33
AP35
AT8
AG32
AG36
AH34
AJ32
AT10
AT12
AT16
AT18
AT20
AT22
AT24
AT26
AT28
AT30
AT32
AT34
AL32
TECHNOLOGY COPR.
Title
661FX-4 Power
Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 12 of 41
8 7 6 5 4 3 2 1
VCC3 AD[0..31]
24,25,35 AD[0..31]
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
INT-A
INT-B
2 * 13 L48
INT-C
4
6 5 *
DUMMY FB L0603 80 Ohm
INT-D 8 7 * R293
4.7K
C338
0.1uF
*
W4
M4
M3
H3
H2
H1
R4
R3
R2
R1
U3
U2
U1
8.2K +/-5% 16V, Y5V, +80%/-20%
K4
K2
K1
V4
V3
V2
V1
T4
T3
T2
T1
L4
L3
L2
L1
J4
J3
J2
J1
D +/-5%
8P4R0603
R0603
Dummy
U15A C0603 D
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
IDEAVDD W1
PREQ-4 F1 W2
35 PREQ-3 PREQ-3 PREQ4# IDEAVSS
F2 PREQ3#
25 PREQ-2 PREQ-2 F3 AE15 ICHRDYA
PREQ2# ICHRDYA ICHRDYA 26
24 PREQ-1 PREQ-1 F4 AD14 IDEREQA
PREQ1# IDREQA IDEREQA 26
24 PREQ-0 PREQ-0 E1 AC15 IDEIRQA
PREQ0# IIRQA IDEIRQA 26
AE16 CBLIDA
CBLIDA 26
35
25
PGNT-3
PGNT-2
PGNT-3
PGNT-2
H4
G1
G2
PGNT4#
PGNT3#
PGNT2#
PCI CBLIDA
IIORA#
IIOWA#
AF15
AC14
IDEIOR-A
IDEIOW-A
IDEIOR-A
IDEIOW-A
26
26
24 PGNT-1 PGNT-1 G3 AD15 IDACK-A
C/BE-[0..3] PGNT1# IDACKA# IDACK-A 26
24 PGNT-0 PGNT-0 G4
24,25,35 C/BE-[0..3] PGNT0# IDESAA2
IDSAA2 AC16
C/BE-3 K3 AF16 IDESAA1 IDESAA[0..2]
C/BE3# IDSAA1 IDESAA[0..2] 26
C/BE-2 M2 AD16 IDESAA0
C/BE-1 C/BE2# IDSAA0
P1 C/BE1#
C/BE-0 U4 AE17 IDECS-A1 IDECS-A[0..1]
C/BE0# IDECSA1# IDECS-A[0..1] 26
AF17 IDECS-A0
INT-A IDECSA0#
11,19,24,25 INT-A F5 INTA#
INT-B E4
19,24,25 INT-B INT-C INTB# ICHRDYB
24,25 INT-C E3 INTC# ICHRDYB AE22 ICHRDYB 26
INT-D E2 AD21 IDEREQB
24,25,35 INT-D INTD# IDREQB IDEREQB 26
AC22 IDEIRQB
IIRQB IDEIRQB 26
FRAME- M1 AE23 CBLIDB
24,25,35 FRAME- FRAME# CBLIDB CBLIDB 26
IRDY- N4
24,25,35 IRDY- TRDY- IRDY# IDEIOR-B
N3 AF22
C IDEIOR-B 26 C
24,25,35 TRDY-
24,25,35 STOP-
24,25,35 SERR-
STOP-
SERR-
P4
P3
TRDY#
STOP#
SERR#
IDE IIORB#
IIOWB#
IDACKB#
AC21
AD22
IDEIOW-B
IDACK-B
IDEIOW-B
IDACK-B
26
26
PAR P2 AF24 IDESAB2
24,25,35 PAR DEVSEL- PAR IDSAB2 IDESAB1 IDESAB[0..2]
24,25,35 DEVSEL- N2 DEVSEL# IDSAB1 AF23 IDESAB[0..2] 26
PLOCK- IDESAB0
964/964L -1
24,25 PLOCK- N1 PLOCK# IDSAB0 AD23
* R305
49.9
*
C339
0.1uF
SZ4XAVSS
SZVREF
AA23
AA26
ZAD16 Y26
Z4XAVDD
Z4XAVSS
ZVREF
HyperZip IDB10
IDB11
IDB12
IDB13
AE19
AC19
AE20
IDEDB11
IDEDB12
IDEDB13
IDEDB14
CP26 X_COPPER
C0603
SZ4XAVSS
IDB15
ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
IDEDB[0..15] 26
SiS964
W24
W25
V22
V23
V26
U22
U25
U24
T22
U26
T23
R22
T24
R24
R26
P22
ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
VCC1.8V Analog Power supplies of Transzip function for 96X Chip. VCC1.8V
R303
CP22 X_COPPER CP24 X_COPPER 56 SZCMP_N
A 11 ZAD[0..16] * +/-5% A
L51 SZ1XAVDD C337 R0603
DUMMY * FB L0603 80 Ohm C365 For EMI * 0.1uF
0.1uF SIORST- 16V, Y5V, +80%/-20%
* 16V, Y5V, +80%/-20% C0603 TECHNOLOGY COPR.
C0603 C534 R311
CP25 X_COPPER SZ1XAVSS 0.1uF 56 SZCMP_P Title
*
*
648M06 B
Date: Wednesday, March 16, 2005 Sheet 13 of 41
8 7 6 5 4 3 2 1
U15B
E
R320 10K R0603 +/-5% TXD1
AF26 C12
VCC3
AC25
APICCK/LDTREQ# TXD2
E13 ? GPWAK- B MMBT3904
5 PROCHOTJ
STHERMTRIP- AB24
APICD0/THERM2#
APICD1/GPIOFF# APIC TXD3
NC34 D13
E14
Q36
C
NC31 1K
28,31 LAD[0..3] NC32 C14
D15 R0603
LAD0 NC30 +/-5%
AC4 LAD0 CPU_PWRG 5
LAD1 AC3
LAD2 LAD1
AE1 LAD2
LAD3
LFRAME-
AF1
AD3
LAD3 LPC C13
28,31 LFRAME- LDRQ- LFRAME# RXCLK
28 LDRQ- AE2 LDRQ#
28 SIRQ
SIRQ AF2 SIRQ
964/964L-2 RXDV A12
A13
OSC32KHO
4
40 BATOK SBPWRGD BATOK RXD2 15pF 15pF
17,38 SBPWRGD D2 PWROK RXD3
NC36
C11
A10
* 50V, NPO, +/-5% * 50V, NPO, +/-5%
C329 RTCVDD C10 C0603 C0603
C * 0.1uF NC35
NC38 A9 Crystal Retainer C
16V, Y5V, +80%/-20% C3 B9
C0603 RTCVDD NC37 SB3V
D3 RTCVSS NC33 A14
VCC3 VCC3
C9
MDC ?
SDATI0 E6 E9 R319 R318
33 SDATI0 AC_SDIN0 MDIO 1K 330
B4 AC_SDIN1 +/-5% +/-1%
SDATO AB3 B7 SB3V R0603 R0603
33 SDATO AC_SDOUT MIIAVDD
33 SYNC
SYNC
AC_RESET-
AC1
B5
AC_SYNC AC97 MIIAVSS A6
STHERMTRIP-
C
33 AC_RESET- BIT_CLK AC_RESET#
33 BIT_CLK AC2 AC_BIT_CLK
Y3 B Q45
GPIO0/SPDIF MMBT3904
C
R321
E
B 17 REFCLK1
REFCLK1
SENTEST
AD2
D1
OSCI GPIO1/LDRQ1# AE3 5 THERMTRIPJ B Q48
MMBT3904
B
SPKR ENTEST
AD1
E
33,40 SPKR SPK THERM- 4.7K
GPIO2/THERM# Y4 THERM- 28 R0603
40 PWRBTN-
19,24,25,28,35 PME-
PWRBTN-
PME-
D5
A7
PWRBTN#
PME#
ACPI GPIO INTRUDER
R313
BAT +/-5%
38 PSON-
PSON-
AUXOK
D8
A3
PSON# /others GPIO3/EXTSMI# AA1 ID2
R314
2
1 1M
R0603 VCC3
11,40 AUXOK ACPILED AUXOK ID1 Dummy +/-5%
40 ACPILED B6 ACPILED GPIO4/CLKRUN# AA2 VCC3
C313 Dummy
0.1uF R312
* 16V, Y5V, +80%/-20%
GPIO5/PREQ5# AA3 4.7K 4.7K THERM- R316 4.7K R0603 +/-5%
C0603 +/-5% R0603
R0603 +/-5% BIOS_PROTECTR228 4.7K R0603 +/-5% Dummy
LAN_DISABLEJ B2 AA4 Dummy Dummy
35 LAN_DISABLEJ GPIO13 GPIO6/PGNT5# SMBDAT R346 4.7K R0603 +/-5%
? 40 S3_LED
S3_LED A5 GPIO14 GPIO7 A4 GPWAK- SMBCLK
GPIO12
R349
R419
4.7K R0603 +/-5%
29 KBCLK
KBCLK A8 GPIO16/KBCLK
KBC GPIO9/AC_SDIN2 C5 SENTEST R282 0 R0603 +/-5%
C4 BIOS_TBL_PROTECT
A 29 PMDAT
PMDAT C8 GPIO17/PMDAT
GPIO10/AC_SDIN3 BIOS_TBL_PROTECT 31 A
F6 BIOS_PROTECT
GPIO11/OSC25M/STP_PCI# BIOS_PROTECT 31
PMCLK D6
29 PMCLK GPIO18/PMCLK
TECHNOLOGY COPR.
SB3V R411 4.7K S3_LED E5 GPIO12
GPIO12/CPUSTP# Title
SIGNAL STATE LEVEL 964_2
S3_LED S3 LOW SiS964
OTHERS HIGH Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 14 of 41
VCC1.8V 8 L52 7 6 5 4 3 2 1
1 2 SATACMPAVDD
C368 C369
FB L0603 80 Ohm 10nF 0.1uF
* 25V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20%
C0603 C0603
CP27 X_COPPER SATACMPAVSS
VCC5 U15C
R221
UV0+ G26
C249 27 UV0+ UV0- UV0+ OSC12MHI
27 UV0- G25 UV0- OSC12MHI E25 USB12M 17
D D
*
UV1+ H24
27 UV1+ UV1- UV1+ OSC12MHO
27 UV1- H23 UV1- OSC12MHO E26 0
0.1uF Dummy UV2+ C21 R234
C0603 27 UV2+ UV2- UV2+ USBREF 127 R0603
D21 A24
*
16V, Y5V, +80%/-20% 27 UV2- UV3+ UV2- USBREF +/-1% +/-5%
27 UV3+ A22 UV3+
C116 UV3- B22 F24 USBPVDD1.8 R0603
27 UV3- UV3- USBPVDD18
*
D25 C310
OC3# 0.1uF
0.1uF Dummy
27 OC4567- D24
E24
OC4#
OC5# IVDD_AUX G21 IVDD_AUX * 16V, Y5V, +80%/-20% FB L0603 80 Ohm
C0603 E23 H21 IVDD_AUX C0603
16V, Y5V, +80%/-20% SB1.8V OC6# IVDD_AUX
F22 OC7#
964-3
E18 UVDD18
C312 C309 E20 SB3V
10nF 0.1uF UVDD18
* 25V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20%
E22
F17
UVDD18
C C0603 C0603 F18
UVDD18
UVDD18
R256 C
F19 IPB_OUT0 4.7K Dummy SB1.8V
**
UVDD18 R259
F20 UVDD18
F21 IPB_OUT1 4.7K Dummy CP45 X_COPPER USBCMPAVDD1.8
UVDD18 C314
G22 UVDD18
VCC1.8V L54 0.1uF
H22 UVDD18 * 16V, Y5V, +80%/-20%
1 2 AA6 C0603
C376 C374 IVDD STX1P CP46 X_COPPER USBCMPAVSS1.8
AA7 IVDD NC AD7
10nF 1uF STX1N
FB L0603 80 Ohm * 25V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20%
AA8
AA9
IVDD
IVDD
NC
NC
AC7
AF6 SRX1P
C0603 C0805 AA10 AE6 SRX1N
SATARXAVDD
AB6
IVDD
IVDD SATA NC
NC
NC
AD9
AC9
STX2P
STX2N
SRX2P
AF3 IVDD NC AF8
VCC1.8V SATARXAVSS AD4 AE8 SRX2N
L49 VSS NC FDLL4148
SATATXAVDD Y2 AB4 SATA_LED 2 1
SATATXAVDD SATATXAVSS IVDD NC HDDLED 26,40
1 2 Y1 VSS
C361 C345 D6
10nF 1uF SATACMPAVDD
FB L0603 80 Ohm * 25V, Y5V, +80%/-20%* 16V, Y5V, +80%/-20% SATACMPAVSS
AB5
AD5
IVDD
VSS
GPIO21/EESK
GPIO22/EEDI
A16
A15
C0603 C0805 B16 R223 4.7K R0603 +/-5%
CP29 X_COPPER SATATXAVSS GPIO23/EEDO SB1.8V
GPIO24/EECS B15
NC
B 17 CLK_SATAJ
SATACLK-
SATACLK
AE4 NC IPB_OUT1/ZCLKSEL B25 IPB_OUT1 C303
0.1uF
B
17 CLK_SATA AF4 NC SB3V * 16V, Y5V, +80%/-20%
R273 C0603
B26 4.7K Dummy
**
TRAP0 R289 CP42 X_COPPER
C25 4.7K Dummy
TRAP1
SiS964
R281 R283
22 22
+/-5% +/-5% SB1.8V
R0603 ** R0603
USBPVDD1.8 CP43 X_COPPER
C330
@SHIELD,ORANGE 0.1uF
* 16V, Y5V, +80%/-20%
SATA1 1 OSC12MHO C0603
SATA 2 STX1P USBPVSS1.8 CP44 X_COPPER
8 3 STX1N R222
4 OSC12MHI 1M
*
648M06 B
Date: Wednesday, March 16, 2005 Sheet 15 of 41
8 7 6 5 4 VCC1.8V 3 2 U15D 1
VSS L10
VCC1.8V P26 L11
VDDZ VSS
P21 VDDZ VSS L12
R21 VDDZ VSS M10
T25 VDDZ VSS M11
V25 VDDZ VSS M12
V21 VDDZ VSS N10
W21 VDDZ VSS N11
Y25 VDDZ VSS N12
Y21 VDDZ VSS N13
SB1.8V N14
VSS
VSS N15
D M21
N21
IVDD VSS N16
P10
D
IVDD VSS
T21 IVDD VSS P11
U21 IVDD VSS P12
FSB_VTT C334 C307 AB18 P13
IVDD VSS
*
AB16 IVDD VSS P14
AB14 IVDD VSS R10
VCC3 0.1uF 0.1uF AB11 R11
C0603 C0603 IVDD VSS
AA5 IVDD VSS R12
16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% Y5 R13
C336 C308 IVDD VSS
T5 IVDD VSS R14
*
C360 C362 R5 T10
IVDD VSS
*
* 0.1uF
16V, Y5V, +80%/-20% 0.1uF 0.1uF
L5
G5
IVDD
IVDD
VSS
VSS
T13
T14
C0603 0.1uF C0603 C0603 VCC3 U10
C0603 16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% VSS
VSS U13
16V, Y5V, +80%/-20% C325 C278 L21 U14
PVDD VSS
*
VCC3 VCC5 AA21 PVDD VSS U15
AB19 PVDD
0.1uF 0.1uF AB13 P15
C0603 C0603 PVDD VSSZ
U5 PVDD VSSZ P16
16V, Y5V, +80%/-20% 16V, Y5V, +80%/-20% M5 R15
C324 PVDD VSSZ
H5 PVDD VSSZ R16
*
VSSZ T15
K21 OVDD VSSZ T16
0.1uF J21 U16
C0603
16V, Y5V, +80%/-20%
AB20
AB17
AB15
OVDD
OVDD
OVDD
OVDD
964-4 VSSZ
USBVSS
USBVSS
F25
F26
C AB12
AB10
OVDD USBVSS G23
G24
C
OVDD USBVSS
W5 OVDD USBVSS H25
V5 H26
P5
N5
OVDD
OVDD
OVDD
Power USBVSS
USBVSS
USBVSS
J23
J24
K5 OVDD USBVSS A23
J5 OVDD USBVSS B23
USBVSS C22
USBVSS D22
FSB_VTT A21
FSB_VTT USBVSS
USBVSS B21
AA22 VTT USBVSS E21
SB1.8V AB21 C20
C524 VTT USBVSS
USBVSS D20
*
Bottom F9 A19
Put under 96X solder side F12
IVDD_AUX
IVDD_AUX
USBVSS
USBVSS B19
0.1uF SB3V F15 E19
C0603 IVDD_AUX USBVSS
USBVSS C18
16V, Y5V, +80%/-20% B10 D18
OVDD_AUX USBVSS
B13 OVDD_AUX USBVSS A17
C306 C305 E7 B17
OVDD_AUX USBVSS
VCC1.8V VCC3
SB3V * 10nF
25V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
E12
E15
OVDD_AUX
OVDD_AUX
USBVSS
USBVSS
E17
C16
C520 C516 C512 C0603 C0603 F10 D16
OVDD_AUX USBVSS
*
VSSZ
VSSZ
VSSZ
NC20
NC21
NC22
NC23
NC24
NC25
NC26
NC27
NC28
NC29
16V, Y5V, +80%/-20% L22 U12
VSS
VSS
VSS
NC19 AVSSSATA
SiS964
K26
K25
K24
K23
J26
J25
J22
K22
F16
E16
D9
D11
D14
R23
U23
W23
A A
TECHNOLOGY COPR.
Title
964_4
Document Number Rev
0.6
648M06 B
Date: Wednesday, March 16, 2005 Sheet 16 of 41
8 7 6 5 4 3 2 1
VCC3
*
Dummy
D C179
1
11
VDD_REF D
VDDZ
* 4.7uF C151 C174 C163 C160
13
19
VDD_PCI
VDD_PCI
C0805 0.1uF 0.1uF 0.1uF 0.1uF R106 33 R0603 +/-5%
10V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20%
28
29
VDD48
VDDAGP
CPUCLK0
CPUCLK#0
40
39 R110 33 R0603 +/-5%
CPUCLK0
CPUCLK-0
5
5
Dummy C0603 C0603 C0603 C0603 42 VDDCPU
48 VDDSRC
44 R99 33 R0603 +/-5%
CPUCLK1 CPUCLK1 9
43 R103 33 R0603 +/-5%
CPUCLK#1 CPUCLK-1 9
C159 C172 C166 C152
0.1uF 0.1uF 0.1uF 0.1uF R105 R111 R98 R102
* 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% 49.9 49.9 49.9 49.9
C0603 C0603 C0603 C0603 +/-1% +/-1% +/-1% +/-1%
5 R0603 R0603 R0603 R0603
VSSREF
8 VSSZ
18 VSSPCI
23 VSSPCI
24 31 R118 22 AGPCLK0
AGPCLK0 9
** **
VSS48 AGPCLK0 R124 22 AGPCLK1
32 VSSAGP AGPCLK1 30 AGPCLK1 19
41 VSSCPU
VCC3 45 9 R104 22 ZCLK0
VSSSRC ZCLK0 ZCLK0 11
VCC3 10 R108 22 ZCLK1
VCCP ZCLK1 ZCLK1 13
* R121
1K 14 FS3
**FS_3/PCICLK6
C * R128
1K
+/-5%
R0603 **FS_4/PCICLK7 15
16
FS4 RN5
33_PCI3
7
5
8 33
6
8P4R0603 +/-5% SIOPCLK
PCICLK3
SIOPCLK
PCICLK3
28
25
C
R123 +/-5% Dummy PCICLK0 33_PCI1 PCICLK1
PCICLK1 17 3 4 PCICLK1 24
10K R0603 20 33_PCI2 1 * 2 PCICLK2
PCICLK2 PCICLK2 24
* Dummy Dummy 33 21 33_964 R130 33 96XPCLK
96XPCLK 13
***
VttPWR_GD/PD# PCICLK3 33_PCI_LAN R131 33 PCICLK_LAN
PCICLK4 22 PCICLK_LAN 35
12 FS2 R100 33
C
*FS2/PCICLK5 PCICLK_FWH 31
C
***
Q17 MMBT3904 IREF FS0 R92 22 REFCLK1
B **FS0/REF0 2 REFCLK1 14
MMBT3904 Dummy 3 FS1 R94 33 AUDIO_CLK
AUDIO_CLK 33
E
Dummy **FS1/REF1
E
** *
SCLK
*
USB12M C158 50V, NPO, +/-5% 10V, Y5V, +80%/-20% C0603 46 R101 33
SRCCLK# CLK_SATAJ 15
10pF C0603 C0805
* * R95
*
*
48MHz R0603
X1
X2
AUDIO_CLK C102 10pF
*
ICS952017 VCC3
6
7
By-Pass Capacitors Dummy
Place near to the Clock Outputs C165
10pF X2
*
* *
Dummy
2.7K
BSEL1 R122 FS3
6 BSEL1
C153
10pF
*
*
TECHNOLOGY COPR.
Title
Clock Gen
Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 17 of 41
8 7 6 5 4 3 2 1
CP36 X_COPPER
L55 CBVDD
VCC2.5_MEM
Dummy * FB L0603 80 Ohm
D C402
0.1uF
C425
0.1uF
C408
0.1uF
C429
10uF
D
* 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 10V, Y5V, +80%/-20%
C0603 C0603 C0603 C1206
Dummy
CBVDD 3 VDD
12 VDD DDRCLK[0..5] 21
23
C CP37 L56 VDD
DDRCLK-[0..5] 21
C
X_COPPER FB L0603 80 Ohm
*
Dummy
10 2 DDRCLK0
C423 C420 C421 AVDD CLK0 DDRCLK1 DDRCLK0 21
CLK1 4 DDRCLK1 21
10uF 0.1uF 0.1uF DDRCLK2
* 10V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% CLK2
CLK3
13
17 DDRCLK3 DDRCLK2
DDRCLK3
21
21
C1206 C0603 C0603 24 DDRCLK4
Dummy CLK4 DDRCLK5 DDRCLK4 21
11 AGND CLK5 26 DDRCLK5 21
I2C 18 NC1
SB5V 1
19 R363 0
*
3 FB_OUT
B SMBCLK
SMBDAT 4 20 FB_IN NC3 21
C416
B
5 * 10pF
Header_1X5_2 C0603
50V, NPO, +/-5%
9 NC2
GND
GND
GND
ICS93732
FB_OUT
A A
TECHNOLOGY COPR.
Title
DDR Clock Buffer
Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 18 of 41
8 7 6 5 4 3 2 1
SBA-[0..7]
9 SBA-[0..7]
ST[0..2] VCC5 +12V
NOTE: This AGP slot support
9 ST[0..2]
AC-BE[0..3]
both AGP3.0 display card GCDET- on card GCDET- AVREFCG APERR
9 AC-BE[0..3]
AAD[0..31] SB3V
VDDQ and SiS301 video bridge
GND 0V 0.35V 0V
9 AAD[0..31] card.
ADSTBF[0..1]
9 ADSTBF[0..1] VCC3 OPEN 1.47V 0.75V 1.5V
ADSTBS[0..1] VDDQ VCC3
9 ADSTBS[0..1]
D D
AGP
B1 OVRCNT# +12V A1
B2 +5V TYPEDET# A2
B3 A3 GCDET-
+5V GC_AGP8X_DET GCDET- 9
B4 USB+ USB- A4
B5 GND GND A5
INT-B B6 A6 INT-A
13,24,25 INT-B INTB# INTA# INT-A 11,13,24,25
AGPCLK1 B7 A7 PCIRST-
17 AGPCLK1 CLK RST# PCIRST- 13,24,25,26
AREQ B8 A8 AGNT
9 AREQ REQ# GNT# AGNT 9
B9 VCC3.3 VCC3.3 A9
ST0 B10 A10 ST1
ST2 ST0 ST1
B11 ST2 MB_AGP8X_DET A11
RBF B12 A12 DBI_HI
9 RBF RBF# PIPE# DBI_HI 9
B13 GND GND A13
B14 A14 WBF
9 DBI_LOW RESERVEDB14 WBF# WBF 9
SBA-0 B15 A15 SBA-1
SBA0 SBA1
B16 VCC3.3 VCC3.3 A16
SBA-2 B17 A17 SBA-3 close to AGP SLOT
SBSTBF SBA2 SBA3 SBSTBS
9 SBSTBF B18 SB_STB SB_STB# A18 SBSTBS 9
B19 GND GND A19
SBA-4 B20 A20 SBA-5 VCC3 VCC5 VDDQ
SBA-6 SBA4 SBA5 SBA-7
B21 SBA6 SBA7 A21
B22 DBI_LO DBI_HI A22
B23 GND GND A23
B24
B25
VCC3_AUX RESERVEDA24 A24
A25
* R207
124
C AAD31 B26
VCC3.3
AD31
VCC3.3
AD30 A26 AAD30
* R125
* R185 +/-1% C
AAD29 B27 A27 AAD28 10K 10K R0603
AD29 AD28 R202
B28 VCC3.3 VCC3.3 A28
AAD27 B29 A29 AAD26 54.9 AVREFCG
*
AAD25 AD27 AD26 AAD24
B30 A30
D
AD25 AD24
ADSTBF1
B31
B32
GND GND A31
A32 ADSTBS1 Q30
* R204
124
AAD23 AD_STB1 AD_STB1# AC-BE3 C285
B33 AD23 C/BE3# A33
10nF
AAD21
B34
B35
VDDQ
AD21
VDDQ
AD22
A34
A35 AAD22
G
2N7002 * 25V, Y5V, +80%/-20%
AAD19 B36 A36 AAD20 C0603
S
AD19 AD20
B37 GND GND A37
AAD17 B38 A38 AAD18 GCDET- R127 4.3KB Q34
*
AC-BE2 AD17 AD18 AAD16 MMBT3904
B39 C/BE#2 AD16 A39
B40 A40
E
AIRDY VDDQ VDDQ AFRAME
9 AIRDY B41 IRDY# FRAME# A41 AFRAME 9
VDDQ
D
GND GND APAR
9 ASERR B50 SERR# PAR A50 APAR 9
AC-BE1 B51 A51 AAD15 Q31
C/BE1# AD15
B52 VDDQ VDDQ A52
B AAD14
AAD12
B53
B54
AD14 AD13 A53
A54
AAD13
AAD11
G
2N7002
B
AD12 AD11
B55 A55
S
AAD10 GND GND AAD9
B56 AD10 AD9 A56
AAD8 B57 A57 AC-BE0
AD8 C/BE0#
ADSTBF0
B58
B59
VDDQ VDDQ A58
A59 ADSTBS0
* R200
1K
AAD7 AD_STB0 AD_STB0# AAD6
B60 AD7 AD6 A60
B61 GND GND A61
AAD5 B62 A62 AAD4
AAD3 AD5 AD4 AAD2
B63 AD3 AD2 A63
B64 VDDQ VDDQ A64
AAD1 B65 A65 AAD0
AVREFCG AD1 AD0
B66 VREF_CG VREF_GC A66 AVREFGC 9
1
2
3
- C241
1
2
3
0.1uF
* 16V, Y5V, +80%/-20%
C0603
AGP CONNECTOR DECOUPLING VDDQ
close to 660
EC28
put CAP close to AGP slot each POWER PIN
* 1000uF
6.3V, +/-20%
ce35d80h140
VDDQ VCC3
+12V VCC5 SB3V
648M06 B
Date: Wednesday, March 16, 2005 Sheet 19 of 41
5 4 3 2 1
D D
VGA CONNECTOR
VCC5
F1 VCC5
F1210_1.1A
*
Dummy
11 ROUT
L5 *** L0603 0.047uH Dummy
For EMI.
B B
A A
TECHNOLOGY COPR.
Title
VGA
Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 20 of 41
5 4 3 2 1
8 MD[0..63] 7 6 5 MD[0..63] 4 3 2 1
10,23 MD[0..63]
MA[0..14] MA[0..14]
10,23 MA[0..14] VCC2.5_MEM VCC2.5_MEM
DQM[0..7] DQM[0..7]
10,23 DQM[0..7]
DQS[0..7] DQS[0..7]
10,23 DQS[0..7]
108
180
172
164
156
143
136
128
112
104
108
180
172
164
156
143
136
128
112
104
DIMM1 DIMM2
85
70
46
38
96
77
62
54
30
22
15
85
70
46
38
96
77
62
54
30
22
15
7
7
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
D 120 120
D
NOTE: VDD MD4 VDD MD4
148 VDD DQ0 2 148 VDD DQ0 2
168 4 MD2 168 4 MD2
VDDID IS A TRAP ON THE DIMM VDD DQ1 MD3 VDD DQ1 MD3
184 VDDSPD DQ2 6 184 VDDSPD
Swap DATA for Layout DQ2 6
MODULE TO INDICATE: 8 MD5 8 MD5
MA0 DQ3 MD0 MA0 DQ3 MD0
48 A0 DQ4 94 48 A0 DQ4 94
VDDID REQUIRED POWER MA1 43 95 MD1 MA1 43 95 MD1
OPEN VDD=VDDQ MA2 A1 DQ5 MD7 MA2 A1 DQ5 MD7
41 A2 DQ6 98 41 A2 DQ6 98
GND VDD!=VDDQ MA3 130 99 MD6 MA3 130 99 MD6
MA4 A3 DQ7 MD8 MA4 A3 DQ7 MD8
37 A4 DQ8 12 37 A4 DQ8 12
MA5 32 13 MD9 MA5 32 13 MD9
MEMORY MUX TABLE: MA6 A5 DQ9 MD10 MA6 A5 DQ9 MD10
125 A6 DQ10 19 125 A6 DQ10 19
MA7 29 20 MD11 MA7 29 20 MD11
SDR DDR MA8 A7 DQ11 MD12 MA8 A7 DQ11 MD12
122 A8 DQ12 105 122 A8 DQ12 105
CS0 CS0 MA9 27 106 MD13 MA9 27 106 MD13
CS1 CS1 MA10 A9 DQ13 MD14 MA10 A9 DQ13 MD14
141 A10 DQ14 109 141 A10 DQ14 109
CS2 CS2 MA13 118 110 MD15 MA13 118 110 MD15
CS3 CS3 MA14 A11 DQ15 MD16 MA14 A11 DQ15 MD16
115 A12 DQ16 23 115 A12 DQ16 23
CS4 CS4 103 24 MD17 103 24 MD17
CS5 CS5 NC9 DQ17 MD18 NC9 DQ17 MD18
DQ18 28 DQ18 28
CSB0 DQS0 MA11 59 31 MD19 MA11 59 31 MD19
CSB1 DQS1 MA12 BA0 DQ19 MD20 MA12 BA0 DQ19 MD20
52 BA1 DQ20 114 52 BA1 DQ20 114
CSB2 DQS2 113 117 MD21 113 117 MD21
CSB3 DQS3 BA2 DQ21 MD22 BA2 DQ21 MD22
DQ22 121 DQ22 121
CSB4 DQS4 DQM0 97 123 MD23 DQM0 97 123 MD23
CSB5 DQS5 DQM1 DM0 DQ23 MD24 DQM1 DM0 DQ23 MD24
107 DM1 DQ24 33 107 DM1 DQ24 33
CSB6 DQS6 DQM2 119 35 MD25 DQM2 119 35 MD25
C CSB7 DQS7 DQM3 129
DM2
DM3
DQ25
DQ26 39 MD26 DQM3 129
DM2
DM3
DQ25
DQ26 39 MD26 C
DQM4 149 40 MD27 DQM4 149 40 MD27
DQM5 DM4 DQ27 MD28 DQM5 DM4 DQ27 MD28
159 DM5 DQ28 126 159 DM5 DQ28 126
DQM6 169 127 MD29 DQM6 169 127 MD29
DQM7 DM6 DQ29 MD30 DQM7 DM6 DQ29 MD30
177 DM7 DQ30 131 177 DM7 DQ30 131
140 133 MD31 140 133 MD31
DM8 DQ31 MD32 DM8 DQ31 MD32
DQ32 53 DQ32 53
DQS0 5 55 MD33 DQS0 5 55 MD33
DQS1 DQS0 DQ33 MD34 DQS1 DQS0 DQ33 MD34
14 DQS1 DQ34 57 14 DQS1 DQ34 57
DQS2 25 60 MD35 DQS2 25 60 MD35
DQS3 DQS2 DQ35 MD36 DQS3 DQS2 DQ35 MD36
36 DQS3 DQ36 146 36 DQS3 DQ36 146
DQS4 56 147 MD37 DQS4 56 147 MD37
DQS5 DQS4 DQ37 MD38 DQS5 DQS4 DQ37 MD38
67 DQS5 DQ38 150 67 DQS5 DQ38 150
DQS6 78 151 MD39 DQS6 78 151 MD39
DQS7 DQS6 DQ39 MD40 DQS7 DQS6 DQ39 MD40
86 DQS7 DQ40 61 86 DQS7 DQ40 61
47 64 MD41 47 64 MD41
DQS8 DQ41 MD42 DQS8 DQ41 MD42
DQ42 68 DQ42 68
44 69 MD43 44 69 MD43
CB0 DQ43 MD44 CB0 DQ43 MD44
45 CB1 DQ44 153 45 CB1 DQ44 153
49 155 MD45 49 155 MD45
CB2 DQ45 MD46 CB2 DQ45 MD46
51 CB3 DQ46 161 51 CB3 DQ46 161
134 162 MD47 134 162 MD47
CB4 DQ47 MD48 CB4 DQ47 MD48
135 CB5 DQ48 72 135 CB5 DQ48 72
142 73 MD49 142 73 MD49
CB6 DQ49 MD50 CB6 DQ49 MD50
144 CB7 DQ50 79 144 CB7 DQ50 79
80 MD51 80 MD51
DQ51 MD52 DQ51 MD52
9 NC1 DQ52 165 9 NC1 DQ52 165
B 10
101
NC5(RESET#) DQ53 166
170
MD53
MD54
10
101
NC5(RESET#) DQ53 166
170
MD53
MD54
B
NC2 DQ54 MD55 NC2 DQ54 MD55
102 NC3 DQ55 171 102 NC3 DQ55 171
173 83 MD56 173 83 MD56
NC4 DQ56 MD57 NC4 DQ56 MD57
167 A13 DQ57 84 167 A13 DQ57 84
87 MD58 87 MD58
/RSRAS- DQ58 MD63 /RSRAS- DQ58 MD63
10,23 /RSRAS- 154 RAS# DQ59 88 154 RAS# DQ59 88
/RSCAS- 65 174 MD60 /RSCAS- 65 174 MD60
10,23 /RSCAS- /RSWE- CAS# DQ60 MD61 /RSWE- CAS# DQ60 MD61
10,23 /RSWE- 63 WE# DQ61 175 63 WE# DQ61 175
178 MD62 178 MD62
CS-0 DQ62 MD59 CS-2 DQ62 MD59
157 S0# DQ63 179 157 S0# DQ63 179
CS-1 158 CS-3 158
S1# DDRVREF S1# DDRVREF
71 NC6(S2#) VREF 1 71 NC6(S2#) VREF 1 DDRVREF 22
163 NC7(S3#) 163 NC7(S3#)
VDDID 82 VDDID 82
CKE0 21 90 CKE2 21 90
CKE1 CKE0 WP SMBCLK CKE3 CKE0 WP SMBCLK
111 CKE1 SCL 92 111 CKE1 SCL 92 SMBCLK 14,17,18,35
91 SMBDAT 91 SMBDAT
DDRCLK0 SDA DDRCLK5 SDA SMBDAT 14,17,18,35
137 CK0 137 CK0
DDRCLK3 16 addr = 181 DDRCLK4 16 addr = 181 R330 8.2K R0603 +/-1%
CK1 SA0 CK1 SA0 VCC2.5_MEM
DDRCLK2 76 182 DDRCLK1 76 182
DDRCLK-0 CK2 1010000b SA1 DDRCLK-5 CK2 1010001b SA1
138 CK0# SA2 183 138 CK0# SA2 183
DDRCLK-3 17 DDRCLK-4 17
DDRCLK-2 CK1# DDRCLK-1 CK1#
75 CK2# 75 CK2#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CS-[0..3]
A 10,23 CS-[0..3] DDR_DIMM DDR_DIMM A
176
160
152
145
139
132
124
116
100
93
89
81
74
66
58
50
42
34
26
18
11
3
176
160
152
145
139
132
124
116
100
93
89
81
74
66
58
50
42
34
26
18
11
3
CKE[0..3]
10 CKE[0..3]
18 DDRCLK[0..5]
TECHNOLOGY COPR.
Title
18 DDRCLK-[0..5]
DIMM1, 2
Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 21 of 41
8 7 6 5 4 3 2 1
VCC2.5_MEM
B B
VCC2.5_MEM
A A
TECHNOLOGY COPR.
Title
Decouple
Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 22 of 41
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SSTL-2 Termination Resistors
MD[0..63]
MD[0..63] 10,21
DQM[0..7]
DQM[0..7] 10,21 SDR DDR
DQS[0..7] Rs Rs Rtt
DQS[0..7] 10,21 MD/DQM(/DQS) LV-CMOS 0/10/- SSTL-2 10 33
MA[0..14] MA/Control LV-CMOS 10 SSTL-2 0 33
MA[0..14] 10,21 CS LV-CMOS 0 SSTL-2 0 47
CS-[0..3] CKE OD 3.3V OD 2.5V
CS-[0..3] 10,21
D D
Termination change 56ohm DDR_VTT
RN44 RN37
MD2
MD1
2
4
* 13 MD34
DQS4
2
4
* 13
MD0 6 5 MD37 6 5
MD4 8 7 MD33 8 7
RN24 RN38
MD7
MD3
2
4
* 1 47
3
MD39
MA11
47 2
4
* 13
DQS0 6 5 MD38 6 5
DQM0 8 7 DQM4 8 7
RN25 RN39
MD9
MD8
47 2
4
* 13 MD40
2
4
* 13 47 DECOUPLING CAPACITOR FOR SSTL-2 END TERMIANTION VTT ISLAND
0603 Package placed within 200mils of VTT Termination R-packs
MD5 6 5 MD44 6 5
MD6 8 7 MD35 8 7 DDR_VTT
RN26 RN30
DQM1
MD13
2
4
* 1
3
47 MD49
MD48
47 2
4
* 1
3 C385 C388 C384 C401 C394
DQS1 MD47 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
MD12
6
8
5
7 MD43
6
8
5
7
* 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20%
C RN15 C0603 C0603 C0603 C0603 C0603 C
MD11
MD10
47 2
4
* 13 47
MD15 6 5
MD14 8 7
RN18 RN31 C396 C399 C400 C387
MA7
MD22
2
4
* 13 47 DQM6 2
4
* 13 * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
MD18 6 5 MD53 6 5 C0603 C0603 C0603 C0603
MA9 8 7 MD52 8 7
RN16 RN32
MD17
MD16
47 2
4
* 13 MD55
MD50
47 2
4
* 13 DDR_VTT
MA14 6 5 MD54 6 5
MD20 8 7 DQS6 8 7
RN21 RN34 C538 C539 C540 C541 C542
MA4
DQM3
2
4
* 13 47 MD62
DQS7
2
4
* 13 47
* 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
DQS3 6 5 DQM7 6 5 C0603 C0603 C0603 C0603 C0603
MD25 8 7 MD57 8 7
RN23 RN33
MA0
MA1
47 2
4
* 13 MD61
MD56
47 2
4
* 13
MA2 6 5 MD60 6 5
MD31 8 7 MD51 8 7
RN22 RN35
B
MD27
MD30
2
4
* 13 47
MD63
2
4
* 13 47
B
MD26 6 5 MD59 6 5
MA3 8 7 MD58 8 7
DDR_VTT
47 47
MA12 6 5 DQS5 6 5
MA10 8 7 DQM5 8 7
RN20 RN27
MD29
MD28
2 * 13 47
10,21 /RSCAS-
/RSCAS-
CS-0
2 * 13 47 C395
0.1uF
C397
0.1uF
C398
0.1uF
C393
0.1uF
MA6
4
6 5 MD41
4
6 5
* 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20%
MD24 8 7 MD45 8 7 C0603 C0603 C0603 C0603
RN19
MA5
MD23
47 2
4
* 13 47
2
RN28
* 13
MD19 6 5 CS-3 4
MA8 8 7 CS-2 6 5
RN17 CS-1 8 7
DQM2
MA13
2
4
* 13 47
56
DQS2 6 5
MD21 8 7
A A
47
/RSRAS- R334 47
* *
10,21 /RSRAS-
TECHNOLOGY COPR.
/RSWE- R335 47
10,21 /RSWE- Title
Termination
Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 23 of 41
8 7 6 5 4 3 2 1
PCI-1 PCI-2
C/BE-[0..3] IDSEL = AD19 IDSEL = AD20
13,25,35 C/BE-[0..3] AD[0..31] PCI Slot 1 & 2
13,25,35 AD[0..31] MASTER = PREQ0 MASTER = PREQ1
INTB# INTC#
13,19,25,26 PCIRST- VCC5 VCC5 VCC5 VCC5
D D
-12V +12V -12V +12V
VCC3 VCC3 VCC3
VCC3
X1
X2
+5V12 +5V13 +5V12 +5V13
X1
X2
X1
X2
VCC5 VCC5 VCC3
RN8 4.7K RN7 2.7K
STOP-
PLOCK- 2 *
1
FRAME-
IRDY- 2 *
1
PREQ-0 R115 8.2K R0603 +/-5% Dummy
648M06 B
Date: Wednesday, March 16, 2005 Sheet 24 of 41
8 7 6 5 4 3 2 1
C/BE-[0..3] PCI-3
13,24,35 C/BE-[0..3] AD[0..31]
13,24,35 AD[0..31] IDSEL = AD21
MASTER = PREQ2
VCC5 INTD# VCC5
D D
-12V +12V
VCC3 VCC3
PCI3 PCI_SLOT
B1 A1 TRST-
-12V TRST# TRST 24
TCK B2 A2
24 TCK TCK +12V TMS
B3 GND1 TMS A3 TMS 24
B4 A4 TDI
TDO TDI TDI 24
B5 +5V1 +5V2 A5
B6 A6 INT-D
+5V3 INTA# INT-D 13,24,35
INT-A B7 A7 INT-B
11,13,19,24 INT-A INTB# INTC# INT-B 13,19,24
INT-C B8 A8
13,24 INT-C INTD# +5V4
B9 PRSNT1# RSV1 A9
B10 A10 SB3V
RSV2 +5V5
B11 PRSNT2# RSV3 A11
B12 GND2 GND3 A12
B13 GND4 GND5 A13
B14 RSV4 SB3V A14
B15 A15 PCIRST-
PCICLK3 GND6 RESET# PCIRST- 13,19,24,26
17 PCICLK3 B16 CLK +5V6 A16
B17 A17 PGNT-2
GND7 GNT# PGNT-2 13
PREQ-2 B18 A18
13 PREQ-2 REQ# GND8 PME-
B19 +5V7 PCI_PME# A19 PME- 14,19,24,28,35
AD31 B20 A20 AD30
AD29 AD(31) AD(30)
B21 A21
C B22
AD(29)
GND9
+3.3V1
AD(28) A22 AD28 C
AD27 B23 A23 AD26
AD25 AD(27) AD(26)
B24 AD(25) GND10 A24
B25 A25 AD24
C/BE-3 +3.3V2 AD(24) R134 100 R0603 +/-5% AD21
B26 C/BE#(3) IDSEL A26
AD23 B27 A27 VCC5_DUAL
AD(23) +3.3V3 AD22
B28 GND11 AD(22) A28
AD21 B29 A29 AD20
AD19 AD(21) AD(20) PME-
B30 AD(19) GND12 A30
B31 A31 AD18
AD17 +3.3V4 AD(18) AD16
B32 A32
D
C/BE-2 AD(17) AD(16) WOL
B33 C/BE#(2) +3.3V5 A33
B34 A34 FRAME- Q15 1 4
GND13 FRAME# FRAME- 13,24,35
IRDY- B35 A35 2
13,24,35 IRDY- IRDY# GND14 TRDY-
B36 +3.3V6 TRDY# A36 TRDY- 13,24,35 G 3
DEVSEL- B37 A37 2N7002
13,24,35 DEVSEL- DEVSEL# GND15 STOP- Dummy Header_1X3 (JWOL)
B38 A38 STOP- 13,24,35
S
PLOCK- GND16 STOP# R114 Dummy
13,24 PLOCK- B39 LOCK# +3.3V7 A39
PERR- B40 A40 SDONE3 10K
24,35 PERR- PERR# SDONE SBO-3 +/-5%
B41 +3.3V8 SBO# A41
SERR- B42 A42 R0603
13,24,35 SERR- SERR# GND17 PAR Dummy
B43 +3.3V9 PAR A43 PAR 13,24,35
C/BE-1 B44 A44 AD15
AD14 C/BE#(1) AD(15)
B45 AD(14) +3.3V10 A45
B46 A46 AD13
AD12 GND18 AD(13) AD11
B47 AD(12) AD(11) A47
AD10 B48 A48 VCC5_DUAL
AD(10) GND19
B B49
A50
GND20 AD(9) A49
B50
AD9 B
A50 B50
A51 A51 B51 B51 14,30 RINGJ
AD8 B52 A52 C/BE-0
AD7 AD(8) C/BE#(0)
B53 A53
D
AD(7) +3.3V11 AD6 WOM
B54 +3.3V12 AD(6) A54
AD5 B55 A55 AD4 1 4
AD3 AD(5) AD(4) R420
B56 AD(3) GND21 A56 2
B57 A57 AD2 Q74 G 1K 3
AD1 GND22 AD(2) AD0 2N7002 +/-5%
B58 AD(1) AD(0) A58
B59 A59 Dummy R0603 Header_1X3 (JWOL)
S
PACK64-3 +5V8 +5V9 PREQ64-3 Dummy Dummy
B60 ACK64# REQ64# A60
B61 A61 R421 WOM
+5V10 +5V11 10K
B62 A62
X1
X2
Dummy
A VCC5 VCC3 A
R120
RN10
PACK64-3
PREQ64-3
*1 2
PREQ-2
TECHNOLOGY COPR.
SDONE3 3 4
SBO-3 5 6 8.2K Title
7 8 R0603
2.7K +/-5%
PCI 3
+/-5% Dummy Document Number Rev
8P4R0603
Dummy 648M06 B
Date: Wednesday, March 16, 2005 Sheet 25 of 41
8 7 6 5 4 3 2 1
R369
IDERST-
33
IDEDA[0..15] R0603
13 IDEDA[0..15] +/-5%
R404 IDE1
1 2
IDEDA7 IDEDA7 3 4 IDEDA8
D IDEDA6
IDEDA5
5
7
6
8
IDEDA9
IDEDA10
D
5.6K IDEDA4 IDEDA11
9 10
R0603 IDEDA3 11 12 IDEDA12
+/-5% IDEDA2 13 14 IDEDA13
IDEDA1 15 16 IDEDA14
IDEDA0 17 18 IDEDA15
19 X
13 IDEREQA 21 22
13 IDEIOW-A 23 24
13 IDEIOR-A 25 26
13 ICHRDYA 27 28
13 IDACK-A 29 30
13 IDEIRQA 31 32
IDESAA1 33 34 CBLIDA
CBLIDA 13
IDESAA0 35 36 IDESAA2
IDESAA2 13
IDECS-A0 37 38 IDECS-A1
IDECS-A1 13
39 40
Header_2X20_20 (IDE)
13 IDESAA1
13 IDESAA0
13 IDECS-A0 Q64
1 HDD_PLED
C 15,40 HDDLED
HDDLED 3 C
2 HDD_SLED
BAT54A
VCC3 VCC5
IDEDB[0..15]
R405 R375 13 IDEDB[0..15]
4.7K 4.7K
+/-5% +/-5%
R374 R0603 R0603
R367
0 Dummy
+/-1% IDERST-
R0603
C
Dummy
33 R376
B Q67
MMBT3904 R0603 IDEDB7
C
R368
Dummy +/-5%
E
B Q72
13,19,24,25 PCIRST- MMBT3904 5.6K
IDE2
Dummy R0603 1 2
E
Header_2X20_20 (IDE)
13 IDESAB1
13 IDESAB0
13 IDECS-B0
HDD_SLED
A A
TECHNOLOGY COPR.
Title
IDE
Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 26 of 41
8 7 6 5 4 3 2 1
MDI2+
MDI3+
MDI0+
MDI1+
MDI0-
MDI1-
MDI2-
MDI3-
1Gbit Green = on , Yellow = off
R8 R9 R10 R11 100Mbit Green = off , Yellow = on
R4 R5 R6 R7 49.9 49.9 49.9 49.9 10Mbit Green = off , Yellow = off
49.9 49.9 49.9 49.9 +/-1% +/-1% +/-1% +/-1%
+/-1% +/-1% +/-1% +/-1% R0603 R0603 R0603 R0603
R0603 R0603 R0603 R0603 Dummy Dummy Dummy Dummy G-bit = JFM31U1A-01UBW
C1 C2 C4 C5 CN1
0.1uF 0.1uF 0.1uF 0.1uF
D * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% D
C0603 C0603 C0603 C0603 27
Dummy Dummy SB3V R40 330 R0603 +/-5% 20 28
GRN_LED
35 ACT_LEDJ 19 29
USB-2
USB-1
30
VCC5_DUAL
TCT 9 1 R_USBPOWER
MDI0+ 10 5 C117
35 MDI0+
*
MDI0- 0.1uF
35 MDI0- 11
*
RJ45-MJ2
MDI1+ 12 2 UV2- 16V, Y5V, +80%/-20%
35 MDI1+ UV2- 15
F2 MDI1- 13 6 UV3- C0603
35 MDI1- UV3- 15
F1813_2.6A MDI2+ 14
35 MDI2+
MDI2- 15 3 UV2+
35 MDI2- UV2+ 15
MDI3+ 16 7 UV3+
35 MDI3+ UV3+ 15
R_USBPOWER MDI3- 17
R_USBPOWER 29 35 MDI3-
18 4
C59 R37 0 R0603 +/-5% Dummy
11
10
8
USB 0.1uF
*
YLW_LED
*
16V, Y5V, +80%/-20% C118 0.1uF C0603 16V, Y5V, +80%/-20%
C0603 Dummy 22 23
8 SB3V 330 R38 R0603 +/-5% LINK_P 21 24
25
7 R39 0 R0603 +/-5% Dummy 26
UV1+ 15 35 LINK_1000J
R418 0 R0603 +/-5%
35 LINK_100J
6 UV1- 15
TOP
USBX2_RJ45 10/100
USB4X2_RJ45P10_LED
Mbit LAN
5
C C
VCC3 2D5V_LAN
4
Only for RTC8110S
BOTTOM
3 UV0+ 15
R32 R33
2 0 0 F_USBPOWER F_USBPOWER
UV0- 15
+/-5% +/-5%
1 R0603 R0603
Dummy Dummy
TCT EC31 C267
USBX2 C109
* 1000uF
6.3V, +/-20% * 0.1uF
16V, Y5V, +80%/-20%
12
F_USBPOWER
F_USBPOWER
B F3
C333
0.1uF C301
B
VCC5_DUAL
* F_USBPOWER * 16V, Y5V, +80%/-20%
FUSB4 * 0.1uF
C0603 F_USBPOWER 16V, Y5V, +80%/-20%
FUSB3
FUSB1 Dummy F_USBPOWER 10 9 C0603
F1813_2.6A UV5- Dummy
F_USBPOWER 10 9 1 2 8 X FUSB2
UV7- 8 X 3 4 UV5+ 6 5 UV4+ 1 2
UV7- 15
UV7+ 6 5 UV6+ 5 6 X 3 UV4- 3 4
UV7+ 15 UV5- 15
X 3 UV6- 7 8 OC4567J 2 1 F_USBPOWER 5 6 UV5+ 15
R227 0 OC4567J 2 1 F_USBPOWER X 10 OC4567J R294 100K OC4567- 7 8
Dummy X 10 OC4567J
Header_2X5_9 Header_2X5_4_7
Dummy Header_2X5_4_7
consumer Dummy Header_2X5_9
Dummy commercial consumer
commercial UV6- 15
UV6+ 15 UV4- 15
UV4+ 15
10K 10K
F_USBPOWER R291 R_USBPOWER R36
OC4567- 15 OC0123- 15
*
* R206
560K
C290
0.1uF EC5
* R41
560K
C119
0.1uF
+/-5% * 16V, Y5V, +80%/-20% * 1000uF +/-5% * 16V, Y5V, +80%/-20%
R0603 C0603 6.3V, +/-20% R0603 C0603
CE35D80H200
A A
TECHNOLOGY COPR.
Title
USB & LAN PORT
Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 27 of 41
5 4 3 2 1
SB5V
VCC5
C433
10uF
* 10V, Y5V, +80%/-20% C419 C444 C404
C1206 0.1uF 0.1uF 0.1uF
R412
VCC5 * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20%
BAT VBAT C0603 C0603 C0603
C446
D 22 * 0.1uF
16V, Y5V, +80%/-20%
D
R0603 C0603
+/-5% PRPD[0..7]
76
77
35
99
PRPD[0..7] 30
4
U18
VCC0
VCC1
VCC2
VBAT
VCCH
118 116 PRPD7
30 DCDJ1 DCD1# PD7 PRPD6
30 RIJ1 119 RI1# PD6 115
120 114 PRPD5
30 CTSJ1 DTRJ1 CTS1# PD5 PRPD4
30 DTRJ1 121 DTR1#/JP1 PD4 113
RTSJ1 122 112 PRPD3
30 RTSJ1 RTS1#/JP2 PD3 PRPD2
30 DSRJ1 123 DSR1# PD2 111
TD1 124 110 PRPD1
30 TD1 SOUT1/JP3 PD1 PRPD0 POWER ON TRAPS
30 RD1 125 SIN1 PD0 109
22 VCC5
7 98 VIN0 R0603
C 8
FD0/GP10
FD1/GP11
VIN0
VIN1 97 VIN1
VIN0
VIN1
+/-5%
32
32
C
9 96 VIN2
FD2/GP12 VIN2 VIN2 32
10 95 VIN3
FD3/GP13 VIN3 VIN3 32 1.If use LPC ROM, pull down S4 ~ S7
11 94 VIN4 R372 2.2K R0603 +/-5%
FD4/IRQIN0/GP14 VIN4 VIN4 32 and pull down S8 with 2.2Kohm.
12 93 VIN5
FD5/IRQIN1/GP15 VIN5 VIN5 32
13 92 TD2
FD6/IRQIN2/GP16 VIN6 VIN7 2.If use Legacy 2MB flash rom, pull high
14 FD7/IRQIN3/GP17 VIN7/TMPIN3 91 VIN7 32 S4 ~ S7 and pull down S8 with 2.2Kohm. R381 2.2K R0603 +/-5% Dummy
16 90 SIOVREF
FA0/VID_I0/GP20 VREF SIOVREF 32 3.If use Legacy 4MB flash rom, pull high
17 FA1/VID_I1/GP21
18 S4 ~ S7 and pull high S8 with 2.2Kohm.
FA2/VID_I2/GP22
19 FA3/VID_I3/GP23
20 ITE8705 POWER ON TRAP
FA4/VID_I4/GP24
21 FA5/VID_O0/GP25 TMPIN1 89 TMPIN1 32
22 88 S8
TMPIN3 32
23
24
25
FA6/VID_O1/GP26
FA7/VID_O2/GP27
FA8/VID_O3/GP30
FA9/VID_O4/GP31
ITE8705 TMPIN2
TMPIN3/COPEN# 87 INTRUDERJ 40 1-2 : 4M FLASH ROM ENABLE
(PIN 75 IS FA18)
26 FA10/VID_O5/GP32
27 85 2-3 : PIN 75 IS FAN_TAC3
FA11/VID_I5/GP33 CIRRX/GP67
28 FA12/GP34 CIRTX/GP66 84
29 FA13/GP35
30 FA14/GP36
31 83 IRRX
FA15/GP37 IRRX/MIDI_IN/GP65 IRTX
32 FA16/GP50 IRTX/MIDI_OUT/GP64 82
33 FA17/GP51
B 34
47
FRD#/GP52
81
B
FCS#/SCIO/GP53 PME#/GP63/SCPRES# PME- 14,19,24,25,35
48 VCC5
FWE#/GP54
FAN_CTL3/GP62/SCPFET# 80 FAN_CTL3 32
42 79 C335
17 SIOPCLK PCICLK FAN_CTL2/GP61 FAN_CTL2 32 0.1uF
14,31 LAD[0..3] FAN_CTL1/GP60 78 FAN_CTL1 32 * 16V, Y5V, +80%/-20% IR CONNECTOR
LAD0 38 C0603
LAD1 LAD0 Dummy
39 IrDA
LAD2 LAD1
40 LAD2 FAN_TAC3/FA18/GP57 75 FAN_TAC3 32 1
LAD3 41 74
LAD3 FAN_TAC2/GP56 FAN_TAC2 32
73 IRRX
FAN_TAC1/GP55 FAN_TAC1 32 3
LDRQ- 36
14 LDRQ- SIRQ LDRQ# IRTX 4
14 SIRQ 37 SERIRQ 5
13,31,35 SIORST- 45 LRESET#
46 72 Header_1X5_2
14,31 LFRAME- LFRAME# DSKCHG# DSKCHGJ 31
WPT# 71 WPJ 31
INDEX# 70 INDEXJ 31
CK_48M_SIO 44 69
17 CK_48M_SIO CLKIN TRK0# TRK0J 31
RDATA# 68 RDATAJ 31
WGATE# 66 WGATEJ 31
49 JSACX/GP40/FAN_TAC1S HDSEL# 65 HEADJ 31
50 JSACY/GP41/FAN_TAC2S STEP# 64 STEPJ 31
14 THERM- 51 JSAB1/GP42/FAN_TAC3S DIR# 63 DIRJ 31
40 BEEP_SIO 52 JSAB2/GP43/FAN_CTL3S WDATA# 62 WDJ 31
61
A 53 JSBCX/GP44
DRVB#/SCCLK/FA19
DRVA# 60
DSBJ
DSAJ
31
31
A
54 JSBCY/GP45 MTRB#/SCRST 59 MOBJ 31
GNDD0
GNDD1
GNDD2
GNDD3
43
15
117
67
CHECK
SIO ITE8705
GND_8705 Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 28 of 41
8 7 6 5 4 3 2 1
D D
27 R_USBPOWER
RN2
8
6
4
2
2.2K
8P4R0603 27 R_USBPOWER
7
5
3
1
*
+/-5% C87
0.1uF
* 16V, Y5V, +80%/-20%
C0603
CP47 X_COPPER
KB/MS
KBDAT L10
14 KBDAT DUMMY* FB L0603 80 Ohm
1
2
1
2
13 13
8 7 6 5
. . . .
. . . .
4 2 1 3
6 5
. .
4 3
. .
CP49 X_COPPER 2 1
. .
PMDAT L12
14 PMDAT DUMMY* FB L0603 80 Ohm
7
8
7
8
16 16
CP50 X_COPPER 9
R_USBPOWER 9
10 10
PMCLK L13
14 PMCLK DUMMY* FB L0603 80 Ohm
11
12
11
12 17 17 NOTE:
B PS2-KBMS-2
SIS IS NOT RESPONSIBLE FOR
ANY ERRORS OR OMISSIONS IN
B
C91 C90 C89 C88 THESE SCHEMATICS. THIS IS
180pF 180pF 180pF 180pF AN EXAMPLE ONLY.
* * * *
50V, X7R, +/-10% C0603
A A
TECHNOLOGY COPR.
Title
Keyboard Mouse
Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 29 of 41
A B C D E
D7
VCC5 1 2
FDLL4148
PRINT PORT
*
PRNT25-M
*
28 PRPD[0..7] R336 RN45 RN42 RN41 RN40
1
3
5
7
7
5
3
1
7
5
3
1
7
5
3
1
PRPD3 4.7K 1K 1K 1K 1K PRN1 1
4 PRPD2 +/-5% 8P4R0603 8P4R0603 8P4R0603 8P4R0603 PRN14 14 4
2
4
6
8
8
6
4
2
8
6
4
2
8
6
4
2
PRPD1 R0603 PRN2 2
PRPD0 +/-5% +/-5% +/-5% +/-5% PRN15 15
PRN3 3
PRN16
PRN15 PRN4
16
4
Parallel Port
PRN14 PRN17 17
PRN16 PRN5 5
PRN17 18
28 PSTBJ PRN6 6
28 PAFDJ PRN1
28 PINITJ 19
PRN2 PRN7 7 28
28 PSLINJ PRN3 20 27
PRN4 PRN8 8 26
PRN5 21
PRN6 PRN9 9
PRN7 22
PRPD7 PRN8 PRN10 10
PRPD6 PRN9 23
PRPD5 PRN10 PRN11 11
PRPD4 PRN11 24
PRN12 PRN12 12
PRN13 25
PRN13 13
C71 C73 C75 C77 C69 C79 C85 C82 C83
28 PRERRJ *180pF *180pF *180pF *180pF *180pF *180pF *180pF *180pF *180pF LPT
RINGJ
RINGJ 14,25
C
R137
D3
NRIA 1 2 B Q75
MMBT3904
FDLL4148 R133 C185
E
10K 1K 100pF
D2 R0603 +/-5% * 50V, X7R, +/-10%
VCC5 +12V VCC5 +12V XRIJ2 1 2 +/-5% R0603 C0603
Dummy
FDLL4148
C375 C367 C171 C170
0.1uF 0.1uF 0.1uF 0.1uF
* 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20%
2 C0603 U16 C0603 C0603 U10 C0603 2
20 VCC COM2-1 COM2-2
+12V 1 20 VCC +12V 1
16 5 NRTSA 16 5 RTS2J
28 RTSJ1 DA1 DY1 28 RTSJ2 DA1 DY1
15 6 NDTRA 15 6 DTR2J
28 DTRJ1 DA2 DY2 28 DTRJ2 DA2 DY2
13 8 NSOUTA 13 8 TXD2
28 TD1 DA3 DY3 28 TD2 DA3 DY3
19 2 NRIA 19 2 XRIJ2
28
28
RIJ1
CTSJ1 18
RY1
RY2
RA1
RA2 3 NCTSA
28
28
RIJ2
CTSJ2 18
RY1
RY2
RA1
RA2 3 CTS2J
X X
GREEN
17 4 NDSRA 17 4 DSR2J Header_2X5_10 Header_2X5_10
28 DSRJ1 RY3 RA3 28 DSRJ2 RY3 RA3
14 7 NSINA 14 7 RXD2 C196 C211 C205 C216 Dummy
28 RD1 RY4 RA4 28 RD2 RY4 RA4
NDCDA DCD2J 180pF 180pF 180pF 180pF
28 DCDJ1 12 RY5 RA5 9 28 DCDJ2 12 RY5 RA5 9
* * * * COM2
5 6 DSR2J
10
TECHNOLOGY COPR.
COM1
Title
Serial Port COM/PRT
Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 30 of 41
A B C D E
8 7 6 5 4 3 2 1
VCC3
13,28,35 SIORST- PCICLK_FWH 17
D VCC3 VCC3 D
*1 2
RN48
8.2K
R354 8.2K +/-5%
R371
3 4 +/-5% 4.7K
VCC3 5 6 8P4R0603 R394 +/-5%
7 8 4.7K R0603 FWH_INITJ
32
31
30
4
3
2
1
U19 +/-5%
C
R398 R0603
RST#
VPP
FGPI2(A8)
FGPI3(A9)
CLK(R/C#)
VCC
FGPI4(A10)
4.7K B Q69
+/-5% MMBT3904
C
R0603 29 R353 8.2K +/-5%
E
R393 330 R0603 +/-5% IC_VIL(IC_VIH) R409 4.7K B Q73
14 BIOS_PROTECT 5 FGPI1(A7) GNDa 28 5,14 INITJ
BIOS_WP1-1 BIOS_WP 6 27 +/-5% MMBT3904
FGPI0(A6) VCCa VCC3
1 7 26
E
R402 4.7K R0603 +/-5% WP#(A5) GND
2 VCC3 8
9
TBL#(A4) FWH VCC 25
24 FWH_INITJ
VCC3
Jumper_2P-Blue Header_1X2 R401 330 R0603 +/-5% ID3(A3) INIT#(OE#)
14 BIOS_TBL_PROTECT 10 ID2(A2) FWH4(WE#) 23 LFRAME- 14,28
11 ID1(A1) RFU(RY/BY#) 22
12 21 U19-1 R380 0 +/-5% FWH_INITJ
FWH1(DQ1)
FWH2(DQ2)
FWH3(DQ3)
ID0(A0) RFU(DQ7) Dummy
RFU(DQ4)
RFU(DQ5)
RFU(DQ6)
13 FWH0(DQ0)
LAD0
GND
PLCC
SST49LF004B 32pin
14
15
16
17
18
19
20
Socket
C C
VCC3 VCC3 VCC3 VCC3
LAD1
LAD2
LAD3
C192 C439 C370 C411
LAD[3..0] 14,28
0.1uF 0.1uF 0.1uF 0.1uF
* 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20%
C0603 C0603 C0603 C0603
VCC5
B B
2
4
6
RN50 8
R410
330
+/-5%
* R0603
* 1
3
5
7
330
FDD FDC
1 1 2 2 RWCJ 28
X 4 4
5 5 6 6
7 7 8 8 INDEXJ 28
9 9 10 10 MOAJ 28
11 11 12 12 DSBJ 28
13 13 14 14 DSAJ 28
15 15 16 16 MOBJ 28
17 17 18 18 DIRJ 28
19 19 20 20 STEPJ 28
21 22
A 23
21
23
22
24 24
WDJ
WGATEJ
28
28
A
25 25 26 26 TRK0J 28
27 27 28 28 WPJ 28
29 29 30 30 RDATAJ 28
31 31 32 32 HEADJ 28 TECHNOLOGY COPR.
33 33 34 34 DSKCHGJ 28
Title
Header_2X17_3 (FDD) BIOS/FLOPPY
FDD34MZO3 Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 31 of 41
8 7 6 5 4 3 2 1
VCC5 +12V -12V SB5V
Voltage Monitor
VCC3
VCC5 +12V +12V R357 R364 R370 R379
6.8K 30K 232K 6.8K FSB_VTT
+/-1% +/-5% +/-1% +/-1%
R310 R306 4.7K R0603 R0603 R0603 R0603 VCCP
4.7K +/-5% R0603
+/-5% U4A R339 10K R0603 +/-1%
28 VIN0
4
R0603 LM324 RN13 R344 10K R0603 +/-1%
2
4
6
8
E
28 VIN1
D R51 3 +
1 R307 1KB
0 +/-5%
8P4R0603 28 VIN2
R347 10K R0603 +/-1%
R350 10K R0603 +/-1%
D
28 VIN3
* 13
5
7
2 +/-5% R0603 Dummy R360 10K R0603 +/-1%
28 FAN_CTL1 - 28 VIN4
Q39 +12V R383 56K R0603 +/-1%
BCP69T1 28 VIN5
SIOVREF 28
11
4
C
200K C129 C131 R373 10K
28 VIN7
2
R0603 10uF 0.1uF D5 R0603
+/-5% * 10V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% R301 C407 C415 C424 C427 +/-1%
C1206 C0603 R53 4.7K 0.1uF 0.1uF 0.1uF 0.1uF
Dummy 3.3K CPU_FAN 1N4148W +/-5% R296 * 16V, Y5V, +80%/-20% *
16V, Y5V, +80%/-20% *
16V, Y5V, +80%/-20% *
16V, Y5V, +80%/-20%
+/-5% R0603 27K C0603 C0603 C0603 C0603
4 4
1
R0603 Dummy Dummy Dummy Dummy
3 3 FAN_TAC1 28
*
R58 EC37 C412 C422 C426
2 2
1K
+/-5%
100uF
25V, +/-20%
* 1 1
R0603
+/-5%
R295
10K * 0.1uF
16V, Y5V, +80%/-20%
0.1uF
*
16V, Y5V, +80%/-20%
0.1uF
*
16V, Y5V, +80%/-20%
R0603 CE25D60H110 +/-5% C0603 C0603 C0603
CPU FAN *R0603 Dummy Dummy Dummy
CPU_FAN1
3
R304 0 R0603 +/-5% Dummy 2
1 4
Header_1X3 (FAN3P)
C C
VCC5 +12V +12V
E
5 R426
R75 + Choosing method of measuring temperature by either thermistor or diode
7 R67 1K B 0 +12V
6 +/-5% R0603 +/-5%
28 FAN_CTL2 -
Dummy R0805
11
4
C
200K C141 C138
28 SIOVREF
2
R0603 10uF 0.1uF D1 R64
+/-5% * 10V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% 4.7K
Dummy C1206 C0603 R71 +/-5% C430
Dummy 3.3K 1N4148W R0603 0.1uF R390 R397
+/-5% EC11 SYS_FAN R66 27K * 16V, Y5V, +80%/-20% 10K 30K
1
R0603 100uF * 3 FAN_TAC2 28
C0603 +/-1% +/-1%
*
R70 Dummy25V, +/-20% 2 R63 R0603 R0603
1K CE25D60H110 4 1 R0603 +/-5% 10K
+/-5% +/-5% Fab-B
R0603 Header_1X3 (FAN3P) 1A *R0603
Dummy 28 TMPIN1
SYS FAN 28 TMPIN3
CP31 X_COPPER
THERMDA 5
B C432
0.1uF
* RT1 C440
B
* 16V, Y5V, +80%/-20% T 10K
* 3.3nF
C0603 +/-1% 50V, X7R, +/-10%
R0603 C0603
For CPU
R0603 LM324
E
10 R427
R72 +
8 R340 1K B 0 +12V
9 +/-5% R0603 +/-5%
28 FAN_CTL3 -
Dummy R0805
11
4
C
648M06 B
Date: Wednesday, March 16, 2005 Sheet 32 of 41
8 7 6 5 4 3 2 1
VCC5
SPDIF_OUT
D 1 1 L14
VCC5 D
SPDIF_OUT 3 FB L0805 80 Ohm
3 VCC5A
4 4 2 1
VCC3 Dummy +12V
Header_1X3 Q3 LM78L05
Dummy 1 3
C99 C103 C15 C48 OUT IN
0.1uF 0.1uF 0.1uF 0.1uF EC6 C65
* * * *
GND
16V, Y5V, +80%/-20%
C0603
16V, Y5V, +80%/-20%
C0603
16V, Y5V, +80%/-20%
C0603
16V, Y5V, +80%/-20%
C0603
* 22uF
25V, +/-20% * 1uF
10V, Y5V, +80%/-20%
Add SPDIF_OUT connector. CE20D50H110 C0603
2
12/10/2004 Dummy
25
38
1
9
U1
DVdd1
DVdd2
AVdd1
AVdd2
3 XTL_OUT
XTL-IN 2
17 AUDIO_CLK XTL_IN EC1 100uF CE25D60H110 16V, +/-20%
LINE_OUT_L 34
* **
AC_RESET- 11 35
14 AC_RESET- BIT_CLK RESET# FRONT_OUT_L EC4 100uF CE25D60H110 16V, +/-20%
14 BIT_CLK 6 BIT_CLK FRONT_OUT_R 36 LINE_OUT_R 34
SYNC 10 37
14 SYNC SDATI0 SYNC MONO_OUT
14 SDATI0 8 SDATA_IN NC_33 33
SDATO 5 34 C12 1uF C0603 10V, Y5V, +80%/-20%
14 SDATO SDATA_OUT Front-MIC1 F_MIC 34
39
C SURR-OUT-L
NC_40 40 C
PC_BEEP 12
13
PC_BEEP ALC655 SURR-OUT-R 41
43
PHONE CEN-OUT
14 AUX_L LFE-OUT 44
15 AUX_R JD0(GPIO0) 45 JD0 34
34 JD2 16 JD2 XTLSEL 46
34 JD1 17 JD1
C62 1uF C0603 10V, Y5V, +80%/-20% 18 28 VREFOUT 34
*******
NC_49
34 LINE_IN_R LINE_IN_R
DVss1
DVss2
AVss1
AVss2
SPDIF_OUT
47
48
SPDIFI(EAPD)
C0603 C0603 C1206
Dummy
* R3
SPDIFO C11 C9 C13 5.6K
1uF 1nF 4.7uF Dummy
ALC655 * * *
4
7
26
42
49
10V, Y5V, +80%/-20% 50V, X7R, +/-10% 10V, Y5V, +80%/-20%
C0603 C0603 C1206
B B
BIT_CLK
C98
R35
C100 PC_BEEP 10K SPKR
SPKR 14,40
*
* 22pF
50V, NPO, +/-5% *
1uF
C0603
C0603
C97
100pF
* R30
1K
10V, Y5V, +80%/-20% * 50V, X7R, +/-10%
C56 0.1uF C0603 Dummy C0603
******
TECHNOLOGY COPR.
Title
AC97 CODEC
Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 33 of 41
8 7 6 5 4 3 2 1
JD2 33
C54
R20 3.3uF
LINE IN 10K * 10V, Y5V, +80%/-20%
+/-5% C0805
R0603
AUDIOC
L6 BLM18BB470SN1D
32 1 2 LINE_IN_L 33
D 40
33
34 L2 BLM18BB470SN1D
D
35 1 2 LINE_IN_R 33
JACK_AUDX3 Vertical C32 C46
100pF 100pF R13 R17 VCC5A
* 50V, X7R, +/-10% * 50V, X7R, +/-10% 22K 22K
C0603 C0603 +/-5% +/-5%
R0603 R0603 R79
0
+/-5%
R0603
VCC5A R80 4.7K R0603 +/-5% Dummy
C14 C7
100pF 100pF
* 50V, X7R, +/-10% * 50V, X7R, +/-10%
C0603 C0603
RN1
*
1
3
2
4
5 6
7 8
22K
B +/-5%
8P4R0603
B
LINE OUT
JD1 33
C67
R27 3.3uF CD_IN
10K * 10V, Y5V, +80%/-20% 4 CD_L 33
+/-5% C0805 3 CD_GND 33
R0603 5 2
AUDIOB 1 CD_R 33
25 FRONT_OUT_R JST-CON4-2-Black
38 24
39 23
22 FRONT_OUT_L
JACK_AUDX3 Vertical
C25 C26
100pF 100pF
A * 50V, X7R, +/-10% * 50V, X7R, +/-10% A
C0603 C0603
TECHNOLOGY COPR.
Title
AC97 I/O
Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 34 of 41
5 4 3 2 1
*
C61 27pF LAN_EECS 1 8
C0603 50V, NPO, +/-5% LAN_EESK CS VCC C121
2 SK NC 7
1
LAN_EEDI 0.1uF
D X1 LAN_EEDO
3
4
DI
DO
ORG
GND
6
5
* 16V, Y5V, +80%/-20% D
1D8V_LAN
1D8V_LAN
XTAL-25MHz C0603
AVDDH
2
*
C55 27pF AT93C46-2.7V
C0603 50V, NPO, +/-5% R42 10K 3D3V_LAN
R0603 +/-5% Dummy
36 CTRL_1D8
PCI-3 36 DVDD_A
R12 5.6K 3D3V_LAN
IDSEL = AD24 R0603 +/-1%
AD0
AD1
MASTER = PREQ3
INTD#
2D5V_LAN
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
USE 6/8/6 U2
WIDTH/SPACE/WIDTH FOR
XTAL2
XTAL1
LED0
LED1
LED2
EESK
EEDO
VDD33
EECS
LWAKE
AD0
AD1
GND
RSET
NC
NC
GND
GND
NC
GND
NC
NC
NC
NC
NC
AUX/EEDI
LAN
1 102 AD2
27 MDI0+ TX+ AD2
27 MDI0- 2 TX- GND 101
3 AVDD33 GND 100
4 GND VDD25 99 1D8V_LAN
5 98 AD3
27 MDI1+ RX+ AD3
C 6 97 AD4 C
27 MDI1- RX- AD4
7 96 AD5
AVDD33 AD5 AD6
36 CTRL_2D5 8 CTRL25 AD6 95
9 NC VDD33 94
AVDDH 10 93 AD7
R2 0 +/-5% HSDAC NC AD7
11 NC CBEB0 92 C/BE-0 13,24,25
R0603 Dummy 12 91
36 V_12P AVDD25 GND
13 90 AD8
NC AD8 AD9
14 89
RTL8100C
27 MDI2+ NC AD9
15 88 R43 1K R0603 +/-5% Dummy
27 MDI2- NC NC
16 87 AD10
NC AD10 AD11
17 GND AD11 86
18 85 AD12
27 MDI3+ NC AD12
27 MDI3- 19 NC VDD33 84
20 83 AD13
AVDD33(REG) AD13 AD14
21 GND AD14 82
22 NC GND 81
LAN_DISABLEJ 23 80
ISOLATEB GND AD15
1D8V_LAN 24 NC AD15 79
13,24,25 INT-D 25 INTAB VDD25 78 1D8V_LAN
3D3V_LAN 26 VDD33 CBEB1 77 C/BE-1 13,24,25
13,28,31 SIORST- 27 PCIRSTB PAR 76 PAR 13,24,25
17 PCICLK_LAN 28 PCICLK SERRB 75 SERR- 13,24,25
13 PGNT-3 29 GNTB NC 74 SMBDAT 14,17,18,21
13 PREQ-3 30 REQB NC 73
14,19,24,25,28 PME- 31 PMEB NC 72 SMBCLK 14,17,18,21
1D8V_LAN 32 VDD25 VDD33 71
B AD31 33 70 B
AD31 PERRB PERR- 24,25
AD30 34 69
AD30 STOPB STOP- 13,24,25
35 GND DEVSELB 68 DEVSEL- 13,24,25
AD29 36 67
AD29 TRDYB TRDY- 13,24,25
AD28 37 66
AD28 GND
38 65
FRAMEB
AD[31..0] GND CLKRUNB
CBEB3
CBEB2
VDD33
VDD25
VDD33
13,24,25 AD[31..0]
IRDYB
IDSEL
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
GND
GND
NC
NC
NC
NC
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1D8V_LAN
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
IRDY- 13,24,25
LAN_IDSEL
FRAME- 13,24,25
3D3V_LAN 3D3V_LAN
C/BE-2 13,24,25
13,24,25 C/BE-3
AD24 R29 100 VCC3
R0603 +/-5%
A A
R26
1K
+/-5%
R0603 TECHNOLOGY COPR.
14 LAN_DISABLEJ LAN_DISABLEJ R23 15K Dummy
R0603 +/-5% Title
SB3V, SB1.8V, VCC1.8V, VDDQ
LAN DISABLE(By disabling LAN clock) Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 35 of 41
5 4 3 2 1
5 4 3 2 1
D D
3D3V_LAN
C L1 C
FB L0805 100 Ohm
*
At RTL8100C application, remove R13 and FB4,keep FB10. At
E
2D5V_LAN
EC2 C18
* 22uF
25V, +/-20% * 0.1uF
16V, Y5V, +80%/-20%
C20
0.1uF
C53
0.1uF
C21
0.1uF
C115
0.1uF
CE20D50H110 C0603 * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20%
Dummy Dummy C0603 C0603 C0603 C0603
R1 0
35 CTRL_2D5 DVDD_A 35
4
C
R0603 +/-5%
1D8V_LAN
C125 C122 C101 C94
0.1uF 0.1uF 0.1uF 0.1uF
* 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20% * 16V, Y5V, +80%/-20%
C0603 C0603 C0603 C0603
Dummy Dummy
A A
TECHNOLOGY COPR.
Title
661FX-1 HOST & AGP
Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 36 of 41
5 4 3 2 1
8 7 6 5 4 3 2 1
+12V
5V DUAL CIRCUIT
U14D
4
12 +
14
SB5V +12V VCC5 13 -
D LM324 D
11
R167 R169
4.7K 1K L
+/-5% +/-5%
R0603 R0603 H
S
H G G
C
S5 L L
B Q28 R60
S0 H MMBT3904 4.7K NTD40N03R NTD40N03R
D
+/-5% Q26 Q7
E
R0603
C
R165
VCC5_DUAL VCC3
B Q27
38 PWOK MMBT3904 L EC46 VCC3 VCC5
* 1000uF
E
G
C0603 C0603 VCC2.5_MEM 1 3 10V, Y5V, +80%/-20%
S0 H H Dummy Dummy VIN VCNTL1 C0603 DDR_VTT
VCNTL0 6
SB5V S D 10K
S3 H L
R163 R0603 4 REFEN VOUT 5
+/-1%
GND
10 S3AUXSW- Q29 EC44 EC45 C386
C 4.7K
APM2301A C268 * 1000uF * 1000uF
* 0.1uF C
0.1uF R194 6.3V, +/-20% 6.3V, +/-20% 16V, Y5V, +80%/-20%
*
2
R0603 16V, Y5V, +80%/-20% 10K CE35D80H200 CE35D80H200 C0603
+/-5% C0603 +/-1%
Dummy R0603
CE20D50H110 R0603
G APM2301A
SOT223
100 Q51
R0603 R345
D
+/-5% 200
+/-5%
R0603 VCC2.5_MEM
B B
+12V VCC3
S5 Q51 Q47 power
Q46
VREF_2_6 3 S3AUXSW- H OFF OFF on(from 46)
VCC2_5SB +
1 G S3 Q51 Q47 power
10K 2 -
NTD40N03R S3AUXSW- L on on on(from 51)
S
+/-5% D47
R0603 Copper B120
R179 C377 0.1uF Q53
*
Q47
R424
C
R324
10K
B G R0603 TECHNOLOGY COPR.
Q49 +/-5%
MMBT3904 2N7002 Dummy Title
E
47K
R0603 DDR 2.5V DDRVTT
+/-5% Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 37 of 41
8 7 6 5 4 3 2 1
6
5
6
5
6
5
6
5
6
5
6
5
R0603 12 2 R0603
-12V 3.3V* +/-5%
13 COM COM 3 7 4 7 4 7 4 7 4 7 4 7 4
14 PSON- 14 PS-ON 5V 4 8 3 8 3 8 3 8 3 8 3 8 3
15 COM COM 5 9 2 9 2 9 2 9 2 9 2 9 2
16 6
1
C435 VCC5 COM 5V
17 COM COM 7
0.1uF PWOK
* 16V, Y5V, +80%/-20%
18
19
-5V
5V
PW-OK
5VSB
8
9 SB5V
PWOK 37
C0603 20 10 C437
21
5V 12V +12V
Dummy 0.1uF
ATX_2X10 * 16V, Y5V, +80%/-20%
21
C0603
SB5V VCC3
C C
R391 R384
4.7K 1K
+/-5% +/-5%
R0603 R0603 TO south-bridge
SBPWRGD 14,17
D
Q68
R385
G RSTSW- 40
2N7002
SB5V SB5V
C
R387
S
100
PWOK B Q66 R0603
MMBT3904 +/-5%
C436
E
R395
B B
D
NBPWRGD 11
VRM_PWRGD B Q60
7 VRM_PWRGD MMBT3904 Q65
C441
E
A A
TECHNOLOGY COPR.
Title
POWER Con
Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 38 of 41
5 4 3 2 1
SB3V
SB3V VCC3
+12V R86
1.13K +12V
* R215
806
+/-1%
R0603 *
EC23
1000uF
C181
0.1uF
D
+/-1% 6.3V, +/-20% * 16V, Y5V, +80%/-20%
D
D
R0603 U14B U7A ce35d80h140 C0603
4
LM324 Q44 LM324 Q19 Dummy
5 + 3 +
7 G 1 G
6 NTD40N03R 2 NTD40N03R
- -
S
C289 R315
11
11
1nF 1K C145 R135
* 50V, X7R, +/-10% +/-1% C147
* 1nF 1K
C0603 R0603 R85 0.1uF 50V, X7R, +/-10% +/-1%
Dummy 1K * 25V, Y5V, +80%/-20% C0603 R0603
+/-1% C0603 Dummy
R0603
EC40 C332
+12V * 470uF
6.3V, +/-20% * 0.1uF
16V, Y5V, +80%/-20% *
EC24
470uF
C186
0.1uF
* R191 CE25D63h110 C0603 6.3V, +/-20% * 16V, Y5V, +80%/-20%
698 Dummy +12V CE25D63h110 C0603
+/-1%
D
R0603 U14C
4
LM324 Q42
D
10 U7B
+
4
8 G LM324 Q18
9 NTD40N03R 5
- +
S 7 G
C C287 R285 6 NTD40N03R FSB_VTT C
11
-
1nF 1K
* 5A
S
50V, X7R, +/-10% +/-1% VCC1.8V
11
C0603 R0603 C146 C148 R140
Dummy R84 0.1uF 1nF 1K
1.24K * 25V, Y5V, +80%/-20% * 50V, X7R, +/-10% +/-1%
+/-1% C0603 C0603 R0603 EC25 EC26 C190 C184
* R192
330 EC34 EC36
R0603 Dummy * 1000uF
6.3V, +/-20%
* 1000uF
6.3V, +/-20% * 0.1uF
16V, Y5V, +80%/-20% * 0.1uF
16V, Y5V, +80%/-20%
+/-1%
R0603
* 1000uF
6.3V, +/-20%
* 1000uF
6.3V, +/-20%
ce35d80h140 ce35d80h140 C0603 C0603
ce35d80h140 ce35d80h140
VCC3
+12V
EC27 C202
SB3.3V SB3.3V
* 1000uF
* 0.1uF Vref=1.25V SB3V
D
1
* R193
S
Vin
4 Vout
ADJ
11
4
EC29 Q33
* 1000uF
6.3V, +/-20%
AMS1085 3
VIN VOUT 2
ce35d80h140
ADJ
R180
124
1
+ *
EC33 EC32 C258
* 22uF
25V, +/-20%
Vref * 470uF
6.3V, +/-20% * 0.1uF
16V, Y5V, +80%/-20%
SB1.8V for 964 CE20D50H110 -
R181
CE25D63h110 C0603
Dummy
SB1.8V 205
*
SB3V
Q35
ADJ 1 * R201
105
A 4 2 +/-1% A
4 Vout R0603 C279
10uF
Vin 3
* 10V, Y5V, +80%/-20%
C1206
AME1117
C274
* R196
47
TECHNOLOGY COPR.
0.1uF +/-1% Title
* 16V, Y5V, +80%/-20% R0603 SB3V, SB1.8V, VCC1.8V, VDDQ
C0603
Dummy Document Number Rev
648M06 B
Date: Wednesday, March 16, 2005 Sheet 39 of 41
5 4 3 2 1
8 7 6 5 4 3 2 1
VCC3 S0: Green LED is on;
*
C418 100pF C0603 50V, X7R, +/-10%
F_PANEL F_PANEL-1 Standard
VCC5 R361 330 R0603 +/-5% HD_LED+ 1 2 R365
R366
330 R0603 +/-5%
0 R0603 +/-5% Dummy HDDLED HD_LED_P 1 2 FP PWR/SLP S1: Green LED is blinking;
15,26 HDDLED
HDDLED
*1 2
RN46 0 +/-5% 8P4R0603 PIN3
PIN5
3 4 PIN4
J6
HD_LED_N
RST_SW_N
3
5
4
6
FP PWR/SLP
PWR_SW_P S3: Green LED is off;
PWRBTN- 3 4 PIN6 PIN6 RST_SW_P 7 8 PWR_SW_N
5 6
ACPILED- GREEN- 5
7
6
8
PIN4
PIN7 7 8
PIN7
PIN5
1
2
1
X
Header_2X5_10
RSVD_DNU 9 10 X
S4: Green LED is off;
2
YELLOW-
*1 2
RN47 0 +/-5% 8P4R0603 9 10 SPKJ
PIN3 3 3 S5: Green LED is off.
D GREEN-
3 4
11 12 RSTSW-
Header_1X3
Dummy
D
5 6 C445
VCC5 7 8 0.1uF
Dummy
14
* 16V, Y5V, +80%/-20%
SB3V R400 4.7K R0603 +/-5% Dummy Header_2X7_13 C0603
Dummy Dummy
38 RSTSW-
R392
R399
0 R0603 +/-5%
330 R0603 +/-5% Dummy
PIN7
PWRBTN
Lenovo S0: Green LED is on;
SB3V
C443
0.1uF
HDD LED+
Power LED- yellow
1
3
2
4
HDD LED-
Speaker S1: Green LED is blinking;
FRISW * 16V, Y5V, +80%/-20% Power LED- green 5 6
SB5V
1 4 C0603 Power LED+
Power Switch
7
9
8
10 Speaker
S3: Yellow LED is on;
2 Dummy
R351
3 SB5V
R422
Power Switch
X
11
13
12
14
Speaker
Reset
S4: All LED are off;
10K
+/-5%
Header_1X3 (FAN3P)
R407
VCC5 GREEN-
S5: All LED are off.
R0603 330 330 SB5V
Dummy +/-5% R0603
R0603 +/-5%
SB3V Dummy R389
R352 R408 0 R0603 +/-5% Dummy R406 2.2K R0603 +/-5% Dummy 330
100 +/-5%
C
R382
+/-5% R358 Q71 R0603
R0603 4.7K R403 2.2K R0603 +/-5% Dummy B MMBT3904 SB5V GREEN- Dummy
14 S3_LED
Dummy +/-5% Dummy
R0603 330 YELLOW-
C S3_LED default must be high. C
E
1 Dummy R0603
C
C409 3 +/-5% Q59 Q63
PWRBTN- 14
0.1uF PWRBTN R377 2.2K R0603 +/-5% Dummy B MMBT3904 MMBT3904
* 16V, Y5V, +80%/-20%
2
C417
14 ACPILED
R225 330 R0603 +/-5% VCC3
B
Dummy
C0603 Q62 0.1uF
*
E
Dummy BAT54A 16V, Y5V, +80%/-20%
Dummy C0603 VCC5
Dummy BZ1
+ 1
BUZZER
VCC5 2
-
BAT FAB B R231 Dummy for Beep volume. Buzzer
R0603 RN49
2
R413
1M R341
*1 2
SPKJ
+/-5% 3 4
10K 5 6
R0603 +/-5%
J7 Dummy 7 8
1
2 Q58 150
28 INTRUDERJ +/-5%
1 1
C
14,33 SPKR
R359 8P4R0603 C431
Header_1X2 BAT54C Q57 0.1uF
Dummy
3 1
100
2
R0603
B
MMBT3904 * 16V, Y5V, +80%/-20%
CASE OPEN 2 +/-5% C0603
28 BEEP_SIO
E
B RTC B
NOTE!
1.The RTCVDD is 3V
2.Decoupling capacitor must be close to 96X RTCVDD pin.
3.RTC circuit must strictly follow SiS's recommended design
SiS is not responsible for RTC problems from foreign designs. SB3V
SB3V D4
D10 2 1
1 2
BAT RTCVDD FDLL4148
1N4148W
D9
Q56 R229 1K
2 1 AUXOK 11,14
*
E MMBT3906
C +/-5%
CLS_CMOS_2-3 FDLL4148 R0603
2
D11
CLR_CMOS
Jumper_2P-Blue R337
* R232
100K *
EC35
22uF
3 3
B
R328 10V, Y5V, +80%/-20% 25V, Y5V, +80%/-20% 10V, Y5V, +80%/-20% TECHNOLOGY COPR.
E
648M06 B
Date: Wednesday, March 16, 2005 Sheet 40 of 41
5 4 3 2 1
D D
C C
B B
A A
TECHNOLOGY COPR.
Title
661FX-1 HOST & AGP
Document Number Rev
661M05 B
Date: Wednesday, March 16, 2005 Sheet 41 of 41
5 4 3 2 1