IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO.
7, JULY 2010
Modeling and DBC-PSC-PWM Control of a
Three-Phase Flying-Capacitor Stacked
Multilevel Voltage Source Inverter
Moncef Ben Smida and Faouzi Ben Ammar
AbstractIn this paper, the authors propose a mathematical
model for a new topology called stacked multicell converter
(SMC). Each phase of the SMC n m multilevel inverter is
formed by a stack of m flying-capacitor multilevel inverters, and
each stack or stage is realized by connecting in series n control-
lable commutation cells. An original multicarrier subharmonic
pulsewidth modulation (PWM), called disposition band carrier
and phase-shifted carrier PWM (DBC-PSC-PWM), method is
developed to produce (n m + 1) output voltage levels and
to improve the output voltage harmonic spectrum with a wide
output frequency range. A diagram state machine is then used to
decode the DBC-PSC-PWM modulator and distribute the com-
mutations evenly to each inverter cell in a cyclical fashion. To
carry out, in practice, the SMC n m modulation technique,
the implementation of the modulation control strategy has been
done in a field-programmable gate array circuit XC4010E+ of
XILINX to control a three-phase SMC 3 2 seven-level inverter,
and the experimental results are carried out to confirm the high
performance of this inverter.
Index TermsMulticarrier modulation, multilevel inverter,
stacked multicell converter (SMC) n m, state machine.
I. I NTRODUCTION
T HE multilevel inverters have become an important tech-
nology in a high-power conversion system [1][7]. The
crucial advantage of multilevel inverters is the increasing of the
number of levels and, consequently, the improvement of har-
monic contents in the output voltage and using devices of low
voltage rating with lesser switching frequency. The topologies,
such as single and three-phase neutral-point-clamped inverters
[8][11], cascaded H-bridge inverter [12][15], and flying-
capacitor inverter [16], are well established in medium voltage
drives and power system applications. However, if the num-
ber of cells is increased to more than five cells, the amount
of energy to be stored in the capacitor strongly impacts the
converters sizing and price. Today, in the field of high power,
we consider that this topology is cost effective for up to four
or five cells in series. A new topology called stacked multicell
converter [(SMC) n m] [17], [18] allows the increase of the
number of configurations and, consequently, the voltage levels
Manuscript received March 6, 2009; revised June 29, 2009; accepted
July 23, 2009. Date of publication August 28, 2009; date of current version
June 11, 2010.
The authors are with the Institut National des Sciences Appliques et de
Technologie, Tunis 1080, Tunisia, and also with the Laboratoire des Systmes
lectriques, Ecole Nationale dIngnieurs de Tunis, Tunis 1002, Tunisia
(e-mail: Moncef.bensmida@yahoo.fr; Faouzi.benamar@insat.rnu.tn).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2009.2030764
0278-0046/$26.00 2010 IEEE
2231
with a wide output frequency range compared with the standard
flying-capacitor multicell inverter while decreasing the energy
stored in the converter. The first part of this paper presents a
novel generalized analytical model description of the output
voltage of three-phase stacked multilevel inverter (SMC nm).
In the second part, a new subharmonic pulsewidth mod-
ulation (PWM), called disposition band carrier and phase-
shifted carrier PWM (PSC-PWM) (DBC-PSC-PWM), method
is developed by combining two modulation techniques, namely,
the disposition band carrier PWM method [10] and PSC-PWM
[16] method, to control the three-phase flying-capacitor stacked
multilevel converter. In the third part, a diagram state machine
is used to describe the control of SMC n m by assigning the
switching events to the converter cells in a cyclical manner,
over a complete fundamental load frequency cycle. This state
machine switching event allocation balances the switching tran-
sitions between the inverter cells, will avoid the generation of
narrow unwanted switching pulses, and also preserves the nat-
ural capacitor voltage balancing property of the flying-capacitor
converters [19][24]. The last part of this paper concerns the
experimental realization of a three-phase SMC 3 2 inverter,
and the experimental results are carried out to confirm the high
performance of this topology.
II. n m S TACKED M ULTILEVEL I NVERTER
(SMC n m) M ODELING
A. Topology of SMC n m Inverter
Each phase of three-phase SMC n m inverter is composed
by a stack of m individual flying-capacitor multilevel inverters,
and each stack or stage is realized by connecting in series
n controllable commutation cells. To describe the topology,
the main notations are i [1, 2, 3] for the three phases and
j [1, . . . , n] for the number of cells in each stack. Considering
the case when m is odd and the voltage of the central point O of
the dc link as the reference, we obtain k [1, . . . , m] different
voltage stages: k [1, . . . , m/2] different voltage stages for the
output positive voltages and k [m/2, . . . , m] for the output
negative voltages (with j = 1 as the first cell being the one
connected to the load).
Each phase of the new multilevel voltage source inverter
is composed of (2 n m) turn-on and turnoff controlled
semiconductor devices T (i, j, k) and T  (i, j, k) [insulated-gate
bipolar transistor (IGBT) switch with an antiparallel diode].
The n m commutation cells are connected with a set of
m (n 1) flying-capacitor voltage sources V c(i, j, k), and
2232 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 7, JULY 2010

Fig. 1. Three-phase schema of stacked multilevel inverter SMC 3 1.

each flying capacitor C(i, j, k) is connected between two com- Fig. 2. Three-phase schema of stacked multilevel inverter SMC 3 2.
plementary switches T (i, j, k) and T  (i, j, k). The dc bus E
of SMC (n m + 1)_level inverter is composed by a stack of TABLE I
m individual dc sources connected in series; for a symmetrical S WITCHING S TATES FOR AN SMC 3 1 F OUR -L EVEL
inverter, the magnitude of each source is equal to E/m. F LYING -C APACITOR I NVERTER
The stacked multilevel inverter (SMC n m) can generate
Nlevel voltage outputs by connecting the flying voltage sources
to the ac sources by Nconfig combinations of the switches.
The number of configurations of the switches per phase is
equal to

Nconfig = (m + 1)n . (1)

The number of levels of the output voltage is with


Nlevel = (n m + 1). (2)
m 
L

VT (1, j, 1) = V c(1, j, L) S(1, j, k)




L=1  k=1
For example, in the case of the SMC 3 1 (three cells m 
L
and one stage) inverter (Fig. 1), we have Nconfig = 8 and VT (2, j, 1) = V c(2, j, L) S(2, j, k) (4)

L=1  k=1
Nlevel = 4. The flying voltage capacitor V c(i, j, k) is j E/3.


m 
L
In the case of the SMC 3 2 (three cells and two stages) VT (3, j, 1) =
V c(3, j, L) S(3, j, k)
L=1 k=1
inverter (Fig. 2), we have Nconfig = 27 and Nlevel = 7. The
flying voltage capacitor V c(i, j, k) is j E/6.
with

B. Modeling of Three-Phase SMC n m V (i, j, L) = V c(i, j, L) V c(i, j 1, L). (5)

In order to obtain a clearer understanding of three-phase
(n m + 1)-level inverter, we develop an analytical general If n = 3 and m = 1, (4) shows that this inverter has redundant
expression of the output voltages that can be extended to any states that achieve the same phase leg voltage output (see
number of cells n and any number of stacks m. Table I). The switching phase voltage VAO is constituted by
In that case, we define the voltages VAO (t), VBO (t), and three voltage zones:
VCO (t) as those between each phase and the middle point of 1) zone 1: from E/2 to E/6;
the dc input source. These voltages are described by 2) zone 2: from E/6 to E/6;
3) zone 3: from E/6 to E/2.
n

VAO = E2 VT (1, j, 1) If n = 3 and m = 2, the switching phase voltage VAO is



j=1 constituted by six voltage zones:
n
VBO = E2 VT (2, j, 1) (3) 1) zone 1: from E/2 to E/3;

j=1 2) zone 2: from E/3 to E/6;

n

3) zone 3: from E/6 to zero;
VCO = E2 VT (3, j, 1)
j=1 4) zone 4: from zero to E/6;
BEN SMIDA AND BEN AMMAR: MODELING AND DBC-PSC-PWM CONTROL OF A VOLTAGE SOURCE INVERTER 2233

TABLE II
S WITCHING S TATES FOR AN SMC 3 2 I NVERTER

5) zone 5: from E/6 to E/3;

6) zone 6: from E/3 to E/2.
The switching phase voltage VAO is constituted by six volt-
age zones. These zones are distributed as shown in Table II. The
per-phase voltages (VAN , VBN , and VCN ) are given by

VAN 2/3 1/3 1/3 VAO
VBN = 1/3 2/3 1/3 VCO . (6)
VCN 1/3 1/3 2/3 VBO

According to (3)(5), the per-phase voltages can be writ-

ten as

VAN 2 1 1
1
VBN = 1 2 1
3
VCN 1 1 2
n m 
  
L
j=1 L=1 V c(1, j, L) S(1, j, k)
 k=1

 n  m 
L

V c(2, j, L) S(2, j, k) . (7) Fig. 3. Algorithm flowchart of the SMC n m three-phase multilevel
j=1 L=1 k=1
 inverter.
 n  m 
L
V c(3, j, L) S(3, j, k)
j=1 L=1 k=1
Expressing the phase-to-phase output waveform in per unit
In the case of the balancing of the flying-capacitor voltages, of the dc bus voltage
we have  
N  1 1 1 N  1
E VAN VBN = 1, , . . . , 0, , . . . , 1 .
V c(i, j, k) = . (8) N N N N
nm (10)
In this case, the three-phase voltages can finally be written as
The algorithm flowchart shown in Fig. 3 can be implemented
follows:
in any simulation package and can be used to produce the SMC

VAN n m output voltage for any number of cells n and any number
VBN = 1 E of stacks m.
3 nm
VCN The three per-phase voltages delivered by the inverter (7) are
n m L expressed in (, ) plane by the space vector voltage Vs (11).
   These voltages depend intimately on the flying voltages of the
S(1, j, k)
j=1 L=1 k=1

capacitors
2 1 1 
n  m  L

1 2 1 S(2, j, k) . (9) 2
1 1 2
j=1 L=1 k=1 V s = V s + jV s = (VAN + a.VBN + a2 .VCN ) (11)
3
 n  m  L
S(3, j, k)
j=1 L=1 k=1 with a = exp(j2/3) and 1 + a + a2 = 0.
2234 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 7, JULY 2010

Fig. 4. Representation in the plan (, ) of the SMC 3 2 inverter voltage vector.

With N  = m.n, N  is the number of strictly positive line-to- number of vectors is (n m + 1)3 = 343. The number of
line voltage levels of the inverter nil vectors at the origin is given as (n m + 1) = 7. The
  number of distinct vectors is equal to [(n m + 1)3 (n
Vs 2 1 12 12
= m)3 ] = 127. The six concentric regular hexagons H2, H3, H4,
Vs 3 0 3
23
n m 2 H5, H6, and H7 represent the levels attained by the output
  
LL
voltages. These hexagons are composed by 36, 60, 72, 72, 60,
j=1 L=1 V c(1, j, L) S(1, j, k)
 k=1
and 36 vectors, respectively.

n  m
V c(2, j, L)

S(2, j, k)
. (12)
j=1 L=1 k=1
n m  III. C ONTROL S TRATEGY W ITH M ULTICARRIER
  
L
V c(3, j, L) S(3, j, k) P ULSEWIDTH M ODULATION T ECHNIQUE
j=1 L=1 k=1
The principle of driving the power semiconductors of SMC
In fact, if the flying-capacitor voltages are balanced, the n m inverter is based on a subharmonic DBC-PSC-PWM
relation (12) is replaced by the relation method. If (n m + 1) levels are required, n m carrier
  signals of fixed frequency will be needed. As shown in Fig. 5,
Vs 2.E 1 12 12
= the carriers have the same peak-to-peak amplitude Ac = E/m
Vs 3.n.m 0 3
3
n 2m  LL2 and are disposed in continuous bands around the zero reference.
  
S(1, j, k) For each kth stage, n triangular carrier signals are generated,
j=1 L=1
 k=1
each to be added with the offset band Ak and the phase shifts

n  m 
S(2, j, k) of j between the adjoining cells. The triangular carrier signal
. (13)
j=1 L=1 k=1 is simulated by the following:
n m  L
  
S(3, j, k) Ac Ac
j=1 L=1 k=1 Tri(i, j, k) = Ak + +
2
  
As shown by the space vector representation of the output
arcsin sin 2.f c.t + i.i + j.j + k.k (14)
voltage of the SMC 3 2 (n = 3, m = 2) (Fig. 4), the total 2
BEN SMIDA AND BEN AMMAR: MODELING AND DBC-PSC-PWM CONTROL OF A VOLTAGE SOURCE INVERTER 2235

Fig. 6. PSC-PWM for a four-level inverter.

The global modulation index is defined as

Fig. 5. n m carrier signals for DBC-PSC-PWM SMC n m multilevel V ref (i)

g = , where 1 g +1. (18)
inverter. E/2
with The modulation index for each commutation cell is defined as
E E m 
Vcell (i, j, k)
Ac = Ak = k . (15) (i, j, k) = . (19)
m m 2 (V c(i, j, k) V c(i, j, k 1))
For example, Tri(1, 1, m/2) is the first triangle above the
The voltage applied across the blocking switch of any cell is
zero reference Ak = 0, which is compared with the modulating
imposed by the voltage source V c(i, j, k) and V c(i, j 1, k).
sinusoidal reference of first phase (i = 1).
In the case of the balancing of the flying-capacitor voltages,
i is the angle of displacement existing between the si-
we have
nusoidal reference and the positive triangular carrier signal
Tri(i, 1, m/2). j is the angle of displacement existing between Vcell (i, j, k)
(i, 1, k) = (i, 2, k) = = (i, n, k) = .
two horizontal triangular carrier signals. k is the angle of E/(n.m)
displacement existing between two vertical triangular carrier (20)
signals
At every instant, each carrier is compared with the reference
E m  E m signal V ref (i). Each comparison gives the driving signals
1 Tri(i, j, 1)
m 2 m 2 S(i, j, k) for the power devices T (i, j, k).
E  m  E m  S(i, j, k) = 1 if the modulating sinusoid is greater than the
2 Tri(i, j, 2) 1
m 2 m 2 triangular carrier, and S(i, j, k) = 0 if otherwise.
..
.
 m E A. PWM Strategy to Control the SMC 3 1
0 Tri i, j,
2 m The principle of per-phase SMC 3 1 PSC-PWM modu-
E  m 
Tri i, j, +1 0 lation control strategy is shown in Fig. 6. The resulting car-
m 2 rier/reference intersections achieve pulse generation. To satisfy
.. the natural voltage balancing of the flying capacitors [19],
.
E m m  [20], a regular phase shift j = 2/n and identical duty cycle
Tri(i, j, m) 2 . (16) (i, j, k) are applied to the control signals S(i, j). In this case,
m 2 2
the flying-capacitor voltages VC (i, 1) and VC (i, 2) are equal
For each phase i, the reference signal V ref (i) is a sinusoid to E/3 and 2E/3, respectively. To avoid narrow unwanted
of variable frequency f s and amplitude As pulsewidths, it is necessary to use the cyclical allocations of
  commutations [18]. Therefore, a state machine structure is
2. E
V ref (i) = As . sin 2..f s.t (i 1) developed to describe the different transitions between two suc-
3 2
cessive output voltage levels. The state machine representation
E is used to decode the PSC-PWM modulator and selected the
V ref (i) . (17)
2 different transition inverter cells. The upper switches T (i, 1, 1),
2236
Fig. 7. Transition diagram between levels 1 and 2.
Fig. 8. Complete state machine for an SMC 3 1 inverter.
T (i, 2, 1), and T (i, 3, 1) describe the state of the three converter
cells 1, 2, and 3, respectively. If the switch is ON, the cor-
responding cell is in state 1, and it is in state 0 if the switch
is OFF.
For example, the cyclical allocation of transitions between
levels 1 and 2 is clearly shown in Fig. 7.
To create the complete state structure of the SMC 3
1 inverter, it is necessary to determine the transitions be-
tween the different subdiagrams. Each subdiagram describes
the commutations between two successive levels. As shown
in Fig. 8, the complete state machine transition diagram
contains three subdiagrams and six states per subdiagram.
Each state corresponds to one rising and falling commutation
per cell.
For example, to pass from subdiagram 1 to subdiagram 2 at
state (1, 0, 1) level 3, it has two fallings, the first one from
state (0, 0, 1) level 2 of subdiagram 2 and the second from state
(0, 0, 1) level 2 of subdiagram 1, and in the case of two risings,
to pass from subdiagram 3 to subdiagram 2 at state (1, 0, 0)
level 2, it has two risings, the first from state (1, 0, 1) level 3
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 7, JULY 2010
Fig. 9. DBC-PSC-PWM for an SMC 3 2 inverter.
of subdiagram 3 and the second from state (1, 0, 1) level 3 of
subdiagram 2.
B. PWM Strategy to Control the SMC 3 2
As shown in Fig. 9, to control the SMC 3 2 inverter,
the DBC-PSC-PWM (i = 0, k = 0) uses six high-frequency
carrier waveforms disposed on two bands (three carriers by
band) compared to a common low-frequency reference sine
waveform. The upper stack of the SMC 3 2 creates the
positive output voltage, and the lower stack creates the negative
output voltage.
If a regular phase shift j = 2/n is applied with an iden-
tical duty cycle (i, j, k), the natural balancing of flying-
capacitor voltages is obtained. In this case, VC (i, 1, k) and
VC (i, 2, k) are equal to E/6 and E/3, respectively.
The cyclical allocation of transitions between the three com-
mutation cells of each stack of SMC 3 2 is clearly shown in
Fig. 10.
To create the complete state structure of the SMC 3 2
inverter, it is necessary to determine the different transitions
between two successive levels and those between the different
subdiagrams. As shown in Fig. 10, the complete state ma-
chine transition diagram contains (n m = 6) subdiagrams
and (n m = 6) states per subdiagram, each state corresponds
to one rising and failing transition per cell. The different transi-
tions are selected by the modulator.
IV. E XPERIMENTAL S ETUP
Fig. 11 shows the experimental setup realized to test the
IGBT three-phase SMC 3 2 inverter (three cells and
BEN SMIDA AND BEN AMMAR: MODELING AND DBC-PSC-PWM CONTROL OF A VOLTAGE SOURCE INVERTER
Fig. 10. Complete state machine for an SMC 3 2 inverter.
two stacks) connected to a 10-kVA power (R, L) load. The
dc bus E = 300 V; the modulation frequency is fixed to
10 kHz. The modulation strategy DBC-PSC-PWM is im-
plemented in logic arrays by the development board XS40
based on XILINX XC4010E field-programmable gate array
(FPGA).
The XC4010 has around 10 000 logic gates, 400 configurable
logic blocks, and 160 input/output blocks. Some important
specifications of the XC4010E+ are listed in Table III.
The generated DBC-PSC-PWM binary file .BIT is loaded in
electrically erasable programmable read-only memory circuit
AT17LV256 (256 b) of the XS40 card by using XSloads tool
of XILINX XSTOOLS software and a parallel link between the
XS4010E card and the computer. At every start of the inverter,
the .Bit file is restored in the FPGA.
The control system is connected to a personal computer and
interfaced to the IGBT IXYS IXSN80N60A U1 (600 V/60 A)
via optical links. Three FPGA control cards (one per phase)
guarantee the generation of the control signals. Each card
produces the control signals of the IGBTs of the concerned
phase. With the SMC 3 2 three-phase inverter, six carrier
(3 2) signals of fixed frequency (10 kHz) are generated in
each phase. Every triangular carrier is realized by means of a
recharged counter/discounter (C/D), every C/D counts from 1 to
N 1 and then deducts until zero. To have a phase shift of 120
between the three triangular carriers, the number [2(N 1)]
must be divisible by three. It also includes the generation of
dead time (T m = 5 s).
2237
Figs. 1214 show the experimental output voltage between
phase A and the middle point O of the dc input source with
modulation index M = 30%, 50%, and 95%, respectively. It is
clearly shown in Fig. 15 that the peak to peak of the phase-
to-phase output voltage VAB has 13 voltage output levels.
According to the experimental results shown in Fig. 16(a),
the DBC-PSC-PWM modulator guarantees the natural bal-
ancing property of all 12 flying-capacitor voltages (four per
phase and two per stack) V c(i, 1, 1) = V c(i, 1, 2) = 50 V and
V c(i, 2, 1) = V c(i, 2, 2) = 100 V. Fig. 16(b) shows the VAO
output voltage for various modulation indexes of three-phase
SMC 3 2 inverter. The maximum voltages across the IGBT
switches are limited to E/6 = 50 V. In fact, the SMC n m
has two advantages: The first one is the reduction of semicon-
ductor switch voltage constraints [25], and the second is the
considerable reduction of flying-capacitor total storage energy
[17] and, therefore, the reduction of the size of these capacitors.
V. C ONCLUSION
In this paper, the authors have proposed a general mathe-
matical model for a new topology called SMC dedicated to
high-power voltage applications. It has been shown that the
disposition band carrier modulation and phase-shifted carrier
modulation can be combined to give a new DBC-PSC-PWM. A
diagram state machine is used to decode the DBC-PSC-PWM
modulator and to allocate the transitions evenly to each cell
over a complete fundamental load frequency cycle, avoiding
2238 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 7, JULY 2010
Fig. 11. Three-phase SMC 3 2 panel (three cells and two stages) IGBT
inverter (seven levels).
TABLE III
S PECIFICATION OF THE FPGA XC4010
Fig. 12. VAO output voltage three-phase SMC 3 2 with modulation index
M = 30%.
narrow unwanted pulses. Experimental results have confirmed
that the high performances of the SMC 3 2 inverter are
obtained with an FPGA implemented modulator. The natural
capacitor voltage balancing property of the SMC converter has
been preserved.
Fig. 13. VAO output voltage three-phase SMC 3 2 with modulation index
M = 50%.
Fig. 14. VAO output voltage of three-phase SMC 3 2 with modulation
index M = 95%.
Fig. 15. Phase-to-phase VAB output voltage three-phase SMC 3 2 with
M = 95%.
Fig. 16. (a) Flying-capacitor voltages [V c(i, 1, 1) and V c(i, 2, 1)]. (b) VAO
output voltage for various modulation indexes.
R EFERENCES
[1] J. Selvaraj and N. A. Rahim, Multilevel inverter for grid-connected
PV system employing digital PI controller, IEEE Trans. Ind. Electron.,
vol. 56, no. 1, pp. 149158, Jan. 2009.
[2] S. Lakshminarayanan, G. Mondal, P. N. Tekwani, K. K. Mohapatra,
and K. Gopakumar, Twelve-sided polygonal voltage space vector based
multilevel inverter for an induction motor drive with common-ode voltage
elimination, IEEE Trans. Ind. Electron., vol. 54, no. 5, pp. 27612768,
Oct. 2007.
[3] J. Rodriguez, S. Bernet, B. Wu, J. O. Pontt, and S. Kouro, Multi-
level voltage-source-converter topologies for industrial medium-voltage
drives, IEEE Trans. Ind. Electron., vol. 54, no. 6, pp. 29302945,
Dec. 2007.
[4] T. A. Meynard, H. Foch, P. Thomas, J. Courault, R. Jakob, and
M. Nahrstaedt, Multicell converters: Basic concepts and industry ap-
plications, IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 955964,
Oct. 2002.
BEN SMIDA AND BEN AMMAR: MODELING AND DBC-PSC-PWM CONTROL OF A VOLTAGE SOURCE INVERTER
[5] S. Bernet, D. Krug, S. Fazel, and K. Jalili, Design and comparison of
4, 16 kV neutral point clamped, flying capacitor and series connected
H-bridge multi-level converter, in Conf. Rec. IEEE IAS Annu. Meeting,
2005, vol. 1, pp. 121128.
[6] A. Gopinath, A. S. A. Mohamed, and M. R. Baiju, Fractal based space
vector PWM for multilevel invertersA novel approach, IEEE Trans.
Ind. Electron., vol. 56, no. 4, pp. 12301237, Apr. 2009.
[7] J. I. Leon, S. Vazquez, A. J. Watson, L. G. Franquelo, P. W. Wheeler, and
J. M. Carrasco, Feed-forward space vector modulation for single-phase
multilevel cascaded converters with any dc voltage ratio, IEEE Trans.
Ind. Electron., vol. 56, no. 2, pp. 315325, Feb. 2009.
[8] J. I. Leon, S. Vazquez, R. Portillo, L. G. Franquelo, J. M. Carrasco,
P. W. Wheeler, and A. J. Watson, Three-dimensional feedforward space
vector modulation applied to multilevel diode-clamped converters, IEEE
Trans. Ind. Electron., vol. 56, no. 1, pp. 101109, Jan. 2009.
[9] J. D. Barros and J. F. Silva, Optimal predictive control of three-phase
NPC multilevel converter for power quality applications, IEEE Trans.
Ind. Electron., vol. 55, no. 10, pp. 36703681, Oct. 2008.
[10] B. P. McGrath and D. G. Holmes, Multicarrier PWM strategies for
multilevel inverters, IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 858
867, Aug. 2002.
[11] F. H. Khan, L. M. Tolbert, and W. E. Webb, Hybrid electric vehicle power
management solutions based on isolated and nonisolated configurations
of multilevel modular capacitor-clamped converter, IEEE Trans. Ind.
Electron., vol. 56, no. 8, pp. 30793086, Aug. 2009.
[12] A. Das, K. Sivakumar, R. Ramchand, C. Patel, and K. Gopakumar, A
combination of hexagonal and 12-sided polygonal voltage space vector
PWM control for IM drives using cascaded two-level inverters, IEEE
Trans. Ind. Electron., vol. 56, no. 5, pp. 16571664, May 2009.
[13] P. Lezana, J. Rodriguez, M. A. Perez, and J. Espinoza, Input current
harmonics in a regenerative multicell inverter with single-phase PWM
rectifiers, IEEE Trans. Ind. Electron., vol. 56, no. 2, pp. 408417,
Feb. 2009.
[14] P. Lezana, C. A. Silva, J. Rodriguez, and M. A. Perez, Zero-steady-state-
error input-current controller for regenerative multilevel converters based
on single-phase cells, IEEE Trans. Ind. Electron., vol. 54, no. 2, pp. 733
740, Apr. 2007.
[15] J. I. Leon, S. Vazquez, S. Kouro, L. G. Franquelo, J. M. Carrasco, and
J. Rodriguez, Unidimensional modulation technique for cascaded multi-
level converters, IEEE Trans. Ind. Electron., vol. 56, no. 8, pp. 2981
2986, Aug. 2009.
[16] T. A. Meynard, H. Foch, F. Forest, C. Turpin, F. Richardeau, L. Delmas,
G. Gateau, and E. Lefeuvre, Multicell converters: Derived topologies,
IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 978987, Oct. 2002.
[17] G. Gateau, T. A. Meynard, and H. Foch, Stacked multilevel converter
(SMC): Properties and design, in Conf. Rec. IEEE Power Electronics
Specialists Conf. Meeting, 2001, pp. 15831588.
[18] B. P. McGrath, G. Gateau, T. Meynard, and D. G. Holmes, Optimal
modulation of flying capacitor and stacked multicell converters using a
state machine decoder, in Proc. 36th IEEE Power Electronics Specialists
Conf., 2005, pp. 16711677.
[19] X. Yuan, H. Stemmler, and I. Barbi, Self-balancing of the clamping-
capacitor-voltages in the multi-level capacitor-clamping-inverter under
sub-harmonic PWM modulation, IEEE Trans. Power Electron., vol. 16,
no. 2, pp. 256263, Mar. 2001.
[20] B. P. McGrath and D. G. Holmes, Analytical modelling of voltage bal-
ance dynamics for a flying capacitor multilevel converter, IEEE Trans.
Power Electron., vol. 23, no. 2, pp. 543550, Mar. 2008.
2239
[21] S. Khomfoi and L. M. Tolbert, Fault diagnosis and reconfiguration for
multilevel inverter drive using AI-based techniques, IEEE Trans. Ind.
Electron., vol. 54, no. 6, pp. 29542968, Dec. 2007.
[22] Y. Liu, H. Hong, and A. Q. Huang, Real-time calculation of switching
angles minimizing THD for multilevel inverters with step modulation,
IEEE Trans. Ind. Electron., vol. 56, no. 2, pp. 285293, Feb. 2009.
[23] P. Barriuso, J. Dixon, P. Flores, and L. Moran, Fault-tolerant reconfig-
uration system for asymmetric multilevel converters using bidirectional
power switches, IEEE Trans. Ind. Electron., vol. 56, no. 4, pp. 1300
1306, Apr. 2009.
[24] P. Lezana, R. Aguilera, and D. E. Quevedo, Model predictive control
of an asymmetric flying capacitor converter, IEEE Trans. Ind. Electron.,
vol. 56, no. 6, pp. 18391846, Jun. 2009.
[25] S. Kouro, J. Rebolledo, and J. Rodriguez, Reduced switching-frequency-
modulation algorithm for high-power multilevel inverters, IEEE Trans.
Ind. Electron., vol. 54, no. 5, pp. 28942901, Oct. 2007.
Moncef Ben Smida was born in Tunis, Tunisia, on
April 15, 1966. He received the Engineer degree
in electrical engineering and the D.E.A. and Ph.D.
degrees from the Ecole Nationale dIngnieurs de
Tunis, Tunis, in 1991, 2002, and 2006, respectively.
From 1991 to 2000, he was an Engineer with
the Society Tunisia Engineering and Construction
Industrial, working on the electrical and instrument
conception and development of industrial process.
From 2000 to 2007, he was a Chief Engineer with the
National Case of Security Social. Since 2007, he has
been an Assistant Professor with the Institut National des Sciences Appliques
et de Technologie, Tunis. His research interests include power electronics and
machine modeling, control induction motor drives, pulsewidth modulation,
multilevel inverter, and active filter.
Faouzi Ben Ammar was born in Tunis, Tunisia, on
May 15, 1962. He received the Engineer degree
in electrical engineering from the Ecole Nationale
dIngnieurs de Monastir, Monastir, Tunisia, in
1987 and the D.E.A. and Ph.D. degrees from
the cole Nationale Suprieure dlectronique,
dlectrotechnique, dInformatique, dHydraulique,
et des Tlcommunications, National Polytechnic
Institute of Toulouse, Toulouse, France, in 1989 and
1993, respectively.
From 1993 to 1998, he was an Engineer with
Alstom (Cegelec) Company, Belfort, France, working on the development of
control drive systems. In 1998, he joined the Institut National des Sciences
Appliques et de Technologie, Tunis, as an Assistant Professor, where he has
been a Habilitation la Direction de la Recherche and a Professor of power
electronics since 2004. His research interests include power electronics and
machine modeling, control induction motor drives, pulsewidth modulation,
multilevel inverter, active filter, reliability, and RMAS analysis.