CENTRAL PROCESSING UNIT Dept.

of IT, AITS, Rajampet Computer System Architecture

CENTRAL PROCESSING UNIT

General Register Organization:
The Central Processing Unit (CPU) is called the brain of the computer that performs data
processing operations.

Intermediate data is stored in the register set during the execution of the instructions.
The microoperations required for executing the instructions are performed by the
arithmetic logic unit whereas the control unit takes care of transfer of information among
the registers and guides the ALU.
The control unit services the transfer of information among the registers and instructs the
ALU about which operation is to be performed.
The computer instruction set is meant for providing the specifications for the design of the
CPU.
The design of the CPU largely, involves choosing the hardware for implementing the
machine instructions.
The need for memory locations arises for storing pointers, counters, return address,
temporary results and partial products.
Memory access consumes the most of the time off an operation in a computer. It is more
convenient and more efficient to store these intermediate values in processor registers.
A common bus system is employed to contact registers that are included in the CPU in a
large number.
Communications between registers is not only for direct data transfer but also for
performing various micro-operations.
A bus organization for such CPU register shown in Figure 3.2, is connected to two
multiplexers (MUX) to form two buses A and B.
The selected lines in each multiplexers select one register of the input data for the
particular bus.
The A and B buses form the inputs to a common arithmetic logic unit (ALU). The
operation selected in the ALU determines the arithmetic or logic microoperation that is to
be performed.

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CENTRAL PROCESSING UNIT Dept. of IT, AITS, Rajampet Computer System Architecture

The result of the microoperation is available for output data and also goes into the inputs
of all the registers.
The register that receives the information from the output bus is selected by a decoder.
The decoder activates one of the register load inputs, thus providing a transfer path
between the data in the output bus and the inputs of the selected destination register.

OPERATION OF CONTROL UNIT:

The control unit directs the information flow through ALU by:
- Selecting various Components in the system
- Selecting the Function of ALU
Example: R1 <- R2 + R3
1. MUX A selector (SELA): BUS A R2
2. MUX B selector (SELB): BUS B R3
3. ALU operation selector (OPR): ALU to ADD
4. Decoder destination selector (SELD): R1 Out Bus

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CENTRAL PROCESSING UNIT Dept. of IT, AITS, Rajampet Computer System Architecture

Encoding of register selection fields

Symbolic Designation:

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CENTRAL PROCESSING UNIT Dept. of IT, AITS, Rajampet Computer System Architecture

Stack organization:
A stack is a storage device that stores information in such a manner that the item stored
last is the first item retrieved.
The stack in digital computers is essentially a memory unit with an address register that
can count only.
The register that holds the address for the stack is called a stack pointer (SP) because its
value always points at the top item in the stack.
The physical registers of a stack are always available for reading or writing. It is the content
of the word that is inserted or deleted.
Register stack:

Figure 5.1: Block diagram of a 64-word stack

A stack can be placed in a portion of a large memory or it can be organized as a collection

of a finite number of memory words or registers. Figure shows the organization of a 64-
word register stack.
The stack pointer register SP contains a binary number whose value is equal to the address
of the word that is currently on top of the stack. Three items are placed in the stack: A, B,
and C, in that order. Item C is on top of the stack so that the content of SP is now 3.
To remove the top item, the stack is popped by reading the memory word at address 3
and decrementing the content of SP. Item B is now on top of the stack since SP holds
address 2.
To insert a new item, the stack is pushed by incrementing SP and writing a word in the
next-higher location in the stack.
In a 64-word stack, the stack pointer contains 6 bits because 26 = 64. Since SP has only six
bits, it cannot exceed a number greater than 63 (111111 in binary).

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CENTRAL PROCESSING UNIT Dept. of IT, AITS, Rajampet Computer System Architecture

When 63 are incremented by 1, the result is 0 since 111111 + 1 = 1000000 in binary, but SP can
accommodate only the six least significant bits.
Similarly, when 000000 is decremented by 1, the result is 111111. The one-bit register FULL is
set to 1 when the stack is full, and the one-bit register EMTY is set to 1 when the stack is
empty of items.
DR is the data register that holds the binary data to be written into or read out of the
stack.
PUSH:
If the stack is not full (FULL =0), a new item is inserted with a push operation. The push
operation consists of the following sequences of microoperations:
SP SP + 1 Increment stack pointer
M [SP] DR WRITE ITEM ON TOP OF THE STACK
IF (SP = 0) then (FULL 1) Check is stack is full
EMPTY 0 Mark the stack not empty
The stack pointer is incremented so that it points to the address of next-higher word. A
memory write operation inserts the word from DR into the top of the stack.
SP holds the address of the top of the stack and that M[SP] denotes the memory word
specified by the address presently available in SP.
The first item stored in the stack is at address 1. The last item is stored at address 0. If SP
reaches 0, the stack is full of items, so FULL is set to 1. This condition is reached if the top
item prior to the last push was in location 63 and, after incrementing SP, the last item is
stored in location 0.
Once an item is stored in location 0, there are no more empty registers in the stack. If an
item is written in the stack, obviously the stack cannot be empty, so EMPTY is cleared to 0.
POP:
A new item is deleted from the stack if the stack is not empty (if EMTY = 0). The pop
operation consists of the following sequences of microoperations:
DR M [SP] Read item on top of the stack
SP SP - 1 Decrement stack pointer
IF (SP = 0) then (EMPTY 1) Check if stack is empty
FULL 0 Mark the stack not full
The top item is read from the stack into DR. The stack pointer is then decremented. If its
value reaches zero, the stack is empty, so EMTY is set to 1.
This condition is reached if the item read was in location 1.
Once this item is read out, SP is decremented and reaches the value 0, which is the initial
value of SP. If a pop operation reads the item from location 0 and then SP is
decremented,
SP is changes to 111111, which is equivalent to decimal 63.
In this configuration, the word in address 0 receives the last item in the stack. Note also
that an erroneous operation will result if the stack is pushed when FULL = 1 or popped
when EMPTY = 1.

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CENTRAL PROCESSING UNIT Dept. of IT, AITS, Rajampet Computer System Architecture

Memory Stack:

Figure 5.2: Computer memory with program, data, and stack segments
The implementation of a stack in the CPU is done by assigning a portion of memory to a
stack operation and using a processor register as a stack pointer.
Figure 5.2 shows a portion of computer memory partitioned into three segments: program,
data, and stack.
The program counter PC points at the address of the next instruction in the program which
is used during the fetch phase to read an instruction.
The address registers AR points at an array of data which is used during the execute phase
to read an operand.
The stack pointer SP points at the top of the stack which is used to push or pop items into
or from the stack.
The three registers are connected to a common address bus, and either one can provide an
address for memory.
As shown in Figure 5.2, the initial value of SP is 4001 and the stack grows with decreasing
addresses. Thus the first item stored in the stack is at address 4000, the second item is
stored at address 3999, and the last address that can be used for the stack is 3000.
We assume that the items in the stack communicate with a data register DR.
PUSH
A new item is inserted with the push operation as follows:
SP SP -1
M[SP] DR
The stack pointer is decremented so that it points at the address of the next word.
A memory write operation inserts the word from DR into the top of the stack.
POP
A new item is deleted with a pop operation as follows:
DR M[SP]
SP SP + 1
The top item is read from the stack into DR.
The stack pointer is then incremented to point at the next item in the stack.
The two microoperations needed for either the push or pop are
1. an access to memory through SP, and

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CENTRAL PROCESSING UNIT Dept. of IT, AITS, Rajampet Computer System Architecture

2. updating SP.
Which of the two microoperations is done first and whether SP is updated by incrementing
or decrementing depends on the organization of the stack.
In figure. 5.2 the stack grows by decreasing the memory address. The stack may be
constructed to grow by increasing the memory also.
The advantage of a memory stack is that the CPU can refer to it without having to specify
an address, since the address is always available and automatically updated in the stack
pointer.
Reverse Polish Notation (RPN) with appropriate example.
The postfix RPN notation, referred to as Reverse Polish Notation (RPN), places the
operator after the operands.
The following examples demonstrate the three representations:
A+B Infix notation
+AB Prefix or Polish notation
AB+ Postfix or reverse Polish notation
The reverse Polish notation is in a form suitable for stack manipulation.
The expression A * B + C * D is written in reverse Polish notation as
AB*CD*+
The conversion from infix notation to reverse Polish notation must take into consideration
the operational hierarchy adopted for infix notation.
This hierarchy dictates that we first perform all arithmetic inside inner parentheses, then
inside outer parentheses, and do multiplication and division operations before addition
and subtraction operations.
Evaluation of Arithmetic Expressions
Any arithmetic expression can be expressed in parenthesis-free Polish notation, including
reverse Polish notation
(3 * 4) + (5 * 6) Infix notation
34*56*+ Postfix or reverse Polish notation

Instruction formats:
The most common fields found in instruction formats are:
1. An operation code field that specifies the operation to be performed.
2. An address field that designates a memory address or a processor register.
3. A mode field that specifies the way the operand or the effective address is determined.
The number of address fields in the instruction format depends on the internal organization
of CPU.

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CENTRAL PROCESSING UNIT Dept. of IT, AITS, Rajampet Computer System Architecture

Most computers fall into one of three types of CPU organizations:

1. Single accumulator organization.
2. General register organization.
3. Stack organization.
The three most common CPU organizations:

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CENTRAL PROCESSING UNIT Dept. of IT, AITS, Rajampet Computer System Architecture

ADDRESSING MODES :
Specifies a rule for interpreting or modifying the address field of the instruction (before the
operand is actually referenced)
Variety of addressing modes to give programming flexibility to the user to use the bits in
the address field of the instruction efficiently
TYPES OF ADDRESSING MODES :

Register Indirect Mode

Instruction specifies a register which contains the memory address of the operand
o Saving instruction bits since register addres is shorter than the memory address
o Slower to acquire an operand than both the register addressing or memory
addressing
o EA = [IR(R)] ([x]: Content of x)
Auto-increment or Auto-decrement features:
Same as the Register Indirect, but:
o When the address in the register is used to access memory, the value in the register
is incremented or decremented by 1 (after or before the execution of the instruction)
Direct Address Mode
Instruction specifies the memory address which can be used directly to the physical memory
o Faster than the other memory addressing modes
o Too many bits are needed to specify the address for a large physical memory space
o EA = IR(address), (IR(address): address field of IR)
Indirect Addressing Mode
The address field of an instruction specifies the address of a memory location that contains
the address of the operand
o When the abbreviated address is used, large physical memory can be addressed
with a relatively small number of bits
o Slow to acquire an operand because of an additional memory access
o EA = M[IR(address)]

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CENTRAL PROCESSING UNIT Dept. of IT, AITS, Rajampet Computer System Architecture

Relative Addressing Modes

The Address fields of an instruction specifies the part of the address(abbreviated address)
which can be used along with a designated register to calculate the address of the operand
o PC Relative Addressing Mode(R = PC)
o EA = PC + IR(address)
o Address field of the instruction is short
o Large physical memory can be accessed with a small number of address bits
Indexed Addressing Mode
XR: Index Register:
o EA = XR + IR(address)
Base Register Addressing Mode
BAR: Base Address Register:
o EA = BAR + IR(address)
ADDRESSING MODES EXAMPLES

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CENTRAL PROCESSING UNIT Dept. of IT, AITS, Rajampet Computer System Architecture

Data Transfer and Manipulation Instructions.

Most computer instructions can be classified into three categories:
o Data transfer instructions
o Data manipulation instructions
o Program control instructions
Data Transfer Instructions:
Data transfer instructions move data from one place in the computer to another without
changing the data content.
The most common transfers are between memory and processor registers, between
processor registers and input or output, and between the processor registers themselves.
The load instruction has been used mostly to designate a transfer from memory to a
processor register, usually an accumulator.
The store instruction designates a transfer from a processor register into memory.
The move instruction has been used in computers with multiple CPU registers to designate
a transfer from one register to another. It has also been used for data transfers between
CPU registers and memory or between two memory words.
The exchange instruction swaps information between two registers or a register and a
memory word.
The input and output instructions transfer data among processor registers and input or
output terminals.
The push and pop instructions transfer data between processor registers and a memory
stack.

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CENTRAL PROCESSING UNIT Dept. of IT, AITS, Rajampet Computer System Architecture

Data Manipulation Instructions:

The data manipulation instructions in a typical computer are usually divided into three
basic types:
1. Arithmetic instructions
2. Logical and bit manipulation instructions
3. Shift instructions
Arithmetic instructions:

Logical and bit manipulation instructions:

Shift instructions:

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CENTRAL PROCESSING UNIT Dept. of IT, AITS, Rajampet Computer System Architecture

PROGRAM CONTROL INSTRUCTIONS :

It is sometimes convenient to supplement the ALU circuit in the CPU with a status register
where status bit conditions be stored for further analysis. Status bits are also called
condition-code bits or flag bits.
Figure 5.3 shows the block diagram of an 8-bit ALU with a 4-bit status register. The four
status bits are symbolized by C, S, Z, and V. The bits are set or cleared as a result of an
operation performed in the ALU.

1. Bit C (carry) is set to 1 if the end carry C8 is 1. It is cleared to 0 if the carry is 0.

2. Bit S (sign) is set to 1 if the highest-order bit F7 is 1. It is set to 0 if set to 0 if the bit is 0.
3. Bit Z (zero) is set to 1 if the output of the ALU contains all 0s. it is cleared to 0
otherwise. In other words, Z = 1 if the output is zero and Z = 0 if the output is not zero.
4. Bit V (overflow) is set to 1 if the exclusives-OR of the last two carries is equal to 1, and
cleared to 0 otherwise. This is the condition for an overflow when negative numbers are
in 2s complement. For the 8-bit ALU, V = 1 if the output is greater than + 127 or less
than -128.
The status bits can be checked after an ALU operation to determine certain relationships
that exist between the vales of A and B.
If bit V is set after the addition of two signed numbers, it indicates an overflow condition.
If Z is set after an exclusive-OR operation, it indicates that A = B.
A single bit in A can be checked to determine if it is 0 or 1 by masking all bits except the bit
in question and then checking the Z status bit.

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CENTRAL PROCESSING UNIT Dept. of IT, AITS, Rajampet Computer System Architecture

CMP and TST instructions do not retain their results of operations(- and AND,
respectively). They only set or clear certain Flags.
Conditional Branch Instructions:

SUBROUTINE CALL AND RETURN

Call subroutine
Jump to subroutine
Branch to subroutine
Branch and save return address
Two Most Important Operations are Implied;

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CENTRAL PROCESSING UNIT Dept. of IT, AITS, Rajampet Computer System Architecture

Branch to the beginning of the Subroutine

o Same as the Branch or Conditional Branch
Save the Return Address to get the address of the location in the Calling Program upon
exit from the Subroutine
o Locations for storing Return Address:
Fixed Location in the subroutine(Memory)
Fixed Location in memory
In a processor Register
In a memory stack
most efficient way
PROGRAM INTERRUPT:
The concept of program interrupt is used to handle a variety of problems that arise out of
normal program sequence.
Program interrupt refers to the transfer of program control from a currently running
program to another service program as a result of an external or internal generated
request. Control returns to the original program after the service program is executed.
After a program has been interrupted and the service routine been executed, the CPU
must return to exactly the same state that it was when the interrupt occurred.
Only if this happens will the interrupted program be able to resume exactly as if nothing
had happened.
The state of the CPU at the end of the execute cycle (when the interrupt is recognized) is
determined from:
1. The content of the program counter
2. The content of all processor registers
3. The content of certain status conditions
The interrupt facility allows the running program to proceed until the input or output
device sets its ready flag. Whenever a flag is set to 1, the computer completes the execution
of the instruction in progress and then acknowledges the interrupt.
The result of this action is that the retune address is stared in location 0. The instruction in
location 1 is then performed; this initiates a service routine for the input or output transfer.
The service routine can be stored in location 1.
The service routine must have instructions to perform the following tasks:
1. Save contents of processor registers.
2. Check which flag is set.
3. Service the device whose flag is set.
4. Restore contents of processor registers.
5. Turn the interrupt facility on.
6. Return to the running program.

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CENTRAL PROCESSING UNIT Dept. of IT, AITS, Rajampet Computer System Architecture

Types of interrupts:
There are three major types of interrupts that cause a break in the normal execution of a
program.
They can be classified as:
1. External interrupts
2. Internal interrupts
3. Software interrupts
1) External interrupts:
External interrupts come from input-output (I/0) devices, from a timing device, from a
circuit monitoring the power supply, or from any other external source.
Examples that cause external interrupts are I/0 device requesting transfer of data, I/o
device finished transfer of data, elapsed time of an event, or power failure. Timeout
interrupt may result from a program that is in an endless loop and thus exceeded its time
allocation.
Power failure interrupt may have as its service routine a program that transfers the
complete state of the CPU into a nondestructive memory in the few milliseconds before
power ceases.
External interrupts are asynchronous. External interrupts depend on external conditions
that are independent of the program being executed at the time.
2) Internal interrupts:
Internal interrupts arise from illegal or erroneous use of an instruction or data. Internal
interrupts are also called traps.
Examples of interrupts caused by internal error conditions are register overflow, attempt to
divide by zero, an invalid operation code, stack overflow, and protection violation. These
error conditions usually occur as a result of a premature termination of the instruction
execution.
The service program that processes the internal interrupt determines the corrective
measure to be taken.
Internal interrupts are synchronous with the program. If the program is rerun, the internal
interrupts will occur in the same place each time.

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CENTRAL PROCESSING UNIT Dept. of IT, AITS, Rajampet Computer System Architecture

3) Software interrupts:
A software interrupt is a special call instruction that behaves like an interrupt rather than a
subroutine call. It can be used by the programmer to initiate an interrupt procedure at any desired
point in the program.
The most common use of software interrupt is associated with a supervisor call instruction.
This instruction provides means for switching from a CPU user mode to the supervisor mode.
Certain operations in the computer may be assigned to the supervisor mode only, as for example, a
complex input or output transfer procedure. A program written by a user must run in the user
mode.
When an input or output transfer is required, the supervisor mode is requested by means of a
supervisor call instruction. This instruction causes a software interrupt that stores the old CPU state
and brings in a new PSW that belongs to the supervisor mode.
The calling program must pass information to the operating system in order to specify the
particular task requested.
REDUCED INSTRUCTION SET COMPUTER (RISC):
An important aspect of computer architecture is the design of the instruction set for the processor.
The instruction set chosen for a particular computer determines the way that machine language
programs are constructed.
A computer with a large number of instructions is classified as a complex instruction set computer,
abbreviated CISC.
A computer with fewer instructions is classified as a reduced instruction set computer, abbreviated
RISC.
CISC Characteristics:
1. A large number of instructions-typically from 100 to 250 instructions
2. Some instructions that perform specialized tasks and are used infrequently
3. A large variety of addressing modes-typically from 5 to 20 different modes
4. Variable-length instruction formats
5. Instructions that manipulate operands in memory
RISC Characteristics:
The major characteristics of a RISC processor are:
1. Relatively few instructions
2. Relatively few addressing modes
3. Memory access limited to load and store instructions
4. All operations done within the registers of the CPU
5. Fixed-length, easily decoded instruction format
6. Single-cycle instruction execution
7. Hardwired rather than microprogrammed control
Other characteristics attributed to RISC architecture are:
1. A relatively large number of registers in the processor unit
2. Use of overlapped register windows to speed-up procedure call and return
3. Efficient instruction pipeline
4. Compiler support for efficient translation of high-level language programs into machine
language programs

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