Characterization

of
Current Source Models

Bob Kezer
Intel Corporation
(Jim Wilmore presenting)

10 November 2006

...1
 Outline
Non Linear Delay Model (NLDM)
Quick Overview

Current Source Models (CSM)

Advantages over NLDM
Solutions to Common Problems of
Deep Sub-Micron (DSM) Design

Characterization Techniques for CSM

Picking an Accurate Input Stimulus
Waveform Smoothing
Picking Model Points
Example Model in Liberty / ECSM Format
Correlation

Whats next?

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Non Linear Delay Models - NLDM
Quick Overview
Work Horse Model for 90nm 130nm and Above
Simple Modeling Methodology

Cell Under Test

Input Slew Capacitive Load

SPICE Simulation is Used to Create Table of Calculated Cell Delays

versus Input Slew Rate and Output Load
Apply Simple Input Stimulus as a Series of Increasing Slew Rates

Commonly Used Input Stimulus is Ramp, Custom PWL,

or Active Gate Drive
Load Output with Series of Increasing Capacitance Loads
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 Non Linear Delay Models
Pros
Sufficient Accuracy for Older Technologies
Fast Timing Engine Evaluation
Simple Model Preparation
Wide Support from EDA Vendors

Cons
Required Multiple Libraries for Multiple Voltage Domains

Does Not Take into Account Current Sharing

under High Impedance Loads (Long Nets)

Limited Input Capacitance Modeling

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 Current Source Models - CSM
Advantages Over NLDM

Required for Designs at 90nm and Below

Increased Accuracy over NLDM when compared to SPICE
Greater Modeling Capabilities
Voltage Waveform Versus Time
More Accurate Input Pin Capacitance
Supports Multiple Voltage Domains
No Need to Create Models at Multiple Voltage Points

Handles Current-Sharing Issues

Long Net, High Impedance Loads
Hi-Fanout
Gaining Industry Acceptance
Supported by major EDA Vendors
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 Current Source Models
Solutions to Common DSM Challenges

High Impedance Loads Limit Output Current of Driver

0.16
OUTPUT DRIVE CURRENT

0.15

0.14

0.13
NLDM Simulation Model
0.12
CSM Affects Delay Calculation
0.11
0.1 Output Slew Rate
1 10 100 1000 10000
RESISTANCE Propagates Inaccurate Timing

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 Current Source Models
Solutions to Common DSM Challenges

CMOS Input Pin Capacitance Varies as a Function of the Input Signal

CSM Must Allow Multiple Points

for Accurate Modeling of
Input Pin Capacitance

Input Capacitance
This supports More Accurate
Modeling of Slew

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CSM Characterization Techniques
Choosing an Accurate Input Stimulus

Simple Ramp is an inaccurate

stimulus model
Active Gate Driver is good choice

Difference = 100*(49-35)/49 = 28.6%

Hence, Ramp is 28% more Optimistic

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 CSM Characterization Techniques
Sufficient Simulation Granularity

SPICE Time Step Should Have Large Number of Data Points

SPICE Time Step Setting Approach:

Simulate the fastest component with the minimum capacitance using SPICE.

Choose the library component with fastest slew rate capability in the
library. This is generally an inverter.

Determine the smallest capacitive load out of all the elements in the
library. This will become the minimum capacitance.

Set the time step of the simulator for modeling runs to 1/100 of the fastest
output slew rate.

Note: Depending on the cell design, the rise or fall may be the fastest.

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 CSM Characterization Techniques
Output Waveform Smoothing

Necessary to achieve a Smooth

Derivative Surface
Point Picking for Models Relies on
a Well-Behaved 2nd Order Derivative
of the Waveform
Simulator Anomalies/Settings can
cause Rapid, Erratic Slope Changes
Waveform Smoothing Creates
a Waveform Easy to Work with

Multi-Point Averaging is Sufficient

Algorithm for Waveform Smoothing
V2 = (V0 + V1 + V2 + V3 + V4) / 5

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 CSM Characterization Techniques
Picking Model Points
Several Methods Exist for Picking Points
Here is one that has been Successful
- Piece-Wise Linear Method - 1.20E+00

Specify Your Maximum 1.00E+00

Tolerated Error (vs SPICE)
8.00E-01
Construct a PWL
Approximation of the 6.00E-01

Volts
Waveform that is within
Desired Tolerance 4.00E-01

In General, More Points 2.00E-01

will be Needed where
0.00E+00
2nd Derivative is Larger 1 189 377 565 753 941 1129 1317 1505 1693 1881
-2.00E-01
Time (pS)

>5%
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 Current Source Models
ECSM Liberty File Model Example
16-Point ECSM Model:

fall_transition(tmg_ntin_oload_5x5) {
index_1("30.0010, 250.020, 400.200, 977.800, 2700.00");
index_2("0.00500000, 0.0250000, 0.0500000, 0.100000, 0.450000");
values("36.00, 81.00, 141.00, 265.00, 1141.00",\
Waveform "41.00, 84.00, 143.00, 266.00, 1141.00",\
Number "47.00, 88.00, 145.00, 267.00, 1141.00",\ 5 x 5 table =
0,1,2 24
"71.00, 106.00, 156.00, 272.00, 1142.00",\ 25 elements
"80.00, 114.00, 162.00, 275.00, 1143.00");
ecsm_waveform("0") {
Normalized index_1 : "1.00000, 0.980000, 0.971150, 0.934568, 0.890889, 0.840837,
Voltage 0.725059, 0.594320, 0.248052, 0.185228, 0.130173, 0.0860942, 0.0686745,
Values 0.0425179, 0.0257973, 0.00000" ;
values : "0.00000, 132.411, 191.000, 195.000, 199.000, 203.000, 211.000,
Time 219.000, 239.000, 243.000, 247.000, 251.000, 253.000, 257.000, 261.000,
Values 273.729" ;
}

1:1 Correspondence Between ECSM Waveforms and Slew/Cap indices

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 CSM Characterization Techniques
Correlation

User defines 1-sigma acceptable variation between SPICE and Timing Engine
Simple Correlation - First Pass Confirmation
Basic Driver with Capacitive Load
Timing Engine Simulation
SPICE Simulation
Compare the two results
Advanced Model - More thorough Verification
Designs with several Standard Cells with RC Extraction
Designs include several Extracted Paths with RC Extraction
Timing Engine Simulation
SPICE Simulation including parasitics
Compare the two results

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 Current Source Models
Whats Next?
a.k.a

Its
Its allall
not in in
thethe
Timing
Timing

Library Models arent just for Timing!

Power Constructs are now part of the ECSM Specification

Rail Power Constructs per Cell/Macro Instance
Inductance Construct is Available
Dynamic Power Analysis is Available

Signal Integrity Specifications is in process for ECSM

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