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Code: 9D57102

M. Tech I Semester Regular & Supplementary Examinations, April/May 2013


ANALOG IC DESIGN
(Common to VLSIS, VLSISD, VLSI & VLSID)
Time: 3 hours Max. Marks: 60
Answer any FIVE questions.
All questions carry equal marks.

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1 (a) Draw the structure of a MOS device and explain how it works, with the help of
characteristics.
(b) What are the deficiencies of MOS technology? How they can be overcome?

2 (a) Explain the large signal modeling for single stage BJT amplifier.
(b) Calculate the voltage gain of the circuit shown in fig(1) if 0 & 0
VDD

RD
Vb .

+
m2
Vout

m1

L D
3 (a)
Vin -

O R
fig(1)

Draw the small signal model for the common source stage and derive the equations for

W
small signal and also explain how to maximize the gain.
(b) With neat sketch explain the source follower with current mirror to supply bias current.

4 (a)
(b)

T
Explain about:
(i) Bi-CMOS comparator U
Explain about two stage CMOS operational amplifier.

N
(ii) Fully differential amplifier.

5 (a)
(b)
J
Compare the design aspects of MOS, CMOS and BICMOS sample and hold circuit.
Explain about:
(i) Switched capacitor gain circuit.
(ii) Biquard filters.

6 (a) Explain the correlated double sampling techniques with suitable example.
(b) Explain about folded cascade operational amplifier operation with circuit diagram.

7 (a) Explain the design procedure for successive approximation type DAC.
(b) Explain about:
(i) Quantization noise
(ii) Nyquist rate in D/A & A/D converters.

8 Write short notes on:


(a) Digital decimation filter.
(b) Cyclic flash type ADC.
(c) Continuous time filters.

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