MAHESH BABAN SHINDE

Mobile: +91-9922004635
Email:mahesh.shinde@smartsocs.com

Career Objective:
To be an integral part of a respected and professional organization, where I can exploit myself
in the field of VLSI and to keep myself updated with the cutting edge technologies.

Work Experience:
Currently working with SmartSoC Solutions with 3.1 Years of experience in Asic
Verification.
Previously worked with GDS Bangalore as Verification Engineer for 2.4 Years from
June2014 to November2016.

Professional Summary:

Strong background in Digital Logic Design, Verilog and System Verilog.

Have Knowledge on both IP and SoC verification.
Have Knowledge on Processor Based SoC verification.
Good understanding of Verilog RTL and ASIC design flow.
Hands on Universal Verification Methodology (UVM).
Have Knowledge on PERL scripting.
Have Knowledge on AMBA AHB, AXI and APB protocols.
Have Knowledge on SPI and I2C protocols.
Have good analytical and debugging skills and flexible to learn new technologies.
Have good communication and technical skills to play as team member and to work
independently to meet work objectives.

EDA Tools and Expertise:

HVL HDL : System Verilog, Verilog

Methodology : UVM
On-chip Bus Protocol : AMBA AHB , AXI and APB
EDA Tools : Cadence IUS, VCS, Verdi, modelsim, questasim.
Scripting Language : Perl
Operating Systems : Windows, LINUX, Ubuntu
Programming languages : C

Projects:
4 Project Name : SPI verification at SOC level
HVL System Verilog, C
Methodology UVM
Tools Ncsim
Project Description Verified SPI peripheral SoC level.

Contribution Working at chip level verification and subsystem level verification.

Coded tests in C language and verified Integration checking
Writing functional coverage on packets, fabric headers at subsystem
interface level
Integrated SPI VIP at SoC level and verified.
Integrating subsystem interface monitors into chip level test bench.
Writing perl script which generates end of test checker
Writing perl script to generate interface connections with DUT
Writing perl script to generate regression list from all testcases whose
status is finished,and additional script to know the status of testcases
Running regressions and debug results.

3 Project Name : Verification of DMA at SOC level

Coding Language C
Methodology Processor based verification
Tools Ncsim
Project Description The Purpose of this IP verification at SoC level is to transfer data from one SoC
memory location to other SoC memory location
Contribution Verified at SoC level
Understand specifications DMA Descriptors and Buffer configurations.
Preparing test plan for this IP at SoC level
Developed tests in C and verified using processor BFM and debugging the
failures
Prepared verification report and data throughput of this IP at different
frequencies.
2 Project Name : Verification of Embedded packet generator for Ethernet
switch
HVL System Verilog
Methodology UVM
Tools Synopsys vcs ,Verdi
Project Description The Purpose of this project is to design an Ethernet switch chip which supports
3.2Tb/s. In This, Embedded packet generator is used for internal debugging of chip.
When chip is in debug mode, this block generates and supplies packets to internal
subsystems of the chip instead of traffic coming from input MAC ports.

Contribution Working at chip level verification

Writing test plan and implementing test cases.
Implementing reference model for embedded packet generator.
Implementing scoreboard for embedded packet generator
Feature verification, debugging and regression

1. Project Name : Development of AMBA AHB VIP

HVL System Verilog
Methodology UVM
Tools Cadence IUS, simvision,imc
Project Description The Purpose of this project is to develope AHB VIP which supports AHB2,AHB-LITE
protocols.
Contribution Coded AHB slave monitor
Coded sequences and test cases
Coded assertions and cover groups
Generated functional coverage report by running regression
Worked on AHB local scoreboard development
Writing perl script for vtags like ctags.