EEE40014- HARDWARE AND

SOFTWARE CODESIGN
Reading PS-X controller reading [Challenge]

Muhammad Ali Tehseen

4905180
Introduction:
This lab is designed to help students in becoming familiar with the process of implementing custom
peripherals for a microcontroller system. The Xilinx EDA tools (Vivado and SDK) are used for implementing
a custom IP block for use in a Zync based system that create a flexible interface to the provided PWM-
based controller. Create a flexible interface to the PS2 controllers provided. The details of the interface
are part of the design exercise but should incorporate the following functionality:
Two-way communication with the controller using required signals.
Initialisation of the controller mode.
Polling of the controller button states
Polling of the controller Joystick positions.

Design

IP BLOCK DIAGRAM

THE PLAYSTATION CONTROLLER PINOUTS

LOOKING AT THE PLUG

-------------------------------
PIN 1->| o o o | o o o | o o o |
\_____________________________/

PIN # USAGE
 DATA
COMMAND
N/C (9 Volts unused)
GND
VCC
ATT
CLOCK
N/C
ACK

SIGNALS
1) DATA
It is a signal from the PSX controller and is an 8 bit serial transmission synchronous to the falling edge of
clock (That is both the incoming and outgoing signals change on a high to low transition of clock. All the
reading of signals is done on the leading edge to allow settling time.)

2) COMMAND
Again a signal from PSX to Controller. This signal is the counter part of DATA and again an 8 bit serial
transmission on the falling edge of clock.

3) ATT
ATT is used to get the attention of the controller. This signal will go low for the duration of a
transmission.

4) CLOCK
Used to keep units in sync.

5) ACK
Acknowledge signal from Controller to PSX. This signal should go low for at least one clock period after
each 8 bits are sent and ATT is still held low. If the ACK signal does not go low within about 60 us the PSX
will then start interrogating other devices. This is a bus of sorts i.e. the wires are all tied together (except
select which is seperate for each device). For the CLK, ATT, and CMD pins this does not matter as the PSX
is always the originator. The DATA and ACK pins however can be driven from any one of four devices. To
avoid contentions on these lines they are open collectors and can only be driven low.

All transmissions are eight bit serial LSB first. All timing in the PSX controller bus is synchronous to the
falling edge of the clock. The logic level on the data lines is changed by the transmitting device on the
falling edge of clock. This is then read by the receiving device on the leading edge allowing time for the
signal to settle. After each COMMAND is received by a selected controller, that controller needs to pull
ACK low for at least one clock tick. If a selected controller does not ACK the PSX will assume that there is
no controller present.

When the PSX wants to read information from a controller it pulls that devices ATT line low and issues a
start command (0x01). The Controller Will then reply with its ID (0x41=Digital, 0x23=NegCon,
0x73=Analogue Red LED, 0x53=Analogue Green LED). At the same time as the controller is sending this
ID byte the PSX is transmitting 0x42 to request the data. Following this the COMMAND line goes idle and
the controller transmits 0x5A to say "here comes the data".

After this command initiation process the controller then sends all its data bytes (in the case of a digital
controller there is only two). After the last byte is sent ATT will go high and the controller does not need
to ACK. Different bytes are send for different type of data.

VHDL DESIGN DESCRIPTION:

In our design, we make use of a state machine. At the first state, it initialize the PSX state as 001 and
then resets the counter and the temporary command register. In 001 state it waits for the 8 clocks and
then change the state to 010. If the 8 clocks are not completed then it detects the rising edge of the clock
and increment the clock and on the failing edge it shift the register 1 and load PSX data. We pull down
the ATN signal ATN signal drives by FPGA to indicate that FPGA need to communicate with PSX controller
after that FPGA generate 8 clock pulses every negative edge of the clock, FPGA place each bit of command
reg (slv_reg0) in PSX_COMMAND signal its sampled by PSX controller in positive edge of the clock and it
reads the command after that controller sends pull down the ACK signal low, so that the FPGA recognize
controller successfully read the command in the next transitions, during negative edge of the clock,
controller place each bit of DATA corresponding to the given command

Changes in Outer Module:

Signals

Changes in Inner Module:

Read Process:
Write Process :
Constrains:

Conclusion:
The VHDL listing couldnt give us positive results, we couldnt receive any signals from the controller. The
reason was there was no ACK signal coming from the controller. There might be a problem with the
controller or with the IP. Due to the lack of time, we couldnt complete the task. However, a valuable
knowledge is gain through this exercise and we learnt quite a bit about the PSX controller and the signal
it generates and how they can be interfaced with the different processor.

*NOTE: Please disregard the previous report submitted, as you know I change the coding, so, I made a new report
for the new. Thanks