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Analog Circuits (Formula Notes/Short Notes)

G/si =1.21 3.6 104 .T ev

Energy gap G/Ge =0.785 2.23 104 .T ev
Energy gap depending on temperature

EF = EC - KT ln = Ev + KT ln

No. of electrons n = Nc e(EcEf)/RT (KT in ev)
No. of holes p = Nv e(EfEv )/RT
Mass action law np = n2i = Nc Nv eEG/KT
Drift velocity d = E (for si d 107 cm/sec)
B.I
Hall voltage H = . Hall coefficient R H = 1/ . charge density = qN0 = ne
we
Conductivity = ; = R H .
q q
Max value of electric field @ junction E0 = - Nd . nn0 = - NA . np0 .
si si
Charge storage @ junction Q + = - Q = qA xn0 ND = qA xp0 NA

dp dn

p
Diffusion current densities Jp = - q Dp Jn = - q Dn
dx dx
Drift current Densities = q(p p + nn )E
p , n decrease with increasing doping concentration .
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Dn Dp
= = KT/q 25 mv @ 300 K
n p
Carrier concentration in N-type silicon nn0 = ND ; pn0 = n2i / ND
Carrier concentration in P-type silicon pp0 = NA ; np0 = ni2 / NA

Junction built in voltage V0 = VT ln
ad
2
2s 1 1
Width of Depletion region Wdep = xp + xn =
q NA
+ (V0 + VR )
ND
2
* = 12.93

xn N
= A
gr

xp ND
q.NA ND
Charge stored in depletion region qJ = NA +ND
. A . Wdep
s A s A
Depletion capacitance Cj = ; Cj0 =
Wdep Wdep / VR =0

VR m
Cj = Cj0 /1 +
V0
Cj = 2Cj0 (for forward Bias)
Dp
Forward current I = Ip + In ; Ip = Aq n2i
/ 1
Lp ND
D
In = Aq n2i L Nn / 1
n A
Dp D
Saturation Current Is = Aq n2i L N + L Nn
p D n A
Minority carrier life time p = L2p / Dp ; n = L2n / Dn

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Minority carrier charge storage Qp = p Ip , Q n = p In

Q = Q p + Q n = T I T = mean transist time

Diffusion capacitance Cd = I = .g Cd I.

carrier life time , g = conductance = I /
I02 = 2(T2 T1 )/10 I01
Junction Barrier Voltage Vj = VB = Vr (open condition)
= Vr - V (forward Bias)
= Vr + V (Reverse Bias)
1
Probability of filled states above E f(E) = (EEf )/KT 1+e
Drift velocity of e d 107 cm/sec
d2 V v nq dv nqx
Poisson equation = = =E=
dx2 dx

Transistor :-
IE = IDE + InE

p
IC = ICo IE Active region
IC = IE + ICo (1- eVC /VT )

Common Emitter :-
IC = (1+ ) ICo + IB
I
=
eu

1
Co
ICEO = 1 Collector current when base open
ICBO Collector current when IE = 0 ICBO > ICo .
0 V
VBE,sat or VBC,sat - 2.5 mv / C ; VCE,sat BE,sat = - 0.25 mv /0 C
ad
10
IC ICBo
Large signal Current gain = IB + ICBo
IC
D.C current gain dc = = hFE
IB
(dc = hFE ) when IB > ICBo
I hFE
gr

Small signal current gain = IC = hfe = h

R VCE 1(ICBo + IB ) FE
IC
active
Over drive factor = IC sat = forced IB sat
forced under saturation

Conversion formula :-
CC CE
hic = hie ; hrc = 1 ; hfc = - (1+ hfe ) ; hoc = hoe

CB CE
h hie hoe h hoe
hib = 1+hie ; hib = 1+h - hre ; hfb = 1+hfe ; hob = 1+h
fe fe fe fe

CE parameters in terms of CB can be obtained by interchanging B & E .

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Specifications of An amplifier :-

hf Av .Zi AI.ZL AIs.ZL

AI = Zi = hi + hr AI ZL Avs = = =
1+h0 ZL Zi +Rs Zi +Rs Rs

AI ZL hf hr Av .Rs Avs .Rs

AV = Y0 = ho - AIs = =
Zi hi + Rs Zi +Rs ZL

Choice of Transistor Configuration :-

For intermediate stages CC cant be used as AV < 1
CE can be used as intermediate stage
CC can be used as o/p stage as it has low o/p impedance
CC/CB can be used as i/p stage because of i/p considerations.

Stability & Biasing :- ( Should be as min as possible)

I I IC
For S = I C S = V C S = V

Co VB0, BE IC0, BE,ICo

p
IC = S. ICo + S VBE + S

1+
For fixed bias S = dI =1+ eu
1 B
dIC

1+ 1+
Collector to Base bias S = RC 0 < s < 1+ = RC + RE
1+ 1+
RC +RB RC + RE + RB
ad
1+ Rth
Self bias S = RE 1+ R E > 10 R 2
1+ Re
RE +Rth

Vcc Rth V R
R1 = Vth
; R 2 = V ccVth
cc th
gr

VCC
For thermal stability [ Vcc - 2Ic (R C + R E )] [ 0.07 Ico . S] < 1/ ; VCE <
2

Hybrid pi()- Model :-

g m = |IC | / VT

rb e = hfe / g m
rb b = hie - rb e
rb c = rb e / hre
g ce = hoe - (1+ hfe ) g b c

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3 Configurations are used on BJT, CE, CB & CC

Common Emitter, VI characteristics

IC
= VCE
IB

VBE V
Ri = hie = = re ; rce = r0 = ce
I B I c

p
eu AMPLIFIER COMPARISON

COMPARISON
CB CE CF
ad
BE BC
Ri LOW MED HIGH

SATURATION f/b f/b

AI AI +1
gr

ACTIVE f/b r/b

AV High High <1

CUT OFF r/b r/b

Ro High High low

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For CE :-
g gm
f = 2(Cb +e C =
e c) hfe 2(Ce + Cc )

1 gbe
fT = hfe f ; fH = = C = Ce + Cc (1 + gm RL )
2 rbe C 2C
fT = S.C current gain Bandwidth product
fH = Upper cutoff frequency

For CC :-
1+gm RL gm fT Ce gm + gbe
fH = = =
2CL RL 2CL CL 2(CL + Ce )

For CB:-
1+ hfe
f = 2r = (1 + hfe ) f = (1 + ) f
b e (CC + Ce )

fT = f f > fT > f
1+

p
Ebress moll model :-
IC = - N IE + ICo (1- eV/VT )

IE = - I IC + IEo (1- eV/VT )

eu
I ICo = N IEo
ad
Multistage Amplifiers :-
fL
fH * = fH 21/n 1 ; fL =
21/n 1
0.35 0.35
Rise time t r = =
gr

fH B.W
t r = 1.1 2 2
t r1 + t r2 +

fL = 1.1 fL21 + fL22 +

1 1 1
= 1.1 2 + +
fH f H1 f2H2

Differential Amplifier :-

Zi = hie + (1 + hfe ) 2R e = 2 hfe R e 2R e

0 |IEE | I
gm = = 4VC = g m of BJT/4 0 DC value of
4VT T

h R
CMRR = R fe+he ; R e , Zi , Ad & CMRR
s ie

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AI = (1 + 1 ) (1 + 2 ) ; Av 1 ( < 1)

(1+hfe )2 Re2
Zi = [ if Q1 & Q 2 have same type ] = AI R e2
1+hfe hoc Re2

Rs 2h
Ro = + 1+hie
(1+hfe )2 fe

g m = (1 + 2 ) g m1

Tuned Amplifiers : (Parallel Resonant ckts used ) :

1
f0 = Q Q factor of resonant ckt which is very high
2LC

B.W = f0 /Q

BW
fL = f 0 -
2
BW
fH = f0 +

p
2
For double tuned amplifier 2 tank circuits with same f0 used . f0 = fL fH .
eu
FIELD EFFECT TRANSISTOR, FET is Unipolar Device
ad

Construction n-Channel p-Channel

S=Source, G=Gate, D=Drain

gr

GS Junction in Reverse Bias Always

Vgs Controls Gate Width

VI CHARACTERSTICS

Transfer Characteristics Circuit Forward Characteristics

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Shockley Equation
2
Vgs V
I d = I dss 1 , g m = g m 0 1 gs
V V
p p

MOSFET (Metal Oxide Semiconductor FET, IGFET)

Depletion Type Mosfet Symbols Enhancement Mosfet

Depletion Type MOSFET can work width Vgs > 0 and Vgs < 0

p
Enhancement MOSFET operates with, Vgs > Vt , Vt = Threshold Voltage

NMOSFET formed in p-substrate
eu
If VGS Vt channel will be induced & iD (Drain source )
Vt +ve for NMOS
iD (VGS - Vt ) for small VDS
ad
VDS channel width @ drain reduces .

VDS = VGS - Vt channel width 0 pinch off further increase no effect

For every VGS > Vt there will be VDS,sat

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2 1
iD = K n [ (VGS - Vt ) VDS - VDS ] triode region ( VDS < VGS - Vt )
2

K n = n Cox

1 2
iD = K n [ VDS ] saturation
2
1
rDS = Drain to source resistance in triode region
Kn (VGS Vt )

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PMOS :-

Device operates in similar manner except VGS , VDS, Vt are ve

iD enters @ source terminal & leaves through Drain .

VGS Vt induced channel VDS VGS - Vt Continuous channel

2 1
iD = K p [(VGS Vt )2 - VDS ] K p = p Cox
2

VDS VGS - Vt Pinched off channel .

NMOS Devices can be made smaller & thus operate faster . Require low power supply .
Saturation region Amplifier
For switching operation Cutoff & triode regions are used

NMOS PMOS

VGS Vt VGS Vt induced channel

p
VGS - VDS > Vt VGS - VDS < Vt Continuous channel(Triode region)

VDS VGS - Vt VDS VGS - Vt

eu Pinchoff (Saturation)

Depletion Type MOSFET :- [ channel is physically implanted . i0 flows with VGS = 0 ]

For n-channel VGS +ve enhances channel .

-ve depletes channel
ad
iD - VDS characteristics are same except that Vt is ve for n-channel

Value of Drain current obtained in saturation when VGS = 0 IDSS .

1
K n Vt2 .
gr

IDSS =
2

MOSFET as Amplifier :-

For saturation VD > VGS - Vt

To reduce non linear distortion gs < < 2(VGS - Vt )

id = K n (VGS Vt ) gs g m = K n (VGS Vt )

d
gs
= - gm RD

gm
Unity gain frequency fT = 2(C
gs +Cgd )

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JFET :-
VGS Vp iD = 0 Cut off

Vp VGS 0, VDS VGS - Vp

2

iD = IDSS 2 1
Triode

Vp VGS 0 , VDS VGS - Vp

2
I
iD = IDSS 1 VGS = Vp 1
IDSS
2IDSS 2I I
Saturation
gm = 1 = DSS I
|Vp | |Vp | DSS

Zener Regulators :-

Vi Vz
For satisfactory operation Rs
IZmin + ILmax
Vsmin Vz0 IZmin rz
R Smax = IZmin + ILmax

p
Load regulation = - (rz || R s )

Line Regulation =
rz
Rs +rz
.
eu
For finding min R L take Vs min & Vzk , Izk (knee values (min)) calculate according to that .

Operational Amplifier:- (VCVS)

ad
Fabricated with VLSI by using epitaxial method
High i/p impedance , Low o/p impedance , High gain , Bandwidth , slew rate .
FET is having high i/p impedance compared to op-amp .
Gain Bandwidth product is constant .
A
gr

Closed loop voltage gain ACL = 1 OLA feed back factor

OL

1
V0 = Vi dt LPF acts as integrator ;
RC

R L dvi
V0 = i dt ; V0 = (HPF)
L R dt

1 dvi
For Op-amp integrator V0 = i dt ; Differentiator V0 = -
dt

V0 V0 Vi Vi
Slew rate SR = t
= t
. t
= A. t

slew rate slew rate

Max operating frequency fmax = = .
2 . V0 2 Vi A

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In voltage follower Voltage series feedback

In non inverting mode voltage series feedback

In inverting mode voltage shunt feed back

V0 = - VT ln I
0

V0 = - VBE

= - VT ln I
0

1
Error in differential % error = 100 %
CMRR

p
Power Amplifiers :-
B 2 B21
Fundamental power delivered to load P1 = 21 R L =
eu RL
2
12 22
Total Harmonic power delivered to load PT = 2 + 2
+ . .

2 2
= P1 1 + 2 + 3 +
1 1
= [ 1+ D2 ] P1
ad
B
Where D = +D22 + . . +D2n Dn = Bn
1
D = total harmonic Distortion .

Class A operation :-
gr

o/p IC flows for entire 3600

Q point located @ centre of DC load line i.e., Vce = Vcc / 2 ; = 25 %
Min Distortion , min noise interference , eliminates thermal run way
Lowest power conversion efficiency & introduce power drain
PT = IC VCE - ic Vce if ic = 0, it will consume more power
PT is dissipated in single transistors only (single ended)

Class B:-

IC flows for 1800 ; Q located @ cutoff ; = 78.5% ; eliminates power drain

Higher Distortion , more noise interference , introduce cross over distortion
Double ended . i.e ., 2 transistors . IC = 0 [ transistors are connected in that way ] PT = ic Vce
PT = ic Vce = 0.4 P0 PT power dissipated by 2 transistors .

Class AB operation :-

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IC flows for more than 1800 & less than 3600

Q located in active region but near to cutoff ; = 60%
Distortion & Noise interference less compared to class B but more in compared to class A
Eliminates cross over Distortion

Class C operation :-
IC flows for < 180 ; Q located just below cutoff ; = 87.5%
Very rich in Distortion ; noise interference is high .

Oscillators :-
1 29
For RC-phase shift oscillator f = hfe 4k + 23 + where k = R c /R
2RC 6+4K k

1
f= > 29
2RC6

p
For op-amp RC oscillator f = | Af | 29 R f 29 R1
2RC6

Wein Bridge Oscillator :- eu 1

f = ,
2 R1 R2C1C2
1 1
if R1=R2=R, C1=C2=C , f = ; A= =3
ad
2 RC

Hartley Oscillator :-
1 L
|hfe | L2
gr

f=
2(L1 +L2 )C 1
L
| | L2
1
L
|A| 2
L1

Rf
R1

Colpits Oscillator :-
1 C
f= C C
|hfe | C1
2L 1 2 2
C1 +C2
C
| | C1
2

C
| A | C1
2

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Phase shift oscillator:-
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FET MODEL
1
f = , A = 29 ,
2 6 RC
Minimum RC sections 3

BJT MODEL
1
f = , A = 29 ,
4R
2 RC 6 + C
R
Minimum RC sections 3

Comparisons:
MOSFET JPET
BJT FET
High Ri = 10 108
10
Current controlled Voltage controlled

p
High gain Med gain R0 = 50 k 1m
Bipolar
Temp sensitive
eu
Unipolar
Little effect of T
Depletion
Enhancement Mode
Depletion
Mode
High GBWP Low GBWP
Delicate Rugged
Rectifiers:
ad
gr

Comparisons:
HW FW CT FW BR

VDC Vm 2Vm 2Vm

Vm Vm Vm
Vrms
2 2 2

1.21 0.482 0.482
Ripple factor

40.6% 81% 81%
Rectification efficiency

PIV Vm 2 Vm Vm
Peak Inverse Voltage
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