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Application Note
- HA0075E MCU Reset and Oscillator Circuits Application Note
Features
CPU Features Peripheral Features
Operating Voltage: Flash Program Memory: 1K14 ~ 12K16
fSYS= 8MHz: 2.2V~5.5V RAM Data Memory: 648 ~ 5768
fSYS= 12MHz: 2.7V~5.5V EEPROM Memory: 328~2568
fSYS= 20MHz: 4.5V~5.5V
Watchdog Timer function
Up to 0.2ms instruction cycle with 20MHz system
Up to 50 bidirectional I/O lines
clock at VDD=5V
Software controlled 4-SCOM lines LCD driver with
Power down and wake-up functions to reduce power
consumption 1/2 bias
Multiple pin-shared external interrupts
Five oscillators:
External Crystal - HXT Multiple Timer Module for time measure, input
External 32.768kHz Crystal - LXT capture, compare match output, PWM output or
External RC - ERC single pulse output function
Internal RC - HIRC Serial Interfaces Module - SIM for SPI or I2C
Internal 32kHz RC - LIRC Dual Comparator functions
Multi-mode operation: NORMAL, SLOW, IDLE and Dual Time-Base functions for generation of fixed time
SLEEP interrupt signals
Fully integrated internal 4MHz, 8MHz and 12MHz Low voltage reset function
oscillator requires no external components Low voltage detect function
All instructions executed in one or two instruction Wide range of available package types
cycles
Table read instructions
63 powerful instructions
Up to 12-level subroutine nesting
Bit manipulation instruction
General Description
The HT68FXX series of devices are Flash Memory I/O A full choice of HXT, LXT, ERC, HIRC and LIRC oscilla-
type 8-bit high performance RISC architecture tor functions are provided including a fully integrated
microcontrollers. Offering users the convenience of Flash system oscillator which requires no external compo-
Memory multi-programming features, these devices also nents for its implementation. The ability to operate and
include a wide range of functions and features. Other switch dynamically between a range of operating
memory includes an area of RAM Data Memory as well as modes using different clock sources gives users the
an area of EEPROM memory for storage of non-volatile ability to optimise microcontroller operation and mini-
data such as serial numbers, calibration data etc. mise power consumption.
Multiple and extremely flexible Timer Modules provide The inclusion of flexible I/O programming features,
timing, pulse generation and PWM generation func- Time-Base functions along with many other features en-
tions. Analog features include dual comparator func- sure that the devices will find excellent use in applica-
tions. Communication with the outside world is catered tions such as electronic metering, environmental
for by including fully integrated SPI or I2C interface func- monitoring, handheld instruments, household appli-
tions, two popular interfaces which provide designers ances, electronically controlled tools, motor driving in
with a means of easy communication with external pe- addition to many others.
ripheral hardware. Protective features such as an inter-
nal Watchdog Timer, Low Voltage Reset and Low
Voltage Detector coupled with excellent noise immunity
and ESD protection ensure that reliable operation is
maintained in hostile electrical environments.
Selection Table
Most features are common to all devices, the main feature distinguishing them are Memory capacity, I/O count, TM
features, stack capacity and package types. The following table summarises the main features of each device.
16DIP/NSOP/SSOP
2.2V~ 10-bit CTM1,
HT68F30 2K14 968 648 22 2 4 20DIP/SOP/SSOP
5.5V 10-bit ETM1
24SKDIP/SOP/SSOP
10-bit CTMx2,
2.2V~ 44/52QFP, 40/48QFN
HT68F60* 12K16 5768 2568 50 4 10-bit ETMx1, 12
5.5V 48SSOP
16-bit STMx1
L o w W a tc h d o g
V o lta g e T im e r
D e te c t
R e s e t
L o w
V o lta g e C ir c u it
R e s e t
8 - b it
R IS C In te rru p t
M C U C o n tr o lle r
C o re
F la s h /E E P R O M S ta c k
E R C /H X T
P r o g r a m m in g
O s c illa to r
C ir c u itr y ( IS P )
H IR C L IR C /L X T
F la s h E E P R O M R A M
P ro g ra m D a ta T B 0 /T B 1 D a ta O s c illa to r O s c illa to r
M e m o ry M e m o ry M e m o ry
C o m p a ra to rs
I/O S IM T M 0 T M 1 T M n
Block Diagram
Pin Assignment
P A 0 /C 0 X /T P 0 _ 0 1 2 0 P A 1 /T P 1 _ 0
V S S 2 1 9 P A 2 /T C K 0 /C 0 +
P A 0 /C 0 X /T P 0 _ 0 1 1 6 P A 1 /T P 1 _ 0 P B 4 /X T 2 3 1 8 P A 3 /IN T 0 /C 0 -
V S S 2 1 5 P A 2 /T C K 0 /C 0 + P B 3 /X T 1 4 1 7 P A 4 /IN T 1 /T C K 1
P B 4 /X T 2 3 1 4 P A 3 /IN T 0 /C 0 - P B 2 /O S C 2 5 1 6 P A 5 /C 1 X /S D O
P B 3 /X T 1 4 1 3 P A 4 /IN T 1 /T C K 1 P B 1 /O S C 1 6 1 5 P A 6 /S D I/S D A
P B 2 /O S C 2 5 1 2 P A 5 /C 1 X /S D O V D D 7 1 4 P A 7 /S C K /S C L
P B 1 /O S C 1 6 1 1 P A 6 /S D I/S D A P B 0 /R E S 8 1 3 P B 5 /S C S
V D D 7 1 0 P A 7 /S C K /S C L P C 1 /S C O M 1 9 1 2 P C 2 /P C K /C 1 + /S C O M 2
P B 0 /R E S 8 9 P B 5 /S C S P C 0 /T P 1 _ 1 /S C O M 0 1 0 1 1 P C 3 /P IN T /C 1 -/S C O M 3
H T 6 8 F 2 0 H T 6 8 F 2 0
1 6 D IP -A /N S O P -A /S S O P -A 2 0 D IP -A /S O P -A /S S O P -A
P A 0 /C 0 X /T P 0 _ 0 1 2 0 P A 1 /T P 1 A
V S S 2 1 9 P A 2 /T C K 0 /C 0 +
P A 0 /C 0 X /T P 0 _ 0 1 1 6 P A 1 /T P 1 A P B 4 /X T 2 3 1 8 P A 3 /IN T 0 /C 0 -
V S S 2 1 5 P A 2 /T C K 0 /C 0 + P B 3 /X T 1 4 1 7 P A 4 /IN T 1 /T C K 1
P B 4 /X T 2 3 1 4 P A 3 /IN T 0 /C 0 - P B 2 /O S C 2 5 1 6 P A 5 /C 1 X /S D O
P B 3 /X T 1 4 1 3 P A 4 /IN T 1 /T C K 1 P B 1 /O S C 1 6 1 5 P A 6 /S D I/S D A
P B 2 /O S C 2 5 1 2 P A 5 /C 1 X /S D O V D D 7 1 4 P A 7 /S C K /S C L
P B 1 /O S C 1 6 1 1 P A 6 /S D I/S D A P B 0 /R E S 8 1 3 P B 5 /S C S
V D D 7 1 0 P A 7 /S C K /S C L P C 1 /T P 1 B _ 1 /[S D O ]/S C O M 1 9 1 2 P C 2 /P C K /C 1 +
P B 0 /R E S 8 9 P B 5 /S C S P C 0 /T P 1 B _ 0 /[S D I/S D A ]/S C O M 0 1 0 1 1 P C 3 /P IN T /C 1 -
H T 6 8 F 3 0 H T 6 8 F 3 0
1 6 D IP -A /N S O P -A /S S O P -A 2 0 D IP -A /S O P -A /S S O P -A
P A 0 /C 0 X /T P 0 _ 0 1 2 4 P A 1 /T P 1 A
V S S 2 2 3 P A 2 /T C K 0 /C 0 +
P B 4 /X T 2 3 2 2 P A 3 /IN T 0 /C 0 -
P B 3 /X T 1 4 2 1 P A 4 /IN T 1 /T C K 1
P B 2 /O S C 2 5 2 0 P A 5 /C 1 X /S D O
P B 1 /O S C 1 6 1 9 P A 6 /S D I/S D A
V D D 7 1 8 P A 7 /S C K /S C L
P B 0 /R E S 8 1 7 P B 5 /S C S
P C 1 /T P 1 B _ 1 /[S D O ]/S C O M 1 9 1 6 P C 2 /P C K /C 1 +
P C 0 /T P 1 B _ 0 /[S D I/S D A ]/S C O M 0 1 0 1 5 P C 3 /P IN T /C 1 -
P C 7 /[S C K /S C L ]/S C O M 3 1 1 1 4 P C 4 /[P IN T ]
P C 6 /[S C S ]/S C O M 2 1 2 1 3 P C 5 /T P 0 _ 1 /[P C K ]
H T 6 8 F 3 0
2 4 S K D IP -A /S O P -A /S S O P -A
P A 0 /C 0 X /T P 0 _ 0 1 2 8 P A 1 /T P 1 A
V S S 2 2 7 P A 2 /T C K 0 /C 0 +
P A 0 /C 0 X /T P 0 _ 0 1 2 4 P A 1 /T P 1 A P B 4 /X T 2 3 2 6 P A 3 /IN T 0 /C 0 -
V S S 2 2 3 P A 2 /T C K 0 /C 0 + P B 3 /X T 1 4 2 5 P A 4 /IN T 1 /T C K 1
P B 4 /X T 2 3 2 2 P A 3 /IN T 0 /C 0 - P B 2 /O S C 2 5 2 4 P A 5 /C 1 X /S D O
P B 3 /X T 1 4 2 1 P A 4 /IN T 1 /T C K 1 P B 1 /O S C 1 6 2 3 P A 6 /S D I/S D A
P B 2 /O S C 2 5 2 0 P A 5 /C 1 X /S D O V D D 7 2 2 P A 7 /S C K /S C L
P B 1 /O S C 1 6 1 9 P A 6 /S D I/S D A P B 0 /R E S 8 2 1 P B 5 /S C S
V D D 7 1 8 P A 7 /S C K /S C L P C 1 /T P 1 B _ 1 /S C O M 1 9 2 0 P C 2 /T C K 2 /P C K /C 1 +
P B 0 /R E S 8 1 7 P B 5 /S C S P C 0 /T P 1 B _ 0 /S C O M 0 1 0 1 9 P C 3 /P IN T /T P 2 _ 0 /C 1 -
P C 1 /T P 1 B _ 1 /S C O M 1 9 1 6 P C 2 /T C K 2 /P C K /C 1 + P C 7 /[T P 1 A ]/S C O M 3 1 1 1 8 P C 4 /[IN T 0 ]/[P IN T ]/T P 2 _ 1
P C 0 /T P 1 B _ 0 /S C O M 0 1 0 1 5 P C 3 /P IN T /T P 2 _ 0 /C 1 - P C 6 /[T P 0 _ 0 ]/S C O M 2 1 2 1 7 P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C K ]
P C 7 /[T P 1 A ]/S C O M 3 1 1 1 4 P C 4 /[IN T 0 ]/[P IN T ]/T P 2 _ 1 P D 3 /[T C K 1 ]/[S D O ] 1 3 1 6 P D 0 /[T C K 2 ]/[S C S ]
P C 6 /[T P 0 _ 0 ]/S C O M 2 1 2 1 3 P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C K ] P D 2 /[T C K 0 ]/[S D I/S D A ] 1 4 1 5 P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C L ]
H T 6 8 F 4 0 H T 6 8 F 4 0
2 4 S K D IP -A /S O P -A /S S O P -A 2 8 S K D IP -A /S O P -A /S S O P -A
P C 3 /P IN T /T P 2 _ 0 /C
P C 2 /T C K 2 /P C K /C
P C 3
P D 0 /[T C K 2 ]/[S C
P C
P D 6 /[S C K /S C
P B 7 /[S D I/S D
_ 1 /T P 1 B _
2 /T C K 2 /P
T 0 ]/[P IN T
/P IN T /T P
P A 5 /C
P A 7 /S
P A 6 /S
P B 6 /[S D
P D 7 /[S C
P
1 X /S D O
C K /S C L
B 5 /S C S
2 _ 0 /C 1 -
C K /C 1 +
]/T P 2 _ 1
2 /[P C K ]
D I/S D A
1 +
_ 1
O ]
S ]
A ]
K ]
S ]
1 -
L ]
L ]
4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1
3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 P B 5 /S C S 1 3 0 P D 2 /[T C K 0 ]/[S D I/S D A ]
P A 4 /IN T 1 /T C K 1 1 2 4 P D 0 /[T C K 2 ]/[S C S ] P A 7 /S C K /S C L 2 2 9 P D 3 /[T C K 1 ]/[S D O ]
P A 3 /IN T 0 /C 0 - 2 2 3 P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C L ] P A 6 /S D I/S D A 3 2 8 P D 4 /[T P 2 _ 1 ]
P A 2 /T C K 0 /C 0 + 3 2 2 P D 2 /[T C K 0 ]/[S D I/S D A ] P A 5 /C 1 X /S D O 4 2 7 P D 5 /[T P 0 _ 1 ]
P A 1 /T P 1 A 4 H T 6 8 F 4 0 2 1 P D 3 /[T C K 1 ]/[S D O ] P A 4 /IN T 1 /T C K 1 5 H T 6 8 F 4 0 2 6 P C 6 /[T P 0 _ 0 ]/S C O M 2
P A 0 /C 0 X /T P 0 _ 0 5 3 2 Q F N -A 2 0 P C 6 /[T P 0 _ 0 ]/S C O M 2 P A 3 /IN T 0 /C 0 - 6 4 0 Q F N -A 2 5 P C 7 /[T P 1 A ]/S C O M 3
P F 1 /[C 1 X ] 6 1 9 P C 7 /[T P 1 A ]/S C O M 3 P A 2 /T C K 0 /C 0 + 7 2 4 P C 0 /T P 1 B _ 0 /S C O M 0
P F 0 /[C 0 X ] 7 1 8 P C 0 /T P 1 B _ 0 /S C O M 0 P A 1 /T P 1 A 8 2 3 P C 1 /T P 1 B _ 1 /S C O M 1
P E 7 /[IN T 1 ] 8 1 7 P C 1 /T P 1 B _ 1 /S C O M 1 P A 0 /C 0 X /T P 0 _ 0 9 2 2 P E 4 /[T P 1 B _ 2 ]
9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 P F 1 /[C 1 X ] 1 0 2 1 P E 5
1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0
P E 6
V S S
P B 4
P B 3
P B 2
P B 1
V D D
P B 0
P F 0
P E 7
P E 6
V S S
P B 4
P B 3
P B 2
P B 1
V D D
P B 0
/[IN T 0 ]
/X T
/X T
/O S
/O S
/R E S
/[C 0 X ]
/[IN T 1 ]
/[IN T 0 ]
/X T
/X T
/O S
/O S
/R E S
2
1
C 2
C 1
2
1
C 2
C 1
P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C
P A 0 /C 0 X /T P 0 _ 0 P A 1 /T P 1 A
P D 0 /[T C K 2 ]/[S C
P E 6 /[IN T 0 ] 5 4 4 P A 5 /C 1 X /S D O
P D 6 /[S C K /S C
P B 7 /[S D I/S D
V S S 6 4 3 P A 6 /S D I/S D A
P B 6 /[S D
P D 7 /[S C
P B 4 /X T 2 7 4 2 P A 7 /S C K /S C L
P B 3 /X T 1 8 4 1 P B 5 /S C S
P B 2 /O S C 2 9 4 0 P B 6 /[S D O ]
1 +
_ 1
O ]
A ]
K ]
S ]
A ]
S ]
1 -
L ]
L ]
P B 1 /O S C 1 1 0 3 9 P B 7 /[S D I/S D A ]
V D D P D 6 /[S C K /S C L ] 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4
1 1 3 8 P B 5 /S C S 1 3 3 P D 3 /[T C K 1 ]/[S D O ]
P B 0 /R E S 1 2 3 7 P D 7 /[S C S ] P A 7 /S C K /S C L 2 3 2 P D 4 /[T P 2 _ 1 ]
P E 5 1 3 3 6 P C 4 /[IN T 0 ]/[P IN T ]/T P 2 _ 1 P A 6 /S D I/S D A 3 3 1 P D 5 /[T P 0 _ 1 ]
P A 5 /C 1 X /S D O 4 3 0 P E 0
P E 4 /[T P 1 B _ 2 ] 1 4 3 5 N C 5
P A 4 /IN T 1 /T C K 1 2 9 P E 1
P C 1 /T P 1 B _ 1 /S C O M 1 3 4 N C H T 6 8 F 4 0
1 5 P A 3 /IN T 0 /C 0 - 6 2 8 P E 2
7
4 4 Q F P -A
P C 0 /T P 1 B _ 0 /S C O M 0 1 6 3 3 N C P A 2 /T C K 0 /C 0 + 2 7 P E 3
P A 1 /T P 1 A 8 2 6 P C 6 /[T P 0 _ 0 ]/S C O M 2
N C 1 7 3 2 P C 2 /T C K 2 /P C K /C 1 +
P A 0 /C 0 X /T P 0 _ 0 9 2 5 P C 7 /[T P 1 A ]/S C O M 3
P C 7 /[T P 1 A ]/S C O M 3 1 8 3 1 P C 3 /P IN T /T P 2 _ 0 /C 1 - P F 1 /[C 1 X ] 1 0 2 4 P C 0 /T P 1 B _ 0 /S C O M 0
P C 6 /[T P 0 _ 0 ]/S C O M 2 1 9 3 0 P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C K ] P F 0 /[C 0 X ] 1 1 2 3 P C 1 /T P 1 B _ 1 /S C O M 1
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
P E 3 2 0 2 9 P D 0 /[T C K 2 ]/[S C S ]
P E 2 2 8 P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C L ]
P E 7
P E 6
V S S
P B 4
P B 3
P B 2
P B 1
V D D
P B 0
P E 5
P E 4
2 1
P E 1 2 2 2 7 P D 2 /[T C K 0 ]/[S D I/S D A ]
/[IN T 1 ]
/[IN T 0 ]
/X T
/X T
/O S
/O S
/R E S
/[T P 1 B _ 2 ]
P E 0 2 3 2 6 P D 3 /[T C K 1 ]/[S D O ]
2
1
C 2
C 1
P D 5 /[T P 0 _ 1 ] 2 4 2 5 P D 4 /[T P 2 _ 1 ]
H T 6 8 F 4 0
4 8 S S O P -A
P C 5 /[IN T 1 ]/T P 0
P D 0 /[T C K 2 ]/[S C
_ 1 /T P 1 B _ 2 /[P C
2 /T C K 2 /P C K /C
T 0 ]/[P IN T ]/T P 2
/P IN T /T P 2 _ 0 /C
P D 6 /[S C K /S C
P B 7 /[S D I/S D
P B 6 /[S D
P D 7 /[S C
N
1 +
_ 1
O ]
A ]
S ]
A ]
S ]
K ]
1 -
L ]
L ]
C
4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7
N C 1 3 6 P D 3 /[T C K 1 ]/[S D O ]
P B 5 /S C S 2 3 5 P D 4 /[T P 2 _ 1 ]
P A 7 /S C K /S C L 3 3 4 P D 5 /[T P 0 _ 1 ]
P A 6 /S D I/S D A 4 3 3 P E 0
P A 5 /C 1 X /S D O 5 3 2 P E 1
P A 4 /IN T 1 /T C K 1 6 H T 6 8 F 4 0 3 1 P E 2
P A 3 /IN T 0 C 0 - 7 4 8 Q F N -A 3 0 P E 3
P A 2 /T C K 0 /C 0 + 8 2 9 P C 6 /[T P 0 _ 0 ]/S C O M 2
P A 1 /T P 1 A 9 2 8 P C 7 /[T P 1 A ]/S C O M 3
P A 0 /C 0 X /T P 0 _ 0 1 0 2 7 N C
N C 1 1 2 6 P C 0 /T P 1 B _ 0 /S C O M 0
P F 1 /[C 1 X ] 1 2 2 5 P C 1 /T P 1 B _ 1 /S C O M 1
1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4
P F 0
P E 7
P E 6
V S S
P B 4
P B 3
P B 2
P B 1
V D D
P B 0
P E 5
P E 4
/[C 0 X ]
/[IN T 1 ]
/[IN T 0 ]
/X T
/X T
/O S
/O S
/R E S
/[T P 1 B _ 2 ]
2
1
C 2
C 1
P C 5 /[IN T
P C 4 /[IN
P D 1 /[T
P
1
D
P
T
]/T P 0 _ 1 /T P 1 B _ 2 /[P C
2 _ 0 ]/[S D O ]/[S C K /S C
0 /[T C K 2 ]/T P 3 _ 1 /[S C
0 ]/[P IN T ]/T C K 3 /T P 2
P C 3 /P IN T /T P 2 _ 0 /C
P C 2 /T C K 2 /P C K /C
P A 0 /C 0 X /T P 0 _ 0 1 2 8 P A 1 /T P 1 A
P D 6 /[S C K /S C
P B 7 /[S D I/S D
V S S 2 2 7 P A 2 /T C K 0 /C 0 +
P B 6 /[S D
P D 7 /[S C
P B 4 /X T 2 3 2 6 P A 3 /IN T 0 /C 0 -
P B 3 /X T 1 4 2 5 P A 4 /IN T 1 /T C K 1
1 +
_ 1
O ]
P B 2 /O S C 2 5 2 4 P A 5 /C 1 X /S D O
S ]
A ]
S ]
K ]
1 -
L ]
L ]
P B 1 /O S C 1 6 2 3 P A 6 /S D I/S D A
4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1
V D D 7 2 2 P A 7 /S C K /S C L P B 5 /S C S 1 3 0 P D 2 /[T C K 0 ]/[S D I/S D A ]
P B 0 /R E S 8 2 1 P B 5 /S C S P A 7 /S C K /S C L 2 2 9 P D 3 /[T C K 1 ]/T P 3 _ 0 /[S D O ]
P A 6 /S D I/S D A 3 2 8 P D 4 /[T P 2 _ 1 ]
P C 1 /T P 1 B _ 1 /S C O M 1 9 2 0 P C 2 /T C K 2 /P C K /C 1 + 4 2 7 P D 5 /[T P 0 _ 1 ]
P A 5 /C 1 X /S D O
P C 0 /T P 1 B _ 0 /S C O M 0 1 0 1 9 P C 3 /P IN T /T P 2 _ 0 /C 1 - P A 4 /IN T 1 /T C K 1 5 H T 6 8 F 5 0 2 6 P C 6 /[T P 0 _ 0 ]/S C O M 2
P C 7 /[T P 1 A ]/S C O M 3 1 1 1 8 P C 4 /[IN T 0 ]/[P IN T ]/T C K 3 /T P 2 _ 1 P A 3 /IN T 0 /C 0 - 6 4 0 Q F N -A 2 5 P C 7 /[T P 1 A ]/S C O M 3
P A 2 /T C K 0 /C 0 + 7 2 4 P C 0 /T P 1 B _ 0 /S C O M 0
P C 6 /[T P 0 _ 0 ]/S C O M 2 1 2 1 7 P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C K ]
P A 1 /T P 1 A 8 2 3 P C 1 /T P 1 B _ 1 /S C O M 1
P D 3 /[T C K 1 ]/T P 3 _ 0 /[S D O ] 1 3 1 6 P D 0 /[T C K 2 ]/T P 3 _ 1 /[S C S ] P A 0 /C 0 X /T P 0 _ 0 9 2 2 P E 4 /[T P 1 B _ 2 ]
P D 2 /[T C K 0 ]/[S D I/S D A ] 1 4 1 5 P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C L ] P F 1 /[C 1 X ] 1 0 2 1 P E 5 /[T P 3 _ 0 ]
1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0
H T 6 8 F 5 0
P F 0
P E 7
P E 6
V S S
P B 4
P B 3
P B 2
P B 1
V D D
P B 0
2 8 S K D IP -A /S O P -A /S S O P -A
/[C 0 X ]
/[IN T 1 ]
/[IN T 0 ]
/X T
/X T
/O S
/O S
/R E S
2
1
C 2
C 1
P C 5 /[IN T
P A 0 /C 0 X /T P 0 _ 0 1 4 8 P A 1 /T P 1 A
P C 4 /[IN
P D 1 /[T
P F 1 /[C 1 X ] 2 4 7 P A 2 /T C K 0 /C 0 +
P
P F 0 /[C 0 X ] 3 4 6 P A 3 /IN T 0 /C 0 -
1
D
P
T
]/T P 0 _ 1 /T P 1 B _ 2 /[P C
P C 3 /P IN T /T P 2 _ 0 /C
4 4 5
P C 2 /T C K 2 /P C K /C
P E 6 /[IN T 0 ] 5 4 4 P A 5 /C 1 X /S D O
P D 6 /[S C K /S C
P B 7 /[S D I/S D
V S S 6 4 3 P A 6 /S D I/S D A
P B 4 /X T 2 7 4 2 P A 7 /S C K /S C L
P B 6 /[S D
P D 7 /[S C
P B 3 /X T 1 8 4 1 P B 5 /S C S
P B 2 /O S C 2 9 4 0 P B 6 /[S D O ]
1 +
_ 1
O ]
A ]
S ]
A ]
S ]
K ]
1 -
L ]
L ]
P B 1 /O S C 1 1 0 3 9 P B 7 /[S D I/S D A ]
V D D 1 1 3 8 P D 6 /[S C K /S C L ] 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4
P B 5 /S C S 1 3 3 P D 3 /[T C K 1 ]/T P 3 _ 0 /[S D O ]
P B 0 /R E S 1 2 3 7 P D 7 /[S C S ]
P A 7 /S C K /S C L 2 3 2 P D 4 /[T P 2 _ 1 ]
P E 5 /[T P 3 _ 0 ] 1 3 3 6 P C 4 /[IN T 0 ]/[P IN T ]/T P 2 _ 1 P A 6 /S D I/S D A 3 3 1 P D 5 /[T P 0 _ 1 ]
P E 4 /[T P 1 B _ 2 ] 1 4 3 5 N C P A 5 /C 1 X /S D O 4 3 0 P E 0
P A 4 /IN T 1 /T C K 1 5 2 9 P E 1
P C 1 /T P 1 B _ 1 /S C O M 1 1 5 3 4 N C H T 6 8 F 5 0
P A 3 /IN T 0 /C 0 - 6 2 8 P E 2
P C 0 /T P 1 B _ 0 /S C O M 0 1 6 3 3 N C 7
4 4 Q F P -A
P A 2 /T C K 0 /C 0 + 2 7 P E 3 /[T P 3 _ 1 ]
N C 1 7 3 2 P C 2 /T C K 2 /P C K /C 1 + P A 1 /T P 1 A 8 2 6 P C 6 /[T P 0 _ 0 ]/S C O M 2
P C 7 /[T P 1 A ]/S C O M 3 P C 3 /P IN T /T P 2 _ 0 /C 1 - P A 0 /C 0 X /T P 0 _ 0 9 2 5 P C 7 /[T P 1 A ]/S C O M 3
1 8 3 1
P F 1 /[C 1 X ] 1 0 2 4 P C 0 /T P 1 B _ 0 /S C O M 0
P C 6 /[T P 0 _ 0 ]/S C O M 2 1 9 3 0 P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C K ] P F 0 /[C 0 X ] 1 1 2 3 P C 1 /T P 1 B _ 1 /S C O M 1
P E 3 /[T P 3 _ 1 ] 2 9 P D 0 /[T C K 2 ]/[S C S ] 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
2 0
P E 2 2 1 2 8 P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C L ]
P E 7
P E 6
V S S
P B 4
P B 3
P B 2
P B 1
V D D
P B 0
P E 5
P E 4
/X T
/X T
/O S
/O S
/R E S
/[T P 3 _ 0 ]
/[T P 1 B _ 2 ]
P E 0 2 3 2 6 P D 3 /[T C K 1 ]/[S D O ]
2
1
C 2
C 1
P D 5 /[T P 0 _ 1 ] 2 4 2 5 P D 4 /[T P 2 _ 1 ]
H T 6 8 F 5 0
P C 5 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C
4 8 S S O P -A
P C 4 /[IN T 0 ]/[P IN T ]/T C K 3 /T P 2
P D 7 /[S C
N
1 +
_ 1
O ]
A ]
S ]
A ]
S ]
K ]
1 -
L ]
L ]
4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7
N C 1 3 6 P D 3 /[T C K 1 ]/T P 3 _ 0 /[S D O ]
P B 5 /S C S 2 3 5 P D 4 /[T P 2 _ 1 ]
P A 7 /S C K /S C L 3 3 4 P D 5 /[T P 0 _ 1 ]
P A 6 /S D I/S D A 4 3 3 P E 0
P A 5 /C 1 X /S D O 5 3 2 P E 1
P A 4 /IN T 1 /T C K 1 6 H T 6 8 F 5 0 3 1 P E 2
P A 3 /IN T 0 /C 0 - 7 4 8 Q F N -A 3 0 P E 3 /[T P 3 _ 1 ]
P A 2 /T C K 0 /C 0 + 8 2 9 P C 6 /[T P 0 _ 0 ]/S C O M 2
P A 1 /T P 1 A 9 2 8 P C 7 /[T P 1 A ]/S C O M 3
P A 0 /C 0 X /T P 0 _ 0 1 0 2 7 N C
N C 1 1 2 6 P C 0 /T P 1 B _ 0 /S C O M 0
P F 1 /[C 1 X ] 1 2 2 5 P C 1 /T P 1 B _ 1 /S C O M 1
1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4
P F 0
P E 7
P E 6
V S S
P B 4
P B 3
P B 2
P B 1
V D D
P B 0
P E 5
P E 4
/[C 0 X ]
/[IN T 1 ]
/[IN T 0 ]
/X T
/X T
/O S
/O S
/R E S
/[T P 3 _ 0 ]
/[T P 1 B _ 2 ]
2
1
C 2
C 1
P C 5 /IN T 3 /[IN T
P C 5 /IN T 3 /[IN T
P C 4 /IN T 2 /[IN
P C 4 /IN T 2 /[IN
P D 1 /[T
P D 1 /[T
P
P
1
D
P
T
1
D
P
]/T P 0 _ 1 /T P 1 B _ 2 /[P C
T
P C 3 /P IN T /T P 2 _ 0 /C
0 ]/[P IN T ]/T C K 3 /T P 2
P C 2 /T C K 2 /P C K /C
P C 3 /P IN T /T P 2 _ 0 /C
P C 2 /T C K 2 /P C K /C
P D 6 /[S C K /S C
P B 7 /[S D I/S D
P D 6 /[S C K /S C
P B 7 /[S D I/S D
P B 6 /[S D
P D 7 /[S C
P B 6 /[S D
P D 7 /[S C
1 +
_ 1
O ]
S ]
A ]
A ]
S ]
K ]
1 -
L ]
L ]
1 +
_ 1
O ]
A ]
K ]
S ]
S ]
1 -
L ]
L ]
4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4
1 3 0 P D 2 /[T C K 0 ]/[S D I/S D A ] P B 5 /S C S 1 3 3 P D 3 /[T C K 1 ]/T P 3 _ 0 /[S D O ]/[S C K /S C L ]
P B 5 /S C S
2 2 9 P D 3 /[T C K 1 ]/T P 3 _ 0 /[S D O ]/[S C K /S C L ] P A 7 /S C K /S C L 2 3 2 P D 4 /[T P 2 _ 1 ]
P A 7 /S C K /S C L
3 2 8 P D 4 /[T P 2 _ 1 ] P A 6 /S D I/S D A 3 3 1 P D 5 /[T P 0 _ 1 ]
P A 6 /S D I/S D A
4 2 7 P D 5 /[T P 0 _ 1 ] P A 5 /C 1 X /S D O 4 3 0 P E 0 /[IN T 0 ]
P A 5 /C 1 X /S D O
5 P A 4 /IN T 1 /T C K 1 5 2 9 P E 1 /[IN T 1 ]
P A 4 /IN T 1 /T C K 1 H T 6 8 F 6 0 2 6 P C 6 /[T P 0 _ 0 ]/S C O M 2 H T 6 8 F 6 0
6 4 0 Q F N -A 2 5 P C 7 /[T P 1 A ]/S C O M 3 P A 3 /IN T 0 /C 0 - 6 2 8 P E 2 /[IN T 2 ]
P A 3 /IN T 0 /C 0 - 4 4 Q F P -A
7 P A 2 /T C K 0 /C 0 + 7 2 7 P E 3 /[T P 3 _ 1 ]
P A 2 /T C K 0 /C 0 + 2 4 P C 0 /T P 1 B _ 0 /S C O M 0
8 2 3 P C 1 /T P 1 B _ 1 /S C O M 1 P A 1 /T P 1 A 8 2 6 P C 6 /[T P 0 _ 0 ]/S C O M 2
P A 1 /T P 1 A
9 2 2 P E 4 /[T P 1 B _ 2 ] P A 0 /C 0 X /T P 0 _ 0 9 2 5 P C 7 /[T P 1 A ]/S C O M 3
P A 0 /C 0 X /T P 0 _ 0
1 0 2 1 P E 5 /[T P 3 _ 0 ] P F 1 /[C 1 X ] 1 0 2 4 P C 0 /T P 1 B _ 0 /S C O M 0
P F 1 /[C 1 X ]
1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 P F 0 /[C 0 X ] 1 1 2 3 P C 1 /T P 1 B _ 1 /S C O M 1
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
P F 0
P E 7
P E 6
V S S
P B 4
P B 3
P B 2
P B 1
V D D
P B 0
P E 7
P E 6
V S S
P B 4
P B 3
P B 2
P B 1
V D D
P B 0
P E 5
P E 4
/[C 0 X ]
/[IN T 1 ]
/[IN T 0 ]
/X T
/X T
/O S
/O S
/R E S
/[IN T 1 ]
/[IN T 0 ]
/X T
/X T
/O S
/O S
/R E S
/[T P 3 _ 0 ]
/[T P 1 B _ 2 ]
2
1
C 2
C 1
2
1
C 2
C 1
P C 5 /IN T 3 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C
P C 4 /IN T 2 /[IN T 0 ]/[P IN T ]/T C K 3 /T P 2
P C 3 /P IN T /T P 2 _ 0 /C
P C 2 /T C K 2 /P C K /C
P D 7 /[S C S ] 3 4 6 P C 4 /IN T 2 /[IN T 0 ]/[P IN T ]/T C K 3 /T P 2 _ 1
P D 6 /[S C K /S C
P B 7 /[S D I/S D
P D 6 /[S C K /S C L ] 4 4 5 P C 5 /IN T 3 /[IN T 1 ]/T P 0 _ 1 /T P 1 B _ 2 /[P C K ]
P B 7 /[S D I/S D A ] 5 4 4 P D 0 /[T C K 2 ]/T P 3 _ 1 /[S C S ]
P B 6 /[S D
P D 7 /[S C
P B 6 /[S D O ] 6 4 3 P D 1 /[T P 2 _ 0 ]/[S D O ]/[S C K /S C L ]
P F 2 7 4 2 P D 2 /[T C K 0 ]/[S D I/S D A ]
N
1 +
_ 1
O ]
A ]
S ]
K ]
S ]
A ]
1 -
L ]
L ]
C
P B 5 /S C S /V R E F 8 4 1 P D 3 /[T C K 1 ]/T P 3 _ 0 /[S D O ]/[S C K /S C L ]
P A 7 /S C K /S C L 9 4 0 P D 4 /[T P 2 _ 1 ] 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7
N C 1 3 6 P D 3 /[T C K 1 ]/T P 3 _ 0 /[S D O ]/[S C K /S C L ]
P A 6 /S D I/S D A 1 0 3 9 P D 5 /[T P 0 _ 1 ] P D 4 /[T P 2 _ 1 ]
P B 5 /S C S 2 3 5
P A 5 /C 1 X /S D O 1 1 3 8 P E 0 /[IN T 0 ] P A 7 /S C K /S C L 3 3 4 P D 5 /[T P 0 _ 1 ]
P A 4 /IN T 1 /T C K 1 1 2 3 7 P E 1 /[IN T 1 ] P A 6 /S D I/S D A 4 3 3 P E 0 /[IN T 0 ]
P A 5 /C 1 X /S D O 5 3 2 P E 1 /[IN T 1 ]
P A 3 /IN T 0 /C 0 - 1 3 3 6 P E 2 /[IN T 2 ]
P A 4 /IN T 1 /T C K 1 6 H T 6 8 F 6 0 3 1 P E 2 /[IN T 2 ]
P A 2 /T C K 0 /C 0 + 1 4 3 5 P E 3 /[T P 3 _ 1 ] P A 3 /IN T 0 /C 0 - 7 4 8 Q F N -A 3 0 P E 3 /[T P 3 _ 1 ]
P A 1 /T P 1 A 1 5 3 4 P G 1 /[C 1 X ] P A 2 /T C K 0 /C 0 + 8 2 9 P C 6 /[T P 0 _ 0 ]/S C O M 2
P A 1 /T P 1 A 9 2 8 P C 7 /[T P 1 A ]/S C O M 3
P A 0 /C 0 X /T P 0 _ 0 1 6 3 3 P C 6 /[T P 0 _ 0 ]/S C O M 2
P A 0 /C 0 X /T P 0 _ 0 1 0 2 7 N C
P F 1 /[C 1 X ] 1 7 3 2 P C 7 /[T P 1 A ]/S C O M 3 N C 1 1 2 6 P C 0 /T P 1 B _ 0 /S C O M 0
P F 0 /[C 0 X ] 1 8 3 1 P C 0 /T P 1 B _ 0 /S C O M 0 P F 1 /[C 1 X ] 1 2 2 5 P C 1 /T P 1 B _ 1 /S C O M 1
1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4
P E 7 /[IN T 1 ] 1 9 3 0 P C 1 /T P 1 B _ 1 /S C O M 1
P E 6 /[IN T 0 ] 2 0 2 9 P E 4 /[T P 1 B _ 2 ]
P F 0
P E 7
P E 6
V S S
P B 4
P B 3
P B 2
P B 1
V D D
P B 0
P E 5
P E 4
V S S 2 1 2 8 P E 5 /[T P 3 _ 0 ]
/[C 0 X ]
/[IN T 1 ]
/[IN T 0 ]
/X T
/X T
/O S
/O S
/R E S
/[T P 3 _ 0 ]
/[T P 1 B _ 2 ]
P B 4 /X T 2 2 2 2 7 P B 0 /R E S
2
1
C 2
C 1
P B 3 /X T 1 2 3 2 6 V D D
P B 2 /O S C 2 2 4 2 5 P B 1 /O S C 1
P C 5 /IN T 3 /[IN T
P C 4 /IN T 2 /[IN
H T 6 8 F 6 0
4 8 S S O P -A
P D 1 /[T
P
1
D
P
T
]/T P 0 _ 1 /T P 1 B _ 2 /[P C
P D 7 /[S C
P
P
F 4
F 5
1 +
_ 1
O ]
S ]
A ]
A ]
S ]
K ]
1 -
L ]
L ]
5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0
P F 3 1 3 9 P D 3 /[T C K 1 ]/T P 3 _ 0 /[S D O ]/[S C K /S C L ]
P F 2 2 3 8 P D 4 /[T P 2 _ 1 ]
P B 5 /S C S 3 3 7 P D 5 /[T P 0 _ 1 ]
P A 7 /S C K /S C L 4 3 6 P E 0 /[IN T 0 ]
P A 6 /S D I/S D A 5 3 5 P E 1 /[IN T 1 ]
P A 5 /C 1 X /S D O 6 3 4 P E 2 /[IN T 2 ]
P A 4 /IN T 1 /T C K 1 7 H T 6 8 F 6 0 3 3 P E 3 /[T P 3 _ 1 ]
5 2 Q F P -A
P A 3 /IN T 0 /C 0 - 8 3 2 P F 6
P A 2 /T C K 0 /C 0 + 9 3 1 P F 7
P A 1 /T P 1 A 1 0 3 0 P G 0 /[C 0 X ]
P A 0 /C 0 X /T P 0 _ 0 1 1 2 9 P G 1 /[C 1 X ]
P F 1 /[C 1 X ] 1 2 2 8 P C 6 /[T P 0 _ 0 ]/S C O M 2
P F 0 /[C 0 X ] 1 3 2 7 P C 7 /[T P 1 A ]/S C O M 3
1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6
P E 7
P E 6
V S S
P B 4
P B 3
P B 2
P B 1
V D D
P B 0
P E 5
P E 4
P C 1
P C 0
/[IN T 1 ]
/[IN T 0 ]
/X T
/X T
/O S
/O S
/R E
/[T P
/[T P
/T P
/T P
2
1
1 B
1 B
S
C 2
C 1
3 _
1 B
_ 1 /S C O M 1
_ 0 /S C O M 0
0 ]
_ 2 ]
Pin Description
With the exception of the power pins, all pins on these devices can be referenced by their Port name, e.g. PA.0, PA.1
etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such
as the Serial Port pins etc. The function of each pin is listed in the following table, however the details behind how each
pin is configured is contained in other sections of the datasheet.
HT68F20
HT68F30
HT68F40
HT68F50
HT68F60
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
fSYS=8MHz 2.2 5.5 V
Operating Voltage
VDD fSYS=12MHz 2.7 5.5 V
(HXT, ERC, HIRC)
fSYS=20MHz 4.5 5.5 V
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
LVR Enable, 2.10V option -5% 2.10 +5% V
3V IOH=-3.2mA 2.7 V
VOH Output High Voltage I/O Port
5V IOH=-7.4mA 4.5 V
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
2.2V~5.5V DC 8 MHz
fCPU Operating Clock 2.7V~5.5V DC 12 MHz
4.5V~5.5V DC 20 MHz
Ta= -40C~85C,
5V -7% 8 +9% MHz
R=120kW *
fERC System Clock (ERC)
3.0V~ Ta= -40C~85C,
-9% 8 +10% MHz
5.5V R=120kW *
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
fLIRC System Clock (LIRC) 5V Ta=25C -10% 32 +10% kHz
fTIMER Timer Input Pin Frequency 1 fSYS
Note: 1. tSYS=1/fSYS
2. * For fERC, as the resistor tolerance will influence the frequency a precision resistor is recommended.
3. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1mF decoupling capacitor should be
connected between VDD and VSS and located as close to the device as possible.
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
VCMP Comparator Operating Voltage 2.2 5.5 V
3V 37 56 mA
ICMP Comparator Operating Current
5V 130 200 mA
VCMPOS Comparator Input Offset Voltage -10 10 mV
VHYS Hysteresis Width 20 40 60 mV
Comparator Common Mode
VCM VSS VDD-1.4V V
Voltage Range
AOL Comparator Open Loop Gain 60 80 dB
With 100mV
tPD Comparator Response Time 370 560 ns
overdrive (Note)
Note: Measured with comparator one input pin at VCM = (VDD-1.4)/2 while the other pin input transition from VSS to
(VCM +100mV) or from VDD to (VCM -100mV).
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
VDD Start Voltage to Ensure
VPOR 100 mV
Power-on Reset
VDD Raising Rate to Ensure
RRVDD 0.035 V/ms
Power-on Reset
Minimum Time for VDD Stays at
tPOR 1 ms
VPOR to Ensure Power-on Reset
V D D
tP O R R R V D D
V P O R
T im e
System Architecture
A key factor in the high-performance features of the ternally generated non-overlapping clocks, T1~T4. The
Holtek range of microcontrollers is attributed to their in- Program Counter is incremented at the beginning of the
ternal system architecture. The range of devices take T1 clock during which time a new instruction is fetched.
advantage of the usual features found within RISC The remaining T2~T4 clocks carry out the decoding and
microcontrollers providing increased speed of operation execution functions. In this way, one T1~T4 clock cycle
and enhanced performance. The pipelining scheme is forms one instruction cycle. Although the fetching and
implemented in such a way that instruction fetching and execution of instructions takes place in consecutive in-
instruction execution are overlapped, hence instructions struction cycles, the pipelining structure of the
are effectively executed in one cycle, with the exception microcontroller ensures that instructions are effectively
of branch or call instructions. An 8-bit wide ALU is used executed in one instruction cycle. The exception to this
in practically all instruction set operations, which carries are instructions where the contents of the Program
out arithmetic operations, logic operations, rotation, in- Counter are changed, such as subroutine calls or
crement, decrement, branch decisions, etc. The internal jumps, in which case the instruction will take one more
data path is simplified by moving data through the Accu- instruction cycle to execute.
mulator and the ALU. Certain internal registers are im-
For instructions involving branches, such as jump or call
plemented in the Data Memory and can be directly or instructions, two machine cycles are required to com-
indirectly addressed. The simple addressing methods of
plete instruction execution. An extra cycle is required as
these registers along with additional architectural fea-
the program takes one cycle to first obtain the actual
tures ensure that a minimum of external components is
jump or call address and then another cycle to actually
required to provide a functional I/O control system with
execute the branch. The requirement for this extra cycle
maximum reliability and flexibility. This makes the de-
should be taken into account by programmers in timing
vice suitable for low-cost, high-volume production for
sensitive applications.
controller applications.
fS Y S
(S y s te m C lo c k )
P h a s e C lo c k T 1
P h a s e C lo c k T 2
P h a s e C lo c k T 3
P h a s e C lo c k T 4
P ro g ra m C o u n te r P C P C + 1 P C + 2
F e tc h In s t. (P C )
P ip e lin in g
E x e c u te In s t. (P C -1 ) F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C ) F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )
1 M O V A ,[1 2 H ] F e tc h In s t. 1 E x e c u te In s t. 1
2 C A L L D E L A Y F e tc h In s t. 2 E x e c u te In s t. 2
3 C P L [1 2 H ] F e tc h In s t. 3 F lu s h P ip e lin e
4 : F e tc h In s t. 6 E x e c u te In s t. 6
5 : F e tc h In s t. 7
6 D E L A Y : N O P
Instruction Fetching
Program Counter If the stack is full and an enabled interrupt takes place,
During program execution, the Program Counter is used the interrupt request flag will be recorded but the ac-
to keep track of the address of the next instruction to be knowledge signal will be inhibited. When the Stack
executed. It is automatically incremented by one each Pointer is decremented, by RET or RETI, the interrupt
time an instruction is executed except for instructions, will be serviced. This feature prevents stack overflow al-
such as JMP or CALL that demand a jump to a lowing the programmer to use the structure more easily.
non-consecutive Program Memory address. Only the However, when the stack is full, a CALL subroutine in-
lower 8 bits, known as the Program Counter Low Regis- struction can still be executed which will result in a stack
ter, are directly addressable by the application program. overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program
When executing instructions requiring jumps to branching.
non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the If the stack is overflow, the first Program Counter save in
microcontroller manages program control by loading the the stack will be lost.
required address into the Program Counter. For condi-
P ro g ra m C o u n te r
tional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is dis- T o p o f S ta c k S ta c k L e v e l 1
carded and a dummy cycle takes its place while the cor- S ta c k L e v e l 2
rect instruction is obtained. S ta c k
S ta c k L e v e l 3 P ro g ra m
P o in te r M e m o ry
Program Counter
Device Program Counter
PCL Register B o tto m o f S ta c k S ta c k L e v e l N
High Byte
HT68F20 PC9, PC8
HT68F30 PC10~PC8 Device Stack Levels
HT68F40 PC11~PC8 PCL7~PCL0 HT68F20/HT68F30 4
HT68F50 PC12~PC8 HT68F40/HT68F50 8
HT68F60 PC13~PC8 HT68F60 12
Program Counter
The lower byte of the Program Counter, known as the Arithmetic and Logic Unit - ALU
Program Counter Low register or PCL, is available for The arithmetic-logic unit or ALU is a critical area of the
program control and is a readable and writeable register. microcontroller that carries out arithmetic and logic oper-
By transferring data directly into this register, a short pro- ations of the instruction set. Connected to the main
gram jump can be executed directly, however, as only microcontroller data bus, the ALU receives related in-
this low byte is available for manipulation, the jumps are struction codes and performs the required arithmetic or
limited to the present page of memory, that is 256 loca- logical operations after which the result will be placed in
tions. When such program jumps are executed it should the specified register. As these ALU calculation or oper-
also be noted that a dummy cycle will be inserted. Manip- ations may result in carry, borrow or other status
ulating the PCL register may cause program branching, changes, the status register will be correspondingly up-
so an extra cycle is needed to pre-fetch. dated to reflect these changes. The ALU supports the
following functions:
Stack
Arithmetic operations: ADD, ADDM, ADC, ADCM,
This is a special part of the memory which is used to SUB, SUBM, SBC, SBCM, DAA
save the contents of the Program Counter only. The Logic operations: AND, OR, XOR, ANDM, ORM,
stack has multiple levels depending upon the device XORM, CPL, CPLA
and is neither part of the data nor part of the program Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
space, and is neither readable nor writeable. The acti- RLC
vated level is indexed by the Stack Pointer, and is nei-
Increment and Decrement INCA, INC, DECA, DEC
ther readable nor writeable. At a subroutine call or
Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
interrupt acknowledge signal, the contents of the Pro-
SIZA, SDZA, CALL, RET, RETI
gram Counter are pushed onto the stack. At the end of a
subroutine or an interrupt routine, signaled by a return
instruction, RET or RETI, the Program Counter is re-
stored to its previous value from the stack. After a device
reset, the Stack Pointer will point to the top of the stack.
A d d re s s
4K15 T B H P R e g is te r D a ta
HT68F50 8K16 0 1 4 ~ 1 6 b its
T B L P R e g is te r
HT68F60 12K16 0, 1
Special Vectors
Table Program Example
Within the Program Memory, certain locations are re-
served for the reset and interrupts. The location 000H is The following example shows how the table pointer and
reserved for use by the device reset for program initialis- table data is defined and retrieved from the
ation. After a device reset is initiated, the program will microcontroller. This example uses raw table data lo-
jump to this location and begin execution. cated in the Program Memory which is stored there us-
H T 6 8 F 2 0 H T 6 8 F 3 0 H T 6 8 F 4 0 H T 6 8 F 5 0 H T 6 8 F 6 0
0 0 0 0 H R e s e t R e s e t R e s e t R e s e t R e s e t
0 0 0 4 H
In te rru p t In te rru p t In te rru p t In te rru p t In te rru p t
0 0 2 C H V e c to r V e c to r V e c to r V e c to r V e c to r
0 0 3 C H
0 3 F F H 1 4 b its
B a n k 0
0 7 F F H 1 4 b its
0 F F F H 1 5 b its
1 F F F H 1 6 b its 1 F F F H 1 6 b its
2 0 0 0 H
B a n k 1
2 F F F H
Program Memory Structure
ing the ORG statement. The value at this ORG As an additional convenience, Holtek has provided a
statement is 700H which refers to the start address of means of programming the microcontroller in-circuit us-
the last page within the 2K Program Memory of the ing a 5-pin interface. This provides manufacturers with
HT68F30. The table pointer is setup here to have an ini- the possibility of manufacturing their circuit boards com-
tial value of 06H. This will ensure that the first data plete with a programmed or un-programmed
read from the data table will be at the Program Memory microcontroller, and then programming or upgrading the
address 706H or 6 locations after the start of the last program at a later stage. This enables product manufac-
page. Note that the value for the table pointer is refer- turers to easily keep their manufactured products sup-
enced to the first address of the present page if the plied with the latest program releases without removal
TABRD [m] instruction is being used. The high byte of and re-insertion of the device.
the table data which in this case is equal to zero will be MCU Programming
Function
transferred to the TBLH register automatically when the Pins
TABRD [m] instruction is executed. PA0 Serial Data Input/Output
Because the TBLH register is a read-only register and PA2 Serial Clock
cannot be restored, care should be taken to ensure its RES Device Reset
protection if both the main routine and Interrupt Service
VDD Power Supply
Routine use table read instructions. If using the table
VSS Ground
read instructions, the Interrupt Service Routines may
change the value of the TBLH and subsequently cause
The Program Memory and EEPROM data memory can
errors if used again by the main routine. As a rule it is
both be programmed serially in-circuit using this 5-wire
recommended that simultaneous use of the table read
interface. Data is downloaded and uploaded serially on
instructions should be avoided. However, in situations
a single pin with an additional line for the clock. Two ad-
where simultaneous use cannot be avoided, the inter-
ditional lines are required for the power supply and one
rupts should be disabled prior to the execution of any
line for the reset. The technical details regarding the
main routine table-read instructions. Note that all table
in-circuit programming of the devices are beyond the
related instructions require two instruction cycles to
scope of this document and will be supplied in supple-
complete their operation.
mentary literature.
In Circuit Programming During the programming process the RES pin will be
held low by the programmer disabling the normal opera-
The provision of Flash type Program Memory provides
tion of the microcontroller and taking control of the PA0
the user with a means of convenient and easy upgrades
and PA2 I/O pins for data and clock programming pur-
and modifications to their programs on the same device.
poses. The user must there take care to ensure that no
other outputs are connected to these two pins.
tabrd tempreg2 ; transfers value in table referenced by table pointer data at program
; memory address 705H transferred to tempreg2 and TBLH in this
; example the data 1AH is transferred to tempreg1 and data 0FH to
; register tempreg2
:
:
org 700h ; sets initial address of program memory
W r ite r C o n n e c to r M C U P r o g r a m m in g
S ig n a ls P in s Device Capacity Banks
0: 60H~7FH
W r ite r _ V D D V D D HT68F20 648
1: 60H~7FH
0: 60H~7FH
R E S R E S HT68F30 1: 60H~7FH
968
2: 60H~7FH
D A T A D A T A
0: 80H~FFH
HT68F40 1928
1: 80H~BFH
C L K C L K 0: 80H~FFH
HT68F50 3848 1: 80H~FFH
W r ite r _ V S S V S S
2: 80H~FFH
0: 80H~FFH
* * * 1: 80H~FFH
HT68F60 5768 2: 80H~FFH
3: 80H~FFH
T o o th e r C ir c u it 4: 80H~FFH
Note: * may be resistor or capacitor. The resistance
of * must be greater than 1kW or the capacitance B a n k 0 , 1 B a n k 0 B a n k 1
of * must be less than 1nF. 0 0 H IA R 0 3 0 H U n u s e d
0 1 H M P 0 3 1 H U n u s e d
0 2 H IA R 1 3 2 H U n u s e d
0 3 H M P 1 3 3 H U n u s e d
Programmer Pin MCU Pins 0 4 H B P C P 0 C
3 4 H
RES PB0 0 5 H A C C 3 5 H C P 1 C
0 6 H P C L 3 6 H S IM C 0
DATA PA0 0 7 H T B L P 3 7 H S IM C 1
0 8 H T B L H 3 8 H S IM D
CLK PA2 0 9 H T B H P 3 9 H S IM A /S IM C 2
0 A H S T A T U S 3 A H T M 0 C 0
Programmer and MCU Pins 0 B H S M O D 3 B H T M 0 C 1
0 C H L V D C 3 C H T M 0 D L
0 D H IN T E G 3 D H T M 0 D H
RAM Data Memory 0 E H W D T C 3 E H T M 0 A L
0 F H T B C 3 F H T M 0 A H
The Data Memory is a volatile area of 8-bit wide RAM in- 1 0 H IN T C 0 4 0 H U n u s e d E E C
ternal memory and is the location where temporary in- 1 1 H IN T C 1 4 1 H E E A
1 2 H IN T C 2 4 2 H E E D
formation is stored. 1 3 H U n u s e d 4 3 H T M P C 0
1 4 H M F I0 4 4 H U n u s e d
Structure 1 5 H M F I1 4 5 H U n u s e d
1 6 H M F I2 4 6 H U n u s e d
Divided into two sections, the first of these is an area of 1 7 H U n u s e d 4 7 H U n u s e d
RAM, known as the Special Function Data Memory. 1 8 H P A W U 4 8 H T M 1 C 0
1 9 H P A P U 4 9 H T M 1 C 1
Here are located registers which are necessary for cor- 1 A H P A 4 A H U n u s e d
rect operation of the device. Many of these registers can 1 B H P A C 4 B H T M 1 D L
be read from and written to directly under program con- 1 C H P B P U 4 C H T M 1 D H
1 D H P B 4 D H T M 1 A L
trol, however, some remain protected from user manipu- 1 E H P B C 4 E H T M 1 A H
lation. 1 F H P C P U 4 F H U n u s e d
2 0 H P C 5 0 H U n u s e d
2 1 H P C C 5 1 H U n u s e d
2 2 H U n u s e d 5 2 H U n u s e d
2 3 H U n u s e d 5 3 H U n u s e d
2 4 H U n u s e d 5 4 H U n u s e d
2 5 H U n u s e d 5 5 H U n u s e d
2 6 H U n u s e d 5 6 H U n u s e d
2 7 H U n u s e d 5 7 H U n u s e d
2 8 H U n u s e d 5 8 H U n u s e d
2 9 H U n u s e d 5 9 H U n u s e d
2 A H U n u s e d 5 A H U n u s e d
2 B H U n u s e d 5 B H U n u s e d
2 C H U n u s e d 5 C H U n u s e d
2 D H U n u s e d 5 D H U n u s e d
2 E H U n u s e d 5 E H S C O M C
2 F H U n u s e d 5 F H U n u s e d
B a n k 0 , 1 , 2 B a n k 0 , 2 B a n k 1 B a n k 0 , 1 B a n k 0 B a n k 1
0 0 H IA R 0 3 0 H U n u s e d 0 0 H IA R 0 4 0 H U n u s e d E E C
0 1 H M P 0 3 1 H U n u s e d 0 1 H M P 0 4 1 H E E A
0 2 H IA R 1 3 2 H U n u s e d 0 2 H IA R 1 4 2 H E E D
0 3 H M P 1 3 3 H U n u s e d 0 3 H M P 1 4 3 H T M P C 0
0 4 H B P 3 4 H C P 0 C 0 4 H B P 4 4 H T M P C 1
0 5 H A C C 3 5 H C P 1 C 0 5 H A C C 4 5 H P R M 0
0 6 H P C L 3 6 H S IM C 0 0 6 H P C L 4 6 H P R M 1
0 7 H T B L P 3 7 H S IM C 1 0 7 H T B L P 4 7 H P R M 2
0 8 H T B L H 3 8 H S IM D 0 8 H T B L H 4 8 H T M 1 C 0
0 9 H T B H P 3 9 H S IM A /S IM C 2 0 9 H T B H P 4 9 H T M 1 C 1
0 A H S T A T U S 3 A H T M 0 C 0 0 A H S T A T U S 4 A H T M 1 C 2
0 B H S M O D 3 B H T M 0 C 1 0 B H S M O D 4 B H T M 1 D L
0 C H L V D C 3 C H T M 0 D L 0 C H L V D C 4 C H T M 1 D H
0 D H IN T E G 3 D H T M 0 D H 0 D H IN T E G 4 D H T M 1 A L
0 E H W D T C 3 E H T M 0 A L 0 E H W D T C 4 E H T M 1 A H
0 F H T B C 3 F H T M 0 A H 0 F H T B C 4 F H T M 1 B L
1 0 H IN T C 0 4 0 H U n u s e d E E C 1 0 H IN T C 0 5 0 H T M 1 B H
1 1 H IN T C 1 4 1 H E E A 1 1 H IN T C 1 5 1 H T M 2 C 0
1 2 H IN T C 2 4 2 H E E D 1 2 H IN T C 2 5 2 H T M 2 C 1
1 3 H U n u s e d 4 3 H T M P C 0 1 3 H U n u s e d 5 3 H T M 2 D L
1 4 H M F I0 4 4 H U n u s e d 1 4 H M F I0 5 4 H T M 2 D H
1 5 H M F I1 4 5 H P R M 0 1 5 H M F I1 5 5 H T M 2 A L
1 6 H M F I2 4 6 H U n u s e d 1 6 H M F I2 5 6 H T M 2 A H
1 7 H U n u s e d 4 7 H U n u s e d 1 7 H U n u s e d 5 7 H T M 2 R P
1 8 H P A W U 4 8 H T M 1 C 0 1 8 H P A W U 5 8 H U n u s e d
1 9 H P A P U 4 9 H T M 1 C 1 1 9 H P A P U 5 9 H U n u s e d
1 A H P A 4 A H T M 1 C 2 1 A H P A 5 A H U n u s e d
1 B H P A C 4 B H T M 1 D L 1 B H P A C 5 B H U n u s e d
1 C H P B P U 4 C H T M 1 D H 1 C H P B P U 5 C H U n u s e d
1 D H P B 4 D H T M 1 A L 1 D H P B 5 D H U n u s e d
1 E H P B C 4 E H T M 1 A H 1 E H P B C 5 E H S C O M C
1 F H P C P U 4 F H T M 1 B L 1 F H P C P U 5 F H U n u s e d
2 0 H P C 5 0 H T M 1 B H 2 0 H P C 6 0 H U n u s e d
2 1 H P C C 5 1 H U n u s e d 2 1 H P C C 6 1 H U n u s e d
2 2 H U n u s e d 5 2 H U n u s e d 2 2 H P D P U 6 2 H U n u s e d
2 3 H U n u s e d 5 3 H U n u s e d 2 3 H P D 6 3 H U n u s e d
2 4 H U n u s e d 5 4 H U n u s e d 2 4 H P D C 6 4 H U n u s e d
2 5 H U n u s e d 5 5 H U n u s e d 2 5 H P E P U 6 5 H U n u s e d
2 6 H U n u s e d 5 6 H U n u s e d 2 6 H P E 6 6 H U n u s e d
2 7 H U n u s e d 5 7 H U n u s e d 2 7 H P E C 6 7 H U n u s e d
2 8 H U n u s e d 5 8 H U n u s e d 2 8 H P F P U 6 8 H U n u s e d
2 9 H U n u s e d 5 9 H U n u s e d 2 9 H P F 6 9 H U n u s e d
2 A H U n u s e d 5 A H U n u s e d 2 A H P F C 6 A H U n u s e d
2 B H U n u s e d 5 B H U n u s e d 2 B H U n u s e d 6 B H U n u s e d
2 C H U n u s e d 5 C H U n u s e d 2 C H U n u s e d 6 C H U n u s e d
2 D H U n u s e d 5 D H U n u s e d 2 D H U n u s e d 6 D H U n u s e d
2 E H U n u s e d 5 E H S C O M C 2 E H U n u s e d 6 E H U n u s e d
2 F H U n u s e d 5 F H U n u s e d 2 F H U n u s e d 6 F H U n u s e d
3 0 H U n u s e d 7 0 H U n u s e d
HT68F30 Special Purpose Data Memory 3 1 H U n u s e d 7 1 H U n u s e d
3 2 H U n u s e d 7 2 H U n u s e d
3 3 H U n u s e d 7 3 H U n u s e d
3 4 H C P 0 C 7 4 H U n u s e d
3 5 H C P 1 C 7 5 H U n u s e d
3 6 H S IM C 0 7 6 H U n u s e d
3 7 H S IM C 1 7 7 H U n u s e d
3 8 H S IM D 7 8 H U n u s e d
3 9 H S IM A /S IM C 2 7 9 H U n u s e d
3 A H T M 0 C 0 7 A H U n u s e d
3 B H T M 0 C 1 7 B H U n u s e d
3 C H T M 0 D L 7 C H U n u s e d
3 D H T M 0 D H 7 D H U n u s e d
3 E H T M 0 A L 7 E H U n u s e d
3 F H T M 0 A H 7 F H U n u s e d
B a n k 0 , 1 , 2 B a n k 0 , 2 B a n k 1 B a n k 0 , 1 , 2 , 3 , 4 B a n k 0 , 2 , 3 , 4 B a n k 1
0 0 H IA R 0 4 0 H U n u s e d E E C 0 0 H IA R 0 4 0 H U n u s e d E E C
0 1 H M P 0 4 1 H E E A 0 1 H M P 0 4 1 H E E A
0 2 H IA R 1 4 2 H E E D 0 2 H IA R 1 4 2 H E E D
0 3 H M P 1 4 3 H T M P C 0 0 3 H M P 1 4 3 H T M P C 0
0 4 H B P 4 4 H T M P C 1 0 4 H B P 4 4 H T M P C 1
0 5 H A C C 4 5 H P R M 0 0 5 H A C C 4 5 H P R M 0
0 6 H P C L 4 6 H P R M 1 0 6 H P C L 4 6 H P R M 1
0 7 H T B L P 4 7 H P R M 2 0 7 H T B L P 4 7 H P R M 2
0 8 H T B L H 4 8 H T M 1 C 0 0 8 H T B L H 4 8 H T M 1 C 0
0 9 H T B H P 4 9 H T M 1 C 1 0 9 H T B H P 4 9 H T M 1 C 1
0 A H S T A T U S 4 A H T M 1 C 2 0 A H S T A T U S 4 A H T M 1 C 2
0 B H S M O D 4 B H T M 1 D L 0 B H S M O D 4 B H T M 1 D L
0 C H L V D C 4 C H T M 1 D H 0 C H L V D C 4 C H T M 1 D H
0 D H IN T E G 4 D H T M 1 A L 0 D H IN T E G 4 D H T M 1 A L
0 E H W D T C 4 E H T M 1 A H 0 E H W D T C 4 E H T M 1 A H
0 F H T B C 4 F H T M 1 B L 0 F H T B C 4 F H T M 1 B L
1 0 H IN T C 0 5 0 H T M 1 B H 1 0 H IN T C 0 5 0 H T M 1 B H
1 1 H IN T C 1 5 1 H T M 2 C 0 1 1 H IN T C 1 5 1 H T M 2 C 0
1 2 H IN T C 2 5 2 H T M 2 C 1 1 2 H IN T C 2 5 2 H T M 2 C 1
1 3 H U n u s e d 5 3 H T M 2 D L 1 3 H IN T C 3 5 3 H T M 2 D L
1 4 H M F I0 5 4 H T M 2 D H 1 4 H M F I0 5 4 H T M 2 D H
1 5 H M F I1 5 5 H T M 2 A L 1 5 H M F I1 5 5 H T M 2 A L
1 6 H M F I2 5 6 H T M 2 A H 1 6 H M F I2 5 6 H T M 2 A H
1 7 H M F I3 5 7 H T M 2 R P 1 7 H M F I3 5 7 H T M 2 R P
1 8 H P A W U 5 8 H T M 3 C 0 1 8 H P A W U 5 8 H T M 3 C 0
1 9 H P A P U 5 9 H T M 3 C 1 1 9 H P A P U 5 9 H T M 3 C 1
1 A H P A 5 A H T M 3 D L 1 A H P A 5 A H T M 3 D L
1 B H P A C 5 B H T M 3 D H 1 B H P A C 5 B H T M 3 D H
1 C H P B P U 5 C H T M 3 A L 1 C H P B P U 5 C H T M 3 A L
1 D H P B 5 D H T M 3 A H 1 D H P B 5 D H T M 3 A H
1 E H P B C 5 E H S C O M C 1 E H P B C 5 E H S C O M C
1 F H P C P U 5 F H U n u s e d 1 F H P C P U 5 F H U n u s e d
2 0 H P C 6 0 H U n u s e d 2 0 H P C 6 0 HU n u s e d
2 1 H P C C 6 1 H U n u s e d 2 1 H P C C 6 1 HU n u s e d
2 2 H P D P U 6 2 H U n u s e d 2 2 H P D P U 6 2 HU n u s e d
2 3 H P D 6 3 H U n u s e d 2 3 H P D 6 3 HU n u s e d
2 4 H P D C 6 4 H U n u s e d 2 4 H P D C 6 4 HU n u s e d
2 5 H P E P U 6 5 H U n u s e d 2 5 H P E P U 6 5 HU n u s e d
2 6 H P E 6 6 H U n u s e d 2 6 H P E 6 6 H U n u s e d
2 7 H P E C 6 7 H U n u s e d 2 7 H P E C 6 7 H U n u s e d
2 8 H P F P U 6 8 H U n u s e d 2 8 H P F P U 6 8 H U n u s e d
2 9 H P F 6 9 H U n u s e d 2 9 H P F 6 9 H U n u s e d
2 A H P F C 6 A H U n u s e d 2 A H P F C 6 A H U n u s e d
2 B H U n u s e d 6 B H U n u s e d 2 B H P G P U 6 B H U n u s e d
2 C H U n u s e d 6 C H U n u s e d 2 C H P G 6 C H U n u s e d
2 D H U n u s e d 6 D H U n u s e d 2 D H P G C 6 D H U n u s e d
2 E H U n u s e d 6 E H U n u s e d 2 E H U n u s e d 6 E H U n u s e d
2 F H U n u s e d 6 F H U n u s e d 2 F H U n u s e d 6 F H U n u s e d
3 0 H U n u s e d 7 0 H U n u s e d 3 0 H U n u s e d 7 0 H U n u s e d
3 1 H U n u s e d 7 1 H U n u s e d 3 1 H U n u s e d 7 1 H U n u s e d
3 2 H U n u s e d 7 2 H U n u s e d 3 2 H U n u s e d 7 2 H U n u s e d
3 3 H U n u s e d 7 3 H U n u s e d 3 3 H U n u s e d 7 3 H U n u s e d
3 4 H C P 0 C 7 4 H U n u s e d 3 4 H C P 0 C 7 4 H U n u s e d
3 5 H C P 1 C 7 5 H U n u s e d 3 5 H C P 1 C 7 5 H U n u s e d
3 6 H S IM C 0 7 6 H U n u s e d 3 6 H S IM C 0 7 6 H U n u s e d
3 7 H S IM C 1 7 7 H U n u s e d 3 7 H S IM C 1 7 7 H U n u s e d
3 8 H S IM D 7 8 H U n u s e d 3 8 H S IM D 7 8 H U n u s e d
3 9 H S IM A /S IM C 2 7 9 H U n u s e d 3 9 H S IM A /S IM C 2 7 9 H U n u s e d
3 A H T M 0 C 0 7 A H U n u s e d 3 A H T M 0 C 0 7 A H U n u s e d
3 B H T M 0 C 1 7 B H U n u s e d 3 B H T M 0 C 1 7 B H U n u s e d
3 C H T M 0 D L 7 C H U n u s e d 3 C H T M 0 D L 7 C H U n u s e d
3 D H T M 0 D H 7 D H U n u s e d 3 D H T M 0 D H 7 D H U n u s e d
3 E H T M 0 A L 7 E H U n u s e d 3 E H T M 0 A L 7 E H U n u s e d
3 F H T M 0 A H 7 F H U n u s e d 3 F H T M 0 A H 7 F H U n u s e d
HT68F50 Special Purpose Data Memory HT68F60 Special Purpose Data Memory
The second area of Data Memory is known as the Gen- pair, IAR0 and MP0 can together access data from Bank
eral Purpose Data Memory, which is reserved for gen- 0 while the IAR1 and MP1 register pair can access data
eral purpose use. All locations within this area are read from any bank. As the Indirect Addressing Registers are
and write accessible under program control. not physically implemented, reading the Indirect Ad-
The overall Data Memory is subdivided into several dressing Registers indirectly will return a result of 00H
banks, the structure of which depends upon the device and writing to the registers indirectly will result in no op-
chosen. The Special Purpose Data Memory registers eration.
are accessible in all banks, with the exception of the
Memory Pointers - MP0, MP1
EEC register at address 40H, which is only accessible in
Bank 1. Switching between the different Data Memory Two Memory Pointers, known as MP0 and MP1 are pro-
banks is achieved by setting the Bank Pointer to the cor- vided. These Memory Pointers are physically imple-
rect value. The start address of the Data Memory for all mented in the Data Memory and can be manipulated in
devices is the address 00H. the same way as normal registers providing a conve-
nient way with which to address and track data. When
Special Function Register Description any operation to the relevant Indirect Addressing Regis-
ters is carried out, the actual address that the
Most of the Special Function Register details will be de- microcontroller is directed to, is the address specified by
scribed in the relevant functional section, however sev- the related Memory Pointer. MP0, together with Indirect
eral registers require a separate description in this Addressing Register, IAR0, are used to access data
section. from Bank 0, while MP1 and IAR1 are used to access
data from all banks according to BP register. Direct Ad-
Indirect Addressing Registers - IAR0, IAR1 dressing can only be used with Bank 0, all other Banks
The Indirect Addressing Registers, IAR0 and IAR1, al- must be addressed indirectly using MP1 and IAR1. Note
though having their locations in normal RAM register that for the HT68F20 and HT68F30 devices, bit 7 of the
space, do not actually physically exist as normal regis- Memory Pointers is not required to address the full
ters. The method of indirect addressing for RAM data memory space. When bit 7 of the Memory Pointers for
manipulation uses these Indirect Addressing Registers HT68F20 and HT68F30 devices is read, a value of 1
and Memory Pointers, in contrast to direct memory ad- will be returned.
dressing, where the actual memory address is speci-
The following example shows how to clear a section of
fied. Actions on the IAR0 and IAR1 registers will result in
four Data Memory locations already defined as loca-
no actual read or write operation to these registers but
tions adres1 to adres4.
rather to the memory location specified by their corre-
sponding Memory Pointers, MP0 or MP1. Acting as a
The important point to note here is that in the example shown above, no reference is made to specific RAM addresses.
The Data Memory is initialised to Bank 0 after a reset, As both the Program Memory and Data Memory share
except for a WDT time-out reset in the Power Down the same Bank Pointer Register, care must be taken
Mode, in which case, the Data Memory bank remains during programming.
Bit
Device
7 6 5 4 3 2 1 0
HT68F20
DMBP0
HT68F40
HT68F30
DMBP1 DMBP0
HT68F50
HT68F60 PMBP0 DMBP2 DMBP1 DMBP0
BP Registers List
BP Register
HT68F20/HT68F40
Bit 7 6 5 4 3 2 1 0
Name DMBP0
R/W R/W
POR 0
HT68F30/HT68F50
Bit 7 6 5 4 3 2 1 0
Name DMBP1 DMBP0
R/W R/W R/W
POR 0 0
HT68F60
Bit 7 6 5 4 3 2 1 0
Name PMBP0 DMBP2 DMBP1 DMBP0
R/W R/W R/W R/W R/W
POR 0 0 0 0
Accumulator - ACC for example using the INC or DEC instructions, al-
The Accumulator is central to the operation of any lowing for easy table data pointing and reading. TBLH is
microcontroller and is closely related with operations the location where the high order byte of the table data is
carried out by the ALU. The Accumulator is the place stored after a table read data instruction has been exe-
where all intermediate results from the ALU are stored. cuted. Note that the lower order table data byte is trans-
Without the Accumulator it would be necessary to write ferred to a user defined location.
the result of each calculation or logical operation such
Status Register - STATUS
as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads. This 8-bit register contains the zero flag (Z), carry flag
Data transfer operations usually involve the temporary (C), auxiliary carry flag (AC), overflow flag (OV), power
storage function of the Accumulator; for example, when down flag (PDF), and watchdog time-out flag (TO).
transferring data between one user defined register and These arithmetic/logical operation and system manage-
another, it is necessary to do this by passing the data ment flags are used to record the status and operation of
through the Accumulator as no direct transfer between the microcontroller.
two registers is permitted. With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
Program Counter Low Register - PCL
other registers. Any data written into the status register
To provide additional program control functions, the low will not change the TO or PDF flag. In addition, opera-
byte of the Program Counter is made accessible to pro- tions related to the status register may give different re-
grammers by locating it within the Special Purpose area sults due to the different instruction operations. The TO
of the Data Memory. By manipulating this register, direct flag can be affected only by a system power-up, a WDT
jumps to other program locations are easily imple- time-out or by executing the CLR WDT or HALT in-
mented. Loading a value directly into this PCL register struction. The PDF flag is affected only by executing the
will cause a jump to the specified Program Memory lo- HALT or CLR WDT instruction or during a system
cation, however, as the register is only 8-bit wide, only power-up.
jumps within the current Program Memory page are per-
The Z, OV, AC and C flags generally reflect the status of
mitted. When such operations are used, note that a
the latest operations.
dummy cycle will be inserted.
C is set if an operation results in a carry during an ad-
Look-up Table Registers - TBLP, TBHP, TBLH dition operation or if a borrow does not take place dur-
ing a subtraction operation; otherwise C is cleared. C
These three special function registers are used to con- is also affected by a rotate through carry instruction.
trol operation of the look-up table which is stored in the
AC is set if an operation results in a carry out of the
Program Memory. TBLP and TBHP are the table pointer low nibbles in addition, or no borrow from the high nib-
and indicates the location where the table data is lo- ble into the low nibble in subtraction; otherwise AC is
cated. Their value must be setup before any table read cleared.
commands are executed. Their value can be changed,
Z is set if the result of an arithmetic or logical operation In addition, on entering an interrupt sequence or execut-
is zero; otherwise Z is cleared. ing a subroutine call, the status register will not be
OV is set if an operation results in a carry into the high- pushed onto the stack automatically. If the contents of
est-order bit but not a carry out of the highest-order bit, the status registers are important and if the subroutine
or vice versa; otherwise OV is cleared. can corrupt the status register, precautions must be
PDF is cleared by a system power-up or executing the taken to correctly save it.
CLR WDT instruction. PDF is set by executing the
HALT instruction.
TO is cleared by a system power-up or executing the
CLR WDT or HALT instruction. TO is set by a
WDT time-out.
STATUS Register
Bit 7 6 5 4 3 2 1 0
Name TO PDF OV Z AC C
R/W R R R/W R/W R/W R/W
POR 0 0 x x x x
x unknown
Bit 7, 6 Unimplemented, read as 0
Bit 5 TO: Watchdog Time-Out flag
0: After power up or executing the CLR WDT or HALT instruction
1: A watchdog time-out occurred.
Bit 4 PDF: Power down flag
0: After power up or executing the CLR WDT instruction
1: By executing the HALT instruction
Bit 3 OV: Overflow flag
0: no overflow
1: an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa.
Bit 2 Z: Zero flag
0: The result of an arithmetic or logical operation is not zero
1: The result of an arithmetic or logical operation is zero
Bit 1 AC: Auxiliary flag
0: no auxiliary carry
1: an operation results in a carry out of the low nibbles in addition, or no borrow from the
high nibble into the low nibble in subtraction
Bit 0 C: Carry flag
0: no carry-out
1: an operation results in a carry during an addition operation or if a borrow does not take place
during a subtraction operation
C is also affected by a rotate through carry instruction.
Bit
Name
7 6 5 4 3 2 1 0
EEA D4 D3 D2 D1 D0
EED D7 D6 D5 D4 D3 D2 D1 D0
EEC WREN WR RDEN RD
HT68F30
Bit
Name
7 6 5 4 3 2 1 0
EEA D5 D4 D3 D2 D1 D0
EED D7 D6 D5 D4 D3 D2 D1 D0
EEC WREN WR RDEN RD
HT68F40
Bit
Name
7 6 5 4 3 2 1 0
EEA D6 D5 D4 D3 D2 D1 D0
EED D7 D6 D5 D4 D3 D2 D1 D0
EEC WREN WR RDEN RD
HT68F50/HT68F60
Bit
Name
7 6 5 4 3 2 1 0
EEA D7 D6 D5 D4 D3 D2 D1 D0
EED D7 D6 D5 D4 D3 D2 D1 D0
EEC WREN WR RDEN RD
EEA Register
HT68F20
Bit 7 6 5 4 3 2 1 0
Name D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W
POR x x x x x
x unknown
Bit 7 ~ 5 Unimplemented, read as 0
Bit 4 ~ 0 Data EEPROM address
Data EEPROM address bit 4 ~ bit 0
HT68F30
Bit 7 6 5 4 3 2 1 0
Name D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W
POR x x x x x x
x unknown
Bit 7 ~ 6 Unimplemented, read as 0
Bit 5 ~ 0 Data EEPROM address
Data EEPROM address bit 5 ~ bit 0
HT68F40
Bit 7 6 5 4 3 2 1 0
Name D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
POR x x x x x x x
x unknown
Bit 7 Unimplemented, read as 0
Bit 6 ~ 0 Data EEPROM address
Data EEPROM address bit 6 ~ bit 0
HT68F50/HT68F60
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR x x x x x x x x
x unknown
Bit 7 ~ 0 Data EEPROM address
Data EEPROM address bit 7 ~ bit 0
Bit 7 6 5 4 3 2 1 0
Name WREN WR RDEN RD
R/W R/W R/W R/W R/W
POR 0 0 0 0
Reading Data from the EEPROM ter and the data placed in the EED register. If the WR bit
To read data from the EEPROM, the read enable bit, in the EEC register is now set high, an internal write cy-
RDEN, in the EEC register must first be set high to en- cle will then be initiated. Setting the WR bit high will not
able the read function. The EEPROM address of the initiate a write cycle if the WREN bit has not been set. As
data to be read must then be placed in the EEA register. the EEPROM write cycle is controlled using an internal
If the RD bit in the EEC register is now set high, a read t i m e r w h o se o p e r a t i o n i s a syn ch r o n o u s t o
cycle will be initiated. Setting the RD bit high will not initi- microcontroller system clock, a certain time will elapse
ate a read operation if the RDEN bit has not been set. before the data will have been written into the EEPROM.
When the read cycle terminates, the RD bit will be auto- Detecting when the write cycle has finished can be im-
matically cleared to zero, after which the data can be plemented either by polling the WR bit in the EEC regis-
read from the EED register. The data will remain in the ter or by using the EEPROM interrupt. When the write
EED register until another read or write operation is exe- cycle terminates, the WR bit will be automatically
cuted. The application program can poll the RD bit to de- cleared to zero by the microcontroller, informing the
termine when the data is valid for reading. user that the data has been written to the EEPROM. The
application program can therefore poll the WR bit to de-
Writing Data to the EEPROM termine when the write cycle has ended.
Write Protection DEF request flag and its associated multi-function inter-
Protection against inadvertent write operation is pro- rupt request flag will both be set. If the global, EEPROM
vided in several ways. After the device is powered-on and Multi-function interrupts are enabled and the stack
the Write Enable bit in the control register will be cleared is not full, a jump to the associated Multi-function Inter-
preventing any write operations. Also at power-on the rupt vector will take place. When the interrupt is serviced
Bank Pointer, BP, will be reset to zero, which means that only the Multi-function interrupt flag will be automatically
Data Memory Bank 0 will be selected. As the EEPROM reset, the EEPROM interrupt flag must be manually re-
control register is located in Bank 1, this adds a further set by the application program. More details can be ob-
measure of protection against spurious write opera- tained in the Interrupt section.
tions. During normal program operation, ensuring that
Programming Considerations
the Write Enable bit in the control register is cleared will
safeguard against incorrect write operations. Care must be taken that data is not inadvertently written
to the EEPROM. Protection can be enhanced by ensur-
EEPROM Interrupt ing that the Write Enable bit is normally cleared to zero
The EEPROM write or read interrupt is generated when when not writing. Also the Bank Pointer could be nor-
an EEPROM write or read cycle has ended. The mally cleared to zero as this would inhibit access to
EEPROM interrupt must first be enabled by setting the Bank 1 where the EEPROM control register exist. Al-
DEE bit in the relevant interrupt register. However as the though certainly not necessary, consideration might be
EEPROM is contained within a Multi-function Interrupt, given in the application program to the checking of the
the associated multi-function interrupt enable bit must validity of new write data by a simple read back process.
also be set. When an EEPROM write cycle ends, the
Programming Examples
Reading data from the EEPROM - polling method
MOV A, EEPROM_ADRES ; user defined address
MOV EEA, A
MOV A, 040H ; setup memory pointer MP1
MOV MP1, A ; MP1 points to EEC register
MOV A, 01H ; setup Bank Pointer
MOV BP, A
SET IAR1.1 ; set RDEN bit, enable read operations
SET IAR1.0 ; start Read Cycle - set RD bit
BACK:
SZ IAR1.0 ; check for read cycle end
JMP BACK
CLR IAR1 ; disable EEPROM read/write
CLR BP
MOV A, EEDATA ; move read data to register
MOV READ_DATA, A
Oscillator
Various oscillator options offer the user a wide range of
functions according to their various application require- Type Name Freq. Pins
ments. The flexible features of the oscillator functions
400kHz~ OSC1/
ensure that the best optimisation can be achieved in External Crystal HXT
20MHz OSC2
terms of speed and power saving. Oscillator selections
and operation are selected through a combination of External RC ERC 8MHz OSC1
configuration options and registers. Internal High
HIRC 4, 8 or 12MHz
Speed RC
Oscillator Overview
External Low XT1/
In addition to being the source of the main system clock LXT 32.768kHz
Speed Crystal XT2
the oscillators also provide clock sources for the Watch-
Internal Low
dog Timer and Time Base Interrupts. External oscilla- LIRC 32kHz
Speed RC
tors requiring some external components as well as fully
integrated internal oscillators, requiring no external Oscillator Types
components, are provided to form a wide range of both
fast and slow system oscillators. All oscillator options System Clock Configurations
are selected through the configuration options. The There are five methods of generating the system clock,
higher frequency oscillators provide higher performance three high speed oscillators and two low speed oscilla-
but carry with it the disadvantage of higher power re- tors. The high speed oscillators are the external crystal/
quirements, while the opposite is of course true for the ceramic oscillator, external RC network oscillator and
lower frequency oscillators. With the capability of dy- the internal 4MHz, 8MHz or 12MHz RC oscillator. The
namically switching between fast and slow system two low speed oscillators are the internal 32kHz RC os-
clock, the device has the flexibility to optimize the perfor- cillator and the external 32.768kHz crystal oscillator. Se-
mance/power ratio, a feature especially important in lecting whether the low or high speed oscillator is used
power sensitive portable applications. as the system oscillator is implemented using the
HLCLK bit and CKS2 ~ CKS0 bits in the SMOD register
and as the system clock can be dynamically selected.
HXT
fH
ERC 6-stage Prescaler
fH/2
HIRC fH /4
High Speed Oscillation
fH/8
Configuration Option fH/16
Low Speed Oscillation fH/32
fH/64
LIRC
fL fSY S
LXT
HLCLK,
CKS2~CKS0 bits
Low Speed Oscillation
fS UB
Configuration Option
The actual source clock used for each of the high speed termines the oscillation frequency; the external
and low speed oscillators is chosen via configuration capacitor has no influence over the frequency and is
options. The frequency of the slow speed or high speed connected for stability purposes only. Device trimming
system clock is also determined using the HLCLK bit during the manufacturing process and the inclusion of
and CKS2 ~ CKS0 bits in the SMOD register. Note that internal frequency compensation circuits are used to en-
two oscillator selections must be made namely one high sure that the influence of the power supply voltage, tem-
speed and one low speed system oscillators. It is not perature and process variations on the oscillation
possible to choose a no-oscillator selection for either the frequency are minimised. As a resistance/frequency ref-
high or low speed oscillator. erence point, it can be noted that with an external 120kW
resistor connected and with a 5V voltage power supply
External Crystal/ Ceramic Oscillator - HXT and temperature of 25C degrees, the oscillator will
The External Crystal/ Ceramic System Oscillator is one have a frequency of 8MHz within a tolerance of 2%.
of the high frequency oscillator choices, which is se- Here only the OSC1 pin is used, which is shared with I/O
lected via configuration option. For most crystal oscilla- pin PB1, leaving pin PB2 free for use as a normal I/O
tor configurations, the simple connection of a crystal pin.
across OSC1 and OSC2 will create the necessary V D D
phase shift and feedback for oscillation, without requir-
ing external capacitors. However, for some crystal types
R O S C
and frequencies, to ensure oscillation, it may be neces-
sary to add two small value capacitors, C1 and C2. O S C 1
Using a ceramic resonator will usually require two small 4 7 0 p F
value capacitors, C1 and C2, to be connected as shown
for oscillation to occur. The values of C1 and C2 should
External RC Oscillator - ERC
be selected in consultation with the crystal or resonator
manufacturers specification. Internal RC Oscillator - HIRC
When the microcontroller enters the SLEEP or IDLE LXT Oscillator Low Power Function
Mode, the system clock is switched off to stop The LXT oscillator can function in one of two modes, the
microcontroller activity and to conserve power. How- Quick Start Mode and the Low Power Mode. The mode
ever, in many microcontroller applications it may be nec- selection is executed using the LXTLP bit in the TBC
essary to keep the internal timers operational even register.
when the microcontroller is in the SLEEP or IDLE Mode.
To do this, another clock, independent of the system LXTLP Bit LXT Mode
clock, must be provided. 0 Quick Start
However, for some crystals, to ensure oscillation and 1 Low-power
accurate frequency generation, it is necessary to add
After power on the LXTLP bit will be automatically
two small value external capacitors, C1 and C2. The ex-
cleared to zero ensuring that the LXT oscillator is in the
act values of C1 and C2 should be selected in consulta-
Quick Start operating mode. In the Quick Start Mode the
tion with the crystal or resonator manufacturers
LXT oscillator will power up and stabilise quickly. How-
specification. The external parallel feedback resistor,
ever, after the LXT oscillator has fully powered up it can
Rp, is required.
be placed into the Low-power mode by setting the
Some configuration options determine if the XT1/XT2 LXTLP bit high. The oscillator will continue to run but
pins are used for the LXT oscillator or as I/O pins. with reduced current consumption, as the higher current
If the LXT oscillator is not used for any clock source, consumption is only required during the LXT oscillator
the XT1/XT2 pins can be used as normal I/O pins. start-up. In power sensitive applications, such as battery
If the LXT oscillator is used for any clock source, the applications, where power consumption must be kept to
32.768kHz crystal should be connected to the a minimum, it is therefore recommended that the appli-
XT1/XT2 pins. cation program sets the LXTLP bit high about 2 seconds
after power-on.
C 1 In te r n a l
X T 1 O s c illa to r It should be noted that, no matter what condition the
C ir c u it LXTLP bit is set to, the LXT oscillator will always func-
R p
In te rn a l R C tion normally, the only difference is that it will take more
3 2 .7 6 8 O s c illa to r
k H z time to start up if in the Low-power mode.
X T 2 T o in te r n a l
c ir c u its Internal 32kHz Oscillator - LIRC
C 2
The Internal 32kHz System Oscillator is one of the low
N o te : 1 . R p , C 1 a n d C 2 a r e r e q u ir e d . frequency oscillator choices, which is selected via con-
2 . A lth o u g h n o t s h o w n p in s h a v e a figuration option. It is a fully integrated RC oscillator with
p a r a s itic c a p a c ita n c e o f a r o u n d 7 p F . a typical frequency of 32kHz at 5V, requiring no external
External LXT Oscillator components for its implementation. Device trimming
during the manufacturing process and the inclusion of
LXT Oscillator C1 and C2 Values internal frequency compensation circuits are used to en-
Crystal Frequency C1 C2 sure that the influence of the power supply voltage, tem-
perature and process variations on the oscillation
32.768kHz 10pF 10pF
frequency are minimised. As a result, at a power supply
Note: 1. C1 and C2 values are for guidance only. of 5V and at a temperature of 25C degrees, the fixed
2. RP=5M~10MW is recommended. oscillation frequency of 32kHz will have a tolerance
32.768kHz Crystal Recommended Capacitor Values within 10%.
Supplementary Oscillators
The low speed oscillators, in addition to providing a sys-
tem clock source are also used to provide a clock
source to two other device functions. These are the
Watchdog Timer and the Time Base Interrupts.
HXT
fH
ERC 6-stage Prescaler
fH /2
HIRC fH /4
High Speed Oscillation
fH/8
Configuration Option fH/16
Low Speed Oscillation f H/32
fH /64
LIRC
fL fS YS
LXT
HLCLK,
CKS2~CKS0 bits
Low Speed Oscillation fSUB
Configuration Option
fTB C
fTB
Time Base
fSYS /4
TBCK
fS UB
fS WDT
fSYS/ 4
Configuration Option
Note: When the system clock source fSYS is switched to fL from fH, the high speed oscillation will stop to conserve the
power. Thus there is no fH~fH/64 for peripheral circuit to use.
Together with fSYS/4 it is also used as one of the clock istics and which can be chosen according to the specific
sources for the Watchdog timer. The fTBC clock is used performance and power requirements of the applica-
as a source for the Time Base interrupt functions and for tion. There are two modes allowing normal operation of
the TMs. the microcontroller, the NORMAL Mode and SLOW
Mode. The remaining four modes, the SLEEP0,
System Operation Modes SLEEP1, IDLE0 and IDLE1 Mode are used when the
There are six different modes of operation for the microcontroller CPU is switched off to conserve power.
microcontroller, each one with its own special character-
Description
Operation Mode
CPU fSYS fSUB fS fTBC
NORMAL Mode On fH~ fH/64 On On On
SLOW Mode On fL On On On
IDLE0 Mode Off Off On On/Off On
IDLE1 Mode Off On On On On
SLEEP0 Mode Off Off Off Off Off
SLEEP1 Mode Off Off On On Off
Control Register
A single register, SMOD, is used for overall control of the internal clocks within the device.
SMOD Register
Bit 7 6 5 4 3 2 1 0
Name CKS2 CKS1 CKS0 FSTEN LTO HTO IDLEN HLCLK
R/W R/W R/W R/W R/W R R R/W R/W
POR 0 0 0 0 0 0 1 1
Fast Wake-up able function is controlled using the FSTEN bit in the
To minimise power consumption the device can enter SMOD register.
the SLEEP or IDLE0 Mode, where the system clock If the HXT oscillator is selected as the NORMAL Mode
source to the device will be stopped. However when the system clock, and if the Fast Wake-up function is en-
device is woken up again, it can take a considerable abled, then it will take one to two tSUB clock cycles of the
time for the original system oscillator to restart, stabilise LIRC or LXT oscillator for the system to wake-up. The
and allow normal operation to resume. To ensure the system will then initially run under the fSUB clock source
device is up and running as fast as possible a Fast until 1024 HXT clock cycles have elapsed, at which
Wake-up function is provided, which allows fSUB, point the HTO flag will switch high and the system will
namely either the LXT or LIRC oscillator, to act as a tem- switch over to operating from the HXT oscillator.
porary clock to first drive the system until the original
If the ERC or HIRC oscillators or LIRC oscillator is used
system oscillator has stabilised. As the clock source for
as the system oscillator then it will take 15~16 clock cy-
the Fast Wake-up function is fSUB, the Fast Wake-up
cles of the ERC or HIRC or 1~2 cycles of the LIRC to
function is only available in the SLEEP1 and IDLE0
wake up the system from the SLEEP or IDLE0 Mode.
modes. When the device is woken up from the SLEEP0
The Fast Wake-up bit, FSTEN will have no effect in
mode, the Fast Wake-up function has no effect because
these cases.
the fSUB clock is stopped. The Fast Wake-up enable/dis-
System FSTEN Wake-up Time Wake-up Time Wake-up Time Wake-up Time
Oscillator Bit (SLEEP0 Mode) (SLEEP1 Mode) (IDLE0 Mode) (IDLE1 Mode)
0 1024 HXT cycles 1024 HXT cycles 1~2 HXT cycles
ID L E 1
N O R M A L
H A L T in s tr u c tio n is e x e c u te d
fS Y S = f H ~ f H / 6 4
C P U s to p
fH o n
ID L E N = 1
C P U ru n
F S Y S O N = 1
fS Y S o n
fS Y S o n
fT B C o n
fT B C o n
fS U B o n
fS U B o n
S L E E P 0 ID L E 0
H A L T in s tr u c tio n is e x e c u te d H A L T in s tr u c tio n is e x e c u te d
fS Y S o ff C P U s to p
C P U s to p ID L E N = 1
ID L E N = 0 F S Y S O N = 0
fT B C o ff fS Y S o ff
fS U B o ff fT B C o n
W D T & L V D o ff fS U B o n
S L E E P 1 S L O W
H A L T in s tr u c tio n is e x e c u te d fS Y S = fL
fS Y S o ff fL o n
C P U s to p C P U ru n
ID L E N = 0 fS Y S o n
fT B C o ff fT B C o n
fS U B o n fS U B o n
W D T o r L V D o n fH o ff
Operating Mode Switching and Wake-up sources will also stop running, which may affect the op-
The device can switch between operating modes dy- eration of other internal functions such as the TMs and
namically allowing the user to select the best perfor- the SIM. The accompanying flowchart shows what hap-
mance/power ratio for the present task in hand. In this pens when the device moves between the various oper-
way microcontroller operations that do not require high ating modes.
performance can be executed using slower clocks thus
NORMAL Mode to SLOW Mode Switching
requiring less operating current and prolonging battery
life in portable applications. When running in the NORMAL Mode, which uses the
high speed system oscillator, and therefore consumes
In simple terms, Mode Switching between the NORMAL
more power, the system clock can switch to run in the
Mode and SLOW Mode is executed using the HLCLK bit
SLOW Mode by set the HLCLK bit to 0 and set the
and CKS2~CKS0 bits in the SMOD register while Mode
Switching from the NORMAL/SLOW Modes to the CKS2~CKS0 bits to 000 or 001 in the SMOD regis-
SLEEP/IDLE Modes is executed via the HALT instruc- ter. This will then use the low speed system oscillator
tion. When a HALT instruction is executed, whether the which will consume less power. Users may decide to do
device enters the IDLE Mode or the SLEEP Mode is de- this for certain operations which do not require high per-
termined by the condition of the IDLEN bit in the SMOD formance and can subsequently reduce power con-
register and FSYSON in the WDTC register. sumption.
When the HLCLK bit switches to a low level, which im- The SLOW Mode is sourced from the LXT or the LIRC
plies that clock source is switched from the high speed oscillators and therefore requires these oscillators to be
clock source, fH, to the clock source, fH/2~fH/64 or fL. If stable before full mode switching occurs. This is moni-
the clock is from the fL, the high speed clock source will tored using the LTO bit in the SMOD register.
stop running to conserve power. When this happens it
must be noted that the fH/16 and fH/64 internal clock
N O R M A L M o d e
C K S 2 ~ C K S 0 = 0 0 x B &
H L C L K = 0
S L O W M o d e
W D T a n d L V D a r e a ll o ff
ID L E N = 0
H A L T in s tr u c tio n is e x e c u te d
S L E E P 0 M o d e
W D T o r L V D is o n
ID L E N = 0
H A L T in s tr u c tio n is e x e c u te d
S L E E P 1 M o d e
ID L E N = 1 , F S Y S O N = 0
H A L T in s tr u c tio n is e x e c u te d
ID E L 0 M o d e
ID L E N = 1 , F S Y S O N = 1
H A L T in s tr u c tio n is e x e c u te d
ID L E 1 M o d e
S L O W M o d e
C K S 2 ~ C K S 0 0 0 0 B , 0 0 1 B a s H L C L K = 0
o r H L C L K = 1
N O R M A L M o d e
W D T a n d L V D a r e a ll o ff
ID L E N = 0
H A L T in s tr u c tio n is e x e c u te d
S L E E P 0 M o d e
W D T o r L V D is o n
ID L E N = 0
H A L T in s tr u c tio n is e x e c u te d
S L E E P 1 M o d e
ID L E N = 1 , F S Y S O N = 0
H A L T in s tr u c tio n is e x e c u te d
ID L E 0 M o d e
ID L E N = 1 , F S Y S O N = 1
H A L T in s tr u c tio n is e x e c u te d
ID L E 1 M o d e
In the status register, the Power Down flag, PDF, will In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be be set and the Watchdog time-out flag, TO, will be
cleared. cleared.
There is only one way for the device to enter the IDLE0 As the main reason for entering the SLEEP or IDLE
Mode and that is to execute the HALT instruction in the Mode is to keep the current consumption of the device
application program with the IDLEN bit in SMOD register to as low a value as possible, perhaps only in the order
equal to 1 and the FSYSON bit in WDTC register equal of several micro-amps except in the IDLE1 Mode, there
are other considerations which must also be taken into
to 0. When this instruction is executed under the condi-
account by the circuit designer if the power consumption
tions described above, the following will occur:
is to be minimised. Special attention must be made to
The system clock will be stopped and the application
the I/O pins on the device. All high-impedance input pins
program will stop at the HALT instruction, but the
must be connected to either a fixed high or low level as
Time Base clock and fSUB clock will be on.
any floating input pins could create internal oscillations
The Data Memory contents and registers will maintain
and result in increased current consumption. This also
their present condition.
applies to devices which have different package types,
The WDT will be cleared and resume counting if the as there may be unbonbed pins. These must either be
WDT clock source is selected to come from the fSUB setup as outputs or if setup as inputs must have
clock and the WDT is enabled. The WDT will stop if its
pull-high resistors connected.
clock source originates from the system clock.
The I/O ports will maintain their present conditions. Care must also be taken with the loads, which are con-
nected to I/O pins, which are setup as outputs. These
In the status register, the Power Down flag, PDF, will
should be placed in a condition in which minimum cur-
be set and the Watchdog time-out flag, TO, will be
cleared. rent is drawn or connected only to external circuits that
do not draw current, such as other CMOS inputs. Also
note that additional standby current will also be required
if the configuration options have enabled the LXT or
LIRC oscillator.
In the IDLE1 Mode the system oscillator is on, if the sys-
tem oscillator is from the high speed system oscillator,
the additional standby current will also be perhaps in the
order of several hundred micro-amps
Watchdog Timer
The Watchdog Timer is provided to prevent program However, it should be noted that this specified internal
malfunctions or sequences from jumping to unknown lo- clock period can vary with VDD, temperature and pro-
cations, due to certain uncontrollable external events cess variations. The LXT oscillator is supplied by an ex-
such as electrical noise. ternal 32.768kHz crystal. The other Watchdog Timer
clock source option is the fSYS/4 clock. The Watchdog
Watchdog Timer Clock Source Timer clock source can originate from its own internal
The Watchdog Timer clock source is provided by the in- LIRC oscillator, the LXT oscillator or fSYS/4. It is divided
ternal clock, fS, which is in turn supplied by one of two by a value of 28 to 215, using the WS2~WS0 bits in the
sources selected by configuration option: fSUB or fSYS/4. WDTC register to obtain the required Watchdog Timer
The fSUB clock can be sourced from either the LXT or time-out period.
LIRC oscillators, again chosen via a configuration op-
Watchdog Timer Control Register
tion. The Watchdog Timer source clock is then subdi-
vided by a ratio of 28 to 215 to give longer timeouts, the A single register, WDTC, controls the required timeout
actual value being chosen using the WS2~WS0 bits in period as well as the enable/disable operation. This reg-
the WDTC register. The LIRC internal oscillator has an ister together with several configuration options control
approximate period of 32kHz at a supply voltage of 5V. the overall operation of the Watchdog Timer.
WDTC Register
Bit 7 6 5 4 3 2 1 0
Name FSYSON WS2 WS1 WS0 WDTEN3 WDTEN2 WDTEN1 WDTEN0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 1 1 1 1 0 1 0
Watchdog Timer Operation bit TO. However, if the system is in the SLEEP or IDLE
The Watchdog Timer operates by providing a device re- Mode, when a Watchdog Timer time-out occurs, the TO
set when its timer overflows. This means that in the ap- bit in the status register will be set and only the Program
plication program and during normal operation the user Counter and Stack Pointer will be reset. Three methods
has to strategically clear the Watchdog Timer before it can be adopted to clear the contents of the Watchdog
overflows to prevent the Watchdog Timer from execut- Timer. The first is an external hardware reset, which
ing a reset. This is done using the clear watchdog in- means a low level on the RES pin, the second is using
structions. If the program malfunctions for whatever the Watchdog Timer software clear instructions and the
reason, jumps to an unkown location, or enters an end- third is via a HALT instruction.
less loop, these clear instructions will not be executed in There are two methods of using software instructions to
the correct manner, in which case the Watchdog Timer clear the Watchdog Timer, one of which must be chosen
will overflow and reset the device. Some of the Watch- by configuration option. The first option is to use the sin-
dog Timer options, such as enable/disable, clock source gle CLR WDT instruction while the second is to use
selection and clear instruction type are selected using the two commands CLR WDT1 and CLR WDT2. For
configuration options. In addition to a configuration op- the first option, a simple execution of CLR WDT will
tion to enable/disable the Watchdog Timer, there are
clear the WDT while for the second option, both CLR
also four bits, WDTEN3~WDTEN0, in the WDTC regis-
WDT1 and CLR WDT2 must both be executed alter-
ter to offer an additional enable/disable control of the
nately to successfully clear the Watchdog Timer. Note
Watchdog Timer. To disable the Watchdog Timer, as
that for this second option, if CLR WDT1 is used to
well as the configuration option being set to disable, the
clear the Watchdog Timer, successive executions of this
WDTEN3~WDTEN0 bits must also be set to a specific
instruction will have no effect, only the execution of a
value of 1010. Any other values for these bits will keep
CLR WDT2 instruction will clear the Watchdog Timer.
the Watchdog Timer enabled, irrespective of the configu-
Similarly after the CLR WDT2 instruction has been ex-
ration enable/disable setting. After power on these bits
will have the value of 1010. If the Watchdog Timer is used ecuted, only a successive CLR WDT1 instruction can
it is recommended that they are set to a value of 0101 for clear the Watchdog Timer.
maximum noise immunity. Note that if the Watchdog The maximum time out period is when the 215 division ra-
Timer has been disabled, then any instruction relating to tio is selected. As an example, with a 32.768kHz LXT
its operation will result in no operation. oscillator as its source clock, this will give a maximum
watchdog period of around 1 second for the 215 division
WDT Configuration WDTEN3~
WDT ratio, and a minimum timeout of 7.8ms for the 28 division
Option WDTEN0 Bits
ration. If the fSYS/4 clock is used as the Watchdog Timer
WDT Enable xxxx Enable clock source, it should be noted that when the system
WDT Disable Except 1010 Enable enters the SLEEP or IDLE0 Mode, then the instruction
clock is stopped and the Watchdog Timer may lose its
WDT Disable 1010 Disable
protecting purposes. For systems that operate in noisy
Watchdog Timer Enable/Disable Control environments, using the fSUB clock source is strongly
recommended.
Under normal program operation, a Watchdog Timer
time-out will initialise a device reset and set the status
C L R W D T 1 F la g C le a r W D T T y p e
C L R W D T 2 F la g C o n fig u r a tio n O p tio n
1 o r 2 In s tr u c tio n s
C L R
fS /2 8
fS Y S /4 M fS 8 - s ta g e D iv id e r W D T P r e s c a le r
U
L X T M fS U B X
U
L IR C X 8 -to -1 M U X W D T T im e - o u t
C o n fig u r a tio n (2 8 /fS ~ 2 15/fS )
O p tio n
C o n fig u r a tio n W S 2 ~ W S 0
O p tio n (fS /2 8 ~ fS /2 15)
Watchdog Timer
In te rn a l R e s e t
Pulling the RES Pin low using external hardware will Program Counter and the Stack Pointer will be
also execute a device reset. In this case, as in the cleared to 0 and the TO flag will be set to 1. Refer
case of other resets, the Program Counter will reset to to the A.C. Characteristics for tSST details.
zero and program execution initiated from this point. Note: The tSST is 15~16 clock cycles if the system
0 .9 V D D clock source is provided by ERC or HIRC. The
R E S 0 .4 V D D
tSST is 1024 clock for HXT or LXT. The tSST is
tR S T D + tS S T
1~2 clock for LIRC.
In te rn a l R e s e t
Reset Initial Conditions
Note: tRSTD is power-on delay, typical time=100ms
The different types of reset described affect the reset
RES Reset Timing Chart flags in different ways. These flags, known as PDF and
TO are located in the status register and are controlled
Low Voltage Reset - LVR
by various microcontroller operations, such as the
The microcontroller contains a low voltage reset circuit
SLEEP or IDLE Mode function or Watchdog Timer. The
in order to monitor the supply voltage of the device,
which is selected via a configuration option. If the supply reset flags are shown in the table:
voltage of the device drops to within a range of TO PDF RESET Conditions
0.9V~VLVR such as might occur when changing the bat-
tery, the LVR will automatically reset the device inter- 0 0 Power-on reset
nally. The LVR includes the following specifications: For
RES or LVR reset during NORMAL or
a valid LVR signal, a low voltage, i.e., a voltage in the u u
SLOW Mode operation
range between 0.9V~VLVR must exist for greater than
the value tLVR specified in the A.C. characteristics. If the WDT time-out reset during NORMAL or
1 u
low voltage state does not exceed tLVR, the LVR will ig- SLOW Mode operation
nore it and will not perform a reset function. One of a
WDT time-out reset during IDLE or SLEEP
range of specified voltage values for VLVR can be se- 1 1
Mode operation
lected using configuration options.
L V R Note: u stands for unchanged
tR S T D + tS S T
The following table indicates the way in which the vari-
In te rn a l R e s e t ous components of the microcontroller are affected after
Note: tRSTD is power-on delay, typical time=100ms a power-on reset occurs.
Note: tRSTD is power-on delay, typical time=100ms Stack Pointer will point to the top
Stack Pointer
of the stack
WDT Time-out Reset during Normal Operation
Timing Chart
In te rn a l R e s e t
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable
continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller
is in after a particular reset occurs. The following table describes how each type of reset affects each of the
microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation
for the larger package type.
HT68F20 Register
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin
fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is
provided with an I/O structure to meet the needs of a wide range of application possibilities.
The device provides bidirectional input/output lines labeled with port names PA~PG. These I/O ports are mapped to the
RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports
can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs
must be ready at the T2 rising edge of instruction MOV A,[m], where m denotes the port address. For output opera-
tion, all the data is latched and remains unchanged until the output latch is rewritten.
I/O Register List
HT68F20
Register Bit
Name 7 6 5 4 3 2 1 0
PAWU D7 D6 D5 D4 D3 D2 D1 D0
PAPU D7 D6 D5 D4 D3 D2 D1 D0
PA D7 D6 D5 D4 D3 D2 D1 D0
PAC D7 D6 D5 D4 D3 D2 D1 D0
PBPU D5 D4 D3 D2 D1 D0
PB D5 D4 D3 D2 D1 D0
PBC D5 D4 D3 D2 D1 D0
PCPU D3 D2 D1 D0
PC D3 D2 D1 D0
PCC D3 D2 D1 D0
HT68F30
Register Bit
Name 7 6 5 4 3 2 1 0
PAWU D7 D6 D5 D4 D3 D2 D1 D0
PAPU D7 D6 D5 D4 D3 D2 D1 D0
PA D7 D6 D5 D4 D3 D2 D1 D0
PAC D7 D6 D5 D4 D3 D2 D1 D0
PBPU D5 D4 D3 D2 D1 D0
PB D5 D4 D3 D2 D1 D0
PBC D5 D4 D3 D2 D1 D0
PCPU D7 D6 D5 D4 D3 D2 D1 D0
PC D7 D6 D5 D4 D3 D2 D1 D0
PCC D7 D6 D5 D4 D3 D2 D1 D0
HT68F40/HT68F50
Register Bit
Name 7 6 5 4 3 2 1 0
PAWU D7 D6 D5 D4 D3 D2 D1 D0
PAPU D7 D6 D5 D4 D3 D2 D1 D0
PA D7 D6 D5 D4 D3 D2 D1 D0
PAC D7 D6 D5 D4 D3 D2 D1 D0
PBPU D7 D6 D5 D4 D3 D2 D1 D0
PB D7 D6 D5 D4 D3 D2 D1 D0
PBC D7 D6 D5 D4 D3 D2 D1 D0
PCPU D7 D6 D5 D4 D3 D2 D1 D0
PC D7 D6 D5 D4 D3 D2 D1 D0
PCC D7 D6 D5 D4 D3 D2 D1 D0
PDPU D7 D6 D5 D4 D3 D2 D1 D0
PD D7 D6 D5 D4 D3 D2 D1 D0
PDC D7 D6 D5 D4 D3 D2 D1 D0
PEPU D7 D6 D5 D4 D3 D2 D1 D0
PE D7 D6 D5 D4 D3 D2 D1 D0
PEC D7 D6 D5 D4 D3 D2 D1 D0
PFPU D1 D0
PF D1 D0
PFC D1 D0
HT68F60
Register Bit
Name 7 6 5 4 3 2 1 0
PAWU D7 D6 D5 D4 D3 D2 D1 D0
PAPU D7 D6 D5 D4 D3 D2 D1 D0
PA D7 D6 D5 D4 D3 D2 D1 D0
PAC D7 D6 D5 D4 D3 D2 D1 D0
PBPU D7 D6 D5 D4 D3 D2 D1 D0
PB D7 D6 D5 D4 D3 D2 D1 D0
PBC D7 D6 D5 D4 D3 D2 D1 D0
PCPU D7 D6 D5 D4 D3 D2 D1 D0
PC D7 D6 D5 D4 D3 D2 D1 D0
PCC D7 D6 D5 D4 D3 D2 D1 D0
PDPU D7 D6 D5 D4 D3 D2 D1 D0
PD D7 D6 D5 D4 D3 D2 D1 D0
PDC D7 D6 D5 D4 D3 D2 D1 D0
PEPU D7 D6 D5 D4 D3 D2 D1 D0
PE D7 D6 D5 D4 D3 D2 D1 D0
PEC D7 D6 D5 D4 D3 D2 D1 D0
PFPU D7 D6 D5 D4 D3 D2 D1 D0
PF D7 D6 D5 D4 D3 D2 D1 D0
PFC D7 D6 D5 D4 D3 D2 D1 D0
PGPU D1 D0
PG D1 D0
PGC D1 D0
Pull-high Resistors
Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external re-
sistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of
being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU~PGPU,
and are implemented using weak PMOS transistors.
PAPU Register
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
PBPU Register
HT68F40/HT68F50/HT68F60
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
PCPU Register
HT68F30/HT68F40/HT68F50/HT68F60
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
PDPU Register
HT68F40/HT68F50/HT68F60
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
PEPU Register
HT68F40/HT68F50/HT68F60
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
PFPU Register
HT68F60
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
PBPU Register
HT68F20/HT68F30
Bit 7 6 5 4 3 2 1 0
Name D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0
PCPU Register
HT68F20
Bit 7 6 5 4 3 2 1 0
Name D3 D2 D1 D0
R/W R/W R/W R/W R/W
POR 0 0 0 0
PFPU Register
HT68F40/HT68F50
Bit 7 6 5 4 3 2 1 0
Name D1 D0
R/W R/W R/W
POR 0 0
PGPU Register
HT68F60
Bit 7 6 5 4 3 2 1 0
Name D1 D0
R/W R/W R/W
POR 0 0
Port A Wake-up
The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is
important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of
which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for
applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this
wake-up feature using the PAWU register.
PAWU Register
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
PAC Register
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 1 1 1 1 1 1 1 1
PBC Register
HT68F40/HT68F50/HT68F60
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 1 1 1 1 1 1 1 1
PCC Register
HT68F30/HT68F40/HT68F50/HT68F60
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 1 1 1 1 1 1 1 1
PDC Register
HT68F40/HT68F50/HT68F60
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 1 1 1 1 1 1 1 1
PEC Register
HT68F40/HT68F50/HT68F60
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 1 1 1 1 1 1 1 1
PFC Register
HT68F60
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 1 1 1 1 1 1 1 1
PBC Register
HT68F20/HT68F30
Bit 7 6 5 4 3 2 1 0
Name D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0
PCC Register
HT68F20
Bit 7 6 5 4 3 2 1 0
Name D3 D2 D1 D0
R/W R/W R/W R/W R/W
POR 0 0 0 0
PFC Register
HT68F40/HT68F50
Bit 7 6 5 4 3 2 1 0
Name D1 D0
R/W R/W R/W
POR 0 0
PGC Register
HT68F60
Bit 7 6 5 4 3 2 1 0
Name D1 D0
R/W R/W R/W
POR 0 0
Pin-remapping Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function.
Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions,
many of these difficulties can be overcome. The way in which the pin function of each pin is selected is different for each
function and a priority order is established where more than one pin function is selected simultaneously. Additionally
there are a series of PRM0, PRM1 and PRM2 registers to establish certain pin functions.
Pin-remapping Registers
The limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device
can contain. However by allowing the same pins to share several different functions and providing a means of function
selection, a wide range of different functions can be incorporated into even relatively small package sizes. Some de-
vices include PRM0, PRM1 or PRM2 registers which can select the functions of certain pins.
Pin-remapping Register List
HT68F30
Register Bit
Name 7 6 5 4 3 2 1 0
PRM0 PCPRM SIMPS0 PCKPS
HT68F40
Register Bit
Name 7 6 5 4 3 2 1 0
PRM0 C1XPS0 C0XPS0 PDPRM SIMPS1 SIMPS0 PCKPS
HT68F50
Register Bit
Name 7 6 5 4 3 2 1 0
PRM0 C1XPS0 C0XPS0 PDPRM SIMPS1 SIMPS0 PCKPS
HT68F60
Register Bit
Name 7 6 5 4 3 2 1 0
PRM0 C1XPS1 C1XPS0 C0XPS1 C0XPS0 PDPRM SIMPS1 SIMPS0 PCKPS
PRM1 TCK2PS TCK1PS TCK0PS INT2PS1 INT1PS1 INT1PS0 INT0PS1 INT0PS0
PRM2 TP31PS TP30PS TP21PS TP20PS TP1B2PS TP1APS TP01PS TP00PS
PRM0 Register
HT68F30
Bit 7 6 5 4 3 2 1 0
Name PCPRM SIMPS0 PCKPS
R/W R/W R/W R/W
POR 0 0 0
PRM0 Register
HT68F40/HT68F50
Bit 7 6 5 4 3 2 1 0
Name C1XPS0 C0XPS0 PDPRM SIMPS1 SIMPS0 PCKPS
R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0
PRM0 Register
HT68F60
Bit 7 6 5 4 3 2 1 0
Name C1XPS1 C1XPS0 C0XPS1 C0XPS0 PDPRM SIMPS1 SIMPS0 PCKPS
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name TCK2PS TCK1PS TCK0PS INT1PS1 INT1PS0 INT0PS1 INT0PS0
R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0
PRM1 Register
HT68F60
Bit 7 6 5 4 3 2 1 0
Name TCK2PS TCK1PS TCK0PS INT2PS INT1PS1 INT1PS0 INT0PS1 INT0PS0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
PRM2 Register
HT68F40
Bit 7 6 5 4 3 2 1 0
Name TP21PS TP20PS TP1B2PS TP1APS TP01PS TP00PS
R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0
PRM2 Register
HT68F50/HT68F60
Bit 7 6 5 4 3 2 1 0
Name TP31PS TP30PS TP21PS TP20PS TP1B2PS TP1APS TP01PS TP00PS
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
I/O Pin Structures be achieved byte-wide by loading the correct values into
The accompanying diagrams illustrate the internal the appropriate port control register or by programming
structures of some generic I/O pin types. As the exact individual bits in the port control register using the SET
logical construction of the I/O pin will differ from these [m].i and CLR [m].i instructions. Note that when using
drawings, they are supplied as a guide only to assist these bit control instructions, a read-modify-write opera-
with the functional understanding of the I/O pins. The tion takes place. The microcontroller must first read in
wide range of pin-shared structures does not permit all the data on the entire port, modify it to the required new
types to be shown. bit values and then rewrite this data back to the output
ports.
Programming Considerations
Port A has the additional capability of providing wake-up
Within the user program, one of the first things to con- functions. When the device is in the SLEEP or IDLE
sider is port initialisation. After a reset, all of the I/O data Mode, various methods are available to wake the device
and port control registers will be set high. This means up. One of these is a high to low transition of any of the
that all I/O pins will default to an input state, the level of Port A pins. Single or multiple pins on Port A can be
which depends on the other connected circuitry and setup to have this function.
whether pull-high selections have been chosen. If the
port control registers, PAC~PGC, are then programmed
to setup some pins as outputs, these output pins will
have an initial high output value unless the associated
port data registers, PA~PG, are first programmed. Se-
lecting which pins are inputs and which are outputs can
P u ll- H ig h V D D
R e g is te r
C o n tr o l B it S e le c t W e a k
D a ta B u s D Q P u ll- u p
W r ite C o n tr o l R e g is te r C K Q
C h ip R e s e t S
I/O p in
R e a d C o n tr o l R e g is te r
D a ta B it
D Q
W r ite D a ta R e g is te r C K Q
S
M
U
R e a d D a ta R e g is te r X
S y s te m W a k e -u p P A o n ly
W a k e - u p S e le c t
Timer Modules - TM
One of the most fundamental functions in any Introduction
microcontroller device is the ability to control and mea-
The devices contain from two to four TMs depending
sure time. To implement time related functions each de-
upon which device is selected with each TM having a
vice includes several Timer Modules, abbreviated to the
reference name of TM0, TM1, TM2 and TM3. Each indi-
name TM. The TMs are multi-purpose timing units and
vidual TM can be categorised as a certain type, namely
serve to provide operations such as Timer/Counter, In-
Compact Type TM, Standard Type TM or Enhanced
put Capture, Compare Match Output and Single Pulse
Type TM. Although similar in nature, the different TM
Output as well as being the functional unit for the gener-
types vary in their feature complexity. The common fea-
ation of PWM signals. Each of the TMs has either two or
tures to all of the Compact, Standard and Enhanced
three individual interrupts. The addition of input and out-
TMs will be described in this section, the detailed opera-
put pins for each TM ensures that users are provided
tion regarding each of the TM types will be described in
with timing units with a wide and flexible range of fea-
separate sections. The main features and differences
tures.
between the three types of TMs are summarised in the
The common features of the different TM types are de- accompanying table.
scribed here with more detailed information provided in
the individual Compact, Standard and Enhanced TM
sections.
TM Function Summary
Each device in the series contains a specific number of either Compact Type, Standard Type and Enhanced Type TM
units which are shown in the table together with their individual reference name, TM0~TM3.
TM Name/Type Reference
TM Output Pins
Bit
Registers Device
7 6 5 4 3 2 1 0
TMPC0 HT68F20 T1CP1 T1CP0 T0CP0
TMPC0 HT68F30 T1ACP0 T1BCP1 T1BCP0 T0CP1 T0CP0
HT68F40
TMPC0 HT68F50 T1ACP0 T1BCP2 T1BCP1 T1BCP0 T0CP1 T0CP0
HT68F60
TMPC1 HT68F40 T2CP1 T2CP0
HT68F50
TMPC1 T3CP1 T3CP0 T2CP1 T2CP0
HT68F60
P A 0 O u tp u t F u n c tio n 0
P A 0 /T P 0 _ 0
1
O u tp u t
T 0 C P 0
T M 0
(C T M )
T C K In p u t
P A 2 /T C K 0
P A 1 O u tp u t F u n c tio n 0
P A 1 /T P 1 _ 0
1
0
1
T 1 C P 0
P A 1
P C 0 O u tp u t F u n c tio n 0
P C 0 /T P 1 _ 1
O u tp u t 1
0
1
T 1 C P 1
P C 0
1
C a p tu re In p u t
0
T M 1
(S T M ) T 1 C P 1
T 1 C P 0
T C K In p u t
P A 4 /T C K 1
P A 0 O u tp u t F u n c tio n 0
P A 0 /T P 0 _ 0
1
0
1
T 0 C P 0
P A 0
P C 5 O u tp u t F u n c tio n 0
P C 5 /T P 0 _ 1
O u tp u t 1
0
1
T M 0 T 0 C P 1
(C T M )
P C 5
T C K In p u t
P A 2 /T C K 0
P A 1 O u tp u t F u n c tio n 0
P A 1 /T P 1 A
1
C C R A O u tp u t
T 1 A C P 0
C C R A C a p tu re In p u t 1
T 1 A C P 0
P C 0 O u tp u t F u n c tio n 0
P C 0 /T P 1 B _ 0
1
0
1
T 1 B C P 0
P C 0
T M 1
(E T M ) P C 1 O u tp u t F u n c tio n 0
P C 1 /T P 1 B _ 1
C C R B O u tp u t 1
0
1
T 1 B C P 1
P C 1
1
C C R B C a p tu re In p u t
0
T 1 B C P 1
T 1 B C P 0
T C K In p u t
P A 4 /T C K 1
P A 0 O u tp u t F u n c tio n 0
P A 0 /T P 0 _ 0
1
0
1
T 0 C P 0
P A 0
P C 5 O u tp u t F u n c tio n 0
P C 5 /T P 0 _ 1
O u tp u t 1
0
1
T M 0 T 0 C P 1
(C T M )
P C 5
T C K In p u t
P A 2 /T C K 0
P C 3 O u tp u t F u n c tio n 0
P C 3 /T P 2 _ 0
1
0
1
T 2 C P 0
P C 3
P C 4 O u tp u t F u n c tio n 0
P C 4 /T P 2 _ 1
O u tp u t 1
0
1
T 2 C P 1
P C 4
1
C a p tu re In p u t
0
T M 2
(S T M ) T 2 C P 1
T 2 C P 0
T C K In p u t
P C 2 /T C K 2
P A 1 O u tp u t F u n c tio n 0
P A 1 /T P 1 A
1
C C R A O u tp u t
T 1 A C P 0
C C R A C a p tu re In p u t 1
T 1 A C P 0
P C 0 O u tp u t F u n c tio n 0
P C 0 /T P 1 B _ 0
1
0
1
T 1 B C P 0
P C 0
P C 1 O u tp u t F u n c tio n 0
P C 1 /T P 1 B _ 1
1
0
1
T 1 B C P 1
T M 1
(E T M ) P C 1
P C 5 O u tp u t F u n c tio n 0
P C 5 /T P 1 B _ 2
C C R B O u tp u t 1
0
1
T 1 B C P 2
P C 5
1
C C R B C a p tu re In p u t
0
T 1 B C P 2
T 1 B C P 1
T 1 B C P 0
T C K In p u t
P A 4 /T C K 1
P A 0 O u tp u t F u n c tio n 0
P A 0 /T P 0 _ 0
1
0
1
T 0 C P 0
P A 0
P C 5 O u tp u t F u n c tio n 0
P C 5 /T P 0 _ 1
O u tp u t 1
0
1
T M 0 T 0 C P 1
(C T M )
P C 5
T C K In p u t
P A 2 /T C K 0
P C 3 O u tp u t F u n c tio n 0
P C 3 /T P 2 _ 0
1
0
1
T 2 C P 0
P C 3
P C 4 O u tp u t F u n c tio n 0
P C 4 /T P 2 _ 1
O u tp u t 1
0
1
T 2 C P 1
P C 4
1
C a p tu re In p u t
0
T M 2
(S T M ) T 2 C P 1
T 2 C P 0
T C K In p u t
P C 2 /T C K 2
P D 3 O u tp u t F u n c tio n 0
P D 3 /T P 3 _ 0
1
0
1
T 3 C P 0
P D 3
P D 0 O u tp u t F u n c tio n 0
P D 0 /T P 3 _ 1
O u tp u t 1
0
1
T M 3 T 3 C P 1
(C T M )
P D 0
T C K In p u t
P C 4 /T C K 3
HT68F50 and HT68F60 TM0, TM2, TM3 Function Pin Control Block Diagram
P A 1 O u tp u t F u n c tio n 0
P A 1 /T P 1 A
1
C C R A O u tp u t
T 1 A C P 0
C C R A C a p tu re In p u t 1
T 1 A C P 0
P C 0 O u tp u t F u n c tio n 0
P C 0 /T P 1 B _ 0
1
0
1
T 1 B C P 0
P C 0
P C 1 O u tp u t F u n c tio n 0
P C 1 /T P 1 B _ 1
1
0
1
T 1 B C P 1
T M 1
(E T M ) P C 1
P C 5 O u tp u t F u n c tio n 0
P C 5 /T P 1 B _ 2
C C R B O u tp u t 1
0
1
T 1 B C P 2
P C 5
1
C C R B C a p tu re In p u t
0
T 1 B C P 2
T 1 B C P 1
T 1 B C P 0
T C K In p u t
P A 4 /T C K 1
TMPC0 Register
HT68F20
Bit 7 6 5 4 3 2 1 0
Name T1CP1 T1CP0 T0CP0
R/W R/W R/W R/W
POR 0 1 1
HT68F30
Bit 7 6 5 4 3 2 1 0
Name T1ACP0 T1BCP1 T1BCP0 T0CP1 T0CP0
R/W R/W R/W R/W R/W R/W
POR 1 0 1 0 1
HT68F40/HT68F50/HT68F60
Bit 7 6 5 4 3 2 1 0
Name T1ACP0 T1BCP2 T1BCP1 T1BCP0 T0CP1 T0CP0
R/W R/W R/W R/W R/W R/W R/W
POR 1 0 0 1 0 1
TMPC1 Register
HT68F40
Bit 7 6 5 4 3 2 1 0
Name T2CP1 T2CP0
R/W R/W R/W
POR 0 1
HT68F50/HT68F60
Bit 7 6 5 4 3 2 1 0
Name T3CP1 T3CP0 T2CP1 T2CP0
R/W R/W R/W R/W R/W
POR 0 1 0 1
Compact Type TM
Although the simplest form of the three TM types, the Compact TM type still contains three operating modes, which are
Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with
an external input pin and can drive one or two external output pins. These two external output pins can be the same sig-
nal or the inverse signal.
C C R P
C o m p a ra to r P M a tc h
3 - b it C o m p a r a to r P T n P F In te rru p t
fS Y S /4 0 0 0
b 7 ~ b 9
fS Y S 0 0 1 T n O C
fH /1 6 0 1 0
fH /6 4 0 1 1
T P n _ 0
fT B C 1 0 0 O u tp u t P o la r ity T P n P in
C o u n te r C le a r 0 C o n tro l C o n tro l O u tp u t
R e s e rv e d 1 0 1 1 0 - b it C o u n t- u p C o u n te r
1 T P n _ 1
1 1 0
T C K n 1 1 1
T n M 1 , T n M 0 T n P O L
T n O N T n C C L R
b 0 ~ b 9 T n IO 1 , T n IO 0
T n P A U
C o m p a ra to r A M a tc h
1 0 - b it C o m p a r a to r A T n A F In te rru p t
T n C K 2 ~ T n C K 0
C C R A
TM0DL Register
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R R R R R R R R
POR 0 0 0 0 0 0 0 0
Bit 7~0 TM0DL: TM0 Counter Low Byte Register bit 7 ~ bit 0
TM0 10-bit Counter bit 7 ~ bit 0
TM0DH Register
Bit 7 6 5 4 3 2 1 0
Name D9 D8
R/W R R
POR 0 0
TM0AL Register
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Bit 7~0 TM0AL: TM0 CCRA Low Byte Register bit 7 ~ bit 0
TM0 10-bit CCRA bit 7 ~ bit 0
TM0AH Register
Bit 7 6 5 4 3 2 1 0
Name D9 D8
R/W R/W R/W
POR 0 0
TM0C0 Register
Bit 7 6 5 4 3 2 1 0
Name T0PAU T0CK2 T0CK1 T0CK0 T0ON T0RP2 T0RP1 T0RP0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Bit 2~0 T0RP2~T0RP0: TM0 CCRP 3-bit register, compared with the TM0 Counter bit 9~bit 7
Comparator P Match Period
000: 1024 TM0 clocks
001: 128 TM0 clocks
010: 256 TM0 clocks
011: 384 TM0 clocks
100: 512 TM0 clocks
101: 640 TM0 clocks
110: 768 TM0 clocks
111: 896 TM0 clocks
These three bits are used to setup the value on the internal CCRP 3-bit register, which are then
compared with the internal counter's highest three bits. The result of this comparison can be
selected to clear the internal counter if the T0CCLR bit is set to zero. Setting the T0CCLR bit to
zero ensures that a compare match with the CCRP values will reset the internal counter. As the
CCRP bits are only compared with the highest three counter bits, the compare values exist in 128
clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at
its maximum value.
TM0C1 Register
Bit 7 6 5 4 3 2 1 0
Name T0M1 T0M0 T0IO1 T0IO0 T0OC T0POL T0DPX T0CCLR
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Compact Type TM Operating Modes rupt request flag will be generated even if the value of
The Compact Type TM can operate in one of three oper- the CCRP bits is less than that of the CCRA registers.
ating modes, Compare Match Output Mode, PWM Therefore when TnCCLR is high no TnPF interrupt re-
Mode or Timer/Counter Mode. The operating mode is quest flag will be generated. If the CCRA bits are all
selected using the TnM1 and TnM0 bits in the TMnC1 zero, the counter will overflow when its reaches its maxi-
register. mum 10-bit, 3FF Hex, value, however here the TnAF in-
terrupt request flag will not be generated.
Compare Match Output Mode As the name of the mode suggests, after a comparison
To select this mode, bits TnM1 and TnM0 in the TMnC1 is made, the TM output pin will change state. The TM
register, should be set to 00 respectively. In this mode output pin condition however only changes state when
once the counter is enabled and running it can be an TnAF interrupt request flag is generated after a com-
cleared by three methods. These are a counter over- pare match occurs from Comparator A. The TnPF inter-
flow, a compare match from Comparator A and a com- rupt request flag, generated from a compare match
pare match from Comparator P. When the TnCCLR bit is occurs from Comparator P, will have no effect on the TM
low, there are two ways in which the counter can be output pin. The way in which the TM output pin changes
cleared. One is when a compare match occurs from state are determined by the condition of the TnIO1 and
Comparator P, the other is when the CCRP bits are all TnIO0 bits in the TMnC1 register. The TM output pin can
zero which allows the counter to overflow. Here both be selected using the TnIO1 and TnIO0 bits to go high,
TnAF and TnPF interrupt request flags for the Compara- to go low or to toggle from its present condition when a
tor A and Comparator P respectively, will both be gener- compare match occurs from Comparator A. The initial
ated. condition of the TM output pin, which is setup after the
TnON bit changes from low to high, is setup using the
If the TnCCLR bit in the TMnC1 register is high then the
TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero
counter will be cleared when a compare match occurs
then no pin change will take place.
from Comparator A. However, here only the TnAF inter-
Counter
Counter TnCCRL = 0; TnM1, TnM0 = 00
Value
overflow
CCRP = 0 CCRP > 0
Counter cleared by CCRP value
0x3FF CCRP > 0
CCRP
Pause Resume Counter
Stop Reset
CCRA
Time
TnON bit
TnPAU bit
TnPOL bit
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM O/P Pin
Output Pin set Output not affected by TnAF flag Output inverts
to Initial Level Output Toggle when TnPOL is high
Remains High until reset by TnON bit
Low if TnOC = 0 with TnAF flag
Now TnIO1, TnIO0 = 10 Output Pin
Active High Output Reset to initial value
Select
Here TnIO1, TnIO0 = 11
Toggle Output Select
Note: 1. With TnCCLR = 0 the Comparator P match will clear the counter
2. TM output pin controlled only by TnAF flag
3. Output pin reset to initial state by TnON bit rising edge
Counter
TnCCLR = 1; TnM1, TnM0 = 00
Value
CCRA = 0
CCRA > 0 Counter cleared by CCRA value Counter overflows
0x3FF
CCRA = 0
CCRA
Pause Resume Counter
Stop Reset
CCRP
Time
TnON bit
TnPAU bit
TnPOL bit
No TnAF flag
CCRA Int. generated on
CCRA overflow
Flag TnAF
CCRP Int.
Flag TnPF
Output does
TnPF not not change
generated
TM O/P Pin
Note: 1. With TnCCLR = 1 the Comparator A match will clear the counter
2. TM output pin controlled only by TnAF flag
3.TM output pin reset to initial state by TnON rising edge
4. TnPF flags not generated when TnCCLR = 1
Timer/Counter Mode As both the period and duty cycle of the PWM waveform
To select this mode, bits TnM1 and TnM0 in the TMnC1 can be controlled, the choice of generated waveform is
register should be set to 11 respectively. The extremely flexible. In the PWM mode, the TnCCLR bit
Timer/Counter Mode operates in an identical way to the has no effect on the PWM operation. Both of the CCRA
Compare Match Output Mode generating the same in- and CCRP registers are used to generate the PWM
terrupt flags. The exception is that in the Timer/Counter waveform, one register is used to clear the internal
Mode the TM output pin is not used. Therefore the counter and thus control the PWM waveform frequency,
above description and Timing Diagrams for the Com- while the other one is used to control the duty cycle.
pare Match Output Mode can be used to understand its Which register is used to control either frequency or duty
function. As the TM output pin is not used in this mode, cycle is determined using the TnDPX bit in the TMnC1
the pin can be used as a normal I/O pin or other register. The PWM waveform frequency and duty cycle
pin-shared function. can therefore be controlled by the values in the CCRA
and CCRP registers.
PWM Output Mode An interrupt flag, one for each of the CCRA and CCRP,
To select this mode, bits TnM1 and TnM0 in the TMnC1 will be generated when a compare match occurs from
register should be set to 10 respectively. The PWM func- either Comparator A or Comparator P. The TnOC bit in
tion within the TM is useful for applications which require the TMnC1 register is used to select the required polar-
functions such as motor control, heating control, illumi- ity of the PWM waveform while the two TnIO1 and
nation control etc. By providing a signal of fixed fre- TnIO0 bits are used to enable the PWM output or to
quency but of varying duty cycle on the TM output pin, a force the TM output pin to a fixed high or low level. The
square wave AC waveform can be generated with vary- TnPOL bit is used to reverse the polarity of the PWM
ing equivalent DC RMS values. output waveform.
Counter
Value Counter Cleared
by CCRP
DPX = 0; TnM1, TnM0 = 10
CCRA
Time
TnON bit
TnPAU bit
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TnIO1, TnIO0 = 00
TnIO1, TnIO0 = 10 PWM Output TnIO1, TnIO0 = 10
Output Inactive
PWM Output
TM Pin
TnOC = 1
TM Pin
TnOC = 0
TnIIO1, TnIO0 = 10 Output Inverts
Here TnIO1, TnIO0 = 00 Resume PWM Output PWM resumes operation When TnPOL = 1
PWM Period Output Forced to Inactive Output remains at same level
set by CCRP level but PWM function
PWM Duty Cycle keeps running internally
set by CCRA
Counter
Value Counter Cleared
by CCRA
DPX = 1; TnM1, TnM0 = 10
CCRP
Time
TnON bit
TnPAU bit
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TnIO1, TnIO0 = 00
TnIO1, TnIO0 = 10 PWM Output Output Inactive TnIO1, TnIO0 = 10
PWM Output
TM Pin
TnOC = 1
TM Pin
TnOC = 0
TnIO1, TnIO0 = 10 Output Inverts
Here TnIO1, TnIO0 = 00 Resume PWM Output PWM resumes operation When TnPOL = 1
PWM Period Output Forced to Inactive Output remains at same level
set by CCRA level but PWM function
PWM Duty Cycle keeps running internally
set by CCRP
C C R P
C o m p a ra to r P M a tc h
3 o r 8 - b it C o m p a r a to r P T n P F In te rru p t
b 7 ~ b 9 o r b 8 ~ b 1 5 T n O C
fS Y S /4 0 0 0
fS Y S 0 0 1
fH /1 6 0 1 0 T P n _ 0
fH /6 4 O u tp u t P o la r ity T P n P in
0 1 1 C o u n te r C le a r 0
1 0 o r 1 6 - b it C o u n t- u p C o u n te r C o n tro l C o n tro l In p u t/O u tp u t
fT B C 1 0 0 1 T P n _ 1
R e s e rv e d 1 0 1
1 1 0
T n C C L R T n M 1 , T n M 0 T n P O L
T C K n 1 1 1 T n O N b 0 ~ b 9 o r
b 0 ~ b 1 5 T n IO 1 , T n IO 0
T n P A U
1 0 o r 1 6 - b it C o m p a ra to r A M a tc h
T n A F In te rru p t
C o m p a ra to r A
T n IO 1 , T n IO 0
T n C K 2 ~ T n C K 0
C C R A
E d g e
D e te c to r
Bit 7 6 5 4 3 2 1 0
Name T1PAU T1CK2 T1CK1 T1CK0 T1ON T1RP2 T1RP1 T1RP0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name T1M1 T1M0 T1IO1 T1IO0 T1OC T1POL T1DPX T1CCLR
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
These two bits are used to determine how the TM output pin changes state when a certain
condition is reached. The function that these bits select depends upon in which mode the TM is
running.
In the Compare Match Output Mode, the T1IO1 and T1IO0 bits determine how the TM output
pin changes state when a compare match occurs from the Comparator A. The TM output pin can
be setup to switch high, switch low or to toggle its present state when a compare match occurs
from the Comparator A. When the bits are both zero, then no change will take place on the
output. The initial value of the TM output pin should be setup using the T1OC bit in the TM1C1
register. Note that the output level requested by the T1IO1 and T1IO0 bits must be different from
the initial value setup using the T1OC bit otherwise no change will occur on the TM output pin
when a compare match occurs. After the TM output pin changes state it can be reset to its initial
level by changing the level of the T1ON bit from low to high.
Bit 3 T1OC: TP1_0, TP1_1 Output control bit
Compare Match Output Mode
0: initial low
1: initial high
PWM Mode/ Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the TM output pin. Its operation depends upon whether TM is
being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode.
It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it
determines the logic level of the TM output pin before a compare match occurs. In the PWM
Mode it determines if the PWM signal is active high or active low.
Bit 2 T1POL: TP1_0, TP1_1 Output polarity Control
0: non-invert
1: invert
This bit controls the polarity of the TP1_0 or TP1_1 output pin. When the bit is set high the TM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the
Timer/Counter Mode.
Bit 1 T1DPX: TM1 PWM period/duty Control
0: CCRP - period; CCRA - duty
1: CCRP - duty; CCRA - period
This bit, determines which of the CCRA and CCRP registers are used for period and duty
control of the PWM waveform.
Bit 0 T1CCLR: Select TM1 Counter clear condition
0: TM1 Comparatror P match
1: TM1 Comparatror A match
This bit is used to select the method which clears the counter. Remember that the Standard
TM contains two comparators, Comparator A and Comparator P, either of which can be selected
to clear the internal counter. With the T1CCLR bit set high, the counter will be cleared when a
compare match occurs from the Comparator A. When the bit is low, the counter will be cleared
when a compare match occurs from the Comparator P or with a counter overflow. A counter
overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The
T1CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode.
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R R R R R R R R
POR 0 0 0 0 0 0 0 0
Bit 7~0 TM1DL: TM1 Counter Low Byte Register bit 7~bit 0
TM1 10-bit Counter bit 7~bit 0
Bit 7 6 5 4 3 2 1 0
Name D9 D8
R/W R R
POR 0 0
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Bit 7~0 TM1AL: TM1 CCRA Low Byte Register bit 7~bit 0
TM1 10-bit CCRA bit 7~bit 0
Bit 7 6 5 4 3 2 1 0
Name D9 D8
R/W R/W R/W
POR 0 0
Bit 7 6 5 4 3 2 1 0
Name T2PAU T2CK2 T2CK1 T2CK0 T2ON
R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name T2M1 T2M0 T2IO1 T2IO0 T2OC T2POL T2DPX T2CCLR
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R R R R R R R R
POR 0 0 0 0 0 0 0 0
Bit 7~0 TM2DL: TM2 Counter Low Byte Register bit 7~bit 0
TM2 16-bit Counter bit 7~bit 0
Bit 7 6 5 4 3 2 1 0
Name D15 D14 D13 D12 D11 D10 D9 D8
R/W R R R R R R R R
POR 0 0 0 0 0 0 0 0
Bit 7~0 TM2DH: TM2 Counter High Byte Register bit 7~bit 0
TM2 16-bit Counter bit 15~bit 8
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Bit 7~0 TM2AL: TM2 CCRA Low Byte Register bit 7~bit 0
TM2 16-bit CCRA bit 7~bit 0
Bit 7 6 5 4 3 2 1 0
Name D15 D14 D13 D12 D11 D10 D9 D8
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Bit 7~0 TM2AH: TM2 CCRA High Byte Register bit 7~bit 0
TM2 16-bit CCRA bit 15~bit 8
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Standard Type TM Operating Modes from Comparator A. However, here only the TnAF inter-
The Standard Type TM can operate in one of five oper- rupt request flag will be generated even if the value of
ating modes, Compare Match Output Mode, PWM Out- the CCRP bits is less than that of the CCRA registers.
put Mode, Single Pulse Output Mode, Capture Input Therefore when TnCCLR is high no TnPF interrupt re-
Mode or Timer/Counter Mode. The operating mode is quest flag will be generated. In the Compare Match Out-
selected using the TnM1 and TnM0 bits in the TMnC1 put Mode, the CCRA can not be set to 0.
register. As the name of the mode suggests, after a comparison
is made, the TM output pin, will change state. The TM
Compare Output Mode output pin condition however only changes state when
To select this mode, bits TnM1 and TnM0 in the TMnC1 an TnAF interrupt request flag is generated after a com-
register, should be set to 00 respectively. In this mode pare match occurs from Comparator A. The TnPF inter-
once the counter is enabled and running it can be rupt request flag, generated from a compare match
cleared by three methods. These are a counter over- occurs from Comparator P, will have no effect on the TM
flow, a compare match from Comparator A and a com- output pin. The way in which the TM output pin changes
pare match from Comparator P. When the TnCCLR bit is state are determined by the condition of the TnIO1 and
low, there are two ways in which the counter can be TnIO0 bits in the TMnC1 register. The TM output pin can
cleared. One is when a compare match from Compara- be selected using the TnIO1 and TnIO0 bits to go high,
tor P, the other is when the CCRP bits are all zero which to go low or to toggle from its present condition when a
allows the counter to overflow. Here both TnAF and compare match occurs from Comparator A. The initial
TnPF interrupt request flags for Comparator A and Com- condition of the TM output pin, which is setup after the
parator P respectively, will both be generated. TnON bit changes from low to high, is setup using the
TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero
If the TnCCLR bit in the TMnC1 register is high then the
then no pin change will take place.
counter will be cleared when a compare match occurs
Counter
TnCCRL = 0; TnM1, TnM0 = 00
Counter
Value
overflow
CCRP = 0 CCRP > 0
Counter cleared by CCRP value
0x3FF CCRP > 0
CCRP
Pause Resume Counter
Stop Reset
CCRA
Time
TnON bit
TnPAU bit
TnPOL bit
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM O/P Pin
Output inverts
Output Pin set Output not affected by TnAF flag
Output Toggle when TnPOL is high
to Initial Level Remains High until reset by TnON bit
Low if TnOC = 0 with TnAF flag
Now TnIO1, TnIO0 = 10 Output Pin
Active High Output Reset to initial value
Select
Here TnIO1, TnIO0 = 11
Toggle Output Select
Note: 1. With TnCCLR = 0 the Comparator P match will clear the counter
2. TM output pin controlled only by TnAF flag
3. Output pin reset to initial state by TnON bit rising edge
Counter
TnCCLR = 1; TnM1, TnM0 = 00
Value
CCRA = 0
CCRA > 0 Counter cleared by CCRA value Counter overflows
0x3FF
CCRA = 0
CCRA
Pause Resume Counter
Stop Reset
CCRP
Time
TnON bit
TnPAU bit
TnPOL bit
No TnAF flag
CCRA Int. generated on
CCRA overflow
Flag TnAF
CCRP Int.
Flag TnPF
Output does
TnPF not not change
generated
TM O/P Pin
Timer/Counter Mode As both the period and duty cycle of the PWM waveform
To select this mode, bits TnM1 and TnM0 in the TMnC1 can be controlled, the choice of generated waveform is
register should be set to 11 respectively. The extremely flexible. In the PWM mode, the TnCCLR bit
Timer/Counter Mode operates in an identical way to the has no effect as the PWM period. Both of the CCRA and
Compare Match Output Mode generating the same in- CCRP registers are used to generate the PWM wave-
terrupt flags. The exception is that in the Timer/Counter form, one register is used to clear the internal counter
Mode the TM output pin is not used. Therefore the and thus control the PWM waveform frequency, while
above description and Timing Diagrams for the Com- the other one is used to control the duty cycle. Which
pare Match Output Mode can be used to understand its register is used to control either frequency or duty cycle
function. As the TM output pin is not used in this mode, is determined using the TnDPX bit in the TMnC1 regis-
the pin can be used as a normal I/O pin or other ter. The PWM waveform frequency and duty cycle can
pin-shared function. therefore be controlled by the values in the CCRA and
CCRP registers.
PWM Output Mode An interrupt flag, one for each of the CCRA and CCRP,
To select this mode, bits TnM1 and TnM0 in the TMnC1 will be generated when a compare match occurs from
register should be set to 10 respectively and also the either Comparator A or Comparator P. The TnOC bit in
TnIO1 and TnIO0 bits should be set to 10 respectively. the TMnC1 register is used to select the required polar-
The PWM function within the TM is useful for applica- ity of the PWM waveform while the two TnIO1 and
tions which require functions such as motor control, TnIO0 bits are used to enable the PWM output or to
heating control, illumination control etc. By providing a force the TM output pin to a fixed high or low level. The
signal of fixed frequency but of varying duty cycle on the TnPOL bit is used to reverse the polarity of the PWM
TM output pin, a square wave AC waveform can be gen- output waveform.
erated with varying equivalent DC RMS values.
Counter
Value Counter Cleared
by CCRP
TnDPX = 0; TnM1, TnM0 = 10
CCRA
Time
TnON bit
TnPAU bit
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
TnIO1, TnIO0 = 00
TnIO1, TnIO0 = 10 PWM Output TnIO1, TnIO0 = 10
Output Inactive
PWM Output
TM Pin
TnOC = 1
TM Pin
TnOC = 0
TnIIO1, TnIO0 = 10 Output Inverts
Here TnIO1, TnIO0 = 00 Resume PWM Output PWM resumes operation When TnPOL = 1
PWM Period Output Forced to Inactive Output remains at same level
set by CCRP level but PWM function
PWM Duty Cycle keeps running internally
set by CCRA
Counter
Value Counter Cleared
by CCRA
TnDPX = 1; TnM1, TnM0 = 10
CCRP
Time
TnON bit
TnPAU bit
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TnIO1, TnIO0 = 00
TnIO1, TnIO0 = 10 PWM Output Output Inactive TnIO1, TnIO0 = 10
PWM Output
TM Pin
TnOC = 1
TM Pin
TnOC = 0
TnIO1, TnIO0 = 10 Output Inverts
Here TnIO1, TnIO0 = 00 Resume PWM Output PWM resumes operation When TnPOL = 1
PWM Period Output Forced to Inactive Output remains at same level
set by CCRA level but PWM function
PWM Duty Cycle keeps running internally
set by CCRP
Single Pulse Mode automatically change from low to high using the external
To select this mode, bits TnM1 and TnM0 in the TMnC1 TCKn pin, which will in turn initiate the Single Pulse out-
register should be set to 10 respectively and also the put. When the TnON bit transitions to a high level, the
TnIO1 and TnIO0 bits should be set to 11 respectively. counter will start running and the pulse leading edge will
The Single Pulse Output Mode, as the name suggests, be generated. The TnON bit should remain high when
will generate a single shot pulse on the TM output pin. the pulse is in its active state. The generated pulse trail-
ing edge will be generated when the TnON bit is cleared
The trigger for the pulse output leading edge is a low to
to zero, which can be implemented using the application
high transition of the TnON bit, which can be imple-
program or when a compare match occurs from Com-
mented using the application program. However in the
parator A.
Single Pulse Mode, the TnON bit can also be made to
L e a d in g E d g e T r a ilin g E d g e
S /W C o m m a n d S /W C o m m a n d
S E T "T n O N " C L R "T n O N "
T n O N b it T n O N b it
o r o r
0 1 1 0
T C K n P in T r a n s itio n C C R A M a tc h C o m p a re
T M n O u tp u t P in
P u ls e W id th = C C R A V a lu e
Counter
Value
TnM1, TnM0 = 10; TnIO1, TnIO0 = 11
Counter Stopped
by CCRA
Time
TnPAU bit
TnPOL bit
No CCRP
Interrupt
generated
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TnIO1, TnIO0 = 00
Output Inactive
TnIO1, TnIO0 = 11 Single Pulse Output
TnIO1, TnIO0 = 11
TM Pin
TnOC = 1
TM Pin
TnOC = 0
Output Inverts
Here TnIO1, TnIO0 = 00 When TnPOL = 1
Pulse Width Output Forced to Inactive TnIO1, TnIO0 = 11
set by CCRA level but counter keeps Resume Single Pulse Output
running internally
However a compare match from Comparator A will also be latched into the CCRA registers and a TM interrupt
automatically clear the TnON bit and thus generate the generated. Irrespective of what events occur on the
Single Pulse output trailing edge. In this way the CCRA TPn_0 or TPn_1 pin the counter will continue to free run
value can be used to control the pulse width. A compare until the TnON bit changes from high to low. When a
match from Comparator A will also generate a TM inter- CCRP compare match occurs the counter will reset
rupt. The counter can only be reset back to zero when back to zero; in this way the CCRP value can be used to
the TnON bit changes from low to high when the counter control the maximum counter value. When a CCRP
restarts. In the Single Pulse Mode CCRP is not used. compare match occurs from Comparator P, a TM inter-
The TnCCLR and TnDPX bits are not used in this Mode. rupt will also be generated. Counting the number of
overflow interrupt signals from the CCRP can be a use-
Capture Input Mode ful method in measuring long pulse widths. The TnIO1
To select this mode bits TnM1 and TnM0 in the TMnC1 and TnIO0 bits can select the active trigger edge on the
register should be set to 01 respectively. This mode en- TPn_0 or TPn_1 pin to be a rising edge, falling edge or
ables external signals to capture and store the present both edge types. If the TnIO1 and TnIO0 bits are both
value of the internal counter and can therefore be used set high, then no capture operation will take place irre-
for applications such as pulse width measurements. spective of what happens on the TPn_0 or TPn_1 pin,
The external signal is supplied on the TPn_0 or TPn_1 however it must be noted that the counter will continue
pin, whose active edge can be either a rising edge, a to run.
falling edge or both rising and falling edges; the active As the TPn_0 or TPn_1 pin is pin shared with other func-
edge transition type is selected using the TnIO1 and tions, care must be taken if the TM is in the Input Cap-
TnIO0 bits in the TMnC1 register. The counter is started ture Mode. This is because if the pin is setup as an
when the TnON bit changes from low to high which is ini- output, then any transitions on this pin may cause an in-
tiated using the application program. put capture operation to be executed. The TnCCLR and
When the required edge transition appears on the TnDPX bits are not used in this Mode.
TPn_0 or TPn_1 pin the present value in the counter will
YY
XX Pause Resume
Time
TnON bit
TnPAU bit
Active
Active Active edges
TM Capture Pin edge edge
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
CCRA
Value XX YY XX YY
TnIO1, TnIO0
Value 00 - Rising edge 01 - Falling edge 10 - Both edges 11 - Disable Capture
Note: 1. TnM1, TnM0 = 01 and active edge set by TnIO1 and TnIO0 bits
2. TM Capture input pin active edge transfers counter value to CCRA
3. TnCCLR bit not used
4. No output function - TnOC and TnPOL bits not used
5. CCRP sets counter maximum value
Enhanced TM Operation The only way of changing the value of the 10-bit counter
At its core is a 10-bit count-up/count-down counter using the application program, is to clear the counter by
which is driven by a user selectable internal or external changing the TnON bit from low to high. The counter will
clock source. There are three internal comparators with also be cleared automatically by a counter overflow or a
the names, Comparator A, Comparator B and Com- compare match with one of its associated comparators.
parator P. These comparators will compare the value in When these conditions occur, a TM interrupt signal will
the counter with the CCRA, CCRB and CCRP registers. also usually be generated. The Enhanced Type TM can
The CCRP comparator is 3-bits wide whose value is operate in a number of different operational modes, can
compared with the highest 3-bits in the counter while be driven by different clock sources including an input
CCRA and CCRB are 10-bits wide and therefore com- pin and can also control output pins. All operating setup
pared with all counter bits. conditions are selected using relevant internal registers.
C C R P
C o m p a ra to r P M a tc h
3 - b it C o m p a r a to r P T n P F In te rru p t
b 7 ~ b 9 T n A O C
fS Y S /4 0 0 0
fS Y S 0 0 1
fH /1 6 0 1 0
C o u n te r O u tp u t P o la r ity T P n A P in
fH /6 4 0 1 1 C le a r 0 T P n A
1 0 - b it U p /D o w n C o u n te r C o n tro l C o n tro l In p u t/O u tp u t
fT B C 1 0 0 1
R e s e rv e d 1 0 1
1 1 0
T n O N T n C C L R T n A M 1 , T n A M 0 T n A P O L
T C K n 1 1 1 T n P A U b 0 ~ b 9 T n A IO 1 , T n A IO 0
C o m p a ra to r A M a tc h T n A F
T n C K 2 ~ T n C K 0 1 0 - b it
In te rru p t
C o m p a ra to r A
T n A IO 1 , T n A IO 0
C C R A
E d g e
D e te c to r
T n B O C
T P n B -0
O u tp u t P o la r ity T P n B P in
1 0 - b it C o m p a ra to r B M a tc h T P n B -1
C o n tro l C o n tro l In p u t/O u tp u t
C o m p a ra to r B T P n B -2
T n B F
In te rru p t
T n B M 1 , T n B M 0 T n B P O L
C C R B T n B IO 1 , T n B IO 0
E d g e
D e te c to r
T n IO 1 , T n IO 0
Bit 7 6 5 4 3 2 1 0
Name T1PAU T1CK2 T1CK1 T1CK0 T1ON T1RP2 T1RP1 T1RP0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial
condition, as specified by the T1OC bit, when the T1ON bit changes from low to high.
Bit 2~0 T1RP2~T1RP0: TM1 CCRP 3-bit register, compared with the TM1 Counter bit 9~bit 7
Comparator P Match Period
000: 1024 TM1 clocks
001: 128 TM1 clocks
010: 256 TM1 clocks
011: 384 TM1 clocks
100: 512 TM1 clocks
101: 640 TM1 clocks
110: 768 TM1 clocks
111: 896 TM1 clocks
These three bits are used to setup the value on the internal CCRP 3-bit register, which are then
compared with the internal counters highest three bits. The result of this comparison can be
selected to clear the internal counter if the T1CCLR bit is set to zero. Setting the T1CCLR bit to
zero ensures that a compare match with the CCRP values will reset the internal counter. As the
CCRP bits are only compared with the highest three counter bits, the compare values exist in 128
clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at
its maximum value.
Bit 7 6 5 4 3 2 1 0
Name T1AM1 T1AM0 T1AIO1 T1AIO0 T1AOC T1APOL T1CDN T1CCLR
R/W R/W R/W R/W R/W R/W R/W R R/W
POR 0 0 0 0 0 0 0 0
In the Compare Match Output Mode, the T1AIO1 and T1AIO0 bits determine how the TM
output pin changes state when a compare match occurs from the Comparator A. The TM output
pin can be setup to switch high, switch low or to toggle its present state when a compare match
occurs from the Comparator A. When the bits are both zero, then no change will take place on
the output. The initial value of the TM output pin should be setup using the T1AOC bit in the
TM1C1 register. Note that the output level requested by the T1AIO1 and T1AIO0 bits must be
different from the initial value setup using the T1AOC bit otherwise no change will occur on the
TM output pin when a compare match occurs. After the TM output pin changes state it can be
reset to its initial level by changing the level of the T1ON bit from low to high.
Bit 3 T1AOC: TP1A Output control bit
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Mode/ Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the TM output pin. Its operation depends upon whether TM is
being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode.
It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it
determines the logic level of the TM output pin before a compare match occurs. In the PWM
Mode it determines if the PWM signal is active high or active low.
Bit 2 T1APOL: TP1A Output polarity Control
0: Non-invert
1: Invert
This bit controls the polarity of the TP1A output pin. When the bit is set high the TM output pin
will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the
Timer/Counter Mode.
Bit 1 T1CDN: TM1 Counter count up or down flag
0: Count up
1: Count down
Bit 0 T1CCLR: Select TM1 Counter clear condition
0: TM1 Comparator P match
1: TM1 Comparator A match
This bit is used to select the method which clears the counter. Remember that the Enhanced
TM contains two comparators, Comparator A and Comparator P, either of which can be selected
to clear the internal counter. With the T1CCLR bit set high, the counter will be cleared when a
compare match occurs from the Comparator A. When the bit is low, the counter will be cleared
when a compare match occurs from the Comparator P or with a counter overflow. A counter
overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The
T1CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode.
Bit 7 6 5 4 3 2 1 0
Name T1BM1 T1BM0 T1BIO1 T1BIO0 T1BOC T1BPOL T1PWM1 T1PWM0
R/W R/W R/W R/W R/W R/W R/W R R/W
POR 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R R R R R R R R
POR 0 0 0 0 0 0 0 0
Bit 7~0 TM1DL: TM1 Counter Low Byte Register bit 7~bit 0
TM1 10-bit Counter bit 7~bit 0
Bit 7 6 5 4 3 2 1 0
Name D9 D8
R/W R R
POR 0 0
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Bit 7~0 TM1AL: TM1 CCRA Low Byte Register bit 7~bit 0
TM1 10-bit CCRA bit 7~bit 0
Bit 7 6 5 4 3 2 1 0
Name D9 D8
R/W R/W R/W
POR 0 0
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
Name D9 D8
R/W R/W R/W
POR 0 0
Compare Output Mode If the TnCCLR bit in the TMnC1 register is high then the
To select this mode, bits TnAM1, TnAM0 and TnBM1, counter will be cleared when a compare match occurs
TnBM0 in the TMnC1/TMnC2 registers should be all from Comparator A. However, here only the TnAF inter-
cleared to zero. In this mode once the counter is en- rupt request flag will be generated even if the value of
abled and running it can be cleared by three methods. the CCRP bits is less than that of the CCRA registers.
These are a counter overflow, a compare match from Therefore when TnCCLR is high no TnPF interrupt re-
Comparator A and a compare match from Comparator quest flag will be generated.
P. When the TnCCLR bit is low, there are two ways in
which the counter can be cleared. One is when a com-
pare match occurs from Comparator P, the other is when
the CCRP bits are all zero which allows the counter to
overflow. Here both the TnAF and TnPF interrupt re-
quest flags for Comparator A and Comparator P respec-
tively, will both be generated.
As the name of the mode suggests, after a comparison be selected using the TnAIO1, TnAIO0 bits (for the
is made, the TM output pin, will change state. The TM TPnA pin) and TnBIO1, TnBIO0 bits (for the TPnB_0,
output pin condition however only changes state when TPnB_1 or TPnB_2 pins) to go high, to go low or to tog-
an TnAF or TnBF interrupt request flag is generated af- gle from its present condition when a compare match
ter a compare match occurs from Comparator A or Com- occurs from Comparator A or a compare match occurs
parator B. The TnPF interrupt request flag, generated from Comparator B. The initial condition of the TM out-
from a compare match from Comparator P, will have no put pin, which is setup after the TnON bit changes from
effect on the TM output pin. The way in which the TM low to high, is setup using the TnAOC or TnBOC bit for
output pin changes state is determined by the condition TPnA or TPnB_0, TPnB_1, TPnB_2 output pins. Note
of the TnAIO1 and TnAIO0 bits in the TMnC1 register for that if the TnAIO1,TnAIO0 and TnBIO1, TnBIO0 bits are
ETM CCRA, and the TnBIO1 and TnBIO0 bits in the zero then no pin change will take place.
TMnC2 register for ETM CCRB. The TM output pin can
Counter
Value
Counter TnCCLR = 0; TnAM1, TnAM0 = 00
overflow
CCRP = 0 CCRP > 0
Counter cleared by CCRP value
0x3FF CCRP > 0
CCRP
Pause Resume Counter
Stop Reset
CCRA
Time
TnON bit
TnPAU bit
TnAPOL bit
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
Output Pin set Output not affected by TnAF flag Output inverts
to Initial Level Output Toggle Remains High until reset by TnON bit when TnAPOL is high
Low if TnAOC = 0 with TnAF flag
Now TnAIO1, TnAIO0 = 10 Output Pin
Active High Output Select Reset to initial value
Note: 1. With TnCCLR = 0 the Comparator P match will clear the counter
2. TPnA output pin controlled only by TnAF flag
3. Output pin reset to initial state by TnON bit rising edge
Counter
Value
Counter TnCCLR = 0; TnBM1, TnBM0 = 00
overflow
CCRP = 0 CCRP > 0
Counter cleared by CCRP value
0x3FF CCRP > 0
CCRP
Pause Resume Counter
Stop Reset
CCRB
Time
TnON bit
TnPAU bit
TnBPOL bit
CCRP Int.
Flag TnPF
CCRB Int.
Flag TnBAF
Note: 1. With TnCCLR = 0 the Comparator P match will clear the counter
2. TPnB output pin controlled only by TnBF flag
3. Output pin reset to initial state by TnON bit rising edge
Counter
TnCCLR = 1; TnAM1, TnAM0 = 00
Value
CCRA = 0
CCRA > 0 Counter cleared by CCRA value Counter overflows
0x3FF
CCRA = 0
CCRA
Pause Resume Counter
Stop Reset
CCRP
Time
TnON bit
TnPAU bit
TnAPOL bit
No TnAF flag
CCRA Int. generated on
CCRA overflow
Flag TnAF
CCRP Int.
Flag TnPF
Output does
TnPF not not change
generated
TPnA O/P Pin
Note: 1. With TnCCLR = 1 the Comparator A match will clear the counter
2. TPnA output pin controlled only by TnAF flag
3. TPnA output pin reset to initial state by TnON rising edge
4. TnPF flags not generated when TnCCLR = 1
Counter
TnCCLR = 1; TnBM1, TnBM0 = 00
Value
CCRA = 0
CCRA > 0 Counter cleared by CCRA value Counter overflows
0x3FF
CCRA = 0
CCRA
Pause Resume Counter
Stop Reset
CCRB
Time
TnON bit
TnPAU bit
TnBPOL bit
No TnAF flag
CCRA Int. generated on
CCRA overflow
Flag TnAF
CCRB Int.
Flag TnBF
Note: 1. With TnCCLR = 1 the Comparator A match will clear the counter
2. TPnB output pin controlled only by TnBF flag
3. TPnB output pin reset to initial state by TnON rising edge
4. TnPF flags not generated when TnCCLR = 1
Timer/Counter Mode can be finely controlled using the CCRA registers. In this
To select this mode, bits TnAM1, TnAM0 and TnBM1, case the CCRB registers are used to set the PWM duty
TnBM0 in the TMnC1 and TMnC2 register should all be value (for TPnB output pins). The CCRP bits are not used
set high. The Timer/Counter Mode operates in an identi- and TPnA output pin is not used. The PWM output can
cal way to the Compare Match Output Mode generating only be generated on the TPnB output pins. With the
the same interrupt flags. The exception is that in the TnCCLR bit cleared to zero, the PWM period is set using
Timer/Counter Mode the TM output pin is not used. one of the eight values of the three CCRP bits, in multi-
Therefore the above description and Timing Diagrams ples of 128. Now both CCRA and CCRB registers can be
for the Compare Match Output Mode can be used to un- used to setup different duty cycle values to provide dual
derstand its function. As the TM output pin is not used in PWM outputs on their relative TPnA and TPnB pins.
this mode, the pin can be used as a normal I/O pin or The TnPWM1 and TnPWM0 bits determine the PWM
other pin-shared function. alignment type, which can be either edge or centre type.
In edge alignment, the leading edge of the PWM signals
PWM Output Mode will all be generated concurrently when the counter is re-
To select this mode, the required bit pairs, TnAM1, set to zero. With all power currents switching on at the
TnAM0 and TnBM1, TnBM0 should be set to 10 respec- same time, this may give rise to problems in higher
tively and also the TnAIO1, TnAIO0 and TnBIO1, power applications. In centre alignment the centre of the
TnBIO0 bits should be set to 10 respectively. The PWM PWM active signals will occur sequentially, thus reduc-
function within the TM is useful for applications which re- ing the level of simultaneous power switching currents.
quire functions such as motor control, heating control, il- Interrupt flags, one for each of the CCRA, CCRB and
lumination control etc. By providing a signal of fixed CCRP, will be generated when a compare match occurs
frequency but of varying duty cycle on the TM output pin, from either the Comparator A, Comparator B or Com-
a square wave AC waveform can be generated with parator P. The TnAOC and TnBOC bits in the TMnC1 and
varying equivalent DC RMS values. TMnC2 register are used to select the required polarity of
As both the period and duty cycle of the PWM waveform the PWM waveform while the two TnAIO1, TnAIO0 and
can be controlled, the choice of generated waveform is TnBIO1, TnBIO0 bits pairs are used to enable the PWM
extremely flexible. In the PWM mode, the TnCCLR bit is output or to force the TM output pin to a fixed high or low
used to determine in which way the PWM period is con- level. The TnAPOL and TnBPOL bit are used to reverse
trolled. With the TnCCLR bit set high, the PWM period the polarity of the PWM output waveform.
TnCCLR = 0;
Counter
Value Counter Cleared by CCRP Mode Bits TnA(B)M1, TnA(B)M0 = 10
TnPWM1/TnPWM0 = 00
CCRP
Counter reset
Counter Stops when TnON
Paus e Resume if TnON bit low returns high
CCRA
CCRB
Time
TnON bit
TnPAU bit
TnAPOL bit
Interrupt
still generated
CCRA Int.
Flag TnAF
CCRB Int.
Flag TnBF
CCRP Int.
Flag TnPF
TPnA Pin
TnAOC = 1 PWM resumes
operation - outputs remain
TnAIO1, TnAIO0 = 10 Output Inverts
Duty Cycle at same level
set by CCRA Resume PWM Output When TnAPOL = 1
TPnB Pin
TnBOC = 1
TPnB Pin
TnBOC = 0
Here TnAIO1,
Duty Cycle TnAIO0 = 00
set by CCRB Output is Inactive
PWM Period
set by CCRP PWM runs internally
Note: 1. Here TnCCLR = 0 therefore CCRP clears counter and determines PWM period
2. Internal PWM function continues even when TnAIO1, TnAIO0 ( or TnBIO1, TnBIO0) = 00 or 01
3. CCRA controls TPnA PWM duty and CCRB controls TPnB PWM duty
TnCCLR = 1;
Mode Bits TnA(B)M1, TnA(B)M0 = 10
TnPW M1/TnPWM0 = 00
Counter Counter Cleared by CCRA
Value
CCRB
Time
TnON bit
TnPAU bit
TnBPOL bit
CCRA Int.
Flag TnAF
CCRB Int.
Flag TnBF
PWM resumes
operation - outputs remain
at same level
TPnB Pin
TnBOC = 1
TPnB Pin
TnBOC = 0
Duty Cycle
Output Inverts
s et by CCRB
When TnBPOL = 1
PWM Period
set by CCRA
Note: 1. Here TnCCLR = 1 therefore CCRA clears counter and determines PWM period
2. Internal PWM function continues even when TnBIO1, TnBIO0 = 00 or 01
3. CCRA controls TPnB PWM period and CCRB controls TPnB PWM duty
TnCCLR = 0;
Mode Bits TnA(B)M1, TnA(B)M0 = 10
TnPWM1/TnPWM0 = 11
Counter
Value
Counter Stops
CCRP if TnON bit low Counter reset when
TnON returns high
Pause Resume
CCRA
CCRB
Time
TnON bit
TnPAU bit
TnAPOL bit
CCRA Int.
Flag TnAF
CCRB Int.
Flag TnBF
CCRP Int.
Flag TnPF
TnAIO1, TnAIO0 = 00
Output Inactive TnAIO1, TnAIO0 = 10
TnAIO1, TnAIO0 = 10 PWM Output PWM Output
TPnA Pin
TnAOC = 1
Duty Cycle
set by CCRA Output Inverts
When TnAPOL = 1
TPnB Pin
TnBOC = 1
TPnB Pin
TnBOC = 0
Duty Cycle
set by CCRB
Note: 1. Here TnCCLR = 0 therefore CCRP clears counter and determines PWM period
2. TnPWM1/TnPWM0 = 11 therefore PWM is centre aligned
3. Internal PWM function continues even when TnAIO1, TnAIO0 ( or TnBIO1, TnBIO0) = 00 or 01
4. CCRA controls TPnA PWM duty and CCRB controls TPnB PWM duty
TnCCLR = 1;
Mode Bits TnA(B)M1, TnA(B)M0 = 10
TnPWM1/TnPWM0 = 11
Counter
Value
Counter Stops
CCRA Counter reset when
if TnON bit low
TnON returns high
Pause Resume
CCRB
Time
TnON bit
TnPAU bit
TnBPOL bit
CCRB Int.
Flag TnBF
CCRA Int.
Flag TnAF
TPnB Pin
TnBOC = 1
TPnB Pin
TnBOC = 0
Duty Cycle
set by CCRB Output Inverts
PWM Period When TnBPOL = 1
set by CCRA
Note: 1. Here TnCCLR = 1 therefore CCRA clears counter and determines PWM period
2. TnPWM1/TnPWM0 = 11 therefore PWM is centre aligned
3. Internal PWM function continues even when TnBIO1, TnBIO0 = 00 or 01
4. CCRA controls the TPnB PWM period and CCRB controls the TPnB PWM duty
Single Pulse Output Mode TPnA will be generated. The TnON bit should remain
To select this mode, the required bit pairs, TnAM1, high when the pulse is in its active state. The generated
TnAM0 and TnBM1, TnBM0 should be set to 10 respec- pulse trailing edge of TPnA and TPnB will be generated
tively and also the corresponding TnAIO1, TnAIO0 and when the TnON bit is cleared to zero, which can be im-
TnBIO1, TnBIO0 bits should be set to 11 respectively. plemented using the application program or when a
The Single Pulse Output Mode, as the name suggests, compare match occurs from Comparator A.
will generate a single shot pulse on the TM output pin. However a compare match from Comparator A will also
The trigger for the pulse TPnA output leading edge is a automatically clear the TnON bit and thus generate the
low to high transition of the TnON bit, which can be im- Single Pulse output trailing edge of TPnA and TPnB. In
plemented using the application program. The trigger this way the CCRA value can be used to control the
for the pulse TPnB output leading edge is a compare pulse width of TPnA. The CCRA-CCRB value can be
match from Comparator B, which can be implemented used to control the pulse width of TPnB. A compare
using the application program. However in the Single match from Comparator A and Comparator B will also
Pulse Mode, the TnON bit can also be made to automat- generate TM interrupts. The counter can only be reset
ically change from low to high using the external TCKn back to zero when the TnON bit changes from low to
pin, which will in turn initiate the Single Pulse output of high when the counter restarts. In the Single Pulse
TPnA. When the TnON bit transitions to a high level, the Mode CCRP is not used. The TnCCLR bit is also not
counter will start running and the pulse leading edge of used.
L e a d in g E d g e T r a ilin g E d g e
S /W C o m m a n d S /W C o m m a n d
S E T "T n O N " C L R "T n O N "
T n O N b it T n O N b it
o r o r
0 1 1 0
T C K n P in T r a n s itio n C C R A M a tc h C o m p a re
T P n A O u tp u t P in
P u ls e W id th = C C R A V a lu e
T P n B O u tp u t P in
P u ls e W id th = C C R A - C C R B V a lu e
Single Pulse Generation
Time
TnON bit
Auto. s et
by TCKn pin
Software Cleared by Software Software Software
Trigger CCRA match Trigger Clear Trigger
TCKn pin
TCKn pin
Trigger
TnPAU bit
TnAPOL,
TnBPOL bit
CCRB Int.
Flag TnBF
CCRA Int.
Flag TnAF
TnAIO1, TnAIO0 and TnBIO1, TnBIO0
TnAIO1, TnAIO0 and TnBIO1, TnBIO0 = 00 Output Inactive
= 11 Single Pulse Output
TnAIO1, TnAIO0 and TnBIO1, TnBIO0 = 11
TPnA Pin
TnAOC = 1
TPnA Pin
TnAOC = 0
TPnB Pin
TnBOC = 0
Output Inverts
When TnBPOL = 1
Capture Input Mode zero; in this way the CCRP value can be used to control
To select this mode bits TnAM1, TnAM0 and TnBM1, the maximum counter value. When a CCRP compare
TnBM0 in the TMnC1 and TMnC2 registers should be match occurs from Comparator P, a TM interrupt will
set to 01 respectively. This mode enables external sig- also be generated. Counting the number of overflow in-
nals to capture and store the present value of the inter- terrupt signals from the CCRP can be a useful method in
nal counter and can therefore be used for applications measuring long pulse widths. The TnAIO1, TnAIO0 and
such as pulse width measurements. The external signal TnBIO1, TnBIO0 bits can select the active trigger edge
is supplied on the TPnA and TPnB_0, TPnB_1, TPnB_2 on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins to be
pins, whose active edge can be either a rising edge, a a rising edge, falling edge or both edge types. If the
falling edge or both rising and falling edges; the active TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits are both set
edge transition type is selected using the TnAIO1, high, then no capture operation will take place irrespec-
TnAIO0 and TnBIO1, TnBIO0 bits in the TMnC1 and tive of what happens on the TPnA and TPnB_0,
TMnC2 registers. The counter is started when the TnON TPnB_1, TPnB_2 pins, however it must be noted that
bit changes from low to high which is initiated using the the counter will continue to run.
application program. As the TPnA and TPnB_0, TPnB_1, TPnB_2 pins are
When the required edge transition appears on the TPnA pin shared with other functions, care must be taken if the
and TPnB_0, TPnB_1, TPnB_2 pins the present value TM is in the Capture Input Mode. This is because if the
in the counter will be latched into the CCRA and CCRB pin is setup as an output, then any transitions on this pin
registers and a TM interrupt generated. Irrespective of may cause an input capture operation to be executed.
what events occur on the TPnA and TPnB_0, TPnB_1, The TnCCLR, TnAOC, TnBOC, TnAPOL and TnBPOL
TPnB_2 pins the counter will continue to free run until bits are not used in this mode.
the TnON bit changes from high to low. When a CCRP
compare match occurs the counter will reset back to
TnAM1, TnAM0 = 01
Counter Counter
Value overflow
CCRP Stop
Counter
Reset
YY
XX Pause Resume
Time
TnON bit
TnPAU bit
Active
Active Active edges
TM Capture Pin edge edge
CCRA Int.
Flag TnAF
CCRP Int.
Flag TnPF
CCRA
Value XX YY XX YY
TnAIO1, TnAIO0
Value 00 - Rising edge 01 - Falling edge 10 - Both edges 11 - Disable Capture
Note: 1. TnAM1, TnAM0 = 01 and active edge set by TnAIO1 and TnAIO0 bits
2. TM Capture input pin active edge transfers counter value to CCRA
3. TnCCLR bit not used
4. No output function - TnAOC and TnAPOL bits not used
5. CCRP sets counter maximum value
TnBM1, TnBM0 = 01
Counter Counter
Value overflow
CCRP Stop
Counter
Reset
YY
XX Pause Resume
Time
TnON bit
TnPAU bit
Active
Active Active edges
TM Capture Pin edge edge
CCRB Int.
Flag TnBF
CCRP Int.
Flag TnPF
CCRB
Value XX YY XX YY
TnBIO1, TnBIO0
Value 00 - Rising edge 01 - Falling edge 10 - Both edges 11 - Disable Capture
Note: 1. TnBM1, TnBM0 = 01 and active edge set by TnBIO1 and TnBIO0 bits
2. TM Capture input pin active edge transfers counter value to CCRB
3. TnCCLR bit not used
4. No output function - TnBOC and TnBPOL bits not used
5. CCRP sets counter maximum value
Comparators
Two independent analog comparators are contained Any pull-high resistors connected to the shared com-
within these devices. These functions offer flexibility via parator input pins will be automatically disconnected
their register controlled features such as power-down, when the comparator is enabled. As the comparator in-
polarity select, hysteresis etc. In sharing their pins with puts approach their switching level, some spurious out-
normal I/O pins the comparators do not waste precious put signals may be generated on the comparator output
I/O pins if there functions are otherwise unused. due to the slow rising or falling nature of the input sig-
nals. This can be minimised by selecting the hysteresis
C n P O L C n O U T
function will apply a small amount of positive feedback
C n + to the comparator. Ideally the comparator should switch
C n X
C n - at the point where the positive and negative inputs sig-
C n S E L nals are at the same voltage level, however, unavoid-
Comparator able input offsets introduce some uncertainties here.
The hysteresis function, if enabled, also increases the
Comparator Operation switching offset value.
Register Bit
Name 7 6 5 4 3 2 1 0
CP0C C0SEL C0EN C0POL C0OUT C0OS C0HYEN
CP1C C1SEL C1EN C1POL C1OUT C1OS C1HYEN
Comparator Registers List
CP0C Register
Bit 7 6 5 4 3 2 1 0
Name C0SEL C0EN C0POL C0OUT C0OS C0HYEN
R/W R/W R/W R/W R R/W R/W
POR 1 0 0 0 0 1
CP1C Register
Bit 7 6 5 4 3 2 1 0
Name C1SEL C1EN C1POL C1OUT C1OS C1HYEN
R/W R/W R/W R/W R R/W R/W
POR 1 0 0 0 0 1
D a ta B u s
S IM D
S D I P in
T x /R x S h ift R e g is te r
S D O P in
C K E N b it C lo c k E n a b le /D is a b le
E d g e /P o la r ity
C K P O L B b it C o n tro l B u s y C o n fig u r a tio n
S ta tu s W C O L F la g
O p tio n
S C K P in
fS Y S T R F F la g
fT B C
C lo c k
S o u r c e S e le c t
T M 0 C C R P m a tc h fre q u e n c y /2
S C S P in
C S E N b it C o n fig u r a tio n
O p tio n
E n a b le /D is a b le
SPI Block Diagram
The SPI function in this device offers the following There are several configuration options associated with
features: the SPI interface. One of these is to enable the SIM
Full duplex synchronous data transfer function which selects the SIM pins rather than normal
Both Master and Slave modes I/O pins. Note that if the configuration option does not
LSB first or MSB first data transmission modes select the SIM function then the SIMEN bit in the SIMC0
register will have no effect. Another two SPI configura-
Transmission complete flag
tion options determine if the CSEN and WCOL bits are
Rising or falling active clock edge to be used.
WCOL and CSEN bit enabled or disable select
SPI Registers
The status of the SPI interface pins is determined by a
number of factors such as whether the device is in the There are three internal registers which control the over-
master or slave mode and upon the condition of certain all operation of the SPI interface. These are the SIMD
control bits such as CSEN and SIMEN. data register and two registers SIMC0 and SIMC2. Note
2
that the SIMC1 register is only used by the I C interface.
Register Bit
Name 7 6 5 4 3 2 1 0
SIMC0 SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN
SIMD D7 D6 D5 D4 D3 D2 D1 D0
SIMC2 D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF
SIM Registers List
The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI
and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the
SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmis-
sion or reception of data from the SPI bus must be made via the SIMD register.
SIMD Register
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR x x x x x x x x
x unknown
There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2 register also has
the name SIMA which is used by the I2C function. The SIMC1 register is not used by the SPI function, only by the I2C
function. Register SIMC0 is used to control the enable/disable function and to set the data transmission clock fre-
quency. Although not connected with the SPI function, the SIMC0 register is also used to control the Peripheral Clock
Prescaler. Register SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag etc.
SIMC0 Register
Bit 7 6 5 4 3 2 1 0
Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN
R/W R/W R/W R/W R/W R/W R/W R/W
POR 1 1 1 0 0 0 0
SIMC2 Register
Bit 7 6 5 4 3 2 1 0
Name D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
SPI Communication The master should output an SCS signal to enable the
After the SPI interface is enabled by setting the SIMEN slave device before a clock signal is provided. The slave
bit high, then in the Master Mode, when data is written to data to be transferred should be well prepared at the ap-
the SIMD register, transmission/reception will begin si- propriate moment relative to the SCS signal depending
multaneously. When the data transfer is complete, the upon the configurations of the CKPOLB bit and CKEG
TRF flag will be set automatically, but must be cleared bit. The accompanying timing diagram shows the rela-
using the application program. In the Slave Mode, when tionship between the slave data and SCS signal for vari-
the clock signal from the master has been received, any ous configurations of the CKPOLB and CKEG bits.
data in the SIMD register will be transmitted and any The SPI will continue to function even in the IDLE Mode.
data on the SDI pin will be shifted into the SIMD register.
S IM E N = 1 , C S E N = 0 ( E x te r n a l P u ll- H ig h )
S C S S IM E N , C S E N = 1
S C K (C K P O L B = 1 , C K E G = 0 )
S C K (C K P O L B = 0 , C K E G = 0 )
S C K (C K P O L B = 1 , C K E G = 1 )
S C K (C K P O L B = 0 , C K E G = 1 )
S D O (C K E G = 0 ) D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
S D O (C K E G = 1 ) D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
S D I D a ta C a p tu re
W r ite to S IM D
SPI Master Mode Timing
S C S
S C K (C K P O L B = 1 )
S C K (C K P O L B = 0 )
S D O D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
S D I D a ta C a p tu re
W r ite to S IM D
( S D O d o e s n o t c h a n g e u n til fir s t S C K e d g e )
S C S
S C K (C K P O L B = 1 )
S C K (C K P O L B = 0 )
S D O D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
S D I D a ta C a p tu re
W r ite to S IM D
( S D O c h a n g e s a s s o o n a s w r itin g o c c u r s ; S D O is flo a tin g if S C S = 1 )
N o te : F o r S P I s la v e m o d e , if S IM E N = 1 a n d C S E N = 0 , S P I is a lw a y s e n a b le d
a n d ig n o r e s th e S C S le v e l.
SPI Slave Mode Timing - CKEG=1
S P I tra n s fe r
W r ite D a ta
C le a r W C O L
in to S IM D
M a s te r m a s te r o r S la v e
s la v e
? Y
W C O L = 1 ?
S IM [2 :0 ]= 0 0 0 ,
S IM [2 :0 ]= 1 0 1 N
0 0 1 ,0 1 0 ,0 1 1 o r 1 0 0
N T r a n s m is s io n
c o m p le te d ?
C o n fig u r e C K P O L B , (T R F = 1 ? )
C K E G , C S E N a n d M L S
R e a d D a ta
S IM E N = 1
fro m S IM D
A C le a r T R F
T ra n s fe r N
F in is h e d ?
E N D
Register Bit
Name 7 6 5 4 3 2 1 0
SIMC0 SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN
SIMC1 HCF HANS HBB HTX TXAK SRW IAMWU RXAK
SIMD D7 D6 D5 D4 D3 D2 D1 D0
SIMA IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 D0
I2C Registers List
SIMC0 Register
Bit 7 6 5 4 3 2 1 0
Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN
R/W R/W R/W R/W R/W R/W R/W R/W
POR 1 1 1 0 0 0 0
SIMC1 Register
Bit 7 6 5 4 3 2 1 0
Name HCF HAAS HBB HTX TXAK SRW IAMWU RXAK
R/W R R R R/W R/W R R/W R
POR 1 0 0 0 0 0 0 1
2
Bit 7 HCF: I C Bus data transfer completion flag
0: Data is being transferred
1: Completion of an 8-bit data transfer
The HCF flag is the data transfer flag. This flag will be zero when data is being transferred.
Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated.
Bit 6 HAAS: I2C Bus address match flag
0: Not address match
1: Address match
The HASS flag is the address match flag. This flag is used to determine if the slave device
address is the same as the master transmit address. If the addresses match then this bit will be
high, if there is no match then the flag will be low.
Bit 5 HBB: I2C Bus busy flag
0: I2C Bus is not busy
1: I2C Bus is busy
The HBB flag is the I2C busy flag. This flag will be 1 when the I2C bus is busy which will
occur when a START signal is detected. The flag will be set to 0 when the bus is free which will
occur when a STOP signal is detected.
Bit 4 HTX: Select I2C slave device is transmitter or receiver
0: Slave device is the receiver
1: Slave device is the transmitter
Bit 3 TXAK: I2C Bus transmit acknowledge flag
0: Slave send acknowledge flag
1: Slave do not send acknowledge flag
The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits of data,
this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device
must always set TXAK bit to 0 before further data is received.
Bit 2 SRW: I2C Slave Read/Write flag
0: Slave device should be in receive mode
1: Slave device should be in transmit mode
The SRW flag is the I2C Slave Read/Write flag. This flag determines whether the master
device wishes to transmit or receive data from the I2C bus. When the transmitted address and
slave address is match, that is when the HAAS flag is set high, the slave device will check the
SRW flag to determine whether it should be in transmit mode or receive mode. If the SRW flag is
high, the master is requesting to read data from the bus, so the slave device should be in transmit
mode. When the SRW flag is zero, the master will write data to the bus, therefore the slave
device should be in receive mode to read this data.
Bit 1 IAMWU: I2C Address Match Wake-up Control
0: Disable
1: Enable
This bit should be set to 1 to enable I2C address match wake up from SLEEP or IDLE Mode.
Bit 0 RXAK: I2C Bus Receive acknowledge flag
0: Slave receive acknowledge flag
1: Slave do not receive acknowledge flag
The RXAK flag is the receiver acknowledge flag. When the RXAK flag is 0, it means that a
acknowledge signal has been received at the 9th clock, after 8 bits of data have been
transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag
to determine if the master receiver wishes to receive the next byte. The slave transmitter will
therefore continue sending out data until the RXAK flag is 1. When this occurs, the slave
transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C
Bus.
The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI
and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the
SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmis-
sion or reception of data from the SPI bus must be made via the SIMD register.
SIMD Register
Bit 7 6 5 4 3 2 1 0
Name D7 D6 D5 D4 D3 D2 D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR x x x x x x x x
x unknown
SIMA Register
Bit 7 6 5 4 3 2 1 0
Name IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0
R/W R/W R/W R/W R/W R/W R/W R/W
POR x x x x x x x
x unknown
2
Bit 7~1 IICA6~ IICA0: I C slave address
IICA6~ IICA0 is the I2C slave address bit 6~ bit 0.
The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA
register is the location where the 7-bit slave address of the slave device is stored. Bits 7~ 1 of the
SIMA register define the device slave address. Bit 0 is not defined.
When a master device, which is connected to the I2C bus, sends out an address, which
matches the slave address in the SIMA register, the slave device will be selected. Note that the
SIMA register is the same register address as SIMC2 which is used by the SPI interface.
Bit 0 Undefined bit
This bit can be read or written by user software program.
D a ta B u s
I2C D a ta R e g is te r S la v e A d d r e s s R e g is te r
(S IM D ) (S IM A )
A d d re s s A d d re s s M a tc h
H T X B it C o m p a ra to r H A A S B it I2C In te rru p t
D ir e c tio n C o n tr o l
S C L P in
D a ta in L S B
S D A P in S h ift R e g is te r
D a ta O u t M S B R e a d /w r ite S la v e
M S R W B it
U
X E n a b le /D is a b le A c k n o w le d g e
8 - b it D a ta C o m p le te H C F B it
T r a n s m it/R e c e iv e
C o n tr o l U n it D e te c t S ta rt o r S to p
H B B B it
2
I C Block Diagram
the master that a slave device has accepted its calling 0, before it can receive the next data byte. If the slave
address. If no acknowledge signal is received by the transmitter does not receive an acknowledge bit signal
master then a STOP signal must be transmitted by the from the master receiver, then the slave transmitter will
master to end the communication. When the HAAS flag release the SDA line to allow the master to send a STOP
is high, the addresses have matched and the slave de- signal to release the I2C Bus. The corresponding data
vice must check the SRW flag to determine if it is to be a will be stored in the SIMD register. If setup as a transmit-
transmitter or a receiver. If the SRW flag is high, the ter, the slave device must first write the data to be trans-
slave device should be setup to be a transmitter so the mitted into the SIMD register. If setup as a receiver, the
HTX bit in the SIMC1 register should be set to 1. If the slave device must read the transmitted data from the
SRW flag is low, then the microcontroller slave device SIMD register.
should be setup as a receiver and the HTX bit in the
When the slave receiver receives the data byte, it must
SIMC1 register should be set to 0. generate an acknowledge bit, known as TXAK, on the
9th clock. The slave device, which is setup as a trans-
I2C Bus Data and Acknowledge Signal
mitter will check the RXAK bit in the SIMC1 register to
The transmitted data is 8-bits wide and is transmitted af- determine if it is to send another data byte, if not then it
ter the slave device has acknowledged receipt of its will release the SDA line and await the receipt of a STOP
slave address. The order of serial bit transmission is the signal from the master.
MSB first and the LSB last. After receipt of 8-bits of data,
the receiver must transmit an acknowledge signal, level
S ta rt S la v e A d d r e s s S R W A C K
S C L
1 0 1 1 0 1 0 1 0
S D A
D a ta A C K S to p
S C L
1 0 0 1 0 1 0 0
S D A
S = S ta rt (1 b it)
S A = S la v e A d d r e s s ( 7 b its )
S R = S R W b it ( 1 b it)
M = S la v e d e v ic e s e n d a c k n o w le d g e b it ( 1 b it)
D = D a ta (8 b its )
A = A C K (R X A K b it fo r tr a n s m itte r , T X A K b it fo r r e c e iv e r 1 b it)
P = S to p (1 b it)
S S A S R M D A D A S S A S R M D A D A P
Note: * When a slave address is matched, the device must be placed in either the transmit mode and then write data
to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to
release the SCL line.
I2C Communication Timing Diagram
S ta rt
N o H A A S = 1 Y e s
?
N o H T X = 1 Y e s Y e s S R W = 1 N o
? ?
R e a d fro m
S IM D to r e le a s e C L R H T X
S E T H T X
S C L lin e C L R T X A K
D u m m y re a d fro m
R E T I W r ite d a ta to S IM D
S IM D to r e le a s e
to r e le a s e S C L L in e
S C L L in e
Y e s R X A K = 1
?
N o R E T I R E T I
C L R H T X W r ite d a ta to S IM D
C L R T X A K r e le a s e S C L L in e
D u m m y re a d fro m
S IM D to r e le a s e R E T I
S C L L in e
R E T I
SIMC0 Register
Bit 7 6 5 4 3 2 1 0
Name SIM2 SIM1 SIM0 PCKEN PCKP1 PCKP0 SIMEN
R/W R/W R/W R/W R/W R/W R/W R/W
POR 1 1 1 0 0 0 0
Interrupts
Interrupts are an important part of any microcontroller ing convention of these follows a specific pattern. First is
system. When an external event or an internal function listed an abbreviated interrupt type, then the (optional)
such as a Timer Module requires microcontroller atten- number of that interrupt followed by either an E for en-
tion, their corresponding interrupt will enforce a tempo- able/disable bit or F for request flag.
rary suspension of the main program allowing the
microcontroller to direct attention to their respective Enable Request
Function Notes
Bit Flag
needs. The device contains several external interrupt
and internal interrupts functions. The external interrupts Global EMI
are generated by the action of the external INT0~INT3
Comparator CPnE CPnF n = 0 or 1
and PINT pins, while the internal interrupts are gener-
ated by various internal functions such as the TMs, INTn Pin INTnE INTnF n = 0~3
Comparators, Time Base, LVD, EEPROM and SIM. Multi-function MFnE MFnF n = 0~5
Overall interrupt control, which basically means the set- SIM SIME SIMF
ting of request flags when certain microcontroller condi- LVD LVE LVF
tions occur and the setting of interrupt enable bits by the
application program, is controlled by a series of regis- EEPROM DEE DEF
ters, located in the Special Purpose Data Memory, as PINT Pin XPE XPF
shown in the accompanying table. The number of regis-
ters depends upon the device chosen but fall into three TnPE TnPF
categories. The first is the INTC0~INTC3 registers TM TnAE TnAF n = 0~3
which setup the primary interrupts, the second is the
TnBE TnBF
MFI0~MFI3 registers which setup the Multi-function in-
terrupts. Finally there is an INTEG register to setup the Interrupt Register Bit Naming Conventions
external interrupt trigger edge type.
Each register contains a number of enable bits to enable
or disable individual registers as well as interrupt flags to
indicate the presence of an interrupt request. The nam-
HT68F20
Bit
Name
7 6 5 4 3 2 1 0
INTEG INT1S1 INT1S0 INT0S1 INT0S0
HT68F30
Bit
Name
7 6 5 4 3 2 1 0
INTEG INT1S1 INT1S0 INT0S1 INT0S0
HT68F40
Bit
Name
7 6 5 4 3 2 1 0
INTEG INT1S1 INT1S0 INT0S1 INT0S0
HT68F50
Bit
Name
7 6 5 4 3 2 1 0
INTEG INT1S1 INT1S0 INT0S1 INT0S0
HT68F60
Bit
Name
7 6 5 4 3 2 1 0
INTEG INT3S1 INT3S0 INT2S1 INT2S0 INT1S1 INT1S0 INT0S1 INT0S0
INTC0 INT2F INT1F INT0F INT2E INT1E INT0E EMI
INTC1 MF0F CP1F CP0F INT3F MF0E CP1E CP0E INT3E
INTC2 MF3F MF2F MF1F MF3E MF2E MF1E
INTC3 MF5F TB1F TB0F MF4F MF5E TB1E TB0E MF4E
MFI0 T2AF T2PF T0AF T0PF T2AE T2PE T0AE T0PE
MFI1 T1BF T1AF T1PF T1BE T1AE T1PE
MFI2 DEF LVF XPF SIMF DEE LVE XPE SIME
MFI3 T3AF T3PF T3AE T3PE
INTEG Register
HT68F20/HT68F30/HT68F40/HT68F50
Bit 7 6 5 4 3 2 1 0
Name INT1S1 INT1S0 INT0S1 INT0S0
R/W R/W R/W R/W R/W
POR 0 0 0 0
HT68F60
Bit 7 6 5 4 3 2 1 0
Name INT3S1 INT3S0 INT2S1 INT2S0 INT1S1 INT1S0 INT0S1 INT0S0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Bit 7~6 INT3S1, INT3S0: Interrupt edge control for INT3 pin
00: disable
01: rising edge
10: falling edge
Bit 5~4 INT2S1, INT2S0: interrupt edge control for INT2 pin
00: disable
01: rising edge
10: falling edge
11: rising and falling edges
Bit 3~2 INT1S1, INT1S0: interrupt edge control for INT1 pin
00: disable
01: rising edge
10: falling edge
11: rising and falling edges
Bit 1~0 INT0S1, INT0S0: interrupt edge control for INT0 pin
00: disable
01: rising edge
10: falling edge
11: rising and falling edges
INTC0 Register
HT68F20/HT68F30/HT68F40/HT68F50
Bit 7 6 5 4 3 2 1 0
Name CP0F INT1F INT0F CP0E INT1E INT0E EMI
R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0
HT68F60
Bit 7 6 5 4 3 2 1 0
Name INT2F INT1F INT0F INT2E INT1E INT0E EMI
R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0
INTC1 Register
HT68F20/HT68F30/HT68F40/HT68F50
Bit 7 6 5 4 3 2 1 0
Name MF1F MF0F CP1F MF1E MF0E CP1E
R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0
HT68F60
Bit 7 6 5 4 3 2 1 0
Name MF0F CP1F CP0F INT3F MF0E CP1E CP0E INT3E
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
INTC2 Register
HT68F20/HT68F30/HT68F40/HT68F50
Bit 7 6 5 4 3 2 1 0
Name MF3F TB1F TB0F MF2F MF3E TB1E TB0E MF2E
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
HT68F60
Bit 7 6 5 4 3 2 1 0
Name MF3F MF2F MF1F MF3E MF2E MF1E
R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0
INTC3 Register
HT68F60
Bit 7 6 5 4 3 2 1 0
Name MF5F TB1F TB0F MF4F MF5E TB1E TB0E MF4E
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
MFI0 Register
HT68F20/HT68F30
Bit 7 6 5 4 3 2 1 0
Name T0AF T0PF T0AE T0PE
R/W R/W R/W R/W R/W
POR 0 0 0 0
HT68F40/HT68F50/HT68F60
Bit 7 6 5 4 3 2 1 0
Name T2AF T2PF T0AF T0PF T2AE T2PE T0AE T0PE
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
MFI1 Register
HT68F20
Bit 7 6 5 4 3 2 1 0
Name T1AF T1PF T1AE T1PE
R/W R/W R/W R/W R/W
POR 0 0 0 0
HT68F30/HT68F40/HT68F50/HT68F60
Bit 7 6 5 4 3 2 1 0
Name T1BF T1AF T1PF T1BE T1AE T1PE
R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0
MFI2 Register
Bit 7 6 5 4 3 2 1 0
Name DEF LVF XPF SIMF DEE LVE XPE SIME
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
MFI3 Register
HT68F50/HT68F60
Bit 7 6 5 4 3 2 1 0
Name T3AF T3PF T3AE T3PE
R/W R/W R/W R/W R/W
POR 0 0 0 0
Interrupt Operation The various interrupt enable bits, together with their as-
When the conditions for an interrupt event occur, such sociated request flags, are shown in the accompanying
as a TM Comparator P, Comparator A or Comparator B diagrams with their order of priority. Some interrupt
match etc, the relevant interrupt request flag will be set. sources have their own individual vector while others
Whether the request flag actually generates a program share the same multi-function interrupt vector. Once an
jump to the relevant interrupt vector is determined by the interrupt subroutine is serviced, all the other interrupts
condition of the interrupt enable bit. If the enable bit is will be blocked, as the global interrupt enable bit, EMI bit
set high then the program will jump to its relevant vector; will be cleared automatically. This will prevent any fur-
if the enable bit is zero then although the interrupt re- ther interrupt nesting from occurring. However, if other
quest flag is set an actual interrupt will not be generated interrupt requests occur during this interval, although
and the program will not jump to the relevant interrupt the interrupt will not be immediately serviced, the re-
vector. The global interrupt enable bit, if cleared to zero, quest flag will still be recorded.
will disable all interrupts. If an interrupt requires immediate servicing while the
When an interrupt is generated, the Program Counter, program is already in another interrupt service routine,
which stores the address of the next instruction to be ex- the EMI bit should be set after entering the routine, to al-
ecuted, will be transferred onto the stack. The Program low interrupt nesting. If the stack is full, the interrupt re-
Counter will then be loaded with a new address which quest will not be acknowledged, even if the related
will be the value of the corresponding interrupt vector. interrupt is enabled, until the Stack Pointer is decre-
The microcontroller will then fetch its next instruction mented. If immediate service is desired, the stack must
from this interrupt vector. The instruction at this vector be prevented from becoming full. In case of simulta-
will usually be a JMP which will jump to another sec- neous requests, the accompanying diagram shows the
tion of program which is known as the interrupt service priority that is applied. All of the interrupt request flags
routine. Here is located the code to control the appropri- when set will wake-up the device if it is in SLEEP or
ate interrupt. The interrupt service routine must be ter- IDLE Mode, however to prevent a wake-up from occur-
ring the corresponding flag should be set before the de-
minated with a RETI, which retrieves the original
vice is in SLEEP or IDLE Mode.
Program Counter address from the stack and allows the
microcontroller to continue with normal execution at the
point where the interrupt occurred.
Legend
Interrupt Request Enable Master Vector
xxF Request Flag no auto reset in ISR Priority
Name Flags Bits Enable
High
xxF Request Flag auto reset in ISR INT0 Pin INT0F INT0E EMI 04H
HT68F30 only
Legend
Interrupt Request Enable Master Vector
xxF Request Flag no auto reset in ISR Priority
Name Flags Bits Enable
High
xxF Request Flag auto reset in ISR INT0 Pin INT0F INT0E EMI 04H
HT68F50 only
The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their clock sources origi-
nate from the internal clock source fTB. This fTB input clock passes through a divider, the division ratio of which is se-
lected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges.
The clock source that generates fTB, which in turn controls the Time Base interrupt period, can originate from several
different sources, as shown in the System Operating Mode section.
TBC Register
Bit 7 6 5 4 3 2 1 0
Name TBON TBCK TB11 TB10 LXTLP TB02 TB01 TB00
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 1 1 0 1 1 1
T B 0 2 ~ T B 0 0
fS Y S /4
L X T
M
M
2
8
~ 2
1 5 T im e B a s e 0 In te r r u p t
U fT B
fT B C U
X
L IR C X
2
1 2
~ 2
1 5 T im e B a s e 1 In te r r u p t
C o n fig u r a tio n T B C K B it
O p tio n T B 1 1 ~ T B 1 0
Serial Interface Module Interrupt must first be set. When the interrupt is enabled, the
The Serial Interface Module Interrupt, also known as the stack is not full and an EEPROM Write or Read cycle
SIM interrupt, is contained within the Multi-function In- ends, a subroutine call to the respective Multi-function
terrupt. A SIM Interrupt request will take place when the Interrupt vector, will take place. When the EEPROM In-
SIM Interrupt request flag, SIMF, is set, which occurs terrupt is serviced, the EMI bit will be automatically
when a byte of data has been received or transmitted by cleared to disable other interrupts, however only the
the SIM interface. To allow the program to branch to its Multi-function interrupt request flag will be also automat-
respective interrupt vector address, the global interrupt ically cleared. As the DEF flag will not be automatically
enable bit, EMI, and the Serial Interface Interrupt enable cleared, it has to be cleared by the application program.
bit, SIME, and Muti-function interrupt enable bits, must
LVD Interrupt
first be set. When the interrupt is enabled, the stack is
not full and a byte of data has been transmitted or re- The Low Voltage Detector Interrupt is contained within
ceived by the SIM interface, a subroutine call to the re- the Multi-function Interrupt. An LVD Interrupt request will
spective Multi-function Interrupt vector, will take place. take place when the LVD Interrupt request flag, LVF, is
When the Serial Interface Interrupt is serviced, the EMI set, which occurs when the Low Voltage Detector func-
bit will be automatically cleared to disable other inter- tion detects a low power supply voltage. To allow the
rupts, however only the Multi-function interrupt request program to branch to its respective interrupt vector ad-
flag will be also automatically cleared. As the SIMF flag dress, the global interrupt enable bit, EMI, Low Voltage
will not be automatically cleared, it has to be cleared by Interrupt enable bit, LVE, and associated Multi-function
the application program. interrupt enable bit, must first be set. When the interrupt
is enabled, the stack is not full and a low voltage condi-
External Peripheral Interrupt tion occurs, a subroutine call to the Multi-function Inter-
The External Peripheral Interrupt operates in a similar rupt vector, will take place. When the Low Voltage
way to the external interrupt and is contained within the Interrupt is serviced, the EMI bit will be automatically
Multi-function Interrupt. A Peripheral Interrupt request cleared to disable other interrupts, however only the
will take place when the External Peripheral Interrupt re- Multi-function interrupt request flag will be also automat-
quest flag, XPF, is set, which occurs when a negative ically cleared. As the LVF flag will not be automatically
edge transition appears on the PINT pin. To allow the cleared, it has to be cleared by the application program.
program to branch to its respective interrupt vector ad-
TM Interrupts
dress, the global interrupt enable bit, EMI, external pe-
ripheral interrupt enable bit, XPE, and associated The Compact and Standard Type TMs have two inter-
Multi-function interrupt enable bit, must first be set. rupts each, while the Enhanced Type TM has three in-
When the interrupt is enabled, the stack is not full and a terrupts. All of the TM interrupts are contained within the
negative transition appears on the External Peripheral Multi-function Interrupts. For each of the Compact and
Interrupt pin, a subroutine call to the respective Standard Type TMs there are two interrupt request flags
Multi-function Interrupt, will take place. When the Exter- TnPF and TnAF and two enable bits TnPE and TnAE.
nal Peripheral Interrupt is serviced, the EMI bit will be For the Enhanced Type TM there are three interrupt re-
automatically cleared to disable other interrupts, how- quest flags TnPF, TnAF and TnBF and three enable bits
ever only the Multi-function interrupt request flag will be TnPE, TnAE and TnBE. A TM interrupt request will take
also automatically cleared. place when any of the TM request flags are set, a situa-
tion which occurs when a TM comparator P, A or B
As the XPF flag will not be automatically cleared, it has
match situation happens.
to be cleared by the application program. The external
peripheral interrupt pin is pin-shared with several other To allow the program to branch to its respective interrupt
pins with different functions. It must therefore be prop- vector address, the global interrupt enable bit, EMI, re-
erly configured to enable it to operate as an External Pe- spective TM Interrupt enable bit, and relevant
ripheral Interrupt pin. Multi-function Interrupt enable bit, MFnE, must first be
set. When the interrupt is enabled, the stack is not full
EEPROM Interrupt and a TM comparator match situation occurs, a subrou-
The EEPROM Interrupt, is contained within the tine call to the relevant Multi-function Interrupt vector lo-
Multi-function Interrupt. An EEPROM Interrupt request cations, will take place. When the TM interrupt is
will take place when the EEPROM Interrupt request serviced, the EMI bit will be automatically cleared to dis-
flag, DEF, is set, which occurs when an EEPROM Write able other interrupts, however only the related MFnF
or Read cycle ends. To allow the program to branch to flag will be automatically cleared. As the TM interrupt re-
its respective interrupt vector address, the global inter- quest flags will not be automatically cleared, they have
rupt enable bit, EMI, EEPROM Interrupt enable bit, to be cleared by the application program.
DEE, and associated Multi-function interrupt enable bit,
Interrupt Wake-up Function It is recommended that programs do not use the CALL
Each of the interrupt functions has the capability of wak- instruction within the interrupt service subroutine. Inter-
ing up the microcontroller when in the SLEEP or IDLE rupts often occur in an unpredictable manner or need to
Mode. A wake-up is generated when an interrupt re- be serviced immediately. If only one stack is left and the
quest flag changes from low to high and is independent interrupt is not well controlled, the original control se-
of whether the interrupt is enabled or not. Therefore, quence will be damaged once a CALL subroutine is exe-
even though the device is in the SLEEP or IDLE Mode cuted in the interrupt subroutine.
and its system oscillator stopped, situations such as ex- Every interrupt has the capability of waking up the
ternal edge transitions on the external interrupt pins, a microcontroller when it is in SLEEP or IDLE Mode, the
low power supply voltage or comparator input change wake up being generated when the interrupt request
may cause their respective interrupt flag to be set high flag changes from low to high. If it is required to prevent
and consequently generate an interrupt. Care must a certain interrupt from waking up the microcontroller
therefore be taken if spurious wake-up situations are to then its respective request flag should be first set high
be avoided. If an interrupt wake-up function is to be dis- before enter SLEEP or IDLE Mode.
abled then the corresponding interrupt request flag
As only the Program Counter is pushed onto the stack,
should be set high before the device enters the SLEEP
then when the interrupt is serviced, if the contents of the
or IDLE Mode. The interrupt enable bits have no effect
accumulator, status register or other registers are al-
on the interrupt wake-up function.
tered by the interrupt service program, their contents
Programming Considerations should be saved to the memory at the beginning of the
interrupt service routine.
By disabling the relevant interrupt enable bits, a re-
quested interrupt can be prevented from being serviced, To return from an interrupt subroutine, either a RET or
however, once an interrupt request flag is set, it will re- RETI instruction may be executed. The RETI instruction
main in this condition in the interrupt register until the in addition to executing a return to the main program
corresponding interrupt is serviced or until the request also automatically sets the EMI bit high to allow further
flag is cleared by the application program. interrupts. The RET instruction however only executes a
return to the main program leaving the EMI bit in its
Where a certain interrupt is contained within a present zero state and therefore disabling the execution
Multi-function interrupt, then when the interrupt service of further interrupts.
routine is executed, as only the Multi-function interrupt
request flags, MF0F~MF5F, will be automatically
cleared, the individual request flag for the function
needs to be cleared by the application program.
LVDC Register
Bit 7 6 5 4 3 2 1 0
Name LVDO LVDEN VLVD2 VLVD1 VLVD0
POR 0 0 0 0 0
V D D /2 S C O M 0 ~
L V D E N S C O M 3
L V D O C O M n E N
S C O M E N
tL V D S
LVD Operation
HT68F20
Bit 7 6 5 4 3 2 1 0
Name D7 ISEL1 ISEL0 SCOMEN COM3EN COM2EN COM1EN COM0EN
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
HT68F30/HT68F40/HT68F50/HT68F60
Bit 7 6 5 4 3 2 1 0
Name D7 ISEL1 ISEL0 SCOMEN COM3EN COM2EN COM1EN COM0EN
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device during the program-
ming process. During the development process, these options are selected using the HT-IDE software development
tools. As these options are programmed into the device using the hardware programming tools, once they are selected
they cannot be changed later using the application program. All options must be defined for proper system function, the
details of which are shown in the table.
No. Options
Oscillator Options
High Speed System Oscillator Selection - fH:
1. HXT
1
2. ERC
3. HIRC
Low Speed System Oscillator Selection - fL:
2 1. LXT
2. LIRC
WDT Clock Selection - fS:
3 1. fSUB
2. fSYS/4
HIRC Frequency Selection:
1. 4MHz
4
2. 8MHz
3. 12MHz
Note: The fSUB and the fTBC clock source are LXT or LIRC selection by the fL configuration option.
Reset Pin Options
PB0/RES Pin Options:
5 1. RES pin
2. I/O pin
Watchdog Options
Watchdog Timer Function:
6 1. Enable
2. Disable
CLRWDT Instructions Selection:
7 1. 1 instructions
2. 2 instructions
LVR Options
LVR Function:
8 1. Enable
2. Disable
LVR Voltage Selection:
1. 2.10V
9 2. 2.55V
3. 3.15V
4. 4.20V
No. Options
SIM Options
SIM Function:
10 1. Enable
2. Disable
SPI - WCOL bit:
11 1. Enable
2. Disable
SPI - CSEN bit:
12 1. Enable
2. Disable
I2C Debounce Time Selection:
1. No debounce
13
2. 1 system clock debounce
3. 2 system clock debounce
Application Circuits
V D D
0 .0 1 m F * *
V D D
1 0 k W ~ R e s e t
1 0 0 k W C ir c u it
1 N 4 1 4 8 *
0 .1 m F
R E S
P A 0 ~ P A 7
3 0 0 W *
0 .1 ~ 1 m F
P B 5 ~ P B 7
V S S
P C 0 ~ P C 7
P D 0 ~ P D 7
O S C O S C 1
C ir c u it P E 0 ~ P E 5
O S C 2
S e e O s c illa to r P F 0 ~ P F 7
S e c tio n
P G 0 ~ P G 1
O S C X T 1
C ir c u it X T 2
S e e O s c illa to r
S e c tio n
Note: * It is recommended that this component is added for added ESD protection.
** It is recommended that this component is added in environments where power line noise is significant.
Instruction Set
Introduction sure correct handling of carry and borrow data when re-
C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y sults exceed 255 for addition and less than 0 for sub-
traction. The increment and decrement instructions
microcontroller is its instruction set, which is a set of pro-
INC, INCA, DEC and DECA provide a simple means of
gram instruction codes that directs the microcontroller to
increasing or decreasing by a value of one of the values
perform certain operations. In the case of Holtek
in the destination specified.
microcontroller, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
Logical and Rotate Operations
to implement their application with the minimum of pro-
gramming overheads. The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
For easier understanding of the various instruction
microcontroller instruction set. As with the case of most
codes, they have been subdivided into several func-
instructions involving data manipulation, data must pass
tional groupings.
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
Instruction Timing
zero flag may be set if the result of the operation is zero.
Most instructions are implemented within one instruc- Another form of logical data manipulation comes from
tion cycle. The exceptions to this are branch, call, or ta- the rotate instructions such as RR, RL, RRC and RLC
ble read instructions where two instruction cycles are which provide a simple means of rotating one bit right or
required. One instruction cycle is equal to 4 system left. Different rotate instructions exist depending on pro-
clock cycles, therefore in the case of an 8MHz system gram requirements. Rotate instructions are useful for
oscillator, most instructions would be implemented serial port programming applications where data can be
within 0.5ms and branch or call instructions would be im- rotated from an internal register into the Carry bit from
plemented within 1ms. Although instructions which re- where it can be examined and the necessary serial bit
quire one more cycle to implement are generally limited set high or low. Another application where rotate data
to the JMP, CALL, RET, RETI and table read instruc- operations are used is to implement multiplication and
tions, it is important to realize that any other instructions division calculations.
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to imple- Branches and Control Transfer
ment. As instructions which change the contents of the Program branching takes the form of either jumps to
PCL will imply a direct jump to that new address, one specified locations using the JMP instruction or to a sub-
more cycle will be required. Examples of such instruc- routine using the CALL instruction. They differ in the
tions would be CLR PCL or MOV PCL, A. For the sense that in the case of a subroutine call, the program
case of skip instructions, it must be noted that if the re- must return to the instruction immediately when the sub-
sult of the comparison involves a skip operation then routine has been carried out. This is done by placing a
this will also take one more cycle, if no skip is involved return instruction RET in the subroutine which will cause
then only one cycle is required. the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
Moving and Transferring Data
program simply jumps to the desired location. There is
The transfer of data within the microcontroller program no requirement to jump back to the original jumping off
is one of the most frequently used operations. Making point as in the case of the CALL instruction. One special
use of three kinds of MOV instructions, data can be and extremely useful set of branch instructions are the
transferred from registers to the Accumulator and conditional branches. Here a decision is first made re-
vice-versa as well as being able to move specific imme- garding the condition of a certain data memory or indi-
diate data directly into the Accumulator. One of the most vidual bits. Depending upon the conditions, the program
important data transfer applications is to receive data will continue with the next instruction or skip over it and
from the input ports and transfer data to the output ports. jump to the following instruction. These instructions are
the key to decision making and branching within the pro-
Arithmetic Operations gram perhaps determined by the condition of certain in-
The ability to perform certain arithmetic operations and put switches or by the condition of internal data bits.
data manipulation is a necessary feature of most
microcontroller appl i c a t i ons . W i t hi n t he H o l t e k
microcontroller instruction set are a range of add and
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to en-
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both CLR WDT1 and
CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
Instruction Definition
DAA [m] Decimal-Adjust ACC for addition with result in Data Memory
Description Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re-
sulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by add-
ing 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation [m] ACC + 00H or
[m] ACC + 06H or
[m] ACC + 60H or
[m] ACC + 66H
Affected flag(s) C
NOP No operation
Description No operation is performed. Execution continues with the next instruction.
Operation No operation
Affected flag(s) None
RET A,x Return from subroutine and load immediate data to ACC
Description The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation Program Counter Stack
ACC x
Affected flag(s) None
RLCA [m] Rotate Data Memory left through Carry with result in ACC
Description Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation ACC.(i+1) [m].i; (i = 0~6)
ACC.0 C
C [m].7
Affected flag(s) C
RRCA [m] Rotate Data Memory right through Carry with result in ACC
Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re-
places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation ACC.i [m].(i+1); (i = 0~6)
ACC.7 C
C [m].0
Affected flag(s) C
SBCM A,[m] Subtract Data Memory from ACC with Carry and result in Data Memory
Description The contents of the specified Data Memory and the complement of the carry flag are sub-
tracted from the Accumulator. The result is stored in the Data Memory. Note that if the re-
sult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation [m] ACC - [m] - C
Affected flag(s) OV, Z, AC, C
SDZA [m] Skip if decrement Data Memory is zero with result in ACC
Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy in-
struction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation ACC [m] - 1
Skip if ACC = 0
Affected flag(s) None
SIZA [m] Skip if increment Data Memory is zero with result in ACC
Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy in-
struction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation ACC [m] + 1
Skip if ACC = 0
Affected flag(s) None
SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory
Description The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation [m] ACC - [m]
Affected flag(s) OV, Z, AC, C
TABRDL [m] Read table (last page) to TBLH and Data Memory
Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation [m] program code (low byte)
TBLH program code (high byte)
Affected flag(s) None
Package Information
16-pin DIP (300mil) Outline Dimensions
A A
1 6 9 1 6 9
B B
1 8 1 8
H H
C C
D D
E G I E G I
F F
Dimensions in mil
Symbol
Min. Nom. Max.
A 780 880
B 240 280
C 115 195
D 115 150
E 14 22
F 45 70
G 100
H 300 325
I 430
Dimensions in mil
Symbol
Min. Nom. Max.
A 735 775
B 240 280
C 115 195
D 115 150
E 14 22
F 45 70
G 100
H 300 325
I 430
Dimensions in mil
Symbol
Min. Nom. Max.
A 745 785
B 275 295
C 120 150
D 110 150
E 14 22
F 45 60
G 100
H 300 325
I 430
1 6 9
A B
1 8
C '
G
D H
E F a
Dimensions in mil
Symbol
Min. Nom. Max.
A 228 244
B 149 157
C 14 20
C 386 394
D 53 69
E 50
F 4 10
G 22 28
H 4 12
a 0 10
1 6 9
A B
1 8
C '
G
D H
E F a
Dimensions in mil
Symbol
Min. Nom. Max.
A 228 244
B 150 157
C 8 12
C 189 197
D 54 60
E 25
F 4 10
G 22 28
H 7 10
a 0 8
A A
2 0 1 1 2 0 1 1
B B
1 1 0 1 1 0
H H
C C
D D
E F G I E F G I
Dimensions in mil
Symbol
Min. Nom. Max.
A 980 1060
B 240 280
C 115 195
D 115 150
E 14 22
F 45 70
G 100
H 300 325
I 430
Dimensions in mil
Symbol
Min. Nom. Max.
A 945 985
B 275 295
C 120 150
D 110 150
E 14 22
F 45 60
G 100
H 300 325
I 430
2 0 1 1
A B
1 1 0
C '
G
D H
E F a
MS-013
Dimensions in mil
Symbol
Min. Nom. Max.
A 393 419
B 256 300
C 12 20
C 496 512
D 104
E 50
F 4 12
G 16 50
H 8 13
a 0 8
2 0 1 1
A B
1 1 0
C '
G
D H
E F a
Dimensions in mil
Symbol
Min. Nom. Max.
A 228 244
B 150 158
C 8 12
C 335 347
D 49 65
E 25
F 4 10
G 15 50
H 7 10
a 0 8
A A
2 4 1 3 2 4 1 3
B B
1 1 2 1 1 2
H H
C C
D D
E F G I E F G I
Dimensions in mil
Symbol
Min. Nom. Max.
A 1230 1280
B 240 280
C 115 195
D 115 150
E 14 22
F 45 70
G 100
H 300 325
I 430
Dimensions in mil
Symbol
Min. Nom. Max.
A 1160 1195
B 240 280
C 115 195
D 115 150
E 14 22
F 45 70
G 100
H 300 325
I 430
Dimensions in mil
Symbol
Min. Nom. Max.
A 1145 1185
B 275 295
C 120 150
D 110 150
E 14 22
F 45 60
G 100
H 300 325
I 430
2 4 1 3
A B
1 1 2
C '
G
D H
E F a
MS-013
Dimensions in mil
Symbol
Min. Nom. Max.
A 393 419
B 256 300
C 12 20
C 598 613
D 104
E 50
F 4 12
G 16 50
H 8 13
a 0 8
2 4 1 3
A B
1 1 2
C '
G
D H
E F a
Dimensions in mil
Symbol
Min. Nom. Max.
A 228 244
B 150 157
C 8 12
C 335 346
D 54 60
E 25
F 4 10
G 22 28
H 7 10
a 0 8
2 8 1 5
B
1 1 4
D
I
E F G
Dimensions in mil
Symbol
Min. Nom. Max.
A 1375 1395
B 278 298
C 125 135
D 125 145
E 16 20
F 50 70
G 100
H 295 315
I 375
2 8 1 5
A B
1 1 4
C '
G
D H
E F a
MS-013
Dimensions in mil
Symbol
Min. Nom. Max.
A 393 419
B 256 300
C 12 20
C 697 713
D 104
E 50
F 4 12
G 16 50
H 8 13
a 0 8
2 8 1 5
A B
1 1 4
C '
G
D H
a
E F
Dimensions in mil
Symbol
Min. Nom. Max.
A 228 244
B 150 157
C 8 12
C 386 394
D 54 60
E 25
F 4 10
G 22 28
H 7 10
a 0 8
D D 2
2 5 3 2
b 2 4 1
E E 2
e
1 7 8
A 1 1 6 9
A 3
L K
Dimensions in mm.
Symbol
Min. Nom. Max.
A 0.70 0.80
A1 0.00 0.05
A3 0.20
b 0.18 0.30
D 5.00
E 5.00
e 0.50
D2 1.25 3.25
E2 1.25 3.25
L 0.30 0.50
K
D D 2
3 1 4 0
b 3 0 1
E E 2
e
2 1 1 0
2 0 1 1
A 1
A 3 L K
Dimensions in mm.
Symbol
Min. Nom. Max.
A 0.70 0.80
A1 0.00 0.05
A3 0.203
b 0.15 0.25
D 5.00
E 5.00
e 0.40
D2 3.20 3.40
E2 3.20 3.40
L 0.35 0.45
K
C H
D G
3 3 2 3
3 4 2 2
L
F
A B
4 4 1 2
K a
J
1 1 1
Dimensions in mm
Symbol
Min. Nom. Max.
A 13.00 13.40
B 9.90 10.10
C 13.00 13.40
D 9.90 10.10
E 0.80
F 0.30
G 1.90 2.20
H 2.70
I 0.25 0.50
J 0.73 0.93
K 0.10 0.20
L 0.10
a 0 7
4 8 2 5
A B
1 2 4
C '
G
D H
a
E F
Dimensions in inch
Symbol
Min. Nom. Max.
A 0.395 0.420
B 0.291 0.299
C 0.008 0.012
C 0.613 0.637
D 0.085 0.099
E 0.025
F 0.004 0.010
G 0.025 0.035
H 0.004 0.012
a 0 8
Dimensions in mm
Symbol
Min. Nom. Max.
A 10.03 10.67
B 7.39 7.59
C 0.20 0.30
C 15.57 16.18
D 2.16 2.51
E 0.64
F 0.10 0.25
G 0.64 0.89
H 0.10 0.30
a 0 8
D D 2
3 7 4 8
b 3 6 1
E E 2
2 5 1 2
2 4 1 3
A 1
A 3 L K
Dimensions in mm.
Symbol
Min. Nom. Max.
A 0.70 0.80
A1 0.00 0.05
A3 0.203
b 0.18 0.30
D 7.0
E 7.0
e 0.50
D2 4.50 5.75
E2 4.50 5.75
L 0.30 0.50
K 0.20
C
H
D
G
3 9 2 7
4 0 2 6
A B
E
5 2 1 4
K
J
1 1 3
Dimensions in mm
Symbol
Min. Nom. Max.
A 17.30 17.50
B 13.90 14.10
C 17.30 17.50
D 13.90 14.10
E 1.00
F 0.40
G 2.50 3.10
H 3.40
I 0.10
J 0.73 1.03
K 0.10 0.20
a 0 7
D
T 2
A B C
T 1
SSOP 16S
Symbol Description Dimensions in mm
A Reel Outer Diameter 330.01.0
B Reel Inner Diameter 100.01.5
+0.5/-0.2
C Spindle Hole Diameter 13.0
SSOP 48W
F
W
B 0
C
D 1 P
K 0
A 0
R e e l H o le
IC p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
SOP 20W
SOP 24W
SSOP 16S
Symbol Description Dimensions in mm
+0.3/-0.1
W Carrier Tape Width 12.0
P 0 P 1 t
D
F
W C B 0
K 1
D 1 P
K 2
A 0
R e e l H o le ( C ir c le )
IC p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
R e e l H o le ( E llip s e )
SSOP 48W
Symbol Description Dimensions in mm
W Carrier Tape Width 32.00.3
P Cavity Pitch 16.00.1
E Perforation Position 1.750.10
F Cavity to Perforation (Width Direction) 14.20.1
D Perforation Diameter 2 Min.
+0.25/-0.00
D1 Cavity Hole Diameter 1.50
P0 Perforation Pitch 4.00.1
P1 Cavity to Perforation (Length Direction) 2.00.1
A0 Cavity Length 12.00.1
B0 Cavity Width 16.20.1
K1 Cavity Depth 2.40.1
K2 Cavity Depth 3.20.1
t Carrier Tape Thickness 0.350.05
C Cover Tape Width 25.50.1