LOS & LOC

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 1

 LOC & LOS

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 2

 Combinational ATPG
Algorithms and representations
Structural vs. functional test
Definitions
ATPG problem
Algorithms
Multi-valued algebra
D-algorithm
Podem
ATPG system
Summary
Exercise

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 3

 Origins of Stuck-Faults
Eldred (1959) First use of structural
testing for the Honeywell Datamatic 1000
computer
Galey, Norby, Roth (1961) First
publication of stuck-at-0 and stuck-at-1
faults
Seshu & Freeman (1962) Use of stuck-
faults for parallel fault simulation
Poage (1963) Theoretical analysis of
stuck-at faults

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9 4

 Functional vs. Structural
ATPG

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9 5

 Carry Circuit

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9 6

Functional vs. Structural
(Continued)
Functional ATPG generate complete set of tests for
circuit input-output combinations
129 inputs, 65 outputs:
2129 = 680,564,733,841,876,926,926,749,
214,863,536,422,912 patterns
Using 1 GHz ATE, would take 2.15 x 1022 years
Structural test:
No redundant adder hardware, 64 bit slices
Each with 27 faults (using fault equivalence)
At most 64 x 27 = 1728 faults (tests)
Takes 0.000001728 s on 1 GHz ATE
Designer gives small set of functional tests augment
with structural tests to boost coverage to 98+ %

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9 7

 Definition of Automatic
Test-Pattern Generator
Operations on digital hardware:
Inject fault into circuit modeled in computer
Use various ways to activate and propagate fault effect
through hardware to circuit output
Output flips from expected to faulty signal
Electron-beam (E-beam) test observes internal signals
picture of nodes charged to 0 and 1 in different colors
Too expensive
Scan design add test hardware to all flip-flops to make
them a giant shift register in test mode
Can shift state in, scan state out
Widely used makes sequential test combinational
Costs: 5 to 20% chip area, circuit delay, extra pin,
longer test sequence
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9 8
 Circuit and Binary
Decision Tree

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9 9

 Binary Decision Diagram
BDD Follow path from source to sink node
product of literals along path gives Boolean
value at sink
Rightmost path: A B C = 1
Problem: Size varies greatly
with variable order

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9 10

 Algorithm Completeness
Definition: Algorithm is complete if it
ultimately can search entire binary
decision tree, as needed, to generate a
test
Untestable fault no test for it even after
entire tree searched
Combinational circuits only untestable
faults are redundant, showing the
presence of unnecessary hardware

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9 11

 Algebras: Roths 5-Valued
and Muths 9-Valued
Good Failing
Symbol Meaning Machine Machine
D 1/0 1 0
D 0/1 0 1 Roths
0 0/0 0 0 Algebra
1 1/1 1 1
X X/X X X
G0 0/X 0 X
G1 1/X 1 X Muths
F0 X/0 X 0 Additions
F1 X/1 X 1

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9 12

 Roths and Muths
Higher-Order Algebras
Represent two machines, which are simulated
simultaneously by a computer program:
Good circuit machine (1st value)
Bad circuit machine (2nd value)
Better to represent both in the algebra:
Need only 1 pass of ATPG to solve both
Good machine values that preclude bad machine
values become obvious sooner & vice versa
Needed for complete ATPG:
Combinational: Multi-path sensitization, Roth Algebra
Sequential: Muth Algebra -- good and bad machines
may have different initial values due to fault

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9 13

 Exhaustive Algorithm

For n-input circuit, generate all 2n input

patterns
Infeasible, unless circuit is partitioned into
cones of logic, with 15 inputs
Perform exhaustive ATPG for each cone
Misses faults that require specific
activation patterns for multiple cones to
be tested

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9 14

Random-Pattern Generation

Flow chart for

method
Use to get
tests for 60-
80% of faults,
then switch to
D-algorithm or
other ATPG
for rest

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9 15

Path Sensitization Method
Circuit Example
1 Fault Sensitization
2 Fault Propagation
3 Line Justification

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9 16

Path Sensitization Method
Circuit Example
Try path f h k L blocked at j, since
there is no way to justify the 1 on i

1 D

D D
1 D
D 0
1

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9 17

Path Sensitization Method
Circuit Example
Try simultaneous paths f h k L and
g i j k L blocked at k because
D-frontier (chain of D or D) disappears
1 D
D 1
1
D D
D
1

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9 18

Path Sensitization Method
Circuit Example
Final try: path g i j k L test found!

0
0 D
1 D
D D D
1
1

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9 19

 History of Algorithm
Speedups
Algorithm Est. speedup over D-ALG Year
(normalized to D-ALG time)
D-ALG 1 1966
PODEM 7 1981
FAN 23 1983
TOPS 292 1987
SOCRATES 1574 ATPG System 1988
Waicukauski et al. 2189 ATPG System 1990
EST 8765 ATPG System 1991
TRAN 3005 ATPG System 1993
Recursive learning 485 1995
Tafertshofer et al. 25057 1997

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9 21

 ATPG Problem
ATPG: Automatic test pattern generation
Given
A circuit (usually at gate-level)
A fault model (usually stuck-at type)
Find
A set of input vectors to detect all modeled faults.
Core problem: Find a test vector for a given fault.
Combine the core solution with a fault
simulator into an ATPG system.

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 22

 What is a Test?
Fault activation
Fault effect
X Combinational circuit
1
0
0 1/0 1/0
Primary inputs
1 Primary outputs
(PI)
0 (PO)
1
X
X

Path sensitization
Stuck-at-0 fault

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 23

 ATPG is a Search Problem
Search the input vector space for a test:
Initialize all signals to unknown (X) state complete
vector space is the playing field
Activate the given fault and sensitize a path to a PO
narrow down to one or more tests

Vector Vector
Space Circuit Space Circuit
X X
X 0
sa1 sa1 0/1
X 1

001 101

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 24

 Need to Deal With Two
Copies of the Circuit
Good circuit
X X
Alternatively, use a multi-valued
0
algebra of signal values for both

Different outputs
0 good and faulty circuits.
Same input

Faulty circuit Circuit

X X X
X
0 0
sa1 1 sa1 0/1
1 1

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 25

 Multiple-Valued Algebras
Symbol Alternative Fault-free Faulty
Representation circuit Circuit

D 1/0 1 0
D 0/1 0 1
Roths
0 0/0 0 0
Algebra
1 1/1 1 1
X X/X X X
G0 0/X 0 X
Muths
G1 1/X 1 X
Additions
F0 X/0 X 0
F1 X/1 X 1

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 26

 Function of NAND Gate
Input a
c
0 1 X D D
D
1/0 0 1 1 1 1 1
a
1
c
0/1
b 1 1 0 X D D
D Input b
X 1 X X X X

D 1 D X D 1

D 1 D X 1 D

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 27

 D-Algorithm
(Roth et al., 1967, D-alg II)
Use D-algebra
Activate fault
Place a D or D at fault site
Do justification, forward implication and consistency check
for all signals
Repeatedly propagate D-chain toward POs through a gate
Do justification, forward implication and consistency check
for all signals
Backtrack if
A conflict occurs, or
D-frontier becomes a null set
Stop when
D or D at a PO, i.e., test found, or
If search exhausted without a test, then no test possible

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 28

 Definitions
Justification: Changing inputs of a gate if the present
input values do not justify the output value.
Forward implication: Determination of the gate output
value, which is X, according to the input values.
Consistency check: Verifying that the gate output is
justifiable from the values of inputs, which may have
changed since the output was determined.
D-frontier: Set of gates whose inputs have a D or D,
and the output is X.

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 29

 Definition: Singular Cover
A singular cover defines the least restrictive inputs for a
deterministic output value.
Used for:
Line justification: determine gate inputs for specified output.
Forward implication: determine gate output.

a X Singular
0 a b c
c covers
b X
SC-1 0 X 1
Examples: XX0 110 = 110
0XX 0X1 = 0X1 SC-2 X 0 1

SC-3 1 1 0
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 30
 Definition: D-Cubes
D-cubes are
D-cube a b c
singular covers with
five-valued signals D-1 D 1 D
Used for D-drive D-2 1 D D
(propagation of D D-3 D 1 D
through gates) and D-4 1 D D
forward implication. D-5 D D D
a X D-6 D D D
X
c D-7 D 0 1
b D
D-8 0 D 1
Examples: XDX 1DD = 1DD D-9 D D 1
0DX 0D1 = 0D1
DDX DD1 = DD1 D-10 D D 1

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 31

 An Example: XOR

a2
d
a1 c1
a c
b f
c2
b1
e
b2

Find tests for: c sa0

c1 sa0
c2 sa0

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 33

 XOR:
a2
Test for c sa0
d
a1 c1
a c
b f
c2
b1
e
b2
Action Operation D-frontier
1. Activate fault c=1 or c=c1=c2=D d, e
2. Justify c=1 XX1 0X1 = 0X1, a=a1=a2=0 d, e
3. Forward impl a2=0 0DX 0D1= 0D1, d=1 e
4. Forward imp d=1 1XX XXX= 1XX, no implication possible e
5. D-drive c2e DXX D1D= D1D, b2=b=b1=1, e=D f
6. Forward impl b1=1 011 0X1 = 011, consistency checked f
7. D-drive ef 1DX 1DD = 1DD, f=D PO
8. Stop, test found Test: (a,b) = (0, 1), f = 1
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 34
Finding Other Detected Faults
by the Generated Test
Use any fault simulator:
Serial
Deductive
Concurrent
Other
Test-Detect: A simple fault simulation algorithm
Uses true-value simulation
Uses D-algebra for fault analysis
Roth et al., 1967

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 35

 Test-Detect: XOR, Test (0,1)
Determine good circuit signal values.
For each fault
Place a D or D at the fault site
Perform forward implications
Fault is detected if any PO assumes a D or D value
D for c1 sa0
0DX 0D1 = 0D1 (null D-frontier) c1 sa0 not
a2 detected
1 d
0 a1 c1
a c 1
b f
1 c2
1 b1 0 D
e
b2 D 1DX 1DD = 1DD, D at PO
c2 sa0 is detected
D for c2 sa0 D1X D1D = D1D
Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 36
 XOR:a2Test for c1 sa0
d
a1 c1
a c
b f
c2
b1
e
b2
Action Operation D-frontier
1. Activate fault c1=1 or c=c2=1, c1=D d
2. Justify c=1 XX1 0X1 = 0X1, a=a1=a2=0 d
3. Forward impl a2=0 0DX 0D1= 0D1, d=1 null
4. Back-up, redo step 3 No choice available null
5. Back-up, redo step 2 XX1 X01 = X01, b=b1=b2=0, a=X, d=X d
6. Forward impl b2=0 10X X01 = 101, e=1 d
7. Forward impl e=1 X1X XXX = X1X, no implication possible d
8. D-drive c1d XDX 1DD= 1DD, a2=a=a1=1,d=D f
9. Forward impl a1=1 101 X01 = 101, consistency checked f
10. Forward impl d=D D1X D1D = D1D, f=D PO
11. Stop, test found Test: (a,b) = (1, 0), f = 1

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 37

 Complexity of D-Alg II
Signal values on all lines (PIs and internal lines) are
manipulated using 5-valued algebra.
Worst-case combinations of signals that may be tried
is 5#lines
For XOR circuit, 512 = 244,140,625.
Podem: A reduced-complexity ATPG algorithm
Recognizes that internal signals depend on PIs.
Only PIs are independent variables and should be
manipulated.
Because faults are internal, a PI can assume only 3
values (0, 1, X).
Worst-case combinations = 3#PI; for XOR circuit, 32 = 9.

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 38

 Podem (Goel, 1981)
Podem: Path oriented decision making
Step 1: Define an objective (fault activation, D-drive, or line
justification)
Step 2: Backtrace from site of objective to PIs (use
testability measure guidance) to determine a value for a PI
Step 3: Simulate logic with new PI value
If objective not accomplished but is possible, then
continue backtrace to another PI (step 2)
If objective accomplished and test not found, then
define new objective (step 1)
If objective becomes impossible, try alternative
backtrace (step 2)
Use X-PATH-CHECK to test whether D-frontier still there
a path of Xs from a D-frontier to a PO must exist.

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 39

 XOR Example Again
Compute SCOAP testability measures: (CC0,CC1)CO

6
(4,2)3
5
(1,1)6 7 (3,2)5
(5,5)0
7
(1,1)6 5

6
(4,2)3

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 40

 Podem: Objective and
Backtrace
2&3. Backtrace to a PI 1. Objective 1: set fault site to 1
and simulate
6
(4,2)3
5 1
(1,1)6 7 (3,2)5 sa0
0 D (5,5)0
7
1
(1,1)6 5

6
X-path check fails
(4,2)3 Back up:
Erase effects of steps 2&3
Try alternative backtrace

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 41

 Podem: Back up
4&5. Alt. backtrace to a PI 1. Objective 1: set fault site to 1
and simulate
6
(4,2)3
5
(1,1)6 7 (3,2)5 sa0
D (5,5)0

0 1
(1,1)6 7 5 X-path
1
X-path check: OK
6 Objective 1 achieved
(4,2)3

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 42

 Podem: D-Drive
5. Backtrace to a PI 4. Objective 2: D-drive, set line to 1
and simulate
6
(4,2)3
1
5 D
(1,1)6 7 (3,2)5 sa0
1 D (5,5)0
7
0 1 D
(1,1)6 5
1 D at PO
6 Test found
(4,2)3

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 43

 Another Podem Example
3. Logic simulation for A=0 2. Backtrace A=0 1. Objective 0

S-a-1

(9, 2)

4. Objective possible but not accomplished

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 44

 Podem Example (Cont.)
6. Logic simulation for A=0, B=0
5. Backtrace B=0 1. Objective 0

0
0
0
S-a-1

0
(9, 2)

7. Objective possible but not accomplished

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 45

 Podem Example (Cont.)
9. Logic simulation for E=0
8. Backtrace E=0 1. Objective 0

0
0
0
0
0
S-a-1

0
(9, 2)

10. Objective possible but not accomplished

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 46

 Podem Example (Cont.)
12. Logic simulation for D=0
1. Objective 0

0
0
0
0
0
S-a-1

0 0
(9, 2)
0

13. Objective accomplished 11. Backtrace D=0

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 47

 An ATPG System
Random pattern
generator

Fault simulator
yes

Fault Random Deterministic

Save coverage patterns ATPG (D-alg.
patterns improved? no no or Podem)
yes effective?

yes
Compact Coverage no
vectors Sufficient?

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 48

Random-Pattern Generation
Easily gets tests
for 60-80% of
faults
Then switch to
D-algorithm,
Podem, or other
ATPG method

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 49

 Vector Compaction
Objective: Reduce the size of test vector set
without reducing fault coverage.
Simulate faults with test vectors in reverse order
of generation
ATPG patterns go first
Randomly-generated patterns go last (because they
may have less coverage)
When coverage reaches 100% (or the original
maximum value), drop remaining patterns
Significantly shortens test sequence testing
cost reduction.
Fault simulator is frequently used for compaction.
Many recent (improved) compaction algorithms.

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 50

 Static and Dynamic
Compaction of Sequences
Static compaction
ATPG should leave unassigned inputs as X
Two patterns compatible if no conflicting values for any
PI
Combine two tests ta and tb into one test tab = ta tb
using intersection
Detects union of faults detected by ta and tb
Dynamic compaction
Process every partially-done ATPG vector immediately
Assign 0 or 1 to PIs to test additional faults

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 51

 Compaction Example
t1 =01X t2 = 0 X 1
t3 = 0 X 0 t4 = X 0 1

Combine t1 and t3, then t2 and t4

Obtain:
t13 = 0 1 0 t24 = 0 0 1

Test Length shortened from 4 to 2

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 52

 Summary
Most combinational ATPG algorithms use D-algebra.
D-Algorithm is a complete algorithm:
Finds a test, or
Determines the fault to be redundant
Complexity is exponential in circuit size
Podem is another complete algorithm:
Works on primary inputs search space is smaller than that of
D-algorithm
Exponential complexity, but several orders faster than D-
algorithm
More efficient algorithms available FAN, Socrates, etc.
See, M. L. Bushnell and V. D. Agrawal, Essentials of Electronic
Testing for Digital, Memory and Mixed-Signal VLSI Circuits,
Springer, 2000, Chapter 7.

Copyright 2001, Agrawal & Bushnell VLSI Test: Lecture 9alt 53