PLL Theory

Digital Phase-Locked Loop (PLL) Based Frequency
Synthesizers: Theory and Analysis

D. W. Hawkins
June 18, 1999
Contents
1 Introduction 3
2 A review of PLL theory 3

2.1 PLL components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.1 Reference frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.2 Phase detectors (and charge pumps) . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.3 Loop lters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.4 Voltage controlled oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.5 Feedback counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 PLL loop analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 PLL phase noise (jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 PLL and loop lter order and type . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5 Loop lter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.6 PLL response analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.6.1 Second order PLL analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6.2 Second order PLL design procedure . . . . . . . . . . . . . . . . . . . . . . . 17
2.6.3 Third order PLL analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.6.4 Third order PLL design procedure . . . . . . . . . . . . . . . . . . . . . . . . 20
3 Synergy PLL Analysis 23

3.1 Synergy PLL overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 PLL loop analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.1 Phase detector gain measurement . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.2 Recommended loop lter analysis . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2.3 Amplier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.4 VCO gain measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3 Optimization for minimum phase noise (jitter) . . . . . . . . . . . . . . . . . . . . . 27
3.3.1 First order loop lter optimization for the SY89421V . . . . . . . . . . . . . . 27
3.3.2 Clamping the SY89421V VCO control voltage . . . . . . . . . . . . . . . . . . 39
3.3.3 Loop response to phase and frequency steps . . . . . . . . . . . . . . . . . . . 43
4 Concluding Remarks 44
2
PLL Theory March 24, 2003
Reference
qi(t) id(t) or vd(t) ve(t)
Phase FM-output
input Filter
Detector
vi(wi,qi )
qf(t) VCO
1/N VCO-output
(optional)
qo(t) vo(wo,qo)
Figure 1: The basic phase-locked loop (PLL).
1 Introduction
This document reviews the theory of phase-locked loops and then analyzes two digital PLLs manu-
factured by Synergy Semiconductor [12, 15]. It is assumed that the reader is familiar with the basic
concept of a PLL and is familiar with the terminology of control theory. Readers are recommended
to review the information in references [3, 5, 6, 8, 18].
2 A review of PLL theory

Phase-locked loops (PLLs) are one of the most widely used circuit blocks. They are found in
televisions, radios, cellular phones, computers, and numerous other electronic devices. They are
used to generate local oscillators in (analog) modulator and demodulator systems, and to generate,
recover, synchronize, or fan-out clocks in digital systems. PLLs are not limited to purely electronic
applications, another common application is motor speed control, where the PLL also contains
motors and transducers (see for example pp163-169 [3]).
The basic PLL, as shown in Fig. 1, is comprised of a feedforward path containing a phase detector,
a loop filter, and a voltage-controlled oscillator (VCO), and a feedback path containing an optional
divide-by-N counter. The phase detector (PD) compares the phase i of the incoming signal vi against
the phase f of the feedback signal and develops an output voltage vd or current id proportional
to the phase dierence or phase error e = i f , where f = o /N . In a linear PLL (LPLL) the
PD is a voltage multiplier (mixer). The LPLL PD output is a voltage containing the desired low
frequency or DC error voltage along with higher-order modulation products. The PDs in digital
PLLs (DPLLs) generate output voltage or current pulses with a pulse length proportional to the
phase dierence [1, 3, 8, 9]. The dierent PDs distinguish a LPLL from a DPLL.
The output from the PD is low-pass ltered by the loop lter to suppress high-frequency ripple
and noise, and the result, called the error voltage ve , is applied to the VCO to adjust its frequency
o . If the input signal is a frequency modulated (FM) waveform, then ve is the demodulated signal.
The error voltage causes the VCO to adjust its output phase such that the dierence between the
reference and feedback phases at the input to the PD is a constant or is zero. When the phase of
the input and feedback signal meet the appropriate phase dierence condition, the PLL is said to
be locked.
2.1 PLL components

2.1.1 Reference frequency
In PLLs, the reference frequency is either externally generated, or more commonly is generated by
an internal crystal oscillator (where the user provides an external crystal). Crystal references are
3
suitable when a system is stand-alone, such as a cellular phone. However, when a digital system
needs to be synchronized over several sub-systems, then it is usual to distribute a common highly
stable reference to which multiple PLLs lock.
In a phase-locked loop, the output frequency is related to the input frequency via fout = N fin ,
where N , the feedback counter, is typically programmable. This relationship shows that the output
frequency has to be an integer multiple of the reference. In cellular phone applications, the output
frequency must be changed by the channel spacing which is on the order of kilohertz (kHz). To
avoid having to use a bulky kHz frequency crystals, PLLs designed for use in wireless applications
use a smaller high frequency (megahertz) crystal reference followed by a reference counter [3, p135].
The output of the reference counter is a kHz waveform of the desired channel spacing. It should be
cautioned however, that such reference counters can degrade the phase noise (jitter) of the reference
frequency due to the slower update rate of the phase detector [23, p1]. Any reference frequency
jitter within the loop bandwidth is passed through to the output signal with the same gain as the
desired signal [1, p12].
2.1.2 Phase detectors (and charge pumps)

There are a number of dierent circuits that can be used as a phase detector. In linear PLLs, the
phase detector is a voltage multiplier (mixer), while in a digital PLL the phase detector can be one
of three dierent logic circuits; an exclusive-or (XOR) gate, an edge-triggered set-reset (SR) or JK
ip-op, or a phase-frequency detector. These devices all produce voltage output signals that, when
low-pass ltered, have a DC component that is proportional to the phase dierence between the
input signals. For detailed descriptions of the operation of each of these devices, see the books by
Best [3], Gardner [8], and Franco [6, p643].
The phase detectors in modern DPLLs are almost exclusively composed of a phase-frequency
detector (PFD) with a charge-pump on the output, i.e., the phase detector generates pulses of
output current. Fig. 2 shows the state machine representation of a PFD, a schematic representation
with a charge-pump output, and operational waveforms. The waveforms in Fig. 2(c) to (e) show the
input and feedback signals with the same frequency, but diering phase. Fig. 2(c) shows that when
the input reference signal leads the feedback signal, the UP output is asserted and the current source
generates a pulse of magnitude Id at the output id . Conversely, when the feedback signal leads the
input reference signal (Fig. 2(e)), the DN (down) signal is asserted and the current sink generates
a sink pulse of magnitude Id . When the signals are in-phase (Fig. 2(d)), no output current pulses
are generated and the output is (ideally) in a high-impedance state. From Fig. 2 it can be seen that
the output current id is composed of current pulses of magnitude Id sgn(e ) for a pulse duration
tp = e /i. The average output current is then
tp Id
id = Id = e = K d e (1)
Ti 2
where Ti is the period of the input reference, and Kd is the phase detector gain or sensitivity.
The phase-frequency detector diers from both the XOR and JK ip-op based phase detectors
in that its output depends not only on the phase dierence (error) i f , but also on the frequency
error i f when the loop has not acquired lock. If the reference and feedback signals are at diering
frequencies, the charge-pump will generate pulses such that the feedback frequency is pulled toward
the reference frequency. A detailed description of this pull-in process can be found in [3, pp97-
102,p117] and [6, pp645-647]. It should be noted however, that the PFD circuits in these last two
references are voltage-output devices, not current-output. In Gardners paper [9] he shows how the use
of a voltage output device leads to non-linearities, hence, most practical PLLs use a current-output
PFD. For an example charge-pump circuit design, see National Semiconductors LMX2315/20/25
data sheet [19, p21]
The PFD/charge-pump combination is the most commonly used phase detector due to the fact
that, in theory, any PLL with a PFD has an innite pull-in range, so will lock under any condition ( [3,
4
D Q Id (source)
vf vf
vi UP
Q
RST
id
Source High- Sink
Current impedance Current RST
DN
D Q
vf Q Id (sink)
vi vi
(a) (b)
qd
vi
vf
UP
DN
+Id
id
-Id
(c) (d) (e)
Figure 2: The Phase-Frequency Detector (PFD) with charge-pump output. Figures (a) and (b)
show the PFD state machine and a schematic representation, while (c), (d), and (e) show waveforms
for; the input reference signal leading the feedback signal, in-phase signals, and the input reference
signal lagging the feedback signal.
p101], [6, p647]), and the charge-pump provides type II PLL operation (see Sec. 2.4) with a passive
loop lter [9] (a voltage-output PFD requires an active lter to obtain type II performance). When
the PLL is locked, the PFD also operates such that the edges of the input reference and feedback
signal are aligned (as in Fig. 2(d)). When an XOR gate is used, the signals have a 90-degree
phase dierence [6, p643], and when the JK ip-op is used the signals have a 180-degree phase
dierence [6, p645].
If the PLL loop bandwidth is about one-tenth of the reference frequency, then the average current
given in (1) can be used to generate an approximate linear model for the PLL. The approximation
is referred to as the continuous-time approximation [1, 9]. If the loop bandwidth begins to approach
the reference frequency, then the discrete nature of the charge-pump output must be accounted for.
The linear and discrete analysis of PFD/charge-pump PLLs is described in Gardners paper [9]. The
rest of this document uses the linear model.
2.1.3 Loop filters

The basic operation of the passive or active loop lter is to remove the high-frequency components
from the output of the phase detector to produce a low-frequency or DC control voltage for the VCO.
5
The loop lter also aects the stability, phase noise performance, and sideband level of the PLL.
Since the phase detector and VCO designs are usually less exible, the loop lter is the principle
tool with which a designer determines the dynamic and noise response of the PLL and as such, it is
dealt with in more detail in Section 2.5.
2.1.4 Voltage controlled oscillators

A voltage controller oscillator is designed so that for a control voltage vVCO it produces an output
frequency according to the linear relationship
o (t) = int + Kv vVCO (t) (2)
where vVCO is the voltage at the input to the VCO, int is the intercept at vVCO = 0, and Kv is the
slope in units of Hz per volt. This linear relationship typically only holds over a small percentage
of the VCO supply voltage range.
The error voltage is typically dened relative to some initial bias voltage at which the VCO
output is c . That is, if we dene vVCO (t) = vbias + ve (t) and c = int + Kv vbias , then the VCO
characteristic is [6, p633]
o (t) = c + Kv ve (t). (3)
In FM applications, it is usually required that the V -F characteristic of the VCO be highly

linear in order to minimize distortion. However, in such applications as frequency synchronization,
synthesis, and reconstruction the linearity requirements are less stringent [6, p642]. Section 3 shows
the (non-linear) VCO transfer function for two Synergy PLLs.
2.1.5 Feedback counters

In Fig. 1, the feedback counter is shown as a simple divide-by-N block. In more complex PLLs,
multiple counters are used. If the VCO output is a high frequency, then it is common to use a
xed value pre-scaler (divide-by-P ) or a pre-scaler with a dual-modulus (divide-by-P or (P + 1)) to
reduce the high frequency VCO output to a lower frequency. The lower frequency pre-scaler output
is then further divided by a (cheaper) programmable counter [2, p5]. The use of a programmable
counter in the feedback loop allows the generation of dierent output frequencies (within the range
of the VCO). Fixed value prescalers are used in simple frequency synthesis PLLs (such as the ones in
Section 3), while dual-modulus prescalers are common in the frequency synthesizers used in wireless
applications (for example see [2, 16, 19, 22], and pp135-147 [3]).
2.2 PLL loop analysis

When in the locked condition, a PLL can be modeled using a linear model as in Fig. 3. This diagram
is the Laplace transformed version of Fig. 1.
If it is assumed that the PLL 3dB bandwidth is about one-tenth of the reference frequency, then
the phase detector output pulses can be modeled by their average value. This assumption is referred
to as the continuous-time approximation [1, 9]. The phase detector output is then modeled as
id (s) = Kd e (s) (4)
where Kd is the phase-detector sensitivity, in amperes per radian (for a voltage output phase detector,
the units are volts per radian). This current produces a voltage output over the loop lter impedance
Z(s). If an active lter is used, then it is congured as a transimpedance amplier [6, p59] with
gain in units of volts per ampere (Ohms). The output of the loop lter is the voltage vVCO , which
contains the bias voltage and the error voltage. The error voltage produces the frequency variation
o = Kv ve (s).
6
Phase
Reference
qi(s) Detector id(s) Filter ve(s) VCO
input Kd Z(s) Ko(s) = Kv/s VCO-output
[A/rad] [V/A] [rad/V]

qf(s) qo(s)
Kn = 1/N
Figure 3: The Laplace form of the basic phase-locked loop (PLL).
Since the phase detector processes phase, we need a means for converting from frequency to phase.
Considering that frequency represents the rate of change of phase with time, or = d(t)/dt, we
have
t
(t) = (0) + ()d. (5)
0
The Laplace transform of the VCO is then clearly that of an integrator [22, p98]; that is,
Kv
Ko (s) = (6)
s
which has units of radians per volt. The feedback counter has a unitless gain of Kn = 1/N .
The (unitless) forward gain of the PLL is then
G(s) = Kd Z(s) Ko (s)

Kd Z(s) Kv (7)
=
s
and the feedback gain is simply
H(s) = Kn (8)
The open loop gain of the PLL is
Tol (s) = G(s)H(s)

Kd Z(s) Kv Kn (9)
=
s
and the closed loop gain is
o (s) G(s)
Tcl (s) = =
i (s) 1 + G(s)H(s)
1/H(s)
= (10)
1 + 1/[G(s)H(s)]
N
= .
1 + 1/Tol(s)
The major component in the close-loop transfer function in (10) that the user has control over, is
the loop transfer function Z(s). Hence, the stability and dynamic characteristics of the PLL are
controllable via the choice of the loop lter. Section 2.5 investigates the design of the loop lter.
7
If the open loop gain is high, then Tcl (s) N , i.e., the output phase and hence frequency is N
times that of the input:
o (t) = N i (t) (11)
which dierentiates to
o (t) = N i (t). (12)
The error response of the loop is also of interest. For the second order PLL, the error response
is [8, p12]
e (s) i (s) f (s)

Te (s) = =
i (s) i (s)
o (s)
= 1 H(s)
i (s) (13)
= 1 H(s)Tcl (s)
1
= .
1 + G(s)H(s)
The open-loop, closed-loop, and error response of a second order, Type II PLL are plotted in Figure 8.
The error response is used to determine the steady state error (after transients have died away)
due to phase steps, frequency steps, and frequency ramps. Using the nal value theorem of Laplace
transforms [5, p76], the steady state error is determined using ( [8, p43], [18, p3])
lim e (t) = lim se (s)

t s0
(14)
= lim sTe (s)i (s)
s0
The steady state phase error due to a phase step is zero for all loop types I, II, and III ( [18, p4], [3,
p44]). The steady state phase error due to a frequency step (a phase ramp) is called the static
phase error. The denominator of the static phase error is proportional to the DC gain of the loop
lter [8, p44]. So, to obtain zero static phase error, it is necessary to use an integrator in the loop
lter, i.e., if it is desired for a PLL to track a reference frequency with zero phase error, a minimum
of type II is required ( [18, p4], [3, p44]). Integrators built using active lters will have a large, but
nite DC gain, so they will have a small static phase error. The steady state phase error due to a
frequency ramp is called the acceleration error. Two integrators in the loop lter are required to
obtain zero acceleration error. Accerelation error is not usually considered a problem in frequency
synthesis applications, it is usually considered for missile and satellite tracking applications (to
account for Doppler eects) [8, p46].
The steady state errors just discussed assume that the input phase jumps are small enough that
the PLL can still be treated as a linear system. When the phase jumps are large, the PLL will
unlock and the non-linear acquisition process of the loop must be considered. The unlocking of the
loop is characterized by the hold-in range and pull-out frequency, while the acquisition process is
characterized by the lock-in range and pull-in range. The transient and non-linear aspects of PLLs
are covered in detail in Gardner [8] and Best [3].
2.3 PLL phase noise (jitter)

In a locked PLL, phase noise in the output produces an uncertainty in the output edge transition
location. This uncertainty is referred to as jitter. Figure 4 shows a linearized PLL model with ve
8
fni Phase
ind vne fnv
Detector Filter VCO
id(s) ve(s)
qi(s) Kd Z(s) Ko(s) qo(s)
Feedback
Counter
qf(s)
1/N
fnf
Figure 4: Noise sources in a PLL.
dierent noise sources. Each of the PLL components are considered as noiseless and a noise source
is added at the output. Figure 4 gives the loop equations
id (s) = Kd {i (s) f (s) + ni nf }

ve (s) = Z(s) {id (s) + ind }
o (s) = Ko (s) {ve (s) + vne } + nv
f (s) = o (s)/N (15)
Solving these equations for the output phase gives
G(s)
o (s) = i (s) + no , (16)
1 + G(s)H(s)
where the output phase noise

G(s) ind 1 Kv vne
no = ni nf + + nv +
1 + G(s)H(s) Kd 1 + G(s)H(s) s
(17)
ind Kv vne
= Tcl (s) ni nf + + Te (s) nv +
Kd s
Phase noise sources in the input, feedback counter, and phase detector undergo gain to the output
proportional to the closed-loop gain. Since this gain is the same as the gain of the input phase to
the output phase, these noise sources are referred to as in-band noise sources. Phase noise in the
loop lter is integrated by the VCO, adding to the VCO phase noise. These two phase noise sources
undergo the same gain to the output as the error response of the input phase into the error phase.
The fact that phase noise in the lter and VCO undergo a loop gain proportional to Te (s), is one
of the most important features of a PLL. In conditions where the loop gain is high, the VCO noise
gain is low, i.e., a VCO with poor phase noise is cleaned up by the PLL. The statement is very
clearly demonstrated in the measurement results in Fig. 15. The phase noise of the free running VCO
in Fig 15(b) is cleaned up to that in Fig 15(d) by the PLL action. The phase noise characteristics
of the PLL output are then more like that of the reference shown in Fig 16. Since the in-band
noise sources have a gain of N within the loop bandwidth, the phase noise oor seen in Fig 15(d)
should be around 20 log10 N higher than that of the reference phase noise in Fig 16. For N = 32 the
dierence should be 30dB, whereas the observed dierence is only 19dB. This discrepancy is due to
9
the phase noise in Fig 16 being determined by the noise oor of the spectrum analyzer (the reference
was removed from the input and the same noise oor was obtained).
The fact that in-band noise sources are multiplied by N is a problem in wireless systems where
N can be larger than 30000 (90dB). For this reason, many PLLs used in wireless applications
are based on fractional-N or dual-modulus techniques, as the feedback counter value is reduced
signicantly [10]. Phase noise due to an active lter is often eliminated by using a passive lter.
However, the use of a passive lter requires the use of a current-output PFD to obtain type II
performance.
The closed-loop gain, input-output frequency relationship, and VCO noise gain equations in (9),
(12), and (13) lead to the two main reasons for using a PLL as a frequency synthesizer. The rst
reason is to translate the frequency accuracy of a high quality signal source (the reference) to a
tunable signal source (the output). The second is to translate the noise characteristics of a high
quality signal source to a lower quality signal source (the VCO) [2].
Jitter can be characterized in the time or frequency domain. Section 3 shows that both domains
need to be observed during loop optimization, as what may seem a signicant change in the frequency
domain may cause no change in the time domain. The interpretation of quality in either domain is
also application dependent. For a wireless application, low sidelobe levels are a denite requirement,
however, for a clock synthesis application low jitter in the time domain is important (Section 3 shows
that high sidelobes can exist in a signal with reasonable time domain jitter).
Phase noise is dened as the ratio of the single sideband power (within a 1Hz bandwidth at
some oset from the output carrier) to the total carrier power. Using a spectrum analyzer, phase
noise is often measured at osets of 1kHz, 10kHz, or 100kHz. The carrier-to-noise reading from the
spectrum analyzer is converted to phase noise in decibels relative to the carrier per Hertz (dBc/Hz)
via [2]
Phase Noise (dBc/Hz) = Carrier-to-noise (dBc) - 10 log10 (RBW (Hz))
where the resolution bandwidth (RBW) is also read from the spectrum analyzer.
Jitter in the time domain is proportional to the integrated phase noise in the spectral domain.
Using this fact, an integration over an approximate phase noise density function (in units of dBc/Hz)
gives the following rule-of-thumb [1, p21]:

RMS 150 10(dBc/Hz)/20 f3dB , (18)
in units of degrees. As an example, the PLL results in Section 3 show time domain jitter of around
30ps and in the spectral domain, a phase noise oor of -85dBc/Hz (at 100kHz oset). The output
waveform is at 1024MHz, the reference is 16MHz, and the loop 3dB bandwidth is around 2MHz.
Inserting the frequency domain parameters into (18) and converting to seconds gives an estimated
RMS jitter of 32ps. Clearly the rule-of-thumb gives a good estimate for time domain jitter in the
test PLL.
The lter in a PLL converts the current or voltage pulses from the phase detector into an almost
constant VCO control voltage. This control voltage still contains residual modulation components at
the reference frequency and multiples of the reference frequency. This residual baseband modulation
modulates the VCO, generating sidebands about the output carrier. These sidebands are referred to
as reference spurs. The reference spurs are another noise component. Their level is quoted directly
in terms of power relative to the carrier in units of dBc.
Two general principles may be abstracted from the preceeding discussions [8, p137]:
1. To minimize output phase jitter due to external noise the loop bandwidth should be made as
small as possible.
10
R0
vd(t) vbias + ve(t)
Zf
R0 Zf
vd(t) -
vbias + ve(t)
vbias +
(a) (b)
id(t) vbias + ve(t)

Zf
Zf
id(t) -
vbias + ve(t)
vbias +
(c) (d)
Figure 5: Some common lters congurations. The active and passive lters shown in (a) and (b)
respectively, are appropriate for voltage-output phase detectors, while the lters shown in (c) and (d)
are appropriate for current-output phase detectors. Fig. 6 shows the passive components required
for rst and second order lters, while Tables 1 and 2 show transfer functions.
2. To minimize output phase jitter due to internal oscillator noise, or to minimize transient
error due to signal modulation, or to obtain best tracking and acquisition properties, the loop
bandwidth should be made as wide as possible.
These principles are directly opposed to one another, so it is necessary to come to a compromise
that is best for a given application. This compromise is made by determining an appropriate loop
lter for a given PLL application.
2.4 PLL and loop filter order and type

Before analyzing the PLL loop lter, some terminology needs clarication. A loop lters order is
determined by the number of poles in its transfer function. A PLLs order is determined by the
number of poles in its open-loop transfer function (this is also equivalent to the highest degree of its
characteristic equation [18, p3]). The PLL or loop lters type is determined by the number of poles
at the origin (1/s terms, or integrations) ( [6, p636], [18, p3], [7, p61], [3, p24], [5, p215]). Due to
the presence of the integrator in the VCO, the PLL type is always at least type I, and the order of
the PLL is the order of the loop lter plus one.
2.5 Loop filter design

The determination of the loop lter components varies depending on the intended application. For
example, if a PLL is to be used in a wireless application in a TDMA system, then it is desirable for
the PLL to be able to switch to dierent output frequencies and settle to the desired frequency in a
very short time. This requirement translates to wide PLL loop bandwidth. However, low reference
frequency spurs (sidebands) are also desired. Low reference spurs require high attenuation at the
11
Table 1: Transfer functions, Z(s), for the lters shown in Fig. 5.
Fig. 5
(a) (b) (c) (d)
Zf (s) Zf (s)
Z(s) Zf (s) Zf (s)
R0 R0 + Zf (s)
R1 R1 R1 C2
Zf = C2
C1 C1
C1
(a) (b) (c)
Figure 6: Passive components required for; (a) rst order, and (b) and (c) second order lters (for
examples, see p8 and p152 [3], pp638-639 [6], [1], and [11]).
reference spur frequency. High attenuation can be obtained by decreasing the PLL loop bandwidth
or by increasing the order of the loop lter. The loop lter components for this form of design are
chosen by trading o settling time and reference spur level requirements [2, 4, 11, 18].
For a frequency synthesis application, where the PLL is used to generate a stable (quiet) high
frequency signal from a much lower reference, then minimizing the output phase noise becomes the
driving design factor. Phase noise in a frequency synthesizer is minimized by adjusting the loop
bandwidth and the phase margin of the closed-loop response. The phase margin is adjusted by
altering the location of the zero within the 3dB bandwidth for a rst order lter, and by adjusting
the location of the zero and the second pole in a second order lter (assuming here that the rst
pole is at the origin). Higher order lter poles are used to suppress sidelobe levels, and are generally
placed above the second lter pole so that they do not overly inuence the phase margin. A system
optimized for frequency synthesis usually has a at phase noise spectrum, as this corresponds to
minimum phase jitter in the time domain waveform [20].
In both of these design cases, if a monolithic PLL has been chosen (perhaps on the basis of
compactness), then the only variable available for optimization is the loop lter. In the case of
the Synergy PLLs investigated in Section 3, the loop lter is an active lter. Other PLLs, such as
National Semiconductors LMX2315/20/25 [19] give the option of using a passive lter.
Figure 5 shows some common passive and active lter congurations, Fig. 6 shows the passive
components needed to make rst and second order lters (and hence second and third order PLLs).
Table 1 shows the transfer functions of the lters in Fig. 5 and Table 2 shows the impedances for
the components in Fig. 6. One of the important observations to make from these gures and tables
is that for a voltage-output phase detector (voltage-input lter), it is necessary to use an active
filter to preserve the poles in the lter impedance Zf (s), whereas for the current-input lters, both
active and passive lter congurations preserve the poles in Zf (s). Now, from Table 2, it can be
seen that all the Zf (s) congurations give a pole at zero, i.e., Zf (s) is a type I impedance. Since
Fig. 5 lter congurations (a), (c), and (d) preserve this zero, all of these lters can obtain type II
12
Table 2: Impedances for the passive components shown in Fig. 6.
Fig. 6 Zf (s) Time constants
s + 1/1
(a) R1 1 = R1 C1
s
1 s + 1/1 C1 C2
(b) 1 = R1 C1 , 2 = R1
C2 s(s + 1/2 ) (C1 + C2 )
(C1 + C2 ) s + 1/3
(c) 3 = R1 (C1 + C2 ), 4 = R1 C2
C1 C2 s(s + 1/4 )
PLL performance. The popularity of using current-output charge-pumps in PLLs is due to the fact
that the PLL can achieve type II performance with a low-noise passive lter.
Active lters are still used in conjunction with current-output phase detectors to reduce the
static phase error due to VCO control terminal loading eects [9, p1851], i.e., if the VCO input
impedance is low, then the active lter acts as a buer between the loop lter and the load of the
VCO input. When an active lter is used in any PLL, it introduces an inversion (see Table 1) that
must be compensated for. The inversion can be compensated for by active inversion (for example
see p639 [6]) or, more commonly, by reversing the direction of the phase detector output current id .
The direction of id can be reversed by interchanging the UP and DN inputs on the charge pump
(see Fig. 2 for the circuit conguration) or by interchanging the phase detector inputs [6, p638].
For a frequency synthesis application, there is no signicant dierence between the two second
order loop lters obtained using the two impedance congurations in Fig. 6(b) and (c). From
Table 2, it can be seen that both lters have a pole at the origin followed by a zero. If the next
pole is to be located somewhat higher than the zero, then C2 C1 , so 3 R1 C1 , 2 R1 C2 ,
and the amplitude factor (C1 + C2 )/(C1 C2 ) 1/C2 , i.e., both lters have approximately equivalent
zero and pole locations and amplitude factors. In wireless applications, optimal dynamic response
is obtained by dening the 0dB intercept of the open-loop transfer function (the 3dB bandwidth of
the closed-loop gain) as the point at which the phase margin of the lter should equal 45 . In this
case, the two dierent second order lter congurations may yield slightly dierent values (since the
pole and zero are quite close together). See reference [11] for an application of this last technique.
Examples of active and passive lter use can be found in the following: the data sheets and
application notes for Micrel-Synergy Semiconductors ClockWorks devices show an external second
order active lter for the SY89429A and a rst order active lter for the SY89421V [1215]. The
data sheet and application notes for the National Semiconductor LMX devices show second, third,
and forth order passive lters [1, 2, 4, 11, 19]. And, Motorola application notes and data sheets show
both active and passive lter congurations [17, 18, 21].
2.6 PLL response analysis

This section gives the procedure for determining the loop lter components for second and third
order, type II PLLs. One set of component values is determined on the basis of dynamic response,
while a second set is determined on the basis of optimal noise performance. The rst set of compo-
nent values would be appropriate for wireless applications, where it is required to switch to dierent
operating frequencies and settle in a very short time. The second set of component values is appro-
priate for a system not requiring fast settling times, but instead is more concerned with low phase
13
noise (low signal jitter).
2.6.1 Second order PLL analysis

A second order, type II PLL is characterized by an open-loop transfer function of the form
(s + a)
Tol (s) = G(s)H(s) = K . (19)
s2
For example, the open-loop gain equation given by
Kd Kv R1 (s + 1/1 )
Tol (s) = . (20)
N s2
is appropriate for a current-output PFD with either an active or passive lter, and with the addition
of a 1/R0 term, it becomes appropriate for a voltage-output PFD with an active lter. See Section 2.5
for the denitions of the lter components.
The characteristic equation of the PLL represents the roots of the denominator of the closed-loop
transfer function, that is;
C.E. 0 = 1 + G(s)H(s)
= s2 + sK + Ka (21)
2
= s + 2n s + n2
From equations (19), (20), and (21) we obtain the set of equations:
Kd Kv R1
K= = 2n
N
1 1
a= =
1 R1 C1
Ka = n2 (22)
The design procedure now assumes that the parameters n , , Kd , Kv , and N are known (or can
be specied), so we can solve (22) for
2n N
R1 = (23)
Kd Kv
and
Kd Kv
C1 = . (24)
n2 N
Since some of the specied parameters may have a range of values, for example the feedback counter,
it is necessary to look at a root-locus plot of the system.
A root-locus plot is useful for graphically visualizing the stability of a system. The root-locus
plot displays the poles and zeros in the open-loop transfer function and displays the variation in
closed-loop stability for dierent loop gains, K [18, p4]. Solving the quadratic equation in (21) gives
the variation in the closed-loop poles

K K 2 4Ka
s =
2 2

= n 2 1 (25)

= n j 1 2 .
14
jw
increasing K
s-plane
path of s+
wn
zero at s = f s
two poles
path of s- at s = 0
zero at s = a a = 1/(R1C1)
Figure 7: Root-locus plot of the second order, type II PLL. The bold lines show the variation in
closed-loop pole location (s+ and s ) for varying values of loop gain K.

where j = 1. The location of the closed-loop poles in the s-plane is then clearly

(, j) = n (, j 1 2 )
(26)
= n ( cos , j sin ),
where cos = for 0 1 (when 1, the poles are real and they lie on the axis). Figure 7
shows the migration of the two roots s+ and s with loop gain K. References [18, p4], [8, p18-21]
and [5, Ch. 13] detail the construction of root-locus plots.
The specication of n and corresponds to choosing a single point on the K curve for a given
zero location. For example, Fig. 7 shows the vector n at angle ( 0.85) for a particular value
of gain K (marked by a small white triangle) and zero location a. Any change in a or K generates
a dierent value for n and . Now when one attempts to optimize the values of R1 and C1 , the
root-locus gives a clear view as to the aect of moving the zero or changing the loop gain. For
example, if a higher value of loop gain was desired, then R1 would need to be increased (since (22)
shows that K is directly proportional to R1 ), however, since a = 1/(R1 C1 ), C1 would have to be
reduced by the proportion that R1 was just increased. The root-locus plot also shows the aect of
a variable counter setting N , since K is proportional to 1/N , the loop gain decreases for increased
N . So if a second order loop is being designed with a critical damping factor of = 0.707, then K
should be calculated with the maximum value N will take on. For lower values of N , the loop will
then have a higher damping factor. (This last design criteria is dierent in a third order PLL).
Once values of R1 and C1 are determined from (23) and (24), they are rounded to the nearest
available value, and the resulting natural frequency and damping factor are recalculated via

Kd Kv
n = (27)
N C1
and

1 Kd Kv R12 C1
= . (28)
2 N
15
100 50
-40dB/decade Nmax
-20dB/decade
50 Nmin Nmin
Nmax -20dB/decade
dB
dB
0 0
-50
-100 a = 1/t1 a = 1/t1

4 6 8
-50 4 6 8
10 10 10 10 10 10
Frequency (Hz) Frequency (Hz)
(a) (c)
-100 0
-20 noise
-120
degrees
reduction Nmax
ym(Nmin) = 71.7
o
dB
-140 -40 region
ym(Nmax) = 59.1
o
-60 Nmin
-160
-180 -80 40dB/decade
4 6 8 4 6 8
10 10 10 10 10 10
(b) (d)
Figure 8: Bode plots for a second order PLL. The open-loop gain and phase (Tol (j2f )) are shown in
(a) and (b), (c) shows the closed-loop gain (Tcl (j2f )), and (d) shows the error gain (Te (j2f )).
The plots all show how changing the feedback counter over the range Nmin to Nmax aects the
loop parameters. The logarithmic scale of the frequency axis de-emphasizes the fact that the 3dB
bandwidth varies by almost a factor of 2 for Nmin to Nmax = 2Nmin (see the text for more details).
The second method commonly used for visualizing system stability is the Bode plot. Figure 8(a)
and (b) shows the Bode plot of the open-loop gain and phase of a second order, type II PLL. The
magnitude plot of the open-loop gain leaves the origin with a slope of -40dB/decade and phase of
-180. These two characteristics are due to the existence of the two poles at the origin (one from
the lter, one from the VCO). The zero at 1/1 (eventually) reduces the -40dB/decade slope to a
single pole response of -20dB/decade. The stability of the closed-loop system is determined by the
point where the open-loop gain crosses 0dB, i.e., Tol (j0dB ) = 1. Solving this equation gives a
2
quadratic in 0dB which has the solution:
1/2
0dB = n 2 2 + 1 + 4 4 . (29)
Figure 8(a) shows two diamonds at the location predicted by this equation for two feedback counter
extremes. The phase margin, m , i.e., the dierence between the open-loop phase and -180 at the
0dB crossover, is
m = tan1 (0dB 1 ). (30)
The open-loop gain depends on the feedback counter value, hence, both the 0dB crossover point and
the phase margin are dependent on the feedback counter setting. Figure 8 shows gain and phase
curves for two dierent counter settings, Nmin and Nmax .
The phase margin at the 0dB crossover point must be greater or equal to 45 for the system
response to be considered acceptable, with minimal overshoot in the closed-loop and error gain
responses (Figure 8(c) and (d)). To ensure that this phase margin is met, the zero, a = 1/1 , is
located prior to the 0dB crossover point. The ultimate distance of the zero from the crossover point
depends on the desired phase margin or damping factor.
16

The 3dB bandwidth of the closed loop system is the point at which Tcl (j3dB ) = N/ 2.
2
Solving this equation gives a quadratic in 3dB which has the solution:
1/2
3dB = n 1 + 2 2 + 2 + 4 2 + 4 4 . (31)
Figure 8(c) shows the closed-loop gain for two feedback counter settings, with two diamonds located
at the 3dB point determined by (31). The closed-loop gain drops o with a single pole roll-o of
-20dB/decade. This roll-o helps to attenuate the reference spur levels. Higher order lters are
often used, as they have a 40dB/decade or higher roll-o after the 3dB bandwidth of the closed-loop
response.
Figure 8(d) shows the error gain in the closed-loop PLL. The low frequency section of this gure
rises at 40dB/decade, reaching 0dB around the 0dB crossover point of the open-loop gain. This high-
pass response is what allows a PLL to take a comparatively noisy VCO (compared to the reference)
and clean it up to produce a very low noise (low jitter) output waveform. If the zero in the loop lter
is moved down in frequency (by specifying a high damping factor or phase margin), then the ability
of the PLL to reject VCO noise is reduced, as the attenuation through the low frequency section is
reduced signicantly. By moving the zero to a lower frequency, the 40dB/decade high-pass response
will leave the origin with a lower amount of attenuation, and then the response will change to a
20dB/decade slope as it passes through the zero and approaches the 0dB gain point. Placing the
zero close to the 0dB crossover point can give the best noise rejection in PLLs with noisy VCOs.
2.6.2 Second order PLL design procedure

The visual understanding of the dynamics of the PLL response provided by the root-locus plot and
the Bode plot lead to the development of the following design procedure. The design procedure for
a second order, type II PLL is:
1. Select the maximum desired 3dB bandwidth as a fraction of the reference frequency.
3dB max = 2fref (32)
For example, for frequency switching applications, the 3dB bandwidth is typically one-tenth of
the reference frequency. For low noise frequency synthesis applications where switching speed
is not of concern, then the 3dB bandwidth is selected to be the intersection of the reference
phase noise spectrum with the VCO phase noise spectrum [21, p274], [1, p14].
2. Select the minimum desired damping factor. For frequency switching applications min =
0.707 is typical, and for frequency synthesis applications min = 10 gives the optimal noise
performance [21, p274].
3. Calculate the natural frequency via
2fref
n = 1/2 , (33)
2
1 + 2max 2
+ 2 + 4max 4
+ 4max

where max = min Nmax /Nmin .
4. Determine the loop components R1 and C1 via (23) and (24) using Nmin and max and choose
the nearest available values.
5. Recalculate n , , m , and 3dB using (27), (28), (30), and (31) for the passive components
chosen and for the range of feedback counter values.
17
N = 64
wn = 3.2 Mrad/s
z = 0.60 jw (Mrad/s)
N = 32 3
wn = 4.5 Mrad/s
z = 0.85 2
N = 48
N = 40 1
-1
-2
-3
-7 -6 -5 -4 -3 -2 -1 0 s (Mrad/s)
Figure 9: Root-locus plot of the SY89421V congured as a second order, type II PLL. The feedback
counter can take on the values N = 32, 40, 48, and 64. The closed-loop poles for each of these
counter settings are marked by small triangles.
Alternative design procedures can be found in the literature. A common wireless design procedure
starts by specifying the damping factor and then the natural frequency required to settle to within
a few percent when the PLL is frequency stepped. Once and n are specied, K and a can be
calculated [18].
The Bode plot in Figure 8 was generated using parameters from the SY89421V PLL tests in the
following sections. That is, Kd = 120/(2)A/rad, Kv = 22500 Mrad/s, there was an additional
divide-by-4 counter in the feedback path, and a reference frequency of 16MHz was used. Since
the feedback counter can only be programmed such that the VCO is within its specied operating
range of 480MHz to 1120MHz, the feedback counter can take on the values 32, 40, 48 ,64, i.e.,
Nmin = 32 and Nmax = 64. Following the design procedure above for a minimum damping factor of
= 0.6 and a 10-percent 3dB bandwidth relative to the reference frequency gave R1 = 806 and
C1 = 470pF (nearest available values). The calculated range of damping is then = 0.60 to 0.85, the
3dB bandwidth ranges over a fractional bandwidth of 6 to 10-percent, and the phase margin ranges
between 59.1 and 71.7 . The logarithmic scale of the frequency axis in Figure 8 de-emphasizes
the fact that the 3dB bandwidth varies by almost a factor of 2 for the variation in Nmin to Nmax .
Figure 9 shows the root-locus plot for the dierent feedback counter settings, i.e., it shows a plot of
the zero and poles in
2N n (s + a)
Tcl (s) = (34)
s2 + 2n s + n2
where the zero is at s = a, and the two poles are located in the s-plane via (26).
Bode plots in many of the references are plotted against a logarithmic frequency axis normalized
to the natural frequency of the loop, /n , making one set of plots applicable to any second order
PLL. For example, see p12-13 [8], or p19-20 [3].
18
2.6.3 Third order PLL analysis

To improve sidelobe (reference spur) levels, a third order (or higher) PLL is often used. A second
order, type II PLL becomes a third order, type II PLL, with the introduction of a pole at a frequency
several times the zero frequency. The pole needs to be far away from the rst reference spur, so
that it introduces the most attenuation at the spur, yet it must be high enough above the zero that
phase margin is not reduced.
The open-loop gain equation
Kd Kv (s + 1/1 )
Tol (s) =
N C2 s2 (s + 1/2 )
(35)
(s + a)
=K 2
s (s + b)
is appropriate for a third order, type II PLL, with a current-output phase-frequency detector, and
a second order active or passive lter. The lter topology is a series resistor and capacitor, R1 and
C1 , in parallel with a capacitor, C2 . From (35) and the lter equations in Section 2.5 we have
Kd Kv
K=
N C2
1 1
a= =
1 R1 C1
1 1 1
b= = + (36)
2 R1 C1 R1 C2
The magnitude and phase of the open-loop gain at frequency are given by

2 + a2
Tol (j) = K (37)
2 + b2
2
and

Tol (j) = tan1 tan1 180 . (38)
a b
Dening the phase margin as the dierence between the open-loop phase and 180 gives

() = tan1 tan1 . (39)
a b
A common procedure for determining the loop lter components begins by making the reasonable
assumptions that the loop-bandwidth and desired phase margin are specied components. It is then
assumed that the desired phase margin is also the maximum value that the phase margin in (39)
achieves [11]. Using this last assumption, we obtain
d 1/a 1/b
= =0 (40)
d 1 + (0dB /a)2 1 + (0dB /b)2
which denes the point where the open-loop gain crosses zero dB,

0dB = ab (41)
That is, the open-loop gain crosses 0dB at the geometric mean of the open-loop zero, a, and pole
b. This observation is important for loops using a range of feedback counter values. In the design
procedure, the specied 3dB bandwidth of the closed-loop is equated with the 0dB intercept, i.e.,
3dB 0dB .
19
The phase margin at the 0dB intercept is then:

m = (0dB ) = tan1 tan1
0dB 0dB
. (42)
a b
Taking the tangent of both sides gives
0dB /a 0dB /b
tan(m ) = 2 /(ab) . (43)
1 + 0dB
Inserting (41) into this and solving the resulting quadratic in a for the positive root gives
a = 0dB {sec(m ) tan(m )} (44)
where 0 m < 90 , i.e., the best the zero can do is introduce a 90 phase margin. Once a has
been solved for, (41) and the specied 3dB bandwidth gives b.
Since maximum phase is dened as occurring at the 0dB intercept, solving Tol (j0dB ) = 1
gives the values of the passive components; that is,
Kd Kv 1
C2 = (45)
N b ab
1
R1 =
C2 (b a)
(46)
N b ab
=
Kd Kv b a
and
1
C1 =
R1 a
(47)
Kd Kv b a
= .
N (ab)3/2
2.6.4 Third order PLL design procedure

The design procedure for a third order, type II PLL is summarized as:
1. Select the maximum desired 3dB bandwidth as a fraction of the reference frequency.
3dB max = 2fref (48)
For example, for frequency switching applications, the 3dB bandwidth is typically one-tenth of
the reference frequency. For low noise frequency synthesis applications where switching speed
is not of concern, then the 3dB bandwidth is selected to be the intersection of the reference
phase noise spectrum with the VCO phase noise spectrum [21, p274], [1, p14].
2. Select the desired phase margin. For frequency switching applications m = 45 is typical, and
for frequency synthesis applications the margin can be larger, but it is limited to 0 m < 90 .
3. Determine the lter zero and pole locations using (44) and (41). For 0dB use 3dB the rst
time through this design procedure. If the Bode plot of the closed-loop response generated
at the end of the design process has a 3dB bandwidth larger than desired, apply the required
fractional reduction here the next time through the design process.
20
4. Determine the loop components R1 , C1 , and C2 via(46), (47), and (45) using the geometric
mean of the feedback counter value range, i.e., N = Nmin Nmax .
5. Draw the Bode plots of the resulting open- and closed-loop gain and determine if the phase
margin and 3dB bandwidth over the feedback counter range are acceptable. If the phase
margin (bandwidth) is too low (high), increase (decrease) the specied value and repeat the
design procedure.
Alternatively, the phase margin for a given counter value is given by (42) with the 0dB intercept
given by

1 1
0dB = 6 b2 (49)
6 3
where

= 36K 2 b2 + 108K 2a2 8b6
1/3 (50)
+12 12K 6 3K 4 b4 54K 4 a2 b2 + 81K 4 a4 12K 2a2 b6
and
1 1
= K 2 b4 . (51)
3 9
This last set of equations is obtained from the square root of the real solution of the cubic
2
equation in 0dB resulting from Tol (j0dB ) = 1 (solved using Maple [24]). The value of the
feedback counter at which the phase margin is to be determined sets the value of K. All other
parameters have been determined by the design procedure.

The 3dB bandwidth can be predicted by solving the equation Tcl(j3dB ) = N/ 2. However,
the resulting equation is lengthy, so is not reproduced here. The visual results provided by the
Bode plots should be adequate for most applications.
The use of the geometric mean of the feedback counter settings means that the phase margin
is only satised at that point and is slightly worse for other counter settings (since this point is a
maxima). However, the maxima is a fairly broad peak, so the variation in phase margin can usually
be tolerated, or can be compensated for by increasing the specied margin.
Although this design procedure is very common (see refs. [11], [19], [4], [1]), it is by no means the
only design procedure. An alternative design procedure can be formulated for a second order loop
that is to be migrated to a third order loop. For example, lets say that the phase noise characteristics
have been optimized for a second order PLL, but the spur levels are too high. It is unlikely that you
would want to change the values of R1 and C1 , you would really just like to know the value of C2
required to modify the loop to third order.
Looking at the open-loop gain equations for the second-order and third-order loops in (19)
and (35) it can be seen that the gain functions are not identical. However, from the Bode plots
in Fig. 8 and Fig. 10, it can be seen that both open-loop gain curves leave the origin with a -
40dB/decade and that this slope is reduced by the zero at a. To determine a value for C2 without
changing R1 and C1 , we have to have identical low-frequency gain curves for the second and third
order PLL open-loop gains. The only way this can occur is if the two gain curves have the same
amplitude at a. Equating the two open-loop gain equation amplitudes at a gives the relationship
1 1
C2 = (52)
2
R1 a + b 2 R1b
where b is given by the rst three steps of the design procedure. For the second order PLL example
in Section 2.6.2, R1 = 806 and C1 = 470pF. With a specied phase margin of 45 , the third order
21
100 50
-40dB/decade Nmax
-40dB/decade
50 Nmin Nmin
Nmax
dB
-40dB/decade
dB
0 0
-50
a = 1/t1 b = 1/t2 a = 1/t1 b = 1/t2
-100 -50
4 6 8 4 6 8
10 10 10 10 10 10
(a) (c)
-100 0
-20 noise
-120
degrees
reduction Nmax
dB
-140 -40 region
ym = 55
o
-60 Nmin
-160
-180 -80 40dB/decade
4 6 8 4 6 8
10 10 10 10 10 10
(b) (d)
Figure 10: Bode plots for a third order PLL. The open-loop gain and phase (Tol (j2f )) are shown in
(a) and (b), (c) shows the closed-loop gain (Tcl (j2f )), and (d) shows the error gain (Te (j2f )).
Comparing the plots to the second order PLL in Fig. 8 shows that the closed-loop response now has
a -40dB/decade roll-o at high frequencies for reference spur attenuation. However, (d) shows that
the noise suppression characteristics are no dierent than a second order loop (see the text for more
details).
design procedure and (52) give C2 = 51pF. The resulting phase margin is 48 at N = 64 and 55 at
N = 32.
The Bode plots in Fig. 10 and the root-locus plot in Fig. 11 were generated using the parameters
used to generate the second order Bode and root-locus plots in Figs. 8 and 9. Following the design
procedure for the third order PLL, for a phase margin of m = 55 and a 10-percent 3dB bandwidth
relative to the reference frequency, gave R1 = 1.68k, C1 = 187pF, and C2 = 21pF (calculated
values). The actual phase margin at N = 32 and 64 was 53.4 . Figure 9 shows the root-locus plot
for the dierent feedback counter settings, i.e., it shows a plot of the zero and the three poles in
N K(s + a)
Tcl (s) = (53)
s2 (s + a) + K(s + a)
where the zero is at s = a (marked by a blue circle), the open-loop pole b is marked by a black cross,
and the three closed-loop poles are marked by small black triangles, with their associated feedback
counter setting nearby. The two closed-loop poles on the left-most side of the gure approach an
asymptote given by s = (a b)/2 forK (N 0). The closed-loop poles breakaway from
the real axis at s = 0, (3a + b)/4 ( 9a2 10ab + b2 )/4. The colored dashed lines are the three
solutions to the cubic characteristic equation for varying K (solved using Maple [24]). For more
details on the construction of root-locus plots, see references [18] and [5].
In the third order PLL design procedure, if the phase margin is increased, then a and b move
further apart, and the system response is damped. If the phase margin is reduced, then the closed-
loop poles in the root-locus move close to s = 0 (phase at the 0dB intercept frequency in the
open-loop Bode plot moves closer to -180) and the system is marginally stable. The operational
amplier used in the active lter will likely introduce further high-frequency poles which will shift
22
jw (Mrad/s)
15
32
10
40
5
64 48 40 32
0
-5
48 64
40 -10
32
-15
-40 -35 -30 -25 -20 -15 -10 -5 0 s (Mrad/s)
Figure 11: Root-locus plot of the SY89421V congured as a third order, type II PLL with a specied
phase margin of 55 and a 3dB bandwidth that is 10-percent of the reference frequency. The feedback
counter can take on the values N = 32, 40, 48, and 64. The three closed-loop poles for each of these
counter settings are marked by small triangles (the triangles for N = 48 and 64 overlap on the real
axis).
any marginally stable root-locus plot into the right-hand side of s = 0 resulting in an unstable
system.
Several other lter topologies can be found in the literature. Other third order PLL lter topolo-
gies can be found in [3, 8, 9, 21]. In wireless applications, it is common to add additional RC poles
above the pole of the second order lter to reduce the reference spurs further still. Forth order
PLLs are analyzed in [1, 11, 19, 22]. Given that these poles have to be at least as high, if not higher,
than the high-frequency pole of the second order lter, in a system with a MHz reference frequency,
the component values required to realize a higher order lter are likely to be too small. Wireless
applications have reference frequencies in the kHz range, so the components tend to be realizable.
Another wireless application temporarily switches between two dierent lters to improve the ac-
quisition time of the PLL, the rst lter has a wide bandwidth for fast acquisition and then once
locked, the lter bandwidth is reduced for lower noise performance [4].
3 Synergy PLL Analysis

This section documents an analysis of the SY89429A programmable frequency synthesizer [15] and
the SY89421V high performance phase-locked loop [12] integrated circuits. Synergy application
notes AN-06 and AN-07 [13, 14] contain application details for the SY89429A.
3.1 Synergy PLL overview

The Synergy SY89429A and SY89421V PLL-based clock generator and frequency synthesizer chips
are based on the block diagrams shown in Fig. 12(a) and (b). The basic dierence between the two
devices is the divide-by-8 reference counter and programmable post-scaling counter on the SY89429A
and the dierence between feedback counter programming options. (Measurements of the internal
VCO range show the VCOs in the devices to be similar and Synergy indicated that the phase
detectors are identical.)
23
fin Reference fref Phase/Frequency Loop

Counter Detector and Charge Filter
1/8 Pump
VCO
400-800MHz
Post-scaling fout
Feedback Counter
Counter
1/M
1/N
(a)
fin Phase/Frequency Loop VCO Hfout

Detector and Charge Filter 480-1120MHz
Pump
Feedback
Counter
1/N
Optional External fout
Feedback Counter
Feedback Counter
1/P
1/M
(b)
Figure 12: Block diagrams of the Synergy PLLs. (a) SY89429A and (b) SY89421V.
The SY89429A can be programmed for the output frequencies
fin M
fout = , (54)
8 N
where, as shown in Fig. 12(a), the reference counter is xed to divide by 8, N is the programmable
post scaler, and M is the feedback counter value. The feedback counter value must be chosen such
that the VCO remains inside its operational range.
Similarly, the SY89421V can be programmed for the output frequencies
fout = fin M N P, (55)
where N and P are counters in the feedback path internal to the device and M is an optional
external counter. The use of multiple feedback counters allows the user to generate multiple output
frequencies.
Equations (54) and (55) express the PLL loop gain multiplied by the reference frequency fref ,
where fref = fin /8 for the SY89429A and fref = fin for the SY89421V. These expressions represent
the loop in a locked state, but do not indicate stability of the system or acquisition characteristics
of the loop. To obtain these details, it is necessary to perform a loop analysis.
24
3.2 PLL loop analysis

To analyze the Synergy PLLs we require:
The phase detector sensitivity Kd
The loop lter conguration Z(s)
The active lter amplier DC gain and unity gain bandwidth
The VCO gain Kv
The programmable counter range Kn
3.2.1 Phase detector gain measurement

Synergy indicated that the phase detector output pulses have a magnitude of 120A, i.e., Kd =
120/(2)A/rad. There are two ways that this value could be conrmed. Both methods require an
external frequency reference that is split into two separate paths with a delay element in one path.
These two signals would be connected to the reference and feedback pins on the phase detector. If
only a xed delay is available, then the phase detector output should be pulses of current with a
constant mark-space ratio. If a load resistor of say 5k is placed on the output of the phase detector,
then the voltage waveform generated over the resistor should have a magnitude of 5k120 = 0.6V.
If an adjustable delay is available, then a passive low-pass lter (one with nite DC gain, eg. a
simple RC lter; for a current source, R is in parallel with C) can be placed on the output of the
phase detector (making sure the feedback loop on the Synergy active lter is broken) and the output
voltage can be measured for phase delays over the range 0 to 2 (or more). The slope of the measured
output voltage versus phase dierence curve can then be related to the phase detector gain. This
last test would also show the linearity of the phase detector. Neither of these tests were performed,
so Synergys quoted value is used in the following analysis.
3.2.2 Recommended loop filter analysis

The data sheet for the SY89421V [12] contains a recommended rst order loop lter (second order,
type II PLL). The loop lter values from the data sheet are R1 = 560 and C1 = 1.0F. Synergy
indicated that Kd = 120/(2) A and the next section measures Kv = 2500MHz/V. Assuming
a reference frequency of 30MHz, the feedback counters can take on the values N P = 16 to 32,
solving (27) and (28) at N = 16 gives n = 137krad/s and = 38 and at N = 32 n = 97krad/s
and = 27. Using (31), the 3dB bandwidth of the PLL is 6-percent of the reference frequency
at N = 16 and 3-percent at N = 32. The closed loop PLL bandwidth for the recommended lter
components is too narrow. The VCO is the dominant noise source in the SY89421V PLL, so the
loop bandwidth should be around 10 to 12-percent of the reference frequency. A wide bandwidth is
necessary to attenuate the close-in VCO noise out to the highest possible frequency (any wider than
12-percent and the continuous-time approximation begins to break down). The following sections
show that the SY89421V needs to have a clamp diode on the VCO control line for it to operate
reliably. The addition of this diode causes an increase in the output noise, and so it is necessary to
use a 2nd order loop lter to achieve acceptable performance.
The SY89429A recommended loop components for a second order lter (3rd order, type II PLL)
are found on p4-31 of [14] or p4-43 of [13]. The gure caption in both of these application notes
incorrectly refers to these components as Recommended Passive Filter Circuit. If these components
are actually in the feedback path of an operational amplier, then they should be referred to as the
Recommended Feedback Components in the Active Filter. It is not clear whether the Synergy
PLLs contain an amplier, or simply bias the voltage seen across a passive loop lter.
25
*** To add: plots showing the recommended lter for SY89429A, (80-degree margin, 1-2 percent
loop BW).
*** MC12430 waveforms (poor phase noise as well).
3.2.3 Amplifier characteristics

The DC gain and unity gain bandwidth specify the main characteristics of an amplier with a single
pole roll-o. This information would be sucient to determine the static phase error and maximum
VCO phase noise attenuation due to the nite DC gain of the active lter, however, it is not enough
information to determine stability. Any data sheet for a PLL with a built in amplier (typically
an op-amp) should indicate the op-amp open-loop transfer function, since any high frequency poles
close to the 0dB crossing of the PLL open-loop gain will aect stability (by decreasing the phase
margin).
It is not clear whether Synergys PLLs use an active lter or passive lter. Once this feature has
been determined, this section will be updated.
3.2.4 VCO gain measurement

Synergy indicated that the VCO in both the SY89429A and SY89421V is non-linear with a gain
ranging from Kv = 200MHz/V to 2000MHz/V. The VCO gain can be measured in a number of ways.
The rst method assumes that the VCO is isolated from the PLL. In this case, a voltage source
can be used to generate vVCO while a frequency counter, or a spectrum analyzer, or an oscilloscope
can be used to measure the output frequency. In the second method, the PLL is in a locked state,
dierent feedback counter settings are programmed (giving dierent output frequencies) and the
voltage on the VCO control voltage pin is measured. The control pin voltage needs to be measured
using a high-impedance probe like the FET probe on an oscilloscope (when a voltmeter was used to
measure the voltage on the Synergy VCO control pins, it overly distorted the output waveform, or
caused the PLL to enter an unlocked error state at 1.39GHz). The third method involves leaving
the PLL locked with a xed feedback counter and then the output frequency is swept by sweeping
the reference frequency. Again, the control voltage on the VCO pin is measured using a FET probe.
Figure 13 shows the VCO transfer function for the SY89421V. These measurement sets were
obtained after optimizing the loop phase jitter. The swept measurements were made using a tunable
reference frequency and a spectrum analyzer, while the programmed measurements were made using
a 16MHz crystal reference (there was also an external divide-by-4 counter, so this gave possible
output options of 512MHz, 640MHz, 768MHz, and 1024MHz). Fig. 13 also shows the loop gain
measured after the addition of a clamping diode. Section 3.3.2 describes the reason for requiring
this clamping diode on the SY89421V.
The measured VCO gain of 2500MHz/V is fairly linear over the recommended operating range,
however, it does exceed the 200MHz/V to 2000MHz/V VCO gain specied by Synergys engineers
(the VCO gain is not specied in the data sheet, even though it should be).
To measure the VCO gain, or raw VCO spectrum, the loop has to be broken. Because the
SY89421V is a monolithic device, it is not possible to drive a voltage onto the VCO control pin, as
the amplier used in the active lter is already driving that pin. Figure 14 shows two setups that
allow a voltage to be driven onto the control pin of the VCO with the PLL unlocked. Figure 14(a)
short circuits the control pin (F1) and the reference pin (F2). This turns the amplier into a voltage
follower and so the control voltage becomes equal the bias voltage. The output of the VCO at the
bias voltage is 530MHz. Figure 14(b) shows a possible method for applying a variable voltage to
the control pin. These setups assume that the inputs Rin and Fin are missing, so that the phase
detector output is tristated. Given this assumption, the voltage at the control pin of the VCO is

R2 R2
vVCO = vbias 1 + vin . (56)
R1 R1
26
1400 1400
ECL Swept ECL Swept
ECL Programmed ECL Programmed
1200 ECL Failure 1200 ECL Failure
LVPECL Swept LVPECL Swept
LVPECL Programmed LVPECL Programmed
LVPECL Failure LVPECL Failure
1000 1000
LVPECL Clamped
HFout (MHz)
HFout (MHz)
VCO Gain = 2500MHz/V
800 800
600 600
400 400
200 200
2.5 2 1.5 1 0.5 0 1 0.5 0 0.5
Pin 5 Vcc (V) Error voltage (Pin 5 Pin 6) (V)
(a) (b)
Figure 13: The SY89421V VCO gain measured from negative ECL and LVPECL congured devices.
(a) Shows the VCO control voltage from pin 5 of the device relative to VCC , while (b) shows the
VCO control voltage relative to vbias , the voltage on pin 6 of the device. The VCO gain over the
specied operating range of 480MHz to 1120MHz is 2500MHz/V. The bias voltage on pin 6 depends
on the supply voltage used (about -900mV for ECL and -800mV relative to Vcc for LVPECL).
If R1 = R2 = R,
vVCO = 2vbias vin . (57)
Choosing an initial input voltage of vin = vbias yields vVCO = vbias as was the case for a short circuit.
Tuning the input voltage above and below this point should sweep the VCO output frequency. This
test was performed, however, for some reason the voltage at F2 also changed. If the amplier in the
SY89421V is an operational-amplier, then F2 should be held at the same voltage as the positive
terminal of the op-amp, i.e., held constant at vbias . Since the data sheet has no details on the
amplier, Synergy will have to be consulted as to the reason for this behavior.
The spectrum of the VCO in the free running state is shown in Figure 15. This gure when
compared to the PLL output spectra shows that the PLL suppresses 40dB of VCO phase noise
around the output frequency.
3.3 Optimization for minimum phase noise (jitter)

In the tests that follow, either a 16MHz crystal oscillator, or a tunable reference source were used.
The tunable reference was not very stable, so it was only used during measurement of the VCO gain
function. Figure 16 show the spectrum of the crystal reference and the spectrum of the output of
the delay chip used in our design. The delay chip is an Analog Devices AD9501. The spectrum of
the delay chip output shows that it does not introduce appreciable amount of jitter.
3.3.1 First order loop filter optimization for the SY89421V

To determine the optimal values for the loop lter components, and to gain an understanding of
the eects of narrow and wide loop bandwidths and dierent damping factors, several dierent loop
lter options were tested. Table 3 shows nine dierent solutions for the loop lter components using
27
Vin R1 R2
F2 F1 F2 F1
Rin Rin
PFD - HFout PFD - HFout
VCO VCO
+ +
vbias vbias
P N P N
SY89421V SY89421V
Fin Fout Fin Fout

(a) (b)
Figure 14: The SY89421V congured to measure the free running spectrum and the VCO gain.
(a) short circuiting F1 and F2 causes the VCO to output 535MHz. (b) adjusting the input voltage
about the bias voltage should change the VCO control voltage about the bias voltage (control pin
S4 = LOW so that the internal VCO is used).
the design procedure from Section 2.6.1. Of the nine dierent options, ve were tested. The values
shown in the table represent the closest values available for the tests, hence, the design goal and
the calculated parameters are slightly dierent. The results of the ve tests are shown in Figures 17
through 26. Table 3 also summarizes the results in these gures.
The most important observation gained from the table and gures, is that the jitter in the time-
domain waveform changed very little between all of the tests. Even though the spectrum analyzer
shows quite dierent spectra for each conguration, the total integrated power within the noise
bandwidth must have remained fairly constant (since jitter in the time domain is proportional to
the total integrated power in the frequency domain).
On the basis of these observations, the choice of optimal components for the rst order lter
in the SY89421V congured as a second order PLL would appear to be fairly arbitrary. A good
recommendation, based on the recommendations in the references at the rear of this paper would
be to choose a loop bandwidth that is one-tenth of the reference frequency, while the choice of a
damping factor of somewhere between 0.707 to 50 would yield similar results, i.e., with the SY89421V
congured as a second order PLL, once the loop is stable then jitter can not be improved by changing
the damping factor. Unfortunately, during testing of the SY89421V it was found that it was necessary
to add a clamp diode to the loop lter. The noise degradation introduced by this diode necessitates
the use of a second order lter. This analysis is performed in Section 3.3.2.
Figures 27 through 30 show the HFout and Fout waveforms and spectra from a LVPECL con-
gured SY89421V with a damping factor of 50 and a 10-percent loop bandwidth. The 1024MHz
output and 128MHz outputs from the SY89421V are to be used as the clocks for a 1024MHz clock
frequency digitizer (SY89421V in ECL mode) and 128MHz clock frequency FPGAs (SY89421V in
LVPECL mode) respectively.
28
Table 3: Summary of the lter component values for the SY89421V rst order loop (second order
PLL) and the measured results from Figs. 17 through 26. The four entries with calculated values of
R1 and C1 only were not tested.
Parameter (design goal)

(design goal) 5% 10% 20%
0.707 R1 740 1.5k 3.0k

C1 790pF 220pF 50pF
calc 0.76
calc 0.1
meas 0.1
Sidelobe level -20.7dB
Noise@100kHz -88.0dBc/Hz
Jitter (pk-pk) 112ps
Jitter (RMS) 33ps
10 R1 1.1k 2.2k 4.3k

C1 75nF 0.02F 4.7nF
calc 10.7
calc 0.1
meas 0.15
Sidelobe level -19.3dB
Noise@100kHz -85.3dBc/Hz
Jitter (pk-pk) 108ps
Jitter (RMS) 27ps
50 R1 1k 2.2k 4.7k
C1 2F 0.47F 0.1F
calc 48.4 52.0 50.9
calc 0.05 0.1 0.22
meas 0.06 0.15 0.28
Sidelobe level -22.7dB -19.3dB -16.8dB
Noise@100kHz -76.3dBc/Hz -84.0dBc/Hz -86.2dBc/Hz
Jitter (pk-pk) 120ps 112ps 112ps
Jitter (RMS) 25ps 24ps 31ps
29
(a) (b)
(c) (d)
Figure 15: VCO phase noise improvement due to phase locking. The free running VCO is shown in
(a), (b), while (c) and (d) show the locked spectra at 512MHz (16MHz reference). The locked phase
noise at 50MHz span is dominated by the reference spurs and the VCO noise. The action of the
PLL to clean up a VCO with poor phase noise is clearly demonstrated in (b) and (d). (Both PLLs
were congured in ECL mode).
30
(a) (b)
Figure 16: Spectra for (a) the 16MHz crystal reference, showing the noise at 100kHz to be
118.3dBc/Hz and (b) the output of the digital delay (Analog Devices AD9501) showing the noise
at 100kHz to be 110.8dBc/Hz.
31
(a)
(b)
Figure 17: Jitter in the time domain for design goals of = 0.707 and a 10-percent 3dB bandwidth
(SY89421V in ECL mode). (a) Tektronix TDS820 screen shot (1s persistence display) showing peak-
to-peak jitter of 112ps, and (b) a Le Croy LC584AXL screen shot showing the RMS distribution of
the jitter to be 33ps (calculated from an innite persistence data set). The jitter in the 1024MHz
waveform is measured relative to the 16MHz reference input (the reference is used as the oscilloscope
trigger).
(a) (b) (c)
Figure 18: Spectra for design goals of = 0.707 and a 10-percent 3dB bandwidth (SY89421V in
ECL mode). (a) 50MHz span showing reference spurs at 20.7dB from the main peak, (b) 8MHz
span showing the actual 3dB bandwidth of the PLL to be 1.6MHz (10-percent of the reference
frequency) (c) 400kHz span showing the phase noise at 100kHz oset from the output frequency to
be 58.0dB10 log10 (RBW) = 88.0dBc/Hz. The origin of the spurs at 30kHz from the carrier is
not clear.
32
(a)
(b)
Figure 19: Jitter in the time domain for design goals of = 10 and a 10-percent 3dB bandwidth
trigger).
(a) (b) (c)
Figure 20: Spectra for design goals of = 10 and a 10-percent 3dB bandwidth (SY89421V in
be 55.3dB10 log10 (RBW) = 85.3dBc/Hz.
33
(a)
(b)
trigger).
(a) (b) (c)
34
(a)
(b)
trigger).
(a) (b) (c)
35
(a)
(b)
trigger).
(a) (b) (c)
span showing the actual 3dB bandwidth of the PLL to be 880kHz (6-percent of the reference fre-
quency) (c) 400kHz span showing the phase noise at 100kHz oset from the output frequency to be
46.3dB10 log10 (RBW) = 76.3dBc/Hz.
36
(a)
(b)
(SY89421V in LVPECL mode). (a) Tektronix TDS820 screen shot (1s persistence display) showing
peak-to-peak jitter of 108ps, and (b) a Le Croy LC584AXL screen shot showing the RMS distribution
of the jitter to be 26ps (calculated from an innite persistence data set). The jitter in the 1024MHz
trigger).
(a) (b) (c)
LVPECL mode). (a) 50MHz span showing reference spurs at 24.3dB from the main peak, (b)
8MHz span showing the actual 3dB bandwidth of the PLL to be 2.4MHz (15-percent of the reference
37
(a)
(b)
Figure 29: Jitter in 128MHz LVPECL clock signal (Fout pin on the SY89421V). (a) Tektronix
TDS820 screen shot (1s persistence display) and (b) a Le Croy LC584AXL screen shot showing the
distribution of the jitter (calculated from an innite persistence data set). Both screen shots show
that the 128MHz waveform has about 50ps RMS (2.3 ) jitter relative to the 16MHz reference input
(the reference is used as the oscilloscope trigger).
(a) (b) (c)
Figure 30: Spectra for the 128MHz LVPECL clock. (a) 50MHz span showing reference spurs
at 42.3dB from the main peak, (b) 8MHz span showing the 3dB bandwidth to be 2.4MHz,
(c) 400kHz span showing the phase noise at 100kHz oset from the output frequency to be
72.3dB10 log10 (RBW) = 102.3dBc/Hz.
38
(a) (b) (c)
Figure 31: Spectra from the PLL in low-voltage positive ECL (LVPECL) mode with a rst order
lter (2nd order PLL). (a) Soft failure at 270MHz. The PLL becomes unlocked, but if the reference
frequency is increased, the PLL locks. (b) 750MHz locked waveform. (c) Hard failure. The output
waveform jumps from a locked 1.22GHz to an unlocked 1.39GHz. Reducing the reference frequency
does not bring the PLL back into lock.
3.3.2 Clamping the SY89421V VCO control voltage

Figure 31 shows three spectra from the SY89421V congured with a rst order lter. For these
tests, the PLL was congured with a feedback count of divide-by-64 (using an external divide-by-4
counter) and a tunable reference frequency was used. Figure 31(b) is representative of the spectra
seen while measuring the VCO gain curves in Fig. 13. Figure 31(a) shows the low frequency failure
mode of the VCO. If the requested PLL output frequency is too low (or if the input reference is
removed), then the VCO unlocks and free runs at 270MHz. If the PLL is then programmed for a
frequency within its VCO range, or the reference input frequency is increased such that the PLL
enters the VCO range, then the PLL locks. Figure 31(c) shows the other extreme. If the requested
PLL output exceeds the VCO range, then the PLL unlocks and free runs at 1.39GHz. If the PLL
is reprogrammed to a frequency within the VCO range, then the PLL does not lock. The output
remains unlocked at 1.39GHz1 . To get the PLL to lock, it is necessary to short the VCO control
voltage and the bias voltage at the input to the lter (pins 5 and 6 on the chip). This action
momentarily brings the VCO into the center of its range and from there it can lock to the requested
frequency. Clearly this is an undesirable feature in a system, as Murphys Law will cause this state
to occur more often than not. In fact, this state was often entered on power-up of the deviceseven
if the control pins were pulled-up or down to a control setting that should have yielded a valid
output frequency. This failure mode was also induced by probing the VCO control voltage pin with
a voltmeter.
The VCO transfer function in Fig. 13 has a maximum control voltage about 300mV above the
VCO bias point. To avoid entering the error state, a Schottky diode with a threshold voltage of
300mV was placed in the feedback path of the VCO. The diode turns on when the control voltage gets
to 300mV above the bias voltage and prevents the VCO getting stuck at 1.39GHz. Unfortunately,
the addition of the clamp diode substantially increased the sidelobe level in the output spectra.
Figure 32(a) and (b) show the output spectra for a 1024MHz output with a 16MHz crystal reference.
The sidelobes in Figure 32(a) are at -24dB, whereas the addition of the clamp diode causes these
spurs to jump 15dB to -9dB. A 1k resistor was placed in series with the diode to see if that helped
1 Programming the feedback counter to zero, i.e., requesting a frequency o the bottom end of the VCO, causes
the PLL to unlock at the soft failure end of the VCO range. From there the PLL can be reprogrammed to within the
VCO range
39
the spur levels, but it made no dierence (the resistor was left in the circuit as it helps keep the
clamp voltage closer to 300mV). To reduce the sidelobe levels, it was necessary to use a second order
lter. The second order lter was implemented by adding a 22pF capacitor in parallel with the RC
(2.2k/0.47F) of the original lter (the new capacitor could have equivalently been placed across
the original R only). The open-loop transfer of the third order PLL is shown in Figure 10. The
new capacitor must generate a new pole slightly higher than the 3dB bandwidth of the second order
PLL. If the pole is placed too far away (i.e., the capacitor is too small), then very little sidelobe
attenuation will be obtained. However, the pole can not be too close to the 0dB cross-over point,
as the phase margin is impacted and the loop will be unstable. Figure 32(c) and (d) show spectra
for the third order PLL. Figure 32(c) has very low sidelobe at -35dB, however, the addition of the
clamp diode causes these sidelobes to jump 16dB to -19dB (slightly worse than the second order
PLL with no clamp).
Figure 33 shows spectra similar to those in Figure 31, but this time with a second order lter
and the clamp in place. The clamp diode introduces a lot more spikes in the spectra, while the
second order lter lowers the 16MHz (and multiples) reference spurs around the 750MHz spectra.
The clamp does however prevent the VCO from getting trapped at 1.39GHz. Now, when the VCO
gets to above 1150MHz, the PLL unlocks and outputs a 1.2GHz waveform. If the PLL requested
output is reduced to within the VCO range, then the PLL locks. Figure 34 shows a block diagram
of the SY89421V with the conguration of the second order lter and clamping diode. The VCO
gain in Fig. 13 shows that the addition of the clamp circuit does not aect the measured VCO gain
relative to the gain without the clamp. The 1k resistor in series with the clamp diode has about
a 50mV drop across it when the diode is clamping the VCO voltage. This indicates about 50A of
current through the clamping diode, far below the rated maximum current of the diode.
40
(a) (b)
(c) (d)
Figure 32: The eect of the clamping diode on the PLL spectrum. (a) 2nd order PLL response with-
out the clamp: highest sidelobe at 24.2dB, 2.3MHz 3dB phase noise bandwidth, and 84.0dBc/Hz
phase noise at 100kHz., (b) 2nd order PLL response with the clamp: highest sidelobe at 9.3dB,
1.6MHz 3dB phase noise bandwidth, and 82.0dBc/Hz phase noise at 100kHz. (c) 3nd order PLL
response without the clamp: highest sidelobe at 35.2dB, 2.5MHz 3dB phase noise bandwidth (with
1-2dB of peaking), and 83.2dBc/Hz phase noise at 100kHz. (d) 3nd order PLL response with the
clamp: highest sidelobe at 19.3dB, 2.2MHz 3dB phase noise bandwidth, and 80.2dBc/Hz phase
noise at 100kHz. All time domain waveforms had about 110ps pk-pk or 30ps RMS jitter. The
addition of the diode clamp causes a signicant increase in the sidelobe level. It is necessary to use
at least a second order lter (3rd order PLL) to obtain acceptable sidelobe levels. The sidelobes
at 128MHz either side of the 1024MHz output are higher, as the Fout pin is programmed to be
128MHz.
41
(a) (b) (c)
Figure 33: Spectra from the PLL in low-voltage positive ECL (LVPECL) mode with a second order
lter (3rd order PLL) and the clamping circuit in place. (a) Soft failure at 270MHz. The PLL
becomes unlocked, but if the reference frequency is increased, the PLL locks. (b) 750MHz locked
waveform. (c) Soft failure. The output waveform becomes unlocked at about 1150MHz, however
this time, reducing reference frequency brings the PLL back into lock.
D1 R2
R1 C1
C2
F2 F1
Rin
PFD - HFout
VCO
+
vbias
P N
SY89421V
Fin Fout
Figure 34: The SY89421V with a 2nd order lter and clamping diode. The clamping diode is either a
MACOM/AMP MA4CS102A, or an HP HSMS-2820. Both of these diodes have a threshold voltage
of 300mV. Any control voltages larger than 300mV are clamped, stopping the VCO from getting
stuck at 1.39GHz.
42
The spectra in this section were from a PLL congured in LVPECL mode. Similar clamping
tests were run on an ECL congured device. The sidelobe levels observed were higher than in the
LVPECL circuit. Since the layout of the clamp circuits was via rework wires, this could be the
cause. Testing of the nal PCB will conrm whether the dierent congurations generate dierent
sidelobe levels. The clamping diodes used were from MA/COM (Amp), replacement parts from HP
yielded .... similar/better/worse ... results???
3.3.3 Loop response to phase and frequency steps

Since many application notes show the PLLs response to phase and frequency steps, Fig. ?? includes
some response plots for completeness.
The loop response to a phase or frequency step can be measured by probing the control voltage
pin on the VCO.
Test 1: (From LeCroy app. notes) Use the 1kHz square wavefrom the scope, FM modulate a
CW reference, use a comparator to turn the CW into a TTL reference wavefrom, then use it as the
reference. The output will be one of two frequencies.
Test 2: Have a loop program the feedback counter repetitively between two dierent values,
trigger the scope o the resulting square wave.
Test 3: Program jumps into the AD9501. Its response may be too slow to see anything though
43
4 Concluding Remarks
This paper has covered the theory and implementation of PLLs. It has also exposed errors in
the recommended lter components and limitations in the documented implementation details for
Synergys SY89429A and SY89421V PLLs. Synergy recommended the use of the Schottky diode
to limit the VCO control voltage, however, it is unlikely that they anticipated the poor sidelobe
response that this clamp diode causes. The sidelobes were lowered by increasing the order of the
loop lter. Whether the sidelobe levels can be considered acceptable is the subject of further testing.
Insucient information in manufacturers data sheets is commonplace. The safest way to ensure
that a complex circuit element such as a PLL can be successfully included in a design is to prototype
the circuit rst. Synergys devices are adequate for our application, it just took a little massaging
to get the devices to behave.
44
References
[1] D. Banerjee. PLL performance simulation and design. National Semiconductor Design Article,
1998. (www.national.com).
[2] C. L. Barker. Introduction to single chip microwave PLLs. National Semiconductor Application
Note AN-885, 1993. (www.national.com).
[3] R. E. Best. Phase-Locked Loops. McGraw-Hill, 3rd edition, 1997.
[4] D. Byrd, C. David, and W. O. Keese. A fast locking scheme for PLL frequency synthesizers.
National Semiconductor Application Note AN-1000, 1995. (www.national.com).
[5] J. J. DiStephano III, A. R. Stubberud, and I. J. Williams. Feedback and Control Systems
(Shaums Outline Series). McGraw-Hill, 2nd edition, 1990.
[6] S. Franco. Design with Operational Amplifiers and Analog Integrated Circuits. McGraw Hill,
2nd edition, 1998.
[7] W. S. Friauf. Feedback Loop Stability Analysis. McGraw-Hill, 1998.
[8] F. M. Gardner. Phaselock Techniques. Wiley, New York, 2nd edition, 1979.
[9] F. M. Gardner. Charge-pump phase-locked loops. IEEE Trans. Commun., 28(11):18491858,

November 1980.
[10] Bar-Giora Goldberg. Analog and digital fractional-n PLL frequency synthesis: A survey and
update. Applied Microwave and Wireless, 11(6):3242, June 1999.
[11] W. O. Keese. An analysis and performance evaluation of a passive lter design technique for
charge-pump phased-locked loops. National Semiconductor Application Note AN-1001, 1996.
(www.national.com).
[12] Micrel-Synergy Semiconductor. SY89421V High-performance phase-locked loop. Data Sheet,

1998. (www.synergysemi.com).
[13] Micrel-Synergy Semiconductor. SY89429/30V Frequency synthesis. Application Note AN-07,

[14] Micrel-Synergy Semiconductor. SY89429A Frequency synthesis. Application Note AN-06, 1998.
(www.synergysemi.com).
[15] Micrel-Synergy Semiconductor. SY89429A Programmable frequency sythesizer. Data Sheet,

[16] Motorola. The technique of direct programming by using a two-modulus prescaler. Application
Note AN827, 1995. (www.mot-sps.com).
[17] Motorola. Hipercomm: high performance frequency control products. Data Book BR1334/D
Rev. 4, 1997. (www.mot-sps.com).
[18] G. Nash. Phase-locked loop design fundamentals. Application Note AN535, 1993. (www.mot-
sps.com).
[19] National Semiconductor. LMX2315/20/25 PLLatinum frequency synthesizer for RF personal

communications. Data Sheet, 1996. (www.national.com).
45
[20] National Semiconductor. Noise oor measurement of PLL frequency synthesizers. Application
Note AN-1052, 1996. (www.national.com).
[21] A. B. Przedpelski. Phase-locked loop design articles. Motorola Article Reprint AR254, 1978.
(www.mot-sps.com).
[22] J. Sun, K. Tiong, and J. Liu. Design and implementation of an L-band PLL frequency synthe-
sizer. Microwave Journal, 42(4):90102, April 1999.
[23] C. Vaidya. Phase-locked loop based clock generators. National Semiconductor Application Note
AN-1006, 1995. (www.national.com).
[24] Waterloo Maple, Inc. Maple V. Release 5.1, 1998. (www.waterloomaple.com).
46

PLL Theory

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PLL Theory

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Digital Phase-Locked Loop (PLL) Based Frequency

Synthesizers: Theory and Analysis

2 A review of PLL theory 3

3 Synergy PLL Analysis 23

Figure 1: The basic phase-locked loop (PLL).

2 A review of PLL theory

2.1 PLL components

2.1.2 Phase detectors (and charge pumps)

2.1.3 Loop filters

2.1.4 Voltage controlled oscillators

o (t) = int + Kv vVCO (t) (2)

o (t) = c + Kv ve (t). (3)

In FM applications, it is usually required that the V -F characteristic of the VCO be highly

2.1.5 Feedback counters

2.2 PLL loop analysis

id (s) = Kd e (s) (4)

[A/rad] [V/A] [rad/V]

Figure 3: The Laplace form of the basic phase-locked loop (PLL).

G(s) = Kd Z(s) Ko (s)

The open loop gain of the PLL is

Tol (s) = G(s)H(s)

o (t) = N i (t) (11)

o (t) = N i (t). (12)

e (s) i (s) f (s)

lim e (t) = lim se (s)

2.3 PLL phase noise (jitter)

Figure 4: Noise sources in a PLL.

id (s) = Kd {i (s) f (s) + ni nf }

Solving these equations for the output phase gives

where the output phase noise

Phase Noise (dBc/Hz) = Carrier-to-noise (dBc) - 10 log10 (RBW (Hz))

id(t) vbias + ve(t)

2.4 PLL and loop filter order and type

2.5 Loop filter design

Table 1: Transfer functions, Z(s), for the lters shown in Fig. 5.

(a) (b) (c)

Table 2: Impedances for the passive components shown in Fig. 6.

Fig. 6 Zf (s) Time constants

2.6 PLL response analysis

noise (low signal jitter).

2.6.1 Second order PLL analysis

-100 a = 1/t1 a = 1/t1

m = tan1 (0dB 1 ). (30)

2.6.2 Second order PLL design procedure

3dB max = 2fref (32)

3. Calculate the natural frequency via

2.6.3 Third order PLL analysis

The phase margin at the 0dB intercept is then:

a = 0dB {sec(m ) tan(m )} (44)

2.6.4 Third order PLL design procedure

3dB max = 2fref (48)

-40 -35 -30 -25 -20 -15 -10 -5 0 s (Mrad/s)

3 Synergy PLL Analysis

3.1 Synergy PLL overview

fin Reference fref Phase/Frequency Loop

fin Phase/Frequency Loop VCO Hfout

The SY89429A can be programmed for the output frequencies

fout = fin M N P, (55)

3.2 PLL loop analysis

The phase detector sensitivity Kd

The loop lter conguration Z(s)

The active lter amplier DC gain and unity gain bandwidth

The VCO gain Kv