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Microelectronics Reliability 54 (2014) 9099

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Microelectronics Reliability
journal homepage: www.elsevier.com/locate/microrel

PVT variations aware low leakage INDEP approach for nanoscale CMOS
circuits
Vijay Kumar Sharma a,, Manisha Pattanaik a, Balwinder Raj b
a
Department of Information Technology, ABV-Indian Institute of Information Technology & Management, Gwalior-474015, India
b
Department of Electronics & Communication, National Institute of Technology, Jalandhar-144011, India

a r t i c l e i n f o a b s t r a c t

Article history: Increasing in device parameter variations is the critical issue in very deep sub-micron regime due to con-
Received 25 March 2013 tinue scaling of the transistor dimensions. The overall performance yield of the logic circuit is diminished
Received in revised form 18 September by raising leakage current and variability issues in scaled devices. In this article; we have proposed an
2013
approach called INDEP, based on Boolean logic calculation for the input signals of the extra inserted tran-
Accepted 18 September 2013
Available online 11 October 2013
sistors between the pull-up and pull-down network of the CMOS logic. INDEP approach is not only
reduces the leakage current but also mitigates the variability issues with minimum susceptible delay
paths. Various process, voltage and temperature (PVT) variations are analyzed at 22 nm BSIM4 bulk
CMOS PTM technology node for chain of 5-inverters using HSPICE tool. Several guidelines are provided
to design the variability aware CMOS circuits in nanoscale regime by considering the leakage current var-
iation. INDEP approach works effectively in both active as well as standby state of the circuit and keeping
the modal performance characteristics of the CMOS gate. The electrical simulation results show that our
proposed INDEP approach is less susceptible to PVT variations as compared to conventional circuit. The
Monte-Carlo simulation results conrm that average INDEP leakage current reduction is 62.31% at 20%
PVT variations under 3r Gaussian distribution for chain of 5-inverters.
2013 Elsevier Ltd. All rights reserved.

1. Introduction when device is more immune to variability. A narrow parametric


yield window contains the chips which may become useless [4].
The evolution of low power dense CMOS integrated circuit is a Technology scaling reduces the channel length by 30% per new
major outcome for modern battery operated portable devices in generated node [5]. All physical dimensions other than source/
nanoscale regime. It is a big challenge to design such portable drain junction depth in MOS device scale in proportional to chan-
applications in very deep sub-micron regime where process vari- nel length. Although numbers of parameters are there to decide the
ability limits the performance yield. Process, voltage and tempera- characteristics of the MOS device, only few of them are essential in
ture (PVT) variations may lead to signicant discrepancies because determining the major performance of the scaled device. Various
of improper manufacturing process, improper biasing and impro- analytical PVT parameters are given as follows: (i) threshold volt-
per working environmental conditions of the device [1]. PVT vari- age (VTH), (ii) channel length (L), (iii) gate oxide thickness (TOX),
ations introduce statistical uctuations in physical properties of (iv) channel width (W), (v) gate doping concentration (NGATE),
the MOS devices which result in degrading the parametric yield (vi) channel doping concentration (NCH), (vii) source drain doping
and logic characteristics of the logic gates [2]. Therefore in order concentration (NSD), (viii) power supply voltage (VDD), (ix) environ-
to continue scaling of transistor dimensions in nanometer regime, mental temperature (T). PVT parameters are not necessarily inde-
it is essential to explore variation tolerant design solutions to mit- pendent to each other [6] thus a statistical distribution has
igate variability issues. PVT variations lead the uncertainties in created over a large number of samples. ITRS 2011 reports that
power characteristics and driving capabilities of the MOS transis- low operating and standby power are increasing with variability is-
tors [3]. Leakage power of the logic gates may change along with sues in very deep sub-micron regime. Variability issue affects the
the location of variations on a die. A high variations sensitive de- logic circuit in different ways. General variation in VTH occurs be-
vice means that the parametric yield window is narrower than cause various device parameters are changing from their nominal
values [7].
In this article; a low leakage approach for reducing PVT
Corresponding author. Address: C-Block, VLSI Design Lab., Department of variations at transistor level in very deep sub-micron regime is
Information Technology, ABV-Indian Institute of Information Technology & Man-
presented. Proposed INDEP approach is based on the Boolean logic
agement, Gwalior-474015, India.
E-mail address: vijay.buland@gmail.com (V.K. Sharma).
calculations for the input signals of the INDEP transistors. Leakage

0026-2714/$ - see front matter 2013 Elsevier Ltd. All rights reserved.
http://dx.doi.org/10.1016/j.microrel.2013.09.018
V.K. Sharma et al. / Microelectronics Reliability 54 (2014) 9099 91

variation in INDEP CMOS logic gate depends on the relative posi- of two transistors, one PMOS (MP1) and other NMOS (MN1). MP1
tion of the MOS transistors in relation to power supply, output and MN1 are called INDEP transistors. MP1 is introduced between
and ground nodes. Important guidelines are explored to design ro- pull-up network and output node while MN1 is connected be-
bust CMOS logic gate in very deep sub-micron regime. tween output node and pull-down network of the CMOS circuit.
The paper is organized as follows. In Section 2, the previous The drain nodes of the INDEP transistors are connected together
works related to variability aware low power design are briey re- to form the output node. The source nodes are connected to nodes
viewed. The methodology of proposed approach is provided in Sec- N0 and N1 of pull-up and pull-down networks respectively. The
tion 3. The robustness of the proposed approach is veried in operation of MP1 and MN1 are controlled by the Boolean logics
Section 4. Finally, conclusions of this work are outlined in at the input terminals V0 and V1 respectively. The generalized sche-
Section 5. matic of approach is given in Fig. 1. The VTH of INDEP transistors
are the same as logic block transistors has. The criterion for reduc-
ing the variability issues depends on input signals, V0 and V1 of the
2. Previous work
INDEP transistors. The accurate selection of V0 and V1 directs the
variability issues in very deep sub-micron regime. Leakage current
PVT variations are increasing signicantly due to aggressive
variation conscious design depends on effective transistors
scaling of CMOS technology in sub-65 nm nodes. The circuit
arrangements in pull-up and pull-down networks of the CMOS cir-
reliability is one of the key challenges in very deep sub-micron
cuits [14]. The pattern of Boolean logic function at the output node
technology nodes. PVT variations refer to the deviations of the cir-
forms the different transistors arrangements in pull-up and
cuit parameters from their nominal values. These variations are
pull-down networks. The transistors in the pull-up and pull-down
mainly responsible for leakage current uctuation, which can vary
networks are in on-state or off-state as these are depending on the
by a large value across the die. PVT variations must be compen-
logic paths in the networks to develop the required Boolean logic
sated by using appropriate circuit technique. Body biasing of the
function at the output node. As INDEP transistors are also the
device is the most prospective idea for controlling the variability
important part of the logic paths in the networks thus these are
issues at transistor level design. Many researchers have proposed
also in on-state or off-state conditions. The off-state INDEP transis-
different PVT variations reduction techniques at transistor level
tors increase the resistive path between the pull-up and pull-down
design.
networks and hence reducing the leakage current variation in
Adaptive body bias is the circuit technique to compensate the
CMOS circuits. The number of off-state transistors in a stack limits
PVT variations. Two algorithms, process temperature adaptive
the switching behavior of the logic circuit [9]. The switching oper-
body bias (PTABB) and process adaptive body bias-temperature
ation of the logic circuit enhances by considering the proper input
adaptive body bias (PABBTABB) were proposed to give the accu-
terminal selections of V0 and V1. The fundamental idea behind our
racy/run-time trade-off [8]. Process and temperature variations
approach for reducing the variability issues is effective transistors
tolerant bias voltages were calculated by the CAD prospective.
arrangements in the path from power supply to ground. MP1 is
PTABB and PABBTABB algorithms permit the circuit to recover
connected between the N0 and output nodes such that it passes
from PVT variations. A self dynamic regulating body bias mecha-
the logic high with full output voltage swing. MN1 is connected
nism was utilized to sense the variability issues with performance
in such a way to pass the logic low completely between the output
constraints. Minimum leakage vector technique with PVT varia-
and N1 nodes. A Boolean logic function can be designed using dif-
tions aware was considered for reducing the standby leakage cur-
ferent transistors congurations in a network [15]. The electrical
rent of the combinational circuits [9]. Boolean SAT solver was
required for both standby leakage and PVT variations reduction
that suits the logic values during the mode transitions. A look up
table method was used to control the process and temperature
variations by generating of adoptively minimum VDD and optimal
device body bias voltage [10]. PVT variations were supervised inde-
pendently based on critical path replica propagation delay line to
mitigate the impact of random intra-die variations [11]. Sub-
threshold circuits are more sensitive to PVT variations because of
ultra low power constraints below the VTH of the device. VDD
reduction meets the performance timing yield of the logic circuits.
Low VTH of the MOS device improves the switching speed while
high VTH reduces the leakage current variation. Therefore, sensitiv-
ity of PVT variations can be control by assigning dual VTH to the
MOS devices. Plackett Burman-Design of Experiment sensitivity
method was used to assign low and high VTH to the MOS transistor
in which sensitivity of each transistor to delay variation was esti-
mated [12]. The energy dissipation of sub-threshold circuits was
evaluated as lowest energy value per operation. An energy efcient
clock generator was proposed to reduce the timing failures under
PVT variations [13]. Clock period was determined by the propaga-
tion delay of the critical paths.

3. INDEP approach

INput DEPendent (INDEP) is the transistor level, low leakage


variability aware circuit approach for CMOS logic circuits. INDEP
approach utilizes an INDEP block between the pull-up network
and pull-down network of the CMOS circuit. INDEP block consists Fig. 1. Generalized structure for INDEP gates.
92 V.K. Sharma et al. / Microelectronics Reliability 54 (2014) 9099

and physical properties of transistors in the networks are varying primary input combination other than all Boolean low logic
for different congurations hence variability issues are also varying signals, V1 supervises the intermediate node voltages and
with different transistors congurations in the networks. giving the full output performance by turning-on of MN1.
Transistors in pull-up and pull-down networks are in comple- MN1 is turned-off to make a large off-state transistors stack
mentary arrangement in CMOS circuit. The computation of V0 for all low logic primary inputs. Number of off-state transis-
and V1 voltage levels depend on transistors congurations in the tors in stack saves large leakage current. The off-state tran-
networks. Transistors congurations in the pull-up/pull-down net- sistor closer to ground reduces the large leakage current as
works can be characterized as series, parallel or non-seriesparallel compared to other off-state transistors. V0 for pull-up net-
arrangements. Selection of V0 and V1 voltage levels are inuenced work is connected in a manner to turned-off the MP1 for
by the relative potential of intermediate nodes with respect to VDD, all primary input combinations excluding all low logic
output and ground terminals. Many algorithms have been inputs. MP1 manages the logic function between VDD and
proposed to control the intermediate node potential. Our INDEP Out terminals. If any primary input in pull-up network is
approach identies the Boolean logic ow through the logical at Boolean high logic level then corresponding PMOS is in
paths in the networks. As leakage current is the strong function cut-off state that breaks the path between VDD and Out ter-
of applied input voltage levels [9] therefore precise selections of minals. MP1 is turned-off in this condition to diminish all
V0 and V1 are sharply cutting the leakage current variation. The kinds of power dissipations. For all low logic primary inputs,
selection priority of V0 and V1 is based on low leakage and high MP1 is turned-on to give the full output performance.
performance by preserving the VTH of the on/off-state devices. V0 (ii) For parallel network of the transistors: If the transistors in
and V1 are dealing with pull-up and pull-down transistors net- pull-down and pull-up networks are in parallel congura-
works respectively. V0 maintains the minimum variation effect in tion as shown in Fig. 2(b) and (a) respectively, then V1 is con-
pull-up network while V1 forces the pull-down network on least nected in such a way that MN1 is turned-on for all primary
variation value. INDEP approach is pertinent to both active as well input combinations excluding all low logic inputs. For any
as standby modes leakage reduction. Logic circuits are not in func- Boolean high logic input signal in pull-down network, V1
tioning situation in the standby mode. INDEP transistors must be provides the path between Out and ground terminals by
in off-state to reduce the standby leakage current by disconnecting turning-on of MN1. Off-state leakage current is mitigating
the path between the power rails. It is also helpful to hugely reduce by MN1 by formation of transistors stack for all low logic
the switching as well as short circuit dissipations. Off-state INDEP primary input combinations in pull-down network. V0 for
transistors are producing more reverse body bias during standby pull-up network is connected in a manner to turned-on
mode. Large reverse body bias causes an increment in VTH that de- the MP1 for all primary input combinations excluding all
creases standby leakage current. The following guidelines explore high logic inputs. If any primary input in pull-up network
the particulate of each transistors arrangement: is at Boolean low logic level then turning-on of MP1 creates
a path between VDD and Out terminals. Intermediate node
(i) For series network of the transistors: If the transistors in potential is handled by turning-off of MP1 for all high logic
pull-down and pull-up networks are in series conguration primary input combinations.
as shown in Fig. 2(a) and (b) respectively, then V1 is con- (iii) For non-seriesparallel network of the transistors: Several
nected in such a way that MN1 is turned-on for all primary complex gates are employed for particular application in
input combinations excluding all low logic inputs. Any low power design that explores the use of CMOS AOI and

Fig. 2. Approach illustration: (a) CMOS NAND and (b) CMOS NOR logic arrangements.
V.K. Sharma et al. / Microelectronics Reliability 54 (2014) 9099 93

CMOS OAI gates. Leakage current of these complex gates is Out = 1


minimized by considering the logic paths of the non-ser- V0 = V1 = 0
iesparallel network of the transistors. If the transistors in else
pull-up and pull-down networks are in form of non-series Out = 0
parallel conguration then selection of V0 and V1 are V0 = V1 = 1
depending on the logic paths formation between VDD and end if
output and output to ground terminals respectively. If all else
the primary input combinations are at same Boolean logic Out = 0
level then V0 and V1 are connected to any primary input sig- V0 = V1 = 1
nal. For all other primary input combinations, selection is end if
based on logic paths in networks. In the pull-up network, end
if logic path passes the Boolean high logic then V0 forced
to low logic level. V0 signal stays on high logic level if logic
path passes the Boolean low logic in pull-up network. V1
input signal hold the Boolean high logic for all primary input 4. Simulation results and discussion
combinations other than all low logic input combinations.
Identication of the off-state transistors in pull-up network This section covers the simulation study of proposed INDEP ap-
is more crucial as compared to pull-down network. proach with various PVT parameters which are susceptible to var-
iability. All experimental data were obtained at 22 nm BSIM4 bulk
Any Boolean logic function can be implemented by using uni- CMOS PTM technology node using transistors effective channel
versal gates like NAND or NOR in digital and mixed signal design. length of 9 nm, effective channel width of 34 nm, NSUB = 6  1016/
The operation of INDEP approach is presented in the form of NAND cm3 and TOX = 1.2 nm. Channel width of NMOS transistor was 2X
or NOR logic as the network topology of the CMOS gates as shown of the respective NMOS channel length and for PMOS; it was sized
in Fig. 2(a) and (b) respectively. Our circuit approach is very simple to 3X of the respective pull-down NMOS size. Electrical simulations
and effective as compared to existing approaches. The estimation were carried out through HSPICE tool with VDD of 0.7 V. HSPICE
of V0 and V1 input signals of INDEP n-input (in1, in2, in3 ,. . . , inn) generates different SPICE model les for different sets of parame-
NAND and NOR logics are given as: ters. The impact of PVT variations was evaluated through Monte-
Carlo simulation with 3r Gaussian distribution performed on
Pseudo code of INDEP NANDn logic for selection of V0 and V1 2000 samples. A chain of 5-CMOS inverters is considered for dem-
signals onstration of performance improvement in term of leakage current
Input: {in1, in2, in3, . . . , inn}: primary n-input signals, of INDEP approach. The chain of 5-CMOS inverters is shown in
c: iteration counter. Fig. 3. Each inverter consists of one PMOS and one NMOS device
Output: Out: a Boolean logic output where high logic = 1 and as pull-up and pull-down networks respectively in CMOS logic.
low logic = 0, The primary input is applied at rst inverter while output has ta-
V0, V1: INDEP transistors input signals. ken after fth inverter operates.
for c = 1 to c 6 2n The proper functional operation of the INDEP approach is
if (in1 = in2 = in3. . . = inn) then judged before any type of performance analysis. Fig. 4 shows the
if (in1 = 0) then voltage transfer characteristics of conventional and INDEP chain
Out = 1 of 5-inverters by varying input voltage from 0 to VDD. It can be ob-
V0 = V1 = 0 served that INDEP circuit has similar characteristics as conven-
else tional circuit in terms of noise margin and differential output
Out = 0 voltage gain. INDEP approach has added extra transistors in CMOS
V0 = V1 = 1 gates and these are not degrading the noise margin and output
end if gain of the logic circuit. Noise margin can be calculated by nding
else the logic levels of the voltage transfer characteristics. The steep
Out = 1 middle region of the voltage transfer characteristics maximizes
V0 = 0 the noise margin. The switching VTH of the circuit is given ideally
V1 = 1 as V TH V2DD . INDEP approach depends on the input signal identi-
end if cation based on the AND or OR logic. It does not affect the internal
end node charge of the logic circuits. The ability of charge free internal
nodes in INDEP approach enhances the robustness of the circuit
which produces perfect Boolean low logic and high logic signals.
The switching time of the approach improves the required access
time of the logic gate by moving the input from one level to
Pseudo code of INDEP NORn logic for selection of V0 and V1 another level quickly.
signals
Input: {in1, in2, in3 ,. . . , inn}: primary n-input signals,
c: iteration counter.
Output: Out: a Boolean logic output where high logic = 1 and
low logic = 0,
V0, V1: INDEP transistors input signals.
for c = 1 to c 6 2n
if (in1 = in2 = in3. . . = inn) then
if (in1 = 0) then Fig. 3. Chain of 5-CMOS inverters.
94 V.K. Sharma et al. / Microelectronics Reliability 54 (2014) 9099

Fig. 4. Voltage transfer characteristics of conventional and INDEP circuit.

Fig. 5. Transient responses of conventional and INDEP circuit.

Fig. 5 shows the comparison of transient curves of conventional levels inuence the performance characteristics of the circuit
and INDEP circuits. It can be observed from the curves that INDEP differently so low logic and high logic are assumed separately
circuit produces exact output voltage levels. Leakage reduction [9]. Fig. 6 illustrates the output voltages and leakage currents of
through INDEP approach is achieved at the cost of increased delay the conventional and INDEP circuits with varying threshold voltage
due to extra inserted INDEP transistors. The amount of increased of NMOS transistors (Vtn) when input voltage is at low logic level.
propagation delay is less in large logic circuits. It can be examined Vtn is varying from 0.4 V to 0.6 V. It can be observed that
that performance degradation due to INDEP transistors does not af- reduction in Vtn below a minimum value degrades the output
fect the functional characteristics of the logic circuit. Extra inserted performance of the logic circuit. Conventional circuit is more prone
transistors in INDEP approach add the resistance path from VDD to to degradation and take large time to settle at stable level as
ground. VLSI circuits have the trade-off between leakage power compared to INDEP circuit. Minimum Vtn required to obtain the
and delay. One performance metric is improved at the cost of deg- settled output is 0.35 V.
radation of the other metric. Therefore separate design models are Sub-threshold and gate leakage are the major leakage current
used for designing low power (low leakage) and high performance components in nanometer regime [10]. Sub-threshold leakage cur-
(low delay) circuits. INDEP approach is based on low power design rent is the off-state current of the MOS device when VDD is applied
model. The sizing of the inserted transistors directs the resistance across it. Gate leakage is the on-state current when nearly low
path value that can change the leakage current variation. INDEP logic level is applied across the device. Increment in Vtn value
transistors are sized such that delay is equal to its conventional diminishes large leakage current. Larger value of Vtn is avoided
circuit to reduce the propagation delay of the INDEP circuit. A because potential nanoscale circuit drives with high performance.
settlement between leakage current and delay is managed by the When input voltage is at high logic level then the output responses
product of leakage power and delay (PDP). INDEP approach is of conventional and INDEP circuits are shown in Fig. 7. It can be
improving the PDP due to large leakage reduction. A particular viewed from the Fig. 7 that Vtn for the settled output is near about
application where lower PDP is targeted as gure of merit, im- 0 V. We have examined that the low logic input signal causes the
proves the reliability of the circuit by reducing the energy con- large leakage current as compared to high logic input signal due
sumption per clock. to off-state NMOS transistors are more leaky as compared to
VTH is the key parameter for controlling the variability issues in on-state NMOS transistors.
CMOS gates at transistor level design. PVT variations deviate device Figs. 8 and 9 illustrate the comparison of conventional and
VTH from their nominal value that affects the leakage current var- INDEP circuits with varying threshold voltage of PMOS transistors
iation. Body biasing is the commonly used method to change the (Vtp) from 0.6 V to 0.4 V at low logic and high logic levels respec-
VTH of the device during its operation [2]. Forward/reverse body tively. PMOS transistors are turned-on for low logic input signals.
bias causes to change in VTH of the device. Reverse body bias im- Therefore, wide Vtp range is selected for turning-on of PMOS tran-
proves the sub-threshold slope thus used for reducing the leakage sistors. Leakage current of the circuit is rising drastically as the Vtp
current [5,8]. We have analyzed the leakage current variation by varies towards the off-state situation of the PMOS transistors.
taking a wide variation range of switching VTH. As input voltage PMOS transistors are completely turned-off for large Vtp value
V.K. Sharma et al. / Microelectronics Reliability 54 (2014) 9099 95

Fig. 6. Comparison of conventional and INDEP circuit with varying Vtn when Vin = 0.

Fig. 7. Comparison of conventional and INDEP circuit with varying Vtn when Vin = VDD.

Fig. 8. Comparison of conventional and INDEP circuit with varying Vtp when Vin = 0.

Fig. 9. Comparison of conventional and INDEP circuit with varying Vtp when Vin = VDD.
96 V.K. Sharma et al. / Microelectronics Reliability 54 (2014) 9099

and high logic input signals. Therefore off-state current is large for approach is 81.95% better while for 20% variations it is 99.59%
high logic input signal as compared to same Vtp, partially on-state better than conventional circuit. INDEP approach is reducing the
current for low logic input signal. The average leakage current leakage current by a large factor as scaled device senses the tremen-
reduction in INDEP approach is 73.14%. INDEP approach enhances dously change in L. Increasing in the L improves the sub-threshold
the output responses of off-state transistors as compared to con- slope. Reverse body bias due to terminal voltages improves the
ventional circuit where large output degradation is occurred. The sub-threshold slope. The position of INDEP transistors and their in-
Vtp for settled output is at 0.35 V and near about 0 V for high put signals provide the reverse body bias caused by intermediate
logic and low logic levels respectively and produce the accurate node voltages. This helps in reduction of leakage current. If the
time bound outputs. PVT parameters values are reduced due to variations then leakage
The standard deviation of VTH is evaluated for distribution of current saving is large as compared to increased parameters values.
variations and it is the function of device physical dimensions. It So, INDEP approach is more efcient for scaled devices.
is given as: Oxide thickness (TOX) is gradually scaling down as technology
r scales. Any variation in TOX impacts the gate capacitance per unit
q NEFF WDEP area. The effective gate capacitance of a device is dominated by
rVTH 1
COX 3WL the intrinsic depletion and parasitic (both overlap and fringe)
capacitances. Reduction in TOX increases the overall parasitic
where q is the electric charge, COX is the oxide capacitance per unit
capacitance which is starting to dominate the intrinsic gate capac-
area, NEFF is the effective channel doping concentration, WDEP is the
itance. Variation in gate capacitance affects the VTH and hence off-
depletion layer width, W is device channel width and L is the chan-
state current. VTH roll-off is avoided by using thinner TOX in scaled
nel length. These values are used for nding the distribution of leak-
devices as C OX TsOX . The crucial value of TOX dimension is needed
age current variation. OX
to meet the leakage power and propagation delay constraints.
In scaled device; the closer proximity of source and drain areas
Fig. 11 explains the variation effect of device TOX on leakage cur-
penetrates into a signicant portion of channel length that reduces
rent for chain of 5-inverters. Gate leakage component increases
the effective channel length of the device. Total charge in the chan-
drastically as TOX is reduced that increases the leakage current.
nel length is reduced and it has affected the VTH of the scaled de-
INDEP approach reduces the leakage current by 96.48% as
vice. Random dopant uctuations in term of channel doping and
compared to conventional design at nominal value of TOX.
VTH variations in terms of mobility, surface potential affect the
MOS transistor width is the primary parameter that can be ad-
channel length, width and oxide thickness of the MOS device [8].
just to meet the required specications of the system. Adjustment
This shift in VTH originates the channel length (L) variation in
of the transistor width mitigates the variability issues in CMOS
scaled device. A relation between VTH and L is approximated by
circuit. INDEP transistors are sized to study its effect on leakage
VTH roll-off effect. Therefore reduction in L causes reduction in
current of the circuit. The sizing of INDEP transistors are obtained
VTH that increases the amount of leakage current. Input voltage
by calculating the widths of the MP1 and MN1 transistors. Sizing
has inverted channel length charge QB to reach the VTH which is
ratio of PMOS (Wp) to NMOS (Wn) widths is chosen to derive
QB the leakage current. When we consider Wp/Wn = 1, which means
VTH VFB uS 2 Wn is 2X and Wp is 6X of the channel length of MOS transistor.
COX
Fig. 12 depicts leakage current as a function of sizing ratio Wp/
Q B / WDEP  L 3 Wn of the transistors. As this ratio is increased, leakage current
is proportionally increasing. Moving from Wp/Wn = 1 to 5, INDEP
where VFB is the at-band voltage, us is the surface potential and approach is constantly saving 96.40% leakage current.
WDEP is depletion layer width along the channel length L. Small VDD reduction is an important scheme to reduce the overall
channel length declines the gate capacitance and used for designing power dissipation of the ICs. Lower value of VDD declines the speed
the high speed circuits with leakage current penalty. Fig. 10 shows and noise margins of the CMOS gate. The reduction in noise mar-
INDEP approach is better to control the leakage current with vary- gins can lead to transient noise errors [16]. Aggressive technology
ing channel length as compared to conventional design. We have scaling has introduced various parameter variation sources. These
taken 20% variations in L parameter. For +20% variations; INDEP variation sources are very critical concern in sub-65 nm technology

Fig. 10. Leakage current as a function of channel length variation. Fig. 11. Leakage current as a function of oxide thickness variation.
V.K. Sharma et al. / Microelectronics Reliability 54 (2014) 9099 97

optimal value of VDD is chosen where trade-off of leakage current


and circuit delay adjust the VTH of the device. The dependency of
leakage current on VTH is given as:
 
VGS  VTH VDS
ILEAK I0 exp 1  exp 4
gVT VT
where I0 is the saturation current, VGS is gate to source voltage, g is
the sub-threshold slope factor, VT is thermal equivalent voltage and
VDS is drain to source voltage.
Conventional design has large leakage current as compared to
INDEP circuit as increasing the VDD voltage. Conventional leakage
current increases by 7.9X while INDEP leakage is increasing by
1.6X by varying the VDD from 0.54 V to 0.84 V (20%@0.7 V). This
implies the effectiveness of INDEP approach to mitigate the VDD
variation effect without degrading the circuit characteristics.
Large energy consumption prevents the success path to design
high performance circuits. Since a battery stores a given amount
Fig. 12. Leakage current as a function of Wp/Wn variation of CMOS circuit. of energy and circuit designers require minimizing the energy con-
sumption. Among the several parameters, VDD is primarily consid-
ered for energy efcient design due to direct relation with energy
nodes. The variation sources are local and global and affect the components. Dynamic energy component is directly related to
circuits in different ways like output performance, power manage- V2DD while static energy component is proportional to VDD. The cir-
ment, timing yield, and other circuit constraints. On-chip resistive cuit delay is inversely depending on VDD. Energy delay product is
drops and inductive effects create local variations while overall dened initially to design energy efcient CMOS gate in ultra-
regulation tolerances cause global variations. Power supply voltage low power applications. Dynamic and static energy components
is eventually shifting due to these local and global variation are given as:
sources. VLSI designers face numerous challenges due to these var-
iation sources and need to analysis these effects. The actual opera- EDYN aCL V2DD 5
tion of MOS device depends on the terminal voltages of the device.
The terminal voltages of the device is the function of many param- EST ILEAK VDD TDEL 6
eters values which are created at the time of manufacturing pro- where a is the transition activity for the gate output node, which is
cess or operating input logics. Therefore, change in power supply calculated using a logic simulator with randomly generated input
voltage due to variation sources affects the operation of ICs as vectors, CL is output load capacitance, ILEAK is the leakage current
threshold voltage of low power devices are at high voltage levels. and TDEL is the circuit delay.
Process variations (L, W, TOX, NSUB, VTH) and network topologies The product of energy consumption and circuit delay in low
(series, parallel, non-seriesparallel) have affected the internal power circuit design is initialized rst. Energy delay product shows
potential variation. The actual value of VDD is different from the the energy consumption requirement per clock of the logic circuit.
applied value by little percentage. By taking a maximum variation The least value of energy delay product is mandatory to design en-
in VDD of 20% from its nominal value we have observed the leak- ergy efcient CMOS gates. Fig. 14 describes the normalized energy
age current as shown in Fig. 13. The terminal voltages of MOS de- delay product with varying VDD by 20% for conventional and
vice are modied and depending on the circuit characterization INDEP circuits. Utilizing the INDEP approach for CMOS gate, can
due to application of different VDD and this is responsible to vary give valuable energy saving in physical design. An optimal value
the VTH of MOS device. VTH scaling limits the performance degrada- of VDD is selected where trade-off of energy consumption and
tion caused by VDD scaling with leakage current penalty. So an circuit delay is occurred. This optimal value is corresponding to

Fig. 13. Leakage current and threshold voltage as a function of supply voltage
variation. Fig. 14. Normalized energy delay product as a function of supply voltage variation.
98 V.K. Sharma et al. / Microelectronics Reliability 54 (2014) 9099

dependence on temperature while I0 is the positive dependence


on temperature. We have analyzed CMOS chain of 5-inverters with
varying temperature from 20 C to 120 C for leakage current as
shown in Fig. 15. VTH decreases approximately at the rate of
0.36 mV/C and 0.31 mV/C for conventional and INDEP circuits
respectively. The reduction in VTH causes leakage current to in-
crease. The slower rate of decreasing VTH in INDEP circuit causes
less variation effect as compared to conventional circuit.
In very deep sub-micron regime, PVT variations are seriously
affecting the performance specications of the circuits. All PVT
variations are combined to estimate the overall effect on leakage
current. Fig. 16 shows the leakage current distribution under
10% variations of VTH, TOX, L, Wp/Wn, VDD and T from their
nominal values. The impact of PVT variations on leakage current
is evaluated through Monte-Carlo simulation performed on 2000
samples at TT process corner. It can be observed that conventional
circuit is prone to large leakage current while INDEP circuit has less
leakage current effect. Various important circuit performance
Fig. 15. Leakage current as a function of temperature variation. metrics such as leakage current, power dissipation, rise delay, fall
delay, energy consumption and energy delay product are analyzed
for PVT variations as listed in Table 1. The performance metrics un-
der PVT variations can be modelled by Gaussian distribution with
probability density function characterized by the statistical data as
mean (l) and standard deviation (r) values. We have compared l
and r of the Monte-Carlo simulation. % change in l and r are
calculated for above said performance metrics. Based on% change
in l and r of the circuit; improvements are shown in Table 1. Per-
formance degradation of a metric is shown by negative sign. From
the Table 1; we can observed that INDEP approach is a good leak-
age reduction PVT mitigate technique with small delay penalty.

5. Conclusion

Fig. 16. Monte-Carlo simulation of leakage current distribution. Variability issues in device characteristics present the major
challenge to design low power reliable circuits in very deep sub-
micron regime. A PVT variations aware transistor level approach
the minimum data point on energy delay product plot. VDD optimal is proposed to design of low leakage nanoscale CMOS circuits.
value for minimum energy consumption and circuit delay is Proposed INDEP approach is based on Boolean logic calculation
occurred at 0.64 V. Optimal VDD depends on EDYN and EST, which of input signals of the extra inserted INDEP transistors between
is varying according to circuit parameters and technology charac- the pull-up and pull-down networks. The selection of input signals
teristics. Optimal energy point is the desired research dimension of INDEP transistors are strongly depending on logic architectures
during the last decade and implemented in various ULV applica- in pull-up/pull-down networks. Extensive study of the robustness
tions [17,18]. At optimal point INDEP approach is 6.16% better than of INDEP approach against PVT variations is comparatively ana-
conventional design. lyzed for leakage current for chain of 5-inverters at 22 nm BSIM4
The environmental conditions play a vital role in the process of bulk CMOS PTM technology node. INDEP approach is tremendously
designing the variations aware ICs. The operating temperature reducing the leakage current for wide variation range of parame-
changes the performance of the ICs in several ways. Different parts ters. We have observed that if the INDEP transistors are equally
of a chip have different power densities that result in temperature sized as other transistors in the networks then 10% variations of
gradient. Environmental temperature gradient impacts on circuits VTH, L, TOX, W, VDD and T achieving 58.32% improvement in statis-
parameters. The on-state and off-state currents are varied since ICs tical mean of leakage current with 14.12% delay penalty as com-
feel thermal behavior due to temperature gradient. Many circuit pared to conventional design. The average energy consumption
parameters such as VTH, l, and I0 are very sensitive to the temper- and energy delay product are improved by 36.12% and 26.94%
ature gradient. The parameters, l and VTH show the negative respectively for 2000 samples of Monte-Carlo simulation.

Table 1
Statistical Monte-Carlo simulation data of different performance metrics for chain of 5-inverters.

Performance metric Conventional circuit INDEP circuit Dl (%) Dr (%)


l r l r
Leakage current (nA) 180 102 75 44 58.32 57.06
Power dissipation (nW) 483 389 256 216 47.08 44.38
Rise delay (ps) 1460 217 1690 251 15.89 16.14
Fall delay (ps) 1340 216 1500 238 12.35 10.32
Energy consumption (fJ) 15.40 2.03 9.83 1.28 36.12 37.05
Energy delay product (yJs) 21.20 1.82 15.50 1.36 26.94 25.51
V.K. Sharma et al. / Microelectronics Reliability 54 (2014) 9099 99

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