Middle Technical University Electronics Lab.

Electrical Engineering Technical College 2nd Stage

Electrical Power Technical Engineering Dept. Mohammed D. Altamemi

Experement-10
Junction Field Effect Transistor (JFET) Characteristics

10-1 Object:
To study the JFET transistor and know its advantages and disadvantages, and
find the VDS-ID characteristics.

10-2 Theory:
The field effect transistor are some semiconductor device, which depend,
concerning the current control, on an electrical field. There are two types of field
effect transistors: the junction field effect transistor (JFET) and the insulated- gate
field-effect transistor (IGFET) more usually designated metal oxide-semiconductor
(MOS, MOST, or MOSFET).

The field effect transistor are different from the junction bipolar transistors in
following important characteristics:

1. It is an unipolar device (just one type of carriers).

2. It is simpler to manufacture and it takes up less space in integrated form.
3. It has great input impedance, usually of many mega ohms.
4. It has less noise than a bipolar transistor.
5. It does not have compensation voltage when the drain current is zero, and
therefore, it is an excellent signal clipper.

The main disadvantage of JFET is its relatively small gain-bandwidth product,

in comparison with one, which can be obtain with a conventional transistor.

The structure of the JEFT of n channel appears in figure (8-1). in this figure we
can see:

Source: the source S is the terminal through which most of the carriers enter the
channel n. the current which enters is called IS.
Drain: the drain D is the terminal through which the majority carriers leave the
channel n. the conventional current which enter the terminal through D, is called ID.
the drainage-Source voltage is called VDC, and it is positive if D is more positive than
S.
Gate: in the two sides of the type n channel in figure (8-1) it has been formed a
region strongly doped of accepter impurities P+. it is applied voltage VGS=-VGG
between gate and source in the direction which polarize the p-n junction inversely.
The conventional current which enters the terminal through G is called IG.
Channel: the region of type n material, it is shown in figure
(10-1) between the two gate region is the channel through which the majority carriers
move from the source to the drain.

MD
Middle Technical University Electronics Lab.
Electrical Engineering Technical College 2nd Stage
Electrical Power Technical Engineering Dept. Mohammed D. Altamemi

Figure (10-1) sideway view to n channel JFET transistor

10-2-1 JFET Characteristics:

In figure (10-2) the circuit, the symbol and the conventional polarity of JFET
are shown.

Figure (10-2) the Circuit and conventional polarity of JFET transistor

The drain characteristics of a JFET of channel n in common source

configuration appears in figure (10-3) giving ID in function of VDS with VGS as a
parameter.

Figure (10-3) the VDS-ID characteristics of a JFET transistor of channel

n in common source

MD
Middle Technical University Electronics Lab.
Electrical Engineering Technical College 2nd Stage
Electrical Power Technical Engineering Dept. Mohammed D. Altamemi

10-3 Procedures:
1. Connect a fixed bias circuit of n-channel JEFT shown in figure (10-4).

Figure (10-4) n- channel JEFT

2. Adjust the VDD voltage source to zero volt.

3. Use the potentiometer to put a voltage VGS equal to -1 volt. To adjust the gate-
source voltage -1volt we use a voltmeter to measure the voltage between gate
and source.

Table (10-1) VDS-ID characteristics of n channel JFET transistor

VDS (V) VGS= - 1V VGS= - 0.5V VGS= 0V
0 ID= ID= ID=
+ 5 ID= ID= ID=
+ 10 ID= ID= ID=
+ 15 ID= ID= ID=
+ 20 ID= ID= ID=

4. With the gate-source voltage fixed in ( -1 volts), you have to change the drain
source voltage VDS, for all the values shown on the left column, and record
current ID of the ammeter in table (10-1).
5. Change the value of VGS to (-0.5, and 0 Volt), and re-change VDS as shown in
left column in each step, and record the value of ID in table (10-1).
6. Increase the gate- source voltage VGS to pinch off voltage VP = -4 V, and
change VDD to +20 V, and then record drain current ID at this condition.

Part II: p-channel JFET

MD
Middle Technical University Electronics Lab.
Electrical Engineering Technical College 2nd Stage
Electrical Power Technical Engineering Dept. Mohammed D. Altamemi

7. Connect a fixed bias circuit of p-channel JEFT shown in figure (10-5).

Figure (10-5) p- channel JEFT

8. Adjust the VDD voltage source to zero volt.

9. Use the potentiometer to put a voltage VGS equal to +1 volt. To adjust the gate-
source voltage +1volt you should use a voltmeter to measure the voltage
between gate and source.

Table (10-2) VDS-ID characteristics of n channel JFET transistor

VDS (V) VGS = + 1V VGS = + 0.5V VGS = 0V
0 ID= ID= ID=
-1 ID= ID= ID=
-2 ID= ID= ID=
-3 ID= ID= ID=
-4 ID= ID= ID=
-5 ID= ID= ID=

10. With the gate-source voltage fixed in ( +1 volts), you have to change the drain
source voltage VDS, for all the values shown on the left column, and record
current ID of the ammeter in table (10-2).
11.Change the value of VGS to (+0.5, and 0 Volt), and re-change VDS as shown in
left column in each step, and record the value of ID in table (10-2).
12.Increase the gate- source voltage VGS to pinch off voltage VP = +6 V, and
change VDD to - 5 V, and record drain current ID at this condition.

MD
Middle Technical University Electronics Lab.
Electrical Engineering Technical College 2nd Stage
Electrical Power Technical Engineering Dept. Mohammed D. Altamemi

10-4 Discussions:
1. In part I, what are IDSS, and VP of the transistor?
2. Draw output characteristics of n-channel JFET, based on results that we get in
table (10-1).
3. Draw transfer characteristics of transistor based on IDSS, and VP, and then find
IDQ and VGSQ at VDD equal to 20V, and compare this result with that you get in
table (10-1).
4. In Part II, what are IDSS, and VP of the transistor?
5. Draw output characteristics of p-channel JFET, based on results that we get in
table (10-2).
6. Draw transfer characteristics of transistor based on IDSS, and VP.

MD