Dr.

Cherif Salama
Faculty of Media Engineering
and Technology

R2 CLR R3
X
CSEN 402 Computer Organization T0
and System Programming n n

Spring 2014

Assignment 1 Y n- bit adder

T2
Deadline: Sunday, March 23rd, 2014
To be submitted as a hard copy at the office of your own TA n

Exercise 1: LD R1

Represent the following conditional control statement by two register transfer statements
with control functions:
If (X = 0) then (R1 R3) else if (Y=1 and Z = 1) then (R1 R3+R2) The values stored by the end of the clock cycle as follows:
R1 = 7 + 3 = 10
Solution: R2 = 7
X : R1 R3 R3 = 0
XYZ: R1 R3+R2
Exercise 3:

Exercise 2: A digital computer has a common bus system for 16 registers of 8 bits each.

Draw a block diagram for the hardware that implements the following statement. Include 3-1) If the bus is constructed with multiplexers.
the logic gates for the control function. Assume that registers are connected point to point a. How many multiplexers are there in the bus?
and not through a common bus. b. What size of multiplexers is needed?
X T0 + yT2: R3 0, R1 R2 + R3 c. How many selection inputs are there in each multiplexer?

If the values stored in the Registers just before this clock cycle as follows: R1 = 9, R2 = 3-2) If the bus is constructed with three state buffers.
7, R3 = 3. State the values stored in the Registers by the end of the clock cycle a. How many three state buffers are needed?
represented by the above RTL statement. b. How many decoders are needed?
c. What is the size of decoders needed?

Solution:

3-1) If the bus is constructed with multiplexers.

a. 8 multiplexers, one for each bit of the registers.
b. 16 × 1 multiplexers.
c. 4 selection lines to select one of 16 registers.
Solution:

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3-2) If the bus is constructed with three state buffers.

a. 128 three state buffers are needed. Solution:
b. Only 1 decoder is needed.
c. 4 × 16 decoder a. R = 01111001
Circular shift-right: 10111100
Logical shift left: 01111000
Exercise 4: Logical shift right: 00111100
Circular shift right: 00011110
Design an arithmetic circuit with one selection variable S and two n-bit data inputs A and
B, the circuit generates the following arithmetic operations: assuming that the Cin of the b. R = 11000011
full adder for the least significant bit is in all cases zero: Arithmetic shift right: 11100001
Arithmetic shift left: 11000010, No overflow, the number was a negative number
and remained negative.
S Operation
0
1 Output = A 1
Draw the logic diagram for the first two stages.

Solution:

S C0
A0 X0
S FA Output 0
B0 0
2×1 MUX Y0
1 1
C1

C1
A1 X1
S FA Output 1
B1 0
2×1 MUX Y1
1 1
C2
C

Exercise 5:

a. Starting from an initial value of R = 01111001, determine the sequence of binary

values in R after a circular shift-right, followed by a logical shift left, followed by
a logical shift right and a circular shift right.

b. Starting from an initial value of R = 11000011, determine the binary value of R

after an arithmetic shift right, followed by an arithmetic shift left. State whether
an overflow occurs or not.

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