VIVEKANANDHA COLLEGE OF ENGINEERING FOR WOMEN

(AUTONOMOUS)

TRAINING AND PLACEMENT CELL

DIGITAL LOGIC CIRCUITS

UNIT-I- MINIMIZATION TECHNIQUES AND LOGIC GATES

1. Representation of hexadecimal number 6DE in the power of 16 is as:

a) 6 * 16^2 + 13 * 16^1 + 14 * 16^0
b) 6 * 16^2 + 12 * 16^1 + 13 * 16^0
c) 6 * 16^2 + 11 * 16^1 + 14 * 16^0
d) 6 * 16^2 + 14 * 16^1 + 15 * 16^0

Answer: a
Explanation: In hexadecimal number D & E represents 13 & 14 respectively.
So, 6DE = 6 * 16^2 + 13 * 16^1 + 14 * 16^0.

2. Convert (0.345)10 in to an octal number.

a) (0.1605)8
b) (0.2605)8
c) (0.1945)8
d) (0.2404)8

Answer: b
Explanation: 0.345*8 = 2.76 2
0.760*8 = 6.08 6
00.08*8 = 0.64 0
0.640*8 = 5.12 5
0.120*8 = 0.96 0
So, (0.345)10 = (0.2605)8

3. In boolean algebra, the OR operation is performed by which properties?

a) Associative properties
b) Commutative properties
c) Distributive properties
d) All of the Mentioned

Answer: d
Explanation: The expression for Associative property is given by A+(B+C) = (A+B)+C &
A*(B*C) = (A*B)*C.
The expression for Commutative property is given by A+B = B+A & A*B = B*A.
The expression for Distributive property is given by A+BC=(A+B)(A+C) & A(B+C) = AB+A
4. The boolean function A + BC is a reduced form of
a) AB + BC
b) (A + B)(A + C)
c) A’B + AB’C
d) (A + C)B

Answer: b
Explanation: (A + B)(A + C) = AA + AC + AB + BC = A + AC + AB + BC = A(1 + C + B) +
BC = A + BC.

5. The canonical sum of product form of the function y(A,B) = A + B is

a) AB + BB + A’A
b) AB + AB’ + A’B
c) BA + BA’ + A’B’
d) None of the Mentioned

6. The output of a logic gate is 1 when all the input are at logic 0 as shown below:

The gate is either

a) A NAND or an EX-OR
b) An OR or an EX-NOR
c) An AND or an EX-OR
d) A NOR or an EX-NOR

Answer: d
Explanation: The output of a logic gate is 1 when all inputs are at logic 0. The gate is either a
NOR or an EX-NOR. (The truth tables for NOR and EX-NOR Gates are shown in above figure.)

7. Identify the function which generates the K-map shown

a) F= Sum m(1,3,4,7)
b) F= Sum m(1,3,5,6)
c) F= Sum m(3,4,5,6)
d) F= Prd M(1,3,4,7)
b) is CORRECT. Plotting F=SUM m(1,3,5,6) on a K-map would result in 1-entries in cells 1,3,5,
and 6, which is
what you want. Note that for a 3 variable K-map the labels dictate the following order for the
minterm cells:
0 2 6 4
1 3 7 5

8. Identify the most simple SOP expression from the K-map shown.
a) B'C + AD + CD
b) BC' + BCD' + AC'D'
c) BC' + BCD' + AB'C'D'
d) AD + BCD' + CD
e) BC' + BD' +AC'D'

5 is CORRECT. Grouping the 1's in two groups of 4 and one group of 2 yields the (most simple)
SOP expression.

9. What is the minimum number of two input NAND gates used to perform the function of two
input OR gates?
a) One
b) Two
c) Three
d) Four
Answer: c
Explanation: Y = A + B. This is the equation of OR gate. We require 3 NAND gates to create
OR gate. We can also write,
1st, 2nd and 3rd NAND operations as: Y = (A AND B)’ = A.B = (A.B)’.

10. Why is the fan-out of CMOS gates frequency dependent?

a) Each CMOS input gate has a specific propagation time and this limits the number of different
gates that can be connected to the output of a CMOS gate
b) When the frequency reaches the critical value the gate will only be capable of delivering 70%
of the normal output voltage and consequently the output power will be one-half of normal and
this defines the upper operating frequency
c) The higher number of gates attached to the output the more frequently they will have to be
serviced thus reducing the frequency at which each will be serviced with an input
signal
d) The input gates of the FETs are predominantly capacitive and as the signal frequency
increases the capacitive loading also increases thereby limiting the number of loads that may be
attached to the output of the driving gate
Answer: d
Explanation: Actually power dissipation in CMOS circuits depends on clock frequency. As the
frequency increases Pd also increases so fan-out depends on frequency.

11. What must be done to interface TTL to CMOS?

a) A dropping resistor must be used on the CMOS of 12 V supply to reduce it to 5 V for the TTL
b) As long as the CMOS supply voltage is 5 V they can be interfaced (however, the fan-out of
the TTL is limited to five CMOS gates)
c) A 5 V zener diode must be placed across the inputs of the TTL gates in order to protect them
from the higher output voltages of the CMOS gates
d) A pull-up resistor must be used between the TTL output-CMOS input node and Vcc; the value
of RP will depend on the number of CMOS gates connected to the node
Answer: d
Explanation: To interface TTL to CMOS a pull-up resistor must be used between the TTL
output-CMOS input node and Vcc; the value of RP will depend on the number of CMOS gates
connected to the node.

12. If the number of bits in the sum exceeds the number of bits in each added numbers, it results
in
a) Successor
b) Overflow
c) Underflow
d) None of the Mentioned

Answer: b
Explanation: If the number of bits in the sum exceeds the number of bits in each added numbers,
it results in overflow and is also known as excess-one.

13. A Boolean function f of two variables X and Y is defined as follows: f(0, 0) = f(0, 1) = f(1, 1)
= 1; f(1, 0) = 0 Assuming complements of X and Y are not available, a minimum cost solution
for realizing using only 2-input NOR gates and 2-input OR gates (each having unit cost) would
have a total cost of
a) 1 unit
b) 4 unit
c) 3 unit
d) 2 unit
14. The Boolean function Y= AB + CD is to be realized using only 2 input NAND gates .The
minimum number of gates required is
a) 2
b) 3
c) 4
d) 5
15. Minimum number of 2 input NAND gates required to implement the function, 𝐹 = (𝑋̅ + 𝑌̅)(𝑍
+ 𝑊) is
(a) 3
(b) 4
(c) 5
(d) 6
16. The output of the logic gate in figure is

a) 0
b) 1
c) 𝐴̅
d) A

17. For the circuit shown below the output F is given by

a) 𝐹 = 1
b) 𝐹 = 0
c) 𝐹 = 𝑋
d) 𝐹 = 𝑋̅
18. For the logic circuit shown in the figure, the required input condition (A,B,C) to make the
output X =1 is

a) 1, 0, 1
b) 0, 0, 1
c) 1, 1, 1
d) 0, 1, 1

Ans. (d)
As per the result the output X has to be 1, so all the inputs of AND gate should be 1.
i.e. C must be equal to 1.
One input to EX-NOR is 1(i.e. C)
The other input should also be 1 to get the 1 output i.e. B=1
One of the input to EX-OR is 1(B=1) the other input has to be 0 to get 1 output at EX-OR Gate.
So, A=0 , B=1 And C=1
Option (d)

19..
20. The K-map for a Boolean function is shown in figure. The number of essential prime
implicants for this function is

a) 4
b) 5
c) 6
d) 8

21. The number of products terms in the minimized sum-of-product expression obtained through
the following K-map is (where, “d” denotes don’t care states)
a) 2
b) 3
c) 4
d) 5

22. -24 is 2’s complement form is

a) 11101000
b) 01001000
c) 01111111
d) 00111111

23. FF16 when converted to 8421 BCD is

a) 0000 0101 0101
b) 0010 0101 0101
c) 1111 0101 0101
d) 1000 0101 0101
24. 11011 in gray code equal to binary
a) (10010)2
b) (11111)2
c) (11100)2
d) (10001)2

25. An equivalent 2’s complement representation of the 2’s complement number 1101 is
a) 110100
b) 001101
c) 110111
d) 111101