The 3rd Vietnam-Korea Joint Workshop of

Solid-State Circuits and Systems

3rd Korea–Vietnam Joint Workshop of Solid-

State Circuits and Systems
January 10-12, 2018
Meeting Room 2, 6th Floor, Main Building,
University of Technology and Education,
HoChiMinh City, Vietnam

https://isdlute.wordpress.com/home/

Co-organized by

Institute of Korean Electrical and Electronics Engineers

(IKEEE), Korea, and
Department of Electrical and Electronics Engineering.
University of Technology and Education, HCMC, Vietnam
(FEEE-HCMUTE)
 INVITED SPEAKERS
3rd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems

ORGANIZING COMMITTEE
Jongsun Kim (Hongik University, Seoul, Korea)
Yong Moon (Soongsil University, Seoul, Korea)
Kwang-Hyun Baek (Chung-Ang University, Seoul, Korea)
Byeongho Choi (Korea Electronics Technology Institute, Gyeonggi-do, Korea)
Kyeong-Sik Min (Kookmin University, Seoul, Korea)
Hieu Giang Le (University of Technology and Education, HCMC, Vietnam)
Minh Tam Nguyen (University of Technology and Education, HCMC, Vietnam)
Chi Kien Le (University of Technology and Education, HCMC, Vietnam)
Son Ngoc Truong (University of Technology and Education, HCMC, Vietnam)
Minh Huan Vo (University of Technology and Education, HCMC, Vietnam)

INVITED SPEAKERS
Jongsun Kim (Hongik University, Seoul, Korea)
Yong Moon (Soongsil University, Seoul, Korea)
Kwang-Hyun Baek (Chung-Ang University, Seoul, Korea)
Byeongho Choi (Korea Electronics Technology Institute, Gyeonggi-do, Korea)
Kyeong-Sik Min (Kookmin University, Seoul, Korea)
Son Ngoc Truong (University of Technology and Education, HCMC, Vietnam)
Le Trong Nhan (University of Technology, HCMC, Vietnam)
Nguyen The Dai Duong (Robert Bosch Engineering, HCMC, Vietnam)
Michael Q. Le (Sitrus Technology Corporation, HCMC, Vietnam)
Trung T. Pham (University of Technology and Education, HCMC, Vietnam)
Khoa Van Pham (Kookmin University, Seoul, Korea)
Minh Huan Vo (University of Technology and Education, HCMC, Vietnam)

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 WORKSHOP PROGRAM
3rd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems

WORKSHOP PROGRAM
Wed. January 10, 2018
17:00-19:00 PM Reception
Thurs. January 11, 2018
09:00-10:00 AM Registration
Opening address, Assoc. Prof. Hieu Giang Le
10:00-10:10 AM Vice President of University of Technology and Education, HCMC,
Vietnam
Energy Efficient Switching Schemes in Capacitive-DAC Designs for
10:10–10:30 AM SAR ADC
Kwang-Hyun Baek, Chung-Ang University, Seoul, Korea
Universal Wireless Power Transfer Circuits
10:30–10:50 AM
Yong Moon, Soongsil University, Seoul, Korea
10:50–11:00 AM Break
Design of CMOS Clocking Circuits for Low-Power SOCs
11:00-11:20 AM
Jongsun Kim, Hongik University, Seoul, Korea
Intelligent Image Processing for Autonomous Driving
11:20-11:40 AM Sung-Joon Jang and Byeongho Choi, Korea Electronics Technology
Institute, Gyeonggi-do, Korea
Memristor Technology for Cognitive Computing
11:40–12:00 AM Tien Van Nguyen and Kyeong-Sik Min, Kookmin University, Seoul,
Korea
12:00-13:40 PM Lunch
The Memristor-Based Crossbar for Hierarchical Temporal Memory
13:40-14:00 PM Son Ngoc Truong, University of Technology and Education, HCMC,
Vietnam
CVD Graphene and Direct Transfer Graphene on Any Arbitrary
Substrates Under Supercritical Carbon Dioxide Assisted-Cleaning
14:00-14:20 PM Technique
Trung T. Pham, University of Technology and Education, HCMC,
Vietnam
Applying LoRa Technology in Smart City: Addressing Problems and
14:20-14:40 PM Design Practices
Nguyen The Dai Duong, Robert Bosch Engineering, HCMC, Vietnam
14:40-15:00 PM Break
Challenges In Serial Gigabit Communications
15:00-15:20 PM
Michael Q. Le, Sitrus Technology Corporation, HCMC, Vietnam
A Combination of Solar and Wind Energy for Autonomous Wireless
15:20-15:40 PM Sensor Nodes
Le Trong Nhan, University of Technology, HCMC, Vietnam
Thermal Energy Harvesting Circuits for On-Body Applications
15:40-16:00 PM
Khoa Van Pham and Son Bao Tran, Kookmin University, Seoul, Korea 3
 WORKSHOP PROGRAM
3rd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems
Mitigating Noise in Image Identification Using Memristor in
Neuromorphic System
16:00-16:20 PM
Huan Minh Vo, University of Technology and Education, HCMC,
Vietnam
16:20-16:30 PM Closing address
17:00-20:00 PM Banquet
Fri. January 12, 2018
09:00–12:00 AM Workshop committee meeting
WORKSHOP PROGRAM

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 ORAL PRESENTATION
3rd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems
10:10 AM - 10:30 AM, Jan. 11, 2018

ENERGY EFFICIENT SWITCHING SCHEMES IN

CAPACITIVE-DAC DESIGNS FOR SAR ADC

Kwang-Hyun Baek
School of Electrical and Electronics Engineering, Chung-Ang Univ., Seoul,
Korea

Successive approximation register analog-to-digital converters (SAR ADCs) are

preferred for low-power applications such as wearable and biomedical sensor
systems because of its simple architecture. Although the semiconductor fabrication
processes have evolved considerably over the years, the analog blocks of ADCs
cannot fully take advantage of the advanced technology and remain as power-hungry
components because of accuracy and speed requirements. Therefore, studies for
reducing the switching energy of the digital-to-analog converter (C-DAC), which is the
most power-consuming block of the SAR ADCs, have been published and these
efforts have led to the development of various switching schemes of the C-DAC. In
this talk, several switching schemes for energy-efficient SAR ADCs will be discussed.

Acknowledgement:
This work was supported by the Technology Innovation Program (or Industrial
Strategic Technology Development Program (10077381, Royalty Free Processor &
Software Platform Development for Low Power IoT & Wearable Devices) funded By
the Ministry of Trade, Industry & Energy (MOTIE, Korea) and . It was also supported
by the IT R&D program of MOTIE/KEIT. [10054819, Development of modular
wearable platform technology for the disaster and industrial site].

Kwang-Hyun Baek received the B.S. and M.S. degrees in electronics engineering
from Korea University, Seoul, Korea, in 1990 and 1998, respectively, and the Ph.D.
degree in electrical and computer engineering from the University of Illinois at
Urbana-Champaign, Urbana, IL, USA, in 2002. From 1990 to 1996, he was with
Samsung Electronics, and he was with the Department of High-Speed Mixed-Signal
ICs as a Senior Scientist at Rockwell Scientific Company, formerly Rockwell Science
Center (RSC), Thousand Oaks, CA, USA, from 2000 to 2006. At RSC, he was
involved in the development of high-speed data converters (ADC/DAC) and direct
digital frequency synthesizers (DDFS). Since 2006, he has been with the School of
Electrical and Electronics Engineering, Chung-Ang University, Seoul, Korea.

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 ORAL PRESENTATION
3rd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems
10:30 AM - 10:50 AM, Jan. 11, 2018

UNIVERSAL WIRELESS POWER TRANSFER

CIRCUITS
Yong Moon
School of Electronic Engineering, Soongsil University, Seoul, Korea
moony@ssu.ac.kr

Wireless Power Transmission (WPT) technology means the transmission of power

without physical connection. WPT has been developed in recent years as the mobile
device and electric car charging needs increases. Many researches are studied to
give the high degree of freedom, reliability and long distance transmission. There are
3 commercial standards for small power wireless transmission like WPC (Wireless
Power Consortium), PMA (Power Matters Alliance) and A4WP (Alliance for Wireless
Power). We need the proper WPT IC according to the standard used, so it is very
convenient to support multi-standards in single chip. So we have designed the
universal WPT circuits to support all the standards with minimizing additional blocks
for multi-standard support. The universal PWT circuits include many blocks like
voltage regulator, matching circuits, DLL (Delay Locked Loop) and Drive circuits. In
this study, we introduce WPT standards, issues in wireless power transfer and key
blocks in WPT. The needs and market for WPT is promising and increasing in the
near future.

Yong Moon received the B.S., M.S., and Ph.D. degrees from the department of
Electronics Engineering, Seoul National University, Seoul, Korea, in 1990, 1992 and
1997, respectively. From 1997 to 1999, he was with LG Semicon co., Ltd., where he
contributed to senior research engineer in analog circuit design group. Since 1999,
he has been with Soongsil University, Seoul, Korea, where he is a professor in School
of Electronic Engineering. He was a visiting professor at University of California,
Santa Cruz, from August 2012 to July 2013. Prof. Moon served on various technical
program committees such as Asian Solid-State Circuits Conference (A-SSCC),
International SoC Design Conference (ISOCC), and Korean Conference on
Semiconductors (KCS). He and his students received ISOCC design Award in 2014
and 2015. He is a member of Institute of Electrical and Electronics Engineers (IEEE)
and Institute of Electronics Engineers of Korea (IEEK). He is the chair of IEEE Solid-
State Circuit Society (SSCS) Seoul Chapter since 2016 and served as the organizing
vice-chair of A-SSCC 2017. His research interests include PLL, ultra-low power circuit
design, NFC/RFID circuit & systems, wireless power transfer circuits, meta-materials
and RF circuits.
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 ORAL PRESENTATION
3rd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems
11:00 AM - 11:20 AM, Jan. 11, 2018

DESIGN OF CMOS CLOCKING CIRCUITS FOR

LOW-POWER SOCS
Jongsun Kim
School of Electronic and Electrical Engineering, Hongik University, Seoul, Korea
js.kim@hongik.ac.kr

In CMOS integrated circuit (IC) design, high-speed clock is very important. System-
on-chips (SoCs), Processors, and Memories require a periodic reference clock to
time synchronization, command execution, and data transfer. On-chip clock
generating/synthesizing circuitry receives an input frequency from a clock source
(e.g., Crystal Oscillator) and either generates new frequencies or distributes that
frequency. On-chip clock generating and synthesizing circuitry such as Phase-
Locked Loop (PLL), Delay-Locked Loop (DLL), and Multiplying Delay-Locked Loop
(MDLL) will be introduced in this talk. Finally, a fast-locking all-digital multiplying DLL
for fractional-ratio dynamic frequency scaling is introduced.

Acknowledgement:
This work was supported by the KIAT grant funded by the Korean government
(MOTIE: Ministry of Trade, Industry & Energy, HRD Program for Software-SoC
convergence).

Jongsun Kim From 1994 to 2001, Prof. Jongsun Kim was with Samsung Electronics
as a senior research engineer in the DRAM Design Team, where he worked on the
design and development of DDR SDRAMs, SGDRAMs, Rambus DRAMs, and other
specialty DRAMs. He received the Ph.D. degree from the Electrical Engineering
Department, University of California, Los Angeles (UCLA) in 2006 in the field of
Integrated Circuits and Systems. He was a Postdoctoral Fellow at UCLA from 2006
to 2007. After his research at UCLA, he returned to South Korea to continue his
memory design career at Samsung, where he was in charge of developing the next
generation high-speed DDR3/DDR4 DRAMs. Dr. Kim joined the School of Electronic
& Electrical Engineering, Hongik University in March 2008. Prof. Kim’s research
interests are in the area of high-performance mixed-mode (analog & digital) circuits
and systems design. His current research areas include high-speed and low-power
transceiver circuits for chip-to-chip communications, clock recovery circuits
(PLLs/DLLs/CDRs/SerDes), frequency synthesizers, low-power and high-bandwidth
memories (DRAM/FLASH), power-management ICs (DC-DC converters), deep-
learning circuits and systems, low-power neuromorphic circuits for AI, and low-power
sensors and transceivers for IoT. He is a member of IEEE, IEIE, IEICE, and ISE.

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 ORAL PRESENTATION
3rd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems

11:20 AM - 11:40 AM, Jan. 11, 2018

INTELLIGENT IMAGE PROCESSING FOR

AUTONOMOUS DRIVING
Sung- Joon Jang and Byeongho Choi
Korea Electronics Technology Institute, Gyeonggi-do, Korea

Autonomous driving requires elaborate and real-time computer vision techniques for
the perfect detection and recognition of objects on a road and driving environments
accurately. In this paper, we present an object detection method based on the
hierarchical graph segmentation, which is robust to pose variations and occlusion and
effective for detecting multi-class objects. And, we propose a method to detect
obstacles exactly with unifying a depth estimation based on the stereo camera,
vehicle detection/tracking and visual odometry. Finally, we implement our schemes
in embedded platforms like nVidia DRIVE PX2 and verify their real-time operation
successfully. Additionally, we present complicated algorithms using a convolutional
neural network, sensor fusion technique and SLAM (Simultaneously Localization &
Mapping) for increasing the accuracy. And, we design dedicated hardware IPs to
accelerate complex functionalities and implement them in FPGA (Field
Programmable Gate Array) or ASIC (Application Specific Integrated Circuits).

Acknowledgement:
The work was financially supported by Industrial Core Technology Development
Program of MOTIE/KEIT (10083639, Development of Camera-based Real-time
Artificial Intelligence System for Detecting Driving Environment & Recognizing
Objects on Road Simultaneously).

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 ORAL PRESENTATION
3rd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems

11:20 AM - 11:40 AM, Jan. 11, 2018

Sung-Joon Jang received the B.S. degree in Electronics Engineering from

Kyungpook National University, Daegu, Korea, in 2005, and the M.S. degrees in
Electrical Engineering from Korea Advanced Institute of Science and Technology
(KAIST), Daejeon, Korea, in 2007. In 2007, he joined Samsung Electronics Co.
Ltd, where he was engaged in the development of low-power VLSI and systems.
In August 2012, he joined Korea Electronics Technology Institute (KETI), where
he was involved in the development of VLSI in terms of intelligent image
processing such as machine learning, computer vision, deep learning. He is
currently a Senior Researcher of Intelligent Image Processing Research Center.
His research interests include intelligent image processing, and its application,
especially such as autonomous vehicle, intelligent robot and drone.

Byeongho Choi received the B.S and M.S. degrees in Electronic Engineering
from the University of Hanyang, Seoul, Korea, in 1991 and 1993. In 1997. He
received the Ph.D. degree in Image Engineering from Jungang University, Seoul,
Korea, in 2010. He had worked for LG Electronics Inc., where he was engaged in
the development of digital video recorder, as a junior researcher from 1993 to
1997. In 1997, he joined Korea Electronics Technology Institute (KETI), where he
was involved in the development of algorithms & VLSI in terms of intelligent image
processing such as machine learning, computer vision, deep learning. He is
currently a Director of Intelligent Image Processing Research Center for KETI. He
has served on technical program committee such as International SoC Design
Conference (ISOCC). He is a member of Institute of Electronics Engineers (IEEK),
The Korean Institute of Broadcast and Media Engineers (KIBME). He is an
operation committee member of Association of Realistic Media Industry (ARMI).
His research interests include algorithm and VLSI Design for Intelligent Image
Processing & Artificial Intelligence (AI).

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 ORAL PRESENTATION
3rd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems
11:40 AM - 12:00 AM, Jan. 11, 2018

MEMRISTOR TECHNOLOGY
FOR COGNITIVE COMPUTING
Kyeong-Sik Min and Tien Van Nguyen
School of Electrical Engineering, Kookmin University, Seoul, Korea
mks@kookmin.ac.kr

We have known very little about brain’s neocortex so far, even though brain’s
neocortex takes the largest portion in brain’s whole volume and is believed to play
the most important role in human’s intelligence and cognition. The neocortex has a
very simple appearance of regular and cellular architecture. This thin-and-wrinkled
organic sheet is approximately 1,000-cm2 in area and 2-mm in thickness. If you look
inside the neocortex, you can find a sort of columns which are composed of six layers.
The six layers have very complicated vertical and lateral connections which can
manage various sensory data in a hierarchical way. The connections which are
realized by biological synapses are strengthened or weakened according to sensory
patterns coming into the neocortex. The synapses in biological neural system can
realize various feed-forward, feed-back, and lateral interconnections with very high
connectivity among the neocortical neurons. Moreover, these synaptic connections
are plastic, self-organized, adaptive, trainable, etc. Combining all these things in the
neocortex, humans acquired our brain’s capability of cognition and intelligence.

In this presentation, we explain how we can use nanoscale memristor technology to

perform cognitive computation similarly with brain’s cognition. The nanoscale
memristors have several good points in mimicking brain’s function and architecture.
They have 3-dimensional connectivity that seems very similar with the real neuronal
structure of neocortex. Moreover, memristor crossbar can be fabricated using Back-
End-Of-Line method that means CMOS-compatible process. The non-volatility and
non-linear behaviors allow memristor to unite both computation and memory
functions into one device.

Acknowledgement:
The work was financially supported by NRF-2011-0030228, NRF-
2015R1A5A7037615, KIST Open Research Program (ORP), and Industrial
Strategic Technology Development program of MOTIE/KEIT (10052653). The
CAD tools were supported by IC Design Education Center (IDEC), Daejeon,
Korea.

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 ORAL PRESENTATION
3rd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems
11:40 AM - 12:00 AM, Jan. 11, 2018

Kyeong-Sik Min received the B.S. degree in Electronics and Computer

Engineering from Korea University, Seoul, Korea, in 1991, and the M.S.E.E. and
Ph. D. degrees in Electrical Engineering from Korea Advanced Institute of Science
and Technology (KAIST), Daejeon, Korea, in 1993 and 1997, respectively. In
1997, he joined Hynix Semiconductor Inc., where he was engaged in the
development of low-power and high-speed DRAM circuits. From 2001 to 2002, he
was a research associate at University of Tokyo, Tokyo, Japan, where he
designed low-leakage memories and low-leakage logic circuits. In September
2002, he joined the faculty of Kookmin University, Seoul, Korea, where he is
currently a Professor in the School of Electrical Engineering. He was a visiting
professor at University of California, Merced, from Aug. 2008 to July 2009. Prof.
Min served on various technical program committees such as Asian Solid-State
Circuits Conference (A-SSCC), International SoC Design Conference (ISOCC),
and Korean Conference on Semiconductors (KCS). He and his students received
IDEC CAD & Design Methodology Award (2011), IDEC Chip Design Contest
Award (2011), and IDEC Chip Design Contest Award (2012). He is a member of
Institute of Electrical and Electronics Engineers (IEEE), Institute of Electronics
Engineers of Korea (IEEK), and Institute of Electronics, Information, and
Communication Engineers (IEICE) in Japan. His research interests include low-
power VLSI, memory design, and power IC design.

Tien Van Nguyen received the B.S. and M.S. degrees in Electronic Engineering from
The University of Technical Education Ho Chi Minh City, Vietnam, in 2014 and 2017,
respectively. He is currently working toward the Ph.D. degree at Kookmin University,
Seoul, Korea. His research interests include memristor crossbar-based neuromorphic
computing systems.

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 ORAL PRESENTATION
3rd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems
13:40 PM - 14:00 PM, Jan. 11, 2018

THE MEMRISTOR-BASED CROSSBAR FOR

HIERARCHICAL TEMPORAL MEMORY

Son Ngoc Truong

University of Technology and Education, HCMC, Vietnam
sontn@hcmute.edu.vn

Hierarchical temporal memory (HTM) is one of machine learning approaches trending

to implement the artificial intelligence. HTM was found by J. Hawkin and demonstrated
as other way to mimic the neocortex. Though HTM was firstly based on software
framework, hardware implementations of HTM have attracted many researchers then.
In this work, we present a memristor-based circuit for implementation of HTM.
Memristor was mathematically found by L. Chua in 1971 and experimentally
demonstrated by HP Lab in 2008, as the fourth fundamental circuit element. Memristor
owns the novel characteristic, which is very similar to the biological synapse, has been
successful in artificial neural network. HTM is composed of the functional blocks that
are encoder, spatial pooler for recognizing the individual patterns, and temporal
memory for storing and recalling the sequence of patterns. The encoder models
human’s sensory organs, where the external signals such as image, voice, smell, taste,
etc are converted to brain’s patterns for the following representation and computation
of sensory information that are performed in the neocortex. In this present, the spatial
pooling layer is implemented by the proposed memristor crossbar with Hebbian
learning. For temporal memory, we present a special memristor chain, in which
memristors successively switch from high resistance state to low resistance state. The
proposed memristor-based HTM is demonstrated to be able to recognize the
handwritten characters with the recognition rate is as high as 95%.

Son Ngoc Truong received the B.S. and M.S. degrees in Electronic Engineering from
The University of Technical Education Ho Chi Minh City, Vietnam, in 2006 and 2011,
respectively, and the Ph.D degree in Electronic Engineering from Kookmin University,
Seoul, Korea, in 2016. He was a research assistant at Kookmin University, Seoul, Korea
in 2016 and 2017. His current research interests include Neuromorphic computing
system, Brain-inspired system, Artificial intelligence, Deep learning, and Internet of
Things (IoT).

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 ORAL PRESENTATION
3rd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems
14:00 PM - 14:20 PM, Jan. 11, 2018

CVD GRAPHENE AND DIRECT TRANSFER

GRAPHENE ON ANY ARBITRARY SUBSTRATES
UNDER SUPERCRITICAL CARBON DIOXIDE
ASSISTED-CLEANING TECHNIQUE
Trung T. Pham
University of Technology and Education, HCMC, Vietnam
trungpt@hcmute.edu.vn

In this report, we present a few results of our LPCVD graphene and a new method for
transferring monolayer/double layer graphene to a variety of substrates. This method
makes use of a biphasic configuration between etchant solution of ammonium
persulphate and low viscocity liquid organic layer of n-hexane during the copper wet
etching. The main advantage from using this hexane layer replaces the deposited
polymeric materials used in the majority of current graphene transfer methods that can
cause severe contamination problems. The graphene-grown copper foil sample sits at
the interface between n-hexane and an aqueous etching solution of ammonium
persulphate to remove the copper. Pre-cleaning cycles of diluted water process are
performed to remove as much as residues from etching solution via a simple home-made
system, followed by supercritical fluid of carbon dioxide to remove further remaining
contamination. Our experimental results are investigated in detail by optical microscope,
Raman spectroscopy, scanning electron microscope and atomic force microscope. This
transferred method might be very promising for graphene-based electronics and its
integration into the silicon technology.

Trung T. Pham received his B.S, M.S degrees in Physical Electronics from the University
of Science, Vietnam in 2002 and 2006 and Ph.D degree in Physics and Materials
Science from University of Namur, Belgium in 2015. His current research interests
include Graphene and its applications. From 2008 to 2009, he worked for AG
Aeschlimann group on the project: photo-semiconductor switch, University of
Kaiserslautern, Germany. From 2015 to 2016, he was Postdoctoral researcher at
Research Center for the Physics of Matter and Radiation, university of Namur, Belgium.
He is currently working as a Lecturer at Department of Physics, University of Technology
and Education, Ho Chi Minh City and a Researcher at The Research Laboratories of
Saigon High-Tech Park (SHTP Labs), Vietnam.

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 ORAL PRESENTATION
3rd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems
14:20 PM - 14:40 PM, Jan. 11, 2018

APPLYING LORA TECHNOLOGY IN SMART

CITY: ADDRESSING PROBLEMS AND DESIGN
PRACTICES

Nguyen The Dai Duong

Robert Bosch Engineering, HCMC, Vietnam
duong.nguyenthedai@vn.bosch.com

In the recent years, Smart City has become one of the most area of interest in which
the Internet of Things is applied. However, unlike Smart Home or Industry applications
where power sources are normally plenty, connection within hundreds of meters is
acceptable and the environment is generally considered as trusted. In Smart City,
sensor nodes are often battery-powered and required to operate several years
without battery replacements. The sensor network coverage ranges to the whole city
that could be tens of kilometers. The operating environment is public which is
obviously a promising area for attackers. In this talk, we will discuss how emerging
LoRa technology has addressed these problems. We will also present some design
practices applying of this technology to a Smart City project.

Nguyen The Dai Duong received B.Eng and M.Eng in Telecommunications and
Electronics at Ho Chi Minh City University of Technology in 2005 and 2007
respectively. He joined Altera Vietnam in 2007 as Design Engineer and involved in
the development and maintenance process of DSP IP cores. In 2009, he joined IC
Design and Research Education Center – VNU where he was in charge of building
up the IP Team. From 2012 to 2014, he worked at Viettel Research and Design
Institute as SoC Architect and Project Manager, contributed to the IC design projects.
He joined Robert Bosch Engineering Vietnam from 2015 as Software Architect
specialized in FPGA, Embedded System and IoT domains.

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 ORAL PRESENTATION
3rd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems
15:00 PM - 15:20 PM, Jan. 11, 2018

CHALLENGES IN SERIAL GIGABIT

COMMUNICATIONS

Michael Q. Le
Sitrus Technology Corporation, HCMC, Vietnam
mle@sitrus-tech.com

High-speed ADC design challenges and the calibration of time-interleaved ADC’s is

presented. As an example, a 28GS/s time-interleaved ADC suitable for PAM4 optical
and backplane applications is presented. The architecture uses a two-rank sampling
network to interleaved 32 8b SAR ADC’s employing redundancy to relax DAC settling
requirements. A DSP core estimates and corrects the gain, offset, and timing error
between channels.

Michael Q. Le received his B.S, M.S., and Ph.D degrees in electrical engineering from
the University of California, Davis. From 2000 to 2014, he was a member of the technical
staff at Broadcom Corporation where he led developments in serial gigabit transceivers,
hard-drive read channel, and wideband ADC’s for satellite communications. From 2014
to 2016, he was at Inphi Corporation where he led the 16nm FinFET development of
high-speed serial transceivers that use PAM4 and higher-order modulation. Currently,
he is the Chief Technical Officer at Sitrus Technology Corporation which develops
integrated circuits for high-speed communication systems.

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 ORAL PRESENTATION
3rd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems

15:20 PM - 15:40 PM, Jan. 11, 2018

A COMBINATION OF SOLAR AND WIND

ENERGY FOR AUTONOMOUS WIRELESS
SENSOR NODES

Nhan Trong Le
University of Technology, HCMC, Vietnam
trongnhanle@hcmut.edu.vn

Wireless Sensor Networks (WSNs) have a great attention in recent years due to their
powerful advantages such as low-powered sensing, wireless communications and
especially, effortless deployment, which are definitely suitable for various monitoring
applications. In order to support a long system-lifetime and expect the battery less
powered WSNs, renewable energies such as solar, wind or heat are integrating in
each wireless node for eternity power supply. In this paper, an efficient multiple
energy sources platform, which is a combination of both solar and wind energy, is
proposed. Our simulations show that, the size of the energy storage is significantly
reduced but still guarantees the Energy Neutral Operation condition for each wireless
node, meaning that the total harvested energy is equal to the consumed energy, in
other words, theoretically infinite system lifetime can be achieved. Experiments
validating this platform are performed on a real WSN platform with both photovoltaic
cells and wind-turbine generators in an indoor environment.

Nhan Trong Le received his Master degree in Computer Science and Engineering
from University of Technology, Viet Nam in 2010 and the Ph.D degree in Computer
Engineering and Electronics from University of Rennes, France in 2014. His current
research interests include Power Management, Wireless Sensor Networks, MAC
Protocol, Energy Harvesting, Network Architecture.

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 ORAL PRESENTATION
3rd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems
15:40 PM - 16:00 PM, Jan. 11, 2018

THERMAL ENERGY HARVESTING CIRCUITS

FOR ON-BODY APPLICATIONS

Khoa Van Pham and Son Bao Tran

School of Electrical Engineering, Kookmin University, Seoul, Korea
khoapv@kookmin.ac.kr

In recent years, wearable smart-fashion applications which are based on the state-of-
the-art sensor technologies gain a lot of attraction form research and industry
communities. Self-powered features is expected critical in future if we take into
account such wearable applications. Energy harvesting technique is one of key
solutions for the self-powered on-body systems. Among the harvesting sources such
as thermal, light, and motion, etc., thermoelectric generator (TEG) harvesting thermal
energy from human’s body temperature, is a strong candidate, because this energy
is easy to be a reliable source of power. Depending on the temperature difference
between the hot side and the cold side, an amount of output power is generated by
the harvesting circuit. However, the amount of power harvested from TEGs is not able
to be delivered to CMOS digital circuit directly. Therefore, a sort of power converter is
essentially needed in the thermal energy harvesting.

In this presentation, the thermal energy harvesting circuit was designed and fabricated
in a 0.6-µm CMOS process, which could generate a regulated output voltage as high
as 4.2V from a very low thermal harvesting voltage around 150mV. The output power
was measured to reach around 40µW from human’s body temperature of 36C. The
experimental results showed the possibility of thermal energy harvesting systems for
wearable applications.

Acknowledgement:
The work was financially supported by NRF-2011-0030228, NRF-
2015R1A5A7037615, KIST Open Research Program (ORP), and Industrial Strategic
Technology Development program of MOTIE/KEIT (10052653). The CAD tools were
supported by IC Design Education Center (IDEC), Daejeon, Korea.

17
 ORAL PRESENTATION
3rd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems
15:40 PM - 16:00 PM, Jan. 11, 2018

Khoa Van Pham received the B.S. and M.S. degrees in electronic engineering from
The University of Technology and Education, Ho Chi Minh City, Vietnam, in 2010 and
2014, respectively. He is currently working toward the Ph.D. degree at Kookmin
University, Seoul, Korea. His research interests include energy harvesting circuit
design and memristor crossbar-based neuromorphic computing systems.

Son Bao Tran received the B.S. degree in electronic and telecommunication
technology engineering from The University of Technology and Education, Ho Chi
Minh City, Vietnam, in 2010. He is currently working toward the M.S. degree at
Kookmin University, Seoul, Korea. His research interests is memristor crossbar-based
neuromorphic computing systems.

18
 ORAL PRESENTATION
3rd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems
16:00 PM - 16:20 PM, Jan. 11, 2018

MITIGATING NOISE IN IMAGE IDENTIFICATION

USING MEMRISTOR IN NEUROMORPHIC
SYSTEM

Minh Huan Vo
University of Technology and Education, HCMC, Vietnam
huanvm@hcmute.edu.vnTION

Image identification using memristor in neuromorphic system is a specific

application to demonstrate the usefulness and popularity of memristor in the future
by the outstanding features such as storage capacity, high integration density, low
power energy. So, this paper have been identified 10 images from 0 to 9, each
image is a 5x6 pixel array, each pixel is a signal to the system, so there will be 30
signals into the system and these signals pass through 600 memristors, which are
divided into 10 anti-additive noise memristor arrays and 10 anti-missing noise
memristor arrays, each array will respectively have 30 memristors. The output
signals from 20 anti-noise memristor arrays then continue into the integrated blocks
which are neurons and switch controller. Image identification will perform two
modes being training and test. The results show that anti-noise memristor
architecture allows images up to 5 pixel noise and identification rate is from 98%
to 100%.

Minh Huan Vo received the B.S. and M.S.E.E. degrees in Electronics and
Communication Engineering from the Ho Chi Minh City University of Technology,
Vietnam in 2005 and 2007 and Ph.D. degree in Electronics Engineering from
Kookmin University, Seoul, Korea in 2013. He is currently working as a lecturer at
the Faculty of Electrical and Electronics Engineering, University of Technology and
Education, Ho Chi Minh City, Vietnam. His current research interests include low
power design optimization in VLSI and IoT system and neuromorphic computation
using emerging technology like memristive devices.

19
 3rd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems

SPONSORS
LIST OF SPONSORS

Module System Smart Fashion Platform

Research Center, Kookmin University

Keysight Technologies Singapore Pte.

Ltd.

Vietnam-Japan International
Orientation & Education Center

Integrated Circuit Design & Education

Research Center

Renesas Design Vietnam Co., Ltd.

Bosch Vietnam Co., Ltd.

20
 3rd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems

HCMUTE
LOCATIO
N
University of
Technology and
Education,
Ho Chi Minh City,
Vietnam

1 Võ Văn Ngân,
Phường Linh
Chiểu,
Quận Thủ Đức,
Thành phố Hồ Chí
Minh.

==============

No. 01
Vo Van Ngan
Street,
Thu Duc District,
21
Ho Chi Minh City.
 3rd Korea–Vietnam Joint Workshop of Solid-State Circuits and Systems

WORKSHOP LOCATION
Meeting Room 2, 6th floor, Main Building,
University of Technology and Education, HoChiMinh City,
Vietnam

1: Main Entrance
7 6 2: Sub Entrance
3: Main Building
(Meeting room 2, 6 th floor)
4: Parking lot
8 5: A block
6: B block
9 7: C block
8: D block

Le van Chi Street

5
9: Viet Duc Block
10: Stadium
2
11: Super market
12: Car parking
3
11
12
10

1
Vo van ngan street

22