Simplified Phase-Shifted Full-Bridge

Converter Design
http://powerelectronics.com/regulators/simplified-phase-shifted-full-bridge-converter-
design?code=UM_Classics09116&utm_rid=CPG05000002112015&utm_campaign=7540&utm_
medium=email&elq2=e921a94d06e244a98945c29a6bc7fe42

To implement a zero voltage switching topology, a streamlined design for a phase-

shifted, full-bridge converter uses fixed delays in place of adaptive delays.
Aug 3, 2011O'Loughlin, Michael | Power Electronics

The 80+ and Climate Savers® initiatives have set a very aggressive Platinum
efficiency standard for server and computer power supplies. To meet this high-
efficiency standard some designers have turned to using a phase-shifted, full-bridge
converter with synchronous rectifiers for the DC/DC portion of the power system.
This is because this type of converter can achieve zero voltage switching (ZVS) with
reduced conduction losses. However, some designers are reluctant to use this
topology due to the complexity and difficulty of setting up adaptive delays, which
some believe is necessary to achieve zero voltage switching. This article reviews a
simplified approach to designing a phase-shifted, full-bridge converter with fixed
delays instead of adaptive delays to simplify the design process and allow zero
voltage switching from 50 to 100 percent load.

Review of a phase-shifted, full-bridge converter

Just the term phase-shifted, full-bridge makes the topology sound complicated.
However, it is simply a buck-derived converter, similar to a forward converter
except the primary of the transformer is driven by an H-bridge configuration.
See Fig. 1 for a functional schematic.
The phase-shifted, full-bridge controller drives FETs QA and QB with gate drive
signals that are 180 degrees out-of-phase at 50 percent duty cycle and are
synchronized with a master clock. FETs QC and QD are also driven with a fixed 50
percent duty cycle and are 180 degrees out of phase with each other. This converter
achieves duty cycle (D) by phase-shifting (θ) the QC and QD gate drive signals. A
better understanding of how a phase-shifted, full-bridge controller achieves duty
cycle can be gained by studying the timing diagram in Fig. 2.
When FET QA and QD are on at the same time (Interval 1), or FET QB and QC, are
on at the same time (Interval 3). The voltage from the primary of the transformer
(T1) is being passed through the transformer through turns ratio (a) to the
secondary (V1). Thus, energy is delivered to the secondary of the converter. During
the free-wheeling periods, FETs QA and QC are on at the same time, while diode D2
is conducting (Interval 2). Or QB and QD are on at the same time (Interval 4) while
diode D1 is conducting.

One of the major benefits of this topology is that if you delay the turn-on of FETs
QA through QD, zero voltage switching can be achieved on the H-Bridge switch
nodes (QBd and QDd,) in Fig. 1. Zero voltage switching at switch node QBd is
achieved by delaying the turn on of FETs QA and QB (tAB_DELAY), allowing time
for the transformers primary leakage inductance (LLK) to ring with the parasitic
capacitance at switch node QBd. In some cases, the energy stored in LLK may not
be enough to swing QBd far enough to achieve zero voltage switching. In this case it
may be beneficial to add a shim inductance (LS) in series with the primary of the
transformer (T1). Refer to Fig. 3 for details.

Zero voltage switching at switch node QDd is achieved by delaying the turn on of
FETs QC and QD (tCD_DELAY), allowing time for the transformers primary
leakage inductance (LLK) and shim inductance (LS), if used to ring with the
parasitic capacitance at switch node QDd, to allow for zero voltage switching.
See Fig. 4 for details.

Note the energy needed for zero voltage switching at switch node QDd is provided
by the reflected output current across the transformer and not the stored energy in
the leakage and shim inductance. This allows for switch node QDd to achieve zero
voltage switching much easier than switch node QBd, which depends on the stored
energy in LS and LLK to achieve zero voltage switching.
To meet these high-efficiency standards, the use of synchronous rectifiers (QE and
QF) most likely will be required on the secondary side of the phase-shifted, full-
bridge converter to reduce conduction losses. See Fig. 5 for a functional schematic.

Fig 5

Fig 6

To design a phase-shifted full-bridge converter, some knowledge of the converter’s

transformer (T1) currents and how the converter achieves zero voltage switching
should prove helpful. Fig. 6 shows the transformer (T1) primary current
(IPRIMARY_T1) and the transformers secondary currents (IQE and IQF) of the
power converter presented in Fig. 5. During Intervals 1 and 3 in Fig. 6, voltage is
being applied across the primary of transformer (T1) and power is being delivered
from the primary to the secondary of the converter. The inductor ripple current is
increasing and the output inductor current is being reflected from the secondary to
the primary of the transformer through the transformer’s turns ratio (a). The QC
and QD turn-on delays (tCD_DELAY) give time for LC tanking to achieve zero
voltage switching at switch node QDd. During this transition, reflected output
current across the transformer provides the energy required to swing switch node
QDd, making it easier to achieve zero voltage switching at this switch node.

During Intervals 2 and 4, the transformer primary is shorted out by the high-side
(Interval 2, QA and QC) or low-side FETs (Interval 4, QC and QD), and the
converter is freewheeling. During this period the output inductor ripple current is
decreasing. During these periods, the output current and inductor ripple current
are still being passed across the transformer to the primary as well. The QA and QB
turn-on delays (tAB_DELAY) give time for LC tanking to achieve zero voltage
switching at switch node QBd. However, during this period LLK and LS provide the
energy to swing switch node QBd to achieve zero voltage switching. This makes it
harder for switch node QBd to achieve zero voltage switching compared to switch
node QDd.

There are many pulse-width modulators (PWM) on the market for controlling a
phase-shifted, full-bridge converter with programmable adaptive delays, including
Texas Instruments’ new UCC28950 phase-shifted, full-bridge controller. These
adaptive delays are used by some engineers to try to reduce the body diode
conduction of the H-bridge FETs, which is not the easiest of things to achieve, and
also may be difficult to maintain in mass production. The adaptive delay approach
used to reduce body diode conduction losses have led to the misconception that
adaptive delays are required to achieve zero voltage switching in a phase-shifted,
full-bridge converter. Since the average capacitance at the switch nodes (QBd and
QDd) and LS and LLK remain approximately the same over line and load, the
resonant tank frequency of the switch nodes (fR) should remain roughly the same.
Since fR remains roughly the same with the proper selection of LS and LLK, Zero
voltage switching can be achieved from 50 to 100 percent load with fixed turn on
delays (tAB_DELAY, tCD_DELAY) for FETs QA through QD.

Phase-shifted, full-bridge converter

design
To show how a phase-shifted, full-bridge converter could achieve zero voltage
switching from 50 to 100 percent with fixed delays, a 600W peak current-mode
control phase-shifted, full-bridge converter with synchronous rectification (Fig. 5)
was designed with the following design parameters.

For T1 in this design a Vitec transformer, part number 75PR8107, was selected with
the following specifications:

a = 21

Primary leakage inductance: LLK = 4uH

Primary magnetizing inductance: LLMAG = 2.8mH

To meet efficiency requirements, Infineon 600V, N Channel FETs and Part Number
SPP20N60CFD, were chosen for FETs QA, QB, QC and QD.

Calculated average COSS for FETs QA, QB, QC and QD [2]:

COSS_QA_AVG = 193pF

The shim inductor (LS) is selected to provide enough energy to swing switch node
QBd down to 50 percent load current. The following equation estimates the size of
LS, approximating that the switch node capacitance at QBd is roughly twice the
average COSS of the QA FET. Note the parasitic capacitance at switch node QBd is
more than twice a single FETs COSS. The total capacitance at switch node should
consist of inter-winding capacitance of T1, trace and stray capacitance and reflected
capacitance across the transformer. It is almost impossible to come up with an
accurate calculation for the QBd. It is just easier to start with an initial ball park
estimate and fine-tune the design at light loads. If zero voltage switching cannot be
achieved with the calculated LS, you will just have to increase the size of LS.

Estimate of peak T1 primary current:

T1 primary current at the end of the free-wheeling period at 50 percent POUT:

A 26 uH Vitec inductor was chosen for LS, part number 60PR964. The shim
inductor has the following specifications:

To set tAB_DELAY and tCD_DELAY requires estimating the tank frequency at

switch nodes QBd and QDd (fR):

As a starting point, we set the fixed delays two one-fourth the period of the tank
frequency, knowing that it would have to be fine-tuned in the design.
Once you have the hardware built you can fine-tune tAB_DELAY at light loads. This
is accomplished by lightly loading the power converter and monitoring QAg, QBg
and QBd and adjusting tAB_DELAY to the time it took switch node QBd at the peak
of the LC ringing. See Fig. 7 for details. In the case of this 600W design,
tAB_DELAY was set at 10 percent load and the tAB_DELAY was adjusted to a fixed
delay of 348 ns.

Fig 7
The tCD_DELAY should be the same as tAB_DELAY that was previously fine-tuned
in the design at light loads. However, the capacitance at switch node QDd might be
slightly different than QBd, tCD_DELAY will need to be adjusted accordingly.
Similar to setting the tAB_DELAY, it is recommended to fine-tune tCDSET at light
load. In this design the QDd node was valley switching at roughly 10 percent load. It
is also worth mentioning that this switch node, even though its tank frequency is
roughly the same as QBd, will achieve zero voltage switching much earlier. This is
because switch-node QDd has the reflected output current across the transformer
to provide energy for the LC tanking; where as, switch node QBd depends on the
energy stored in LS and LLK to swing the switch node with a great enough
amplitude to achieve zero voltage switching. In the case of this 600W design,
tCD_DELAY was set at 10 percent load and the tCD_DELAY was adjusted to a fixed
delay of 348 ns.

The following scope plots were taken of switch nodes QBd and QDd and gate drive
signal QBg and QDg at 10 to 100 percent load in the 600W converter. See
Figs. 8 9 10 11 12 13for details. Note the gate drive signals look slightly different
than Fig. 7 because a 1:2 gate drive transformers were used instead of 1:1. Also gate
drive signal QAg is the inverse of QBg; while, gate drive signals QCg is the inverse of
QDg. At 10 percent load it can be observed that both switch node QBd (Fig. 8) and
QDd (Fig. 9) were valley switching under these test conditions.

Fig 8
Fig 9

Fig 10
Fig 11

Fig 12
 Fig 13

OnE can also see that switch node QDd LC tanks with a greater amplitude than
switch node QBd. This is due to the reflected output current providing the energy
for the LC tanking at switch node QDd, where, switch node QBd depends on the
energy stored in LS and LLK for the LC tanking.

At 50 percent load both switch nodes QBd (Fig. 10) and QDd (Fig. 11) achieved zero
voltage switching. Also, note in these figures that there is no presence of the FET
gate miller plateau.

The 600W converter maintained zero voltage switching at switch node QBd (Fig.
12) and QDd (Fig. 13) up to 100 percent output power with fixed delays.

Using the fixed turn-on delay technique and TI’s new UCC28950 phase-shifted,
full-bridge controller. We were able to achieve greater than 94 percent efficiency
from 20 to 100 percent load in this 600W converter.

To help meet high-efficiency initiatives such as 80 + and Climate Savers Platinum

specifications, the phase-shifted, full-bridge converter is an attractive choice for the
DC/DC power stage. This is due to being able to achieve zero voltage switching on
the H-bridge switch nodes. However, some engineers struggle to set up the adaptive
delays they believe are necessary to achieve zero voltage switching.
Therefore, with the proper selection of the shim inductor, zero voltage switching
can be achieved with fixed delays from 50 to 100 percent load. The fixed delays
simplify the design process of this complicated power converter.

References

1. Bill Andreycak, “Phase-shifted, zero voltage transition design considerations and

the UC3875 PWM controller,” Unitrode Application Note (SLUA107), September 5,
1999.

2. Lazlo Balogh, “Design and Application Guide for High-Speed MOSFET Gate
Drive,” Unitrode Power Supply. Design Seminar 1400, Topic 2, 2001.

3. Michael OíLoughlin, “UCC28950 600-W, Phase-Shifted, Full-Bridge,”

Application Report (UCC28950), September 2010.

4. “Using the UCC28950EVM-442 User’s Guide,” User’s Guide (SLUU421A), May

2010:

5. “Green Phase-Shifted Full-Bridge Controller with Synchronous Rectification,”

Data Sheet (SLUA16A), July 2010.

About the Author

Michael O’Loughlin is a Senior Applications Engineer with the Power Supply

Control Products group at Texas Instruments. He specializes in offline and isolated
power supply design and has authored numerous articles on power factor
correction and power supply design related topics. Michael received his Bachelor of
Science degree from the University of Massachusetts.