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The frontend is writing RTL , linting and Verifying the RTL using testbenches and testcases.

Synthesis aids as an interface for frontend and backend.

Backend encompases ur static timing analysis,floorplanning,clock tree synthesis, layout,signal


integrity issues,frormal verification etc.

As far as VHDL is concerned its scope lies under frontend only.Some simulators may be used for post
layout simulation.

The vendors providing tools are :

Synopsys
Cadence
Magma
Tanner
Mentor Graphics
fintronics

for the front end :


1- It starts from system-level description and verification, like extracting the architecture from an
IEEE standard and modeling the system using C/C++/SystemC or Matlab.

2- Then the output of the modeling and verification, which is the test vectors, is passed to RTL team
to design the hardware using any common HDL language like VHDL or Verilog. This designed
hardware has be simulated using an HDL simulator like Mentor Graphics' Modelsim (commonly used) ..
or any other RTL simulator/wave viewer from Cadence or Synopsis as mentioned before.

3- After the design is verified on the RTL level, it goes for Synthesis and Netlist generation. Most of
the time, people use Design Compiler (by Synopsis) and some others use Leonardo (By Mentor) ..
Simply, u get the netlist out of this process (without more details), then pass it to the backend people.

That was the front end. For the backend people, they take the netlist with the timing inputs, then start
layouting the chip in many steps .. the final output is the layout itself, which goes to the Fab House as
a file called GDSII.

With respect to Digital Design.

Front End: RTL coding,Functional Simulation/Verification.


Backend means Implementation which includes, Synthesis,Place and Route,Static Timing
Analysis,Physical verification.

Synthsis can be done by either Front end or Backend Engineer.


Front-end means it could be any schematic, RTL coding, RTL Verification & etc...
Back-end means implementing the design in terms of transistor with std cells.This invloves
floorplan,placement,CTS, routing & DRC/LVS..

Anything to do with the logic, algorithms etc comes in frontend.

If you are designing a Digital Design, Then RTL coding, Verification forms the front End.(Ex
MicroProcessor). Anything that refers to the Physical design of the chip,
Floorplanning, Place& Route, Clock tree Synthesis, Layout, DRC, LVS, Parasitic Extraction evrything
comes is usually called as backend.

If you are doing analog/RF/DSP Designs, transitor level Schematic design and Simulation, Matlab etc
forms your frontend. (Ex, OpAmp, ADCs etc)
Custom layout, DRC, LVS, Extracion, DFM everything becomes a part of back end.

VLSI Design Flow

The chip design includes different types of processing steps to finish the entire flow. For anyone,
who just started his carrier as a VLSI engineer has to understand all the steps of the VLSI design
flow to become  good in his area of operations. There are different types of design procedures for
analog/digital designs and FPGA designs. The analog design is mainly focusing on the back end
design of a chip while FPGA on front end design.
Front End Design

The steps involved are explained below.

Design entry: It describes the RTL (Register Transfer Level) logics in HDLs. For this, we use
any of the hardware description languages (HDLs) such as verilog and VHDL. This design
specification contains all the details which all are required for the design architecture, RTL block
diagram, clock frequency, frequency domain details, waveforms, port details etc.

Logic Synthesis: The RTL logic written is synthesized to get the gate level netlist. This process
can be done with the help of EDA tools. The code written can be implemented on an FPGA
board only if, it is synthesizable.

Gate level simulation: The gate level simulation of the logic is very important in the verification.
The functional check, timing checks and the Power analysis checks are included in the
verification.

Back End Design

The back end design includes following steps.


Schematic entry: Using the cadence schematic editor in icms, you can create and extract the
logic design you needed.

Pre layout simulation: The logic design is then verified, before doing its layout. The netlist of
the schematic is generated and simulated using any of the tools such as Cadence ultrasim or
Synopsys hspice. The working of each circuit can be checked using the simulation results.

Layout Design: After the schematic is simulated and verified, the corresponding mask layers of
the circuit should be created which can be done using the Layout Editor by cadence. The layout
design includes the floor planning, placement and routing. The locations of each schematic
component are decided in the floor planning and are placed accordingly. While routing, the
interconnections are done between the components.

Extracted simulation: The layout design should be extracted with the parasitics and simulate the
system for performance using hspice or ultrasim. The parasitics can be either resistance or
capacitances which are produced because of the interconnecting wires using for the routing. The
parasitic components may affect the circuit performance badly.  The parasitics cannot be avoided
but can be reduced by proper routing. Finally the routed netlist that is called as GDS-II will be
sent to the foundry and the chip will be manufactured as per the technology requirement.

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