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CHAPTER 8 – COMPARATORS
INTRODUCTION
Chapter Outline
8.1 Characterization of Comparators
8.2 Two-Stage, Open-Loop Comparators
8.3 Other Open-Loop Comparators
8.4 Improving the Performance of Open-Loop Comparators
8.5 Discrete-Time Comparators
8.6 High-Speed Comparators
8.7 Summary
Comparator symbol:
vP +
vO
vN -
Fig. 8.1-1
vP-vN vP-vN
VOL VOL
Noninverting Comparator Inverting Comparator
Fig. 8.1-2A
STATIC CHARACTERIZATION
Static Characteristics
• Gain
• Output high and low states
• Input resolution
• Offset
• Noise
vP-vN
Model:
vP
+ +
vP-vN f0(vP-vN) vO
- -
vN
Comparator
VOH for (vP-vN) > 0
f0(vP-vN) =
VOL for (vP-vN) < 0 Fig. 8.1-3
VOH-VOL
Gain = Av = lim V where V is the input voltage change
V0
VOH+VOL
VOS = the input voltage necessary to make the output equal 2 when vP = vN.
Model:
vP
+vP' +
±VOSv '-v ' f1(vP'-vN') vO
P N
-v ' -
vN N
Comparator Fig. 8.1-7
Other aspects of the model:
ICMR = input common mode voltage range (all transistors remain in saturation)
Rin = input differential resistance
Ricm = common mode input resistance
;;
Comparator Noise
Noise of a comparator is modeled as if the comparator were biased in the transition
region.
vo
VOH
Rms Noise
vP-vN
VOL
Transition Uncertainty Fig. 8.1-8
Noise leads to an uncertainty in the transition region causing jitter or phase noise.
DYNAMIC CHARACTERIZATION
Propagation Delay Time
Rising propagation delay time:
vo
VOH
V +V
vo = OH OL
t 2
VOL
vi = vP-vN
VIH
V +V
tp vi = IH IL
2
t
VIL
Fig. 8.1-9
Thus, if k = 1, tp = 0.693c.
Illustration: vout
Vin > Vin(min)
VOH
Obviously, the more overdrive vin + vout VOH+VOL
applied to the input, the smaller - Vin = Vin(min)
2
VOL
the propagation delay time. 0 t t (max) t
0 p p Fig. 8.1-10
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 8 – Section 1 (8/7/06) Page 8.1-12.
1 2·100 200
tp = 103 ln2·100-1 = 10-3 ln199 = 5.01μs
Therefore, the propagation delay time for this case is limited by the linear response and is
5.01μs.
VPBias2
MC3 MC4 vo
CL
MC1 MC2
vp M1 M2 v
VBias n
-
+ M5
VNBias1
-
060808-02
• Gain gm2rds2
• Slew rate = I5/CL
• Dominant pole = -1/(RoutCL) = -1/(gmrds2CL)
• VBias is replaced as shown in Chapter 6
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 8 – Section 2 (8/7/06) Page 8.2-3.
Folded-Cascode Comparator
VDD
VPB1
M4 M5
VPB2
vOUT
vP M6 M7
M1 M2 VNB2
M8 M9 CL
vN
M3
VNB1 I3 M11
M10
060808-03
• Gain gm2rds2
• Slew rate = I3/CL
• Dominant pole = -1/(RoutCL) -1/(gmrds2CL)
• Slightly improved ICMR
M10 M11
VPB1 M3
vP -A
M8 M9
vOUT
vN M1 M2
M6 M7 CL
-A -A
VNB1 M4
M5
060808-04
• Gain gm1Rout
• Rout [Ards7gm7(rds1||rds5)]|| (Ards9gm9rds11)
• Slew rate = I3/CL
• Dominant pole = -1/(RoutCL)
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 8 – Section 2 (8/7/06) Page 8.2-5.
TWO-POLE COMPARATORS
Two-Stage Comparator
The two-stage op amp without compensation is an excellent implementation of a
high-gain, open-loop comparator.
VDD
M3 M4
M6
vn vout
M1 M2
vp CL
+ M7
VNB1 M5
-
060808-05
• Much faster linear response – the two poles of the comparator are typically much larger
than the dominant pole of the self-compensated type of comparator.
• Be careful not to close the loop because the amplifier is uncompensated.
I7 I6-I7
• Slew rate: SR- = CII and SR+ = CII
CMOS Analog Circuit Design © P.E. Allen - 2006
• Poles
Input: Output:
-(gds2+gds4) -(gds6+gds7)
p1 = CI p2 = CII
• Frequency response
Av(0)
Av(s) = s s
p1 - 1
p2 - 1
0.8
m=2 m = 1 m = 0.5
m = 0.25
0.6
0.4
p2
m= p
1
0.2
0
0 2 4 6 8 10
Normalized Time (tn = -tp1 ) Fig. 8.2-2
can’t be easily solved so approximate the step response as a power series to get
m
tn2 1
m2tn2
mtn2Av(0)Vin
vout(tn) Av(0)Vin1 - m-11-tn+ 2 + ··· + m-11-mtn+ 2 +···
2
Therefore, set vout(tn) = 0.5(VOH-VOL)
VOH-VOL mtpn2Av(0)Vin
2 2
or
VOH-VOL Vin(min) 1
tpn mAv(0)Vin = mVin = mk
This approximation is particularly good for large values of k.
0.8
16.366 which gives tpn 0.491. m=2 m = 1 m = 0.5
m = 0.25
The propagation time delay is 0.6
equal to 0.491/6.75x106 or
72.9nS. This corresponds well 0.4
with Fig. 8.2-2 where the m= p
p2
1
normalized propagation time 0.2
delay is the time at which the
amplitude is 1/2k or 0.031 2k 1 = 0.031
0
which corresponds to tpn of 0
0.52
2 4 6 8 10
Normalized Time (tn = tp1 = t/τ1)
approximately 0.5. Similarly, tp = 0.52 = 77ns
6.75x106 Fig. 8.2-2A
for Vin = 100mV and 1V we get
a propagation time delay of 23ns and 7.3ns, respectively.
0V t(μs)
0 0.2 0.4 0.6
-2.5V Fig. 8.2-5
Solution
1.) Total delay = sum of the first and second stage delays, t1 and t2
2.) First, consider the change of vG2 from -2.5V to 2.5V at 0.2μs.
The last row of Table 8.2-1 gives vo1 = +2.5V and vout = -2.5V
3.) tf1, requires CI, Vo1, and I5. CI = 0.2pF, I5 = 30μA and V1 can be calculated by
finding the trip point of the output stage.
CMOS Analog Circuit Design © P.E. Allen - 2006
M4 M6
M3 M8
vn vout
M1 M2
vp CL
M5
+ M9 M7 Metal
VBias
-
060808-06
Comments:
• Gain reduced Larger input resolution
• Push-pull output Higher slew rates
M4 M6
VNB2
M3 M7 M8
vn vout
M1 M2 M9
VNB2 M10 CL
vp
M5
+ M11 M12
VNB1
-
060808-07
Comments:
• Can also use the folded cascode architecture
• Cascode output stage results in a slow linear response (dominant pole is small)
• Poorer noise performance
M8 M10
M3 M4
M6
vn
M1 M2 vout
vp CL
+ M7 M9 M11
VNB1 M5
-
060808-08
Comments:
• Slew rate = 3V/μs into 50pF
• Linear rise/fall time = 100ns into 50pF
• Propagation delay time 1μs
• Loop gain 32,000 V/V
• The quiescent dc currents in the output stages are not well defined
SUMMARY
• The two-stage, open-loop comparator has two poles which should as large as possible
• The transient response of a two-stage, open-loop comparator will be limited by either
the bandwidth or the slew rate
• It is important to know the initial states of a two-stage, open-loop comparator when
finding the propagation delay time
• If the comparator is gainbandwidth limited then the poles should be as large as possible
for minimum propagation delay time
• If the comparator is slew rate limited, then the current sinking and sourcing ability
should be as large as possible
AUTOZEROING
Principle of Autozeroing
Use the comparator as an op amp to sample the dc input offset voltage and cancel the
offset during operation.
Ideal Ideal Ideal
Comparator Comparator Comparator
vIN
- - - vOUT
+ + - +
VOS VOS CAZ VOS +VOS
+ VOS
-C
AZ
Comments:
• The comparator must be stable in the unity-gain mode (self-compensating comparators
are ideal, the two-stage comparator would require compensation to be switched in
during the autozero cycle.)
• Complete offset cancellation is limited by charge injection
CMOS Analog Circuit Design © P.E. Allen - 2006
φ1Ideal
vIN-
+ - vOUT = VOS
Comparator VOS
φ2 - +
- vOUT
φ1 VOS
vIN+ + Comparator during φ1 phase
φ2 VOS vIN- - vOUT
CAZ φ1 +
vIN+ + -
VOS VOS
Differential Autozeroed Comparator Comparator during φ2 phase
Fig. 8.4-2
Comment on autozeroing:
Need to be careful about noise that gets sampled onto the autozeroing capacitor and
is present on the comparison phase of the process.
HYSTERESIS
Influence of Input Noise on the Comparator
Comparator without hysteresis:
Comparator vin
threshold
t
vout
VOH
t
VOL Fig. 8.4-6A
Comparator with hysteresis:
vin
VTRP+
t
VTRP-
vout
VOH
t
VOL
Fig. 8.4-6B
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 8 – Section 3 (8/7/06) Page 8.3-6.
VTRP+ R1 (V -V )
R2 OH OL VTRP+
vIN 0 vIN
0
VTRP- VTRP-
VOL VOL
Fig. 8.4-8
Upper Trip Point:
R1
vIN = VTRP+ = R1+R2VOH
Shifting Factor:
R
2
V
R1+R2 REF
and
R1 R
2
0 = R1+R2 (-2) + R1+R2VREF
IBias M3 M6 M7 M4
vo1 vo2
vi1 M1 M2 vi2
M8 M5
Fig. 8.4-11
VSS
2.4
2.2
2
vo2
1.8
(volts)
1.6
1.4
1.2
1
-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
vin (volts) Fig. 8.4-13
CMOS Analog Circuit Design © P.E. Allen - 2006
IBias M3 M6 M7 M4
M9 M8
vi1 vi2
M1 M2 vout
M10 M11
M8 M5
Schmitt Trigger
The Schmitt trigger is a circuit that has better defined switching points.
Consider the following circuit:
VDD How does this circuit work?
Assume the input voltage, vin, is low and the output
M5
voltage, vout , is high.
M3, M4 and M5 are on and M1, M2 and M6 are off.
M4 When vin is increased from zero, M2 starts to turn on causing
vin M3 vout M3 to start turning off. Positive feedback causes M2 to turn
M6
on further and eventually both M1 and M2 are on and the
M2 output is at zero.
The upper switching point, VTRP+ is found as follows:
M1 When vin is low, the voltage at the source of M2 (M3) is
vS2 = VDD-VTN3
Fig. 8.4-15
VTRP+ = vin when M2 turns on given as VTRP+ = VTN2 + vS2
VTRP+ occurs when the input voltage causes the currents in M3 and M1 to be equal.
0 vin
0 VTRP- VTRP+ VDD
Fig. 8.4-16
I1 I2 M1 M2
vo1 vo2 vo1 vo2
M1 M2 I1 I2
I1 I2 M1 M2
Enable Enable Enable Enable
Vo1ʼ Vo2ʼ Vo1ʼ Vo2ʼ
M1 M2 I1 I2
Vo2’
gm2Vo1+G2Vo2+sC2Vo2- s = gm2Vo1+G2Vo2+sC2V o2-C2Vo2’ = 0
0
0 1 2 3 4 5
t
τL Fig. 8.5-5
V
OH- VOL
The propagation delay time is tp = L ln 2Vi
CMOS Analog Circuit Design © P.E. Allen - 2006
Since the propagation time delay is the time when the output is 0.5(VOH-VOL), then
using the above results or Fig. 8.5-5 we find for Vi = 0.01(VOH-VOL) that tp = 3.91L =
0.512ns and for Vi = 0.1(VOH-VOL) that tp = 1.61L = 0.211ns.
†
T.B. Cho and P.R. Gray, “A 10b, 20Msamples/s, 35mW pipeline A/D Converter,” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166-172, March
1995.
CMOS Analog Circuit Design © P.E. Allen - 2006
φ1 M5 M6 φ1
vout+ vout-
M3 M4
vin+ M1 M2 vin-
Fig. 8.5-7
Dissipated 50μW when clocked at 2MHz.
†
A. Coban, “1.5V, 1mW, 98-dB Delta-Sigma ADC”, Ph.D. dissertation, School of ECE, Georgia Tech, Atlanta, GA 30332-0250.
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 8 – Section 4 (8/7/06) Page 8.4-9.
CMOS Latch
Circuit:
VDD
φLatch
M6
M8 M3 M4 +
VREF vout
vin vout-
M7
M1 M2
φLatch
M5
Fig. 8.5-8
;;
;;
;;
;;
Input offset voltage distribution:
L = 1.2μm
of Samples
20
Number
;;
;;;
;;;
σ = 5.65 (0.6μm Process)
10
0 -15 -10 -5 0 15
5 10
Input offset voltage (mV) Fig. 8.5-9
Power dissipation/sampling rate = 4.3μW/Ms/s
CMOS Analog Circuit Design © P.E. Allen - 2006
M1 M2
Latch
M7 Outputs
M3 M4
060808-10
When Latch_bar is high, M5, M6 and M7 are off and the latch is disabled and the outputs
are shorted together.
When Latch_bar is low, the input voltages stored at the sources of M1 and M2 will cause
one of the latch outputs to be high and the other to be low.
The source of M1 and M2 that is higher will have a larger source-gate voltage
resulting in a larger transconductance and more gain than the other transistor.
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 8 – Section 4 (8/7/06) Page 8.4-11.
Metastability
Metastability is the condition where the latch cannot make a decision in the time
allocated. Normally due to the fact that the input is small (within the input resolution
range).
Metastability can be improved (reduced) by increasing the gain of the comparator by
preceding it with an amplifier to keep the signal input to the latch as large as possible
under all conditions. The preamplifier also reduced the input offset voltage.
VDD
Latch_bar
Latch
Inputs
Comparator
Inputs Latch
Outputs
VNB1
SUMMARY
• Discrete-time comparators must work with clocks
• Switched capacitor comparators use op amps to transfer charge and autozero
• Regenerative comparators (latches) use positive feedback
• The propagation delay of the regenerative comparator is slow at the beginning and
speeds up rapidly as time increases
• The highest speed comparators will use a combination of open-loop comparators and
latches
Assuming a W/L ratio of 10 for M1 and 40 for M2, if the input can swing to VDD (=2.5V)
and ground, the sourcing and sinking currents are:
Kp'W 25·40
ISourcing = 2L (VDD – |VTP|)2 = 2 (2.5V-0.5)2 μA = 2.0 mA
Kn'W 120·10
ISinking = 2L (VDD – VTN)2 = 2 (2.5V-0.5)2 μA = 2.4 mA
If larger currents are required, cascaded stages can be used to optimize the delay versus
the current output.
CMOS Analog Circuit Design © P.E. Allen - 2006
M1 M2
M1 M2
M5
VBias M5
VSS Fig. 8.3-4
VSS
Advantage:
Large sink or source current with out a large quiescent current.
Disadvantage:
Poor common mode range (vin+ slower than vin-)
†
M. Bazes, “Two Novel Full Complementary Self-Biased CMOS Differential Amplifiers,” IEEE Journal of Solid-State Circuits, Vol. 26, No. 2, Feb.
1991, pp. 165-168.
CMOS Analog Circuit Design © P.E. Allen - 2006
Chapter 8 – Section 5 (8/7/06) Page 8.5-5.
A Study in Exponentials
The step response of an amplifier with a gain of Ao and a dominant pole at A is,
vout(t) = Ao[1 – exp(-At)] Vin
vout
Slow rising
AoVin
Fast rising
0 t
060810-04
Fast rising
2.72Vin
Slow rising
0 t
τL 060810-05
+ + +
Vin Ao Vo1 Latch Vout
− − −
060810-06
In order to keep the bandwidth of the amplifier large, the gain will be small. To achieve
Preamplifier 1 Preamplifier 2 Preamplifier n
+ + + + + +
Vin Ao1/n Vo1 Ao1/n Vo2 Von-1 Ao1/n Von Latch Vout
− − − − − −
Gain = Ao 060810-08
Therefore, the question is how many stages of the amplifier and what is the gain of each
stage for optimum results?
1 1 1 dtp
tp = t1 + t2 = -3dB ln 1-2x + L ln 2x dx = 0 gives
2L-3dB 0.4
2x = 2+2L-3dB = 2+0.4 = 0.3859 (x = 0.1930)
10ns 1
t1 = 2 ln 1-0.3859 = 1.592ns·0.4875 = 0.7762 ns
1
and t2 = 1ns ln 0.3859= 0.9522ns
An Improved Preamplifier
Circuit:
VDD
VBiasP VBiasP
M3 M4
vout- M5 M6 vout+
Reset
M10 M12
FB M11 FB
M7 M8
VBias
vin+ vin-
M1 M2
VBiasN
M9
Fig. 8.6-5
Gain:
gm1 KN’(W1/L1)I1 KN’(W1/L1) I5
Av = - gm3 = - KP’(W3/L3)I3 = - KP’(W3/L3) 1+I3
If I5 = 24I3, the gain is increased by a factor of 5
Gain = 20dB
f-3dB = 551MHz
CHAPTER 8 - SUMMARY
Types of Comparators Presented
• High-gain, open-loop
• Improved high-gain, open-loop, comparators
Hysteresis
Autozeroing
• Regenerative comparators
• High-speed comparators
Performance Characterization
• Propagation delay time
• Binary output swing
• Input resolution and/or gain
• Input offset voltage
• Power dissipation
Important Principles
• The speed of the comparator depends on the linear and slewing responses
• The dc input offset voltage depends on the matching and is reduced by autozeroing.
Charge injection is the limit of autozeroing
• The comparator gain should be large enough for a binary output when vin = Vin(min)
• High speed comparator use preamplifiers cascaded with a latch
CMOS Analog Circuit Design © P.E. Allen - 2006