Iem ch1

Digital to Analog Converter
Analog to Digital Converter
DAC - ADC
EIM Chap 2 – Digital to analog converter . Analog to digital converter
Digital to Analog Converter
Function: converts binary input number in analog output;

fDAC:N→R
Parameters:
Conversion type: unipolar, bipolar;
Binary code (natural, offset, two’s complement, etc.);
Output type (U, I);
Output range ΔU = U O _ max − U O _ min ΔI = I O _ max − I O _ min
Resolution - output variation for LSB variation of input code
δ U = U LSB = ΔU /(2n − 1)
- number of bits used for binary cod (n)
Settling time - interval between an input command and the time
when the output reaches its final value;
2
EIM Chap 2– Digital to analog converter
Binary representation n 2
N = ∑ bk 2k ; bk ∈ {0,1} ;
of numbers (n1+n2+1 bits): k =− n 1
Binary coding (sub-unitary, N<1)
Natural binary (unsigned)

n
N = ∑ bk 2− k N min = 0 N max = 1 − 2− n δ N = 2− n
k =1
Offset binary (signed)

n
1 1 −n
N = ∑ bk 2 − 2 k −1
N min =− N max = −2 δ N = 2− n
k =1 2 2
Two’s complement (signed)
n
1 1 −n
N = −2 ⋅ (1 − b1 ) + ∑ bk 2
−1 k
N min = − N max = −2 δ N = 2− n
k =2 2 2
3
Binary coding (cont’d)

Sign – Magnitude (signed)
n
N = ( −1) ⋅ ∑ bk 2k
b1
N min = −2−1 + 2− n N max = 2+1 − 2− n δ N = 2− n
k =2
Binary coded decimal (BCD) – 4 bits (nibble) used to

represent one digit ;
Gray – the difference between codes of two successive
number is 1 bit;
One’s complement (signed);
4
Unipolar Codes
N (natural) Fraction ( subunitar nr) NB BCD Gray
0 0 0000 0000 0000
1 1/16 0001 0001 0001
2 2/16 0010 0010 0011
3 3/16 0011 0011 0010
4 4/16 0100 0100 0110
5 5/16 0101 0101 0111
6 6/16 0110 0110 0101
7 7/16 0111 0111 0100
8 8/16 1000 1000 1100
9 9/16 1001 1001 1101
10 10/16 1010 - 1111
11 11/16 1011 - 1110
12 12/16 1100 - 1010
13 13/16 1101 - 1011
14 14/16 1110 - 1001
15 15/16 1111 - 1000
5
Bipolar Codes
N Fraction SM C1 C2 OB* OB
+3 +3/8 011 011 011 111 000
+2 +2/8 010 010 010 110 001
+1 +1/8 001 001 001 101 010
+0 +0 000 000 000 100 011
-0 -0 100 111 - - -
-1 -1/8 101 101 111 011 100
-2 -2/8 110 101 110 010 101
-3 -3/8 111 100 101 001 110
-4 -4/8 - - 100 000 111
6
Binary codes conversion
7
Binary codes conversion
8
Ideal characteristic for unipolar DAC :

n
b1…bn
U CS
U ( N ) = U R ⋅ ∑ bk 2− k δU = U R ⋅ 2 −n
= n
k =1 2 −1 VR V(N)
U min = U ( N = 0..0h ) = 0V
U max = U ( N = F ...Fh ) = U R (1 − 2 ) =U
V(N)
−n
CS VR
V CS
Ideal characteristic for bipolar DAC

(offset binary code) V MSB
⎛ n ⎞
U ( N ) = U R ⋅ ⎜ ∑ bk 2− k − 2−1 ⎟
⎝ k =1 ⎠ V LSB
U max = U R ⋅ ( 2 − 2 )
N
000
LSB 001
010
011
MSB 100
101
110
Nmax+1
Nmax 111
−1
U min = −U R ⋅ 2 −1 −n
δ U = U R ⋅ 2− n 0 1/8 4/8 7/8
9
Non-ideality errors
Static errors
Offset error - analog output response to an input code
corresponding to output zero;
Gain error – difference between slope of actual and ideal
transfer function;
Full-Scale error - difference between the actual and the ideal
output maximum value (offset error + gain error) ;
Integrated nonlinearity error (INL) - deviation of an actual
transfer function from a straight line (after nullifying offset and
gain errors);
Differential nonlinearity error (DNL) - difference between the
ideal and the measured output responses for successive
DAC codes;
Dynamic error: overshoot, undershoot (during settling time)
10
Offset error Gain error

Factor scale error
UO
Overshoot
+ δV
2
UO(N)
− δV
2 Undershoot
tsw ts tsettling t
INL error DNL error Settling time
11
D/A converter – traditional data converter at Nyquist

rate (fs>2fm)
- LPF is antialiasing filter (for extinction of image signal on fS ) ;

- Droop correction means inverse “Sinc” function ;
- The S/H is a “deglitching” circuit and could be eliminated for
small glitches;
12
EIM Course 3 – Digital to analog converter
D/A converter – mathematical representation:

Pulse Amplitude Modulation
y (t )
p(t) y sh (t )
⎧
+∞
⎫
y sh (t )= ⎨ ∑ y (t )⋅δ (t −nTS )⎬ ⊗ p(t ) hold
⎩n=−∞ ⎭ +∞
δ T (t )= ∑ δ (t −nTS )
⎧ +∞ ⎫
n =−∞
F { y sh (t )}=F ⎨ ∑ y(nTS )⋅δ (t −nTS )⎬ ⋅ F { p(t )}

⎩n=−∞ ⎭ |Y ( f ) |
∞
Ysh ( f ) = w⋅sinc(π f ⋅w)⋅ f s ∑ Y ( f −nf )
n =−∞
k s
For w = TS (practical DAC converter) -fm fm

|Ysh ( f ) |
⎛ Ts ⎞ ∞
Ysh ( f ) =sinc⎜ 2π f ⋅ ⎟⋅ ∑ Yk ( f −nf s )
⎝ 2 ⎠ n=−∞
-fS -fm fm fS 1/w
13
Types of DAC’s
• Binary Weighted Resistor Network
• R-2R Ladder Network
• Stochastic
• Multiplying DAC
14
Binary-Weighted Resistor DAC

VR
Using Tellegen’s theorem: 1

bn 2nR
⎛n 1 1 ⎞ n
bi
Vg ( N )⋅⎜ ∑ i + n ⎟=VR ∑ i bi ∈{0,1} 0 .....
⎝ i=1 2 R 2 R ⎠ i=1 2 R
8R
n b3
Vg ( N ) =VR ∑bi 2−i =VR ⋅N 1

i=1 4R
b2
Vg _min =Vg ( 0...0h) =0V δVg =Vg ( 0...1h) =2−n VR 0 R(N)
Vg _max =Vg ( F...Fh) =VR (1−2−n )

2R
b1
Vg(N)
0
RT=2nR
After source passivization:
n
1 = 1 + 1 = 1 ⇒ R N =R
∑
R( N ) i=1 2 R 2 R R
i n ( )
15
Binary-Weighted Resistor DAC (cont’d)

Steady state voltage command
V0 ( N ) =Vg ( N )
Dynamic regime (Laplace transform )
voltage command
V0 ( s ) =Vg ( s )⋅ 1 ⋅1 =V ( s )⋅⎛1 − 1 ⎞
g ⎜ ⎟
sRC p +1 s ⎝ s s +1/τ ⎠
⎛ −t ⎞ 1
V0 (t ) =Vg ⋅⎜1− e τ ⎟⋅σ (t ) , τ= current command
⎜
⎝
⎟
⎠ R( N )C p R(N)
1 ⎛ − n−1 VR ⎞ V0(t)
V0 (ts ) −Vg ( N ) ≤ δ V ⇒ ts ≥ τ ⋅ln ⎜ 2 ⎟⎟
2 ⎜
⎝ Vg ( N ) ⎠ Vg(N) σ(t)
Cp
Steady state current command

V0 ( N ) = − R ⋅V N = − V N
g( ) g( )
R( N )
16
Binary-Weighted Resistor DAC (cont’d)
Disadvantages:
• Resistance Values Require Great Accuracy:
e.g. Tolerance of R must be < 1/2n
• Often limited to 4-Bit conversions because of the limited current
range possible with resistors;
• Larger bit numbers difficult due desired current changes being

close in magnitude to noise amplitudes (for less significant bits);
• Hardware difficult realization for large bits number (due the weight
inaccuracy for the large range);
17
R-2R ladder network DAC

R R R
IR R R R It
I1 I2
VR 2R 2R ..... 2R 2R RT=2R
Ik = 2 R ⋅ I = 2 − k VR = 2 − k I
k −1 R
2R + 2R
b1 b2 bn-1 bn
R 0 1
Rr
0 1
[B]
V0 ( N ) =− Rr I ( N ) V0(N)
Convertor I - U
n n
Rr n
I ( N ) = ∑ I k = 1 VR ∑bk 2 − k ⇒ V0 ( N ) = − VR ∑bk 2 − k
k =1 R k =1 R k =1
Rr
V0_ max ( N = 0...0h ) = 0V V0_ min ( N = F ...F h ) = − ⋅VR ⋅(1− 2 − n )
R
Rr
δV =V0 ( N = 0...1h ) = − ⋅VR ⋅2 − n
R
18
R-2R ladder network resistor DAC (cont’d)
• Maintains constant current through all branches = no voltage

transients;
• Less hardware constrain (easy to find R-2R resistor pair
values);
• Faster response time due to lack of voltage transients.
19
Stochastic DAC (without resistor network)

fCK
NUM
∞
C y out ( t ) = A0 + ∑ Ak cos⎛⎜ k 2π t +φk ⎞⎟
n
R
Cy out
k =1 ⎝ T ⎠ SUM
C
V(N)
out
T = ( 2n − 1) TCK
n unused
(nefolosit)
n
N
η=Ν/2n
Cy out
ηT
1 1 1 1
H(f) = = fT = <<
1 + j 2π fRC ⎛ f ⎞
2
2π RC T t
1+ ⎜ ⎟
⎝ fT ⎠ T nTn
= (2
T=2 -1)TCK
CK
τN1 2n E n
V ( N ) = A0 = E = n N = VR ∑ bk 2− k
Cy out(ω)
E= n LPF
T 2 −1 2 −1 k =1 A0 A1
A2
N sub-unitary number (N1 supra-unitary )

0 2π/Τ 4π/Τ ω
Multiplying DAC
U out ( t )
• slow time varying external U Ref
U Ref = U in ( t ) t
U out ( t )
dU in ( t ) δUo
<<
dt max
2 ⋅ tconv t
• binary code on digital input → command for controlled amplification /

attenuation;
• Uin(t) must preserve DAC functionality;
DAC applications
• Industrial Control Systems

e.g. motor speed & valves;
• Digital Audio
e.g. CD player;
• Digital Communications
e.g. digital telephone and video systems;
• Waveform Function Generators

e.g. direct digital synthesizer (DDS);
Example 1: Digital to analog converter (8 bits) - DAC 08
Ik = 2-k· I
n
V n
I '0 ( N ) = ∑ I ' k = R ∑ k
(1− b ) 2 −k
k =1 Rref k =1
n
V n
I 0 ( N ) = ∑I k = R ∑b 2 k
−k
k =1 Rref k =1
VR VR − 8
I '0_ min ( N = FFh ) = 0 I '0_ max ( N = 00h ) =
Rref
(1− 2 −8 ) δ I '0 = −
Rref
⋅2
V V
I '0_ min ( N = 00h ) = 0 I '0_ max ( N = FFh ) = R (1− 2 −8 ) δ I '0 = + R ⋅2 − 8
Rref Rref
23
EIM Chap 2 – Digital to analog converter
Example 2: Inversion amplifier with digital adjustment gain

R
I _
DAC - 08 +
vout =− RI ( N )
u(t)
IN Vout
I
N
n
vout (t ) =−uin ( t )⋅ R ⋅∑bk 2 − k = Au ( N )⋅uin ( t )
Rref k =1
n
Au ( N ) =− R ⋅∑bk 2 − k
Rref k =1
24
EIM Chap 2 – Analog to digital converter
s(t) {n}
Analog to Digital Converter ADC
Function: converts input analog signal into a digital signal;

ADC conversion comprises :
Time sampling: samples are taken from the analog signal

(sampling frequency) and its values are maintained for a certain
time interval;
Quantization : rounding off of the sampled value to the nearest of
a limited number of digital values;
Binary coding: conversion of the quantized value into a binary
code;
Sampling and quantization operation may give rise to loss of information.
Under certain conditions ADC loss can be limited to an acceptable
minimum;
25
s(t) {n}
Analog to Digital Converter ADC
Mathematical representation of ADC Function:

fADC:R→N
Parameters:
Conversion type: unipolar, bipolar;
Quantization type: truncate, round, round-ceiling;
Binary code (natural, offset, two’s complement, etc.);
Input type (U, I);
Input range;
Resolution - the smallest change required in the ADC analog input to
change its output code by one level;
- number of bits used for binary cod (n);
Conversion time - required time before the converter can provide valid
output data
Accuracy of conversion - the difference between the actual input voltage
and the full-scale weighted equivalent of the binary output code
26
Parameters (cont’d)
Converter Throughput Rate - the number of times the input signal can be
sampled maintaining full accuracy
- Inverse of the total time required for one
successful conversion
- Inverse of Conversion time if no S/H
(Sample and Hold) circuit is used
ADC Interface Signals :
Data: Digital I/O pins the ADC uses to supply data
Parallel output – n+1 pins (fast transmission, short distances)
Serial output – 2 pins (for long distances, need a internal shift-register)
Start: Pulse high to start conversion (input)
EOC (End of Conversion): Typically active low → low level of pulse
indicate complete conversion (output value can be read);
Clock: Clock used for conversion (for synchronising ADC sub-blocks, for
internal FSM);
27
A/D Converter – traditional data converter at Nyquist rate

(fs>2fm)
X SH ( f ) XQ ( f )
f f f f
Successive operations for AD conversion process.

ADC introduces a non-compensable quantization noise.
28
Sampling process (remember)

- continuous signal conversion into a discrete time samplers sequence
(ideal sampling, natural sampling, flat-top sampling);
Ideal sampling
x(t ) → xs (t ) = x[n] = x(nTs )∈R
+∞
xs (t ) = ∑ x(t )⋅δ (t −nTS ) = x(t )⋅δ TS (t )
n =−∞
+∞ 2π
jn t
δ T (t ) = 1 ∑e TS
S
TS n =−∞
+∞
⎛ n ⎞
{ }
X S ( f ) = F x(t )⋅δ TS (t ) = X ( f ) ⊗ 1
∑ ⎜ T ⎟
δ
TS n=−∞ ⎝
f −
-fm fm
S ⎠
|XS( f )|
1
+∞
⎛ n ⎞ +∞
= ∑ X ⎜ f − ⎟ = f S ⋅ ∑ X ( f −n⋅ f S )
TS n=−∞ ⎝ TS ⎠ n=−∞
-fS -fm fm fS
29
Sampling process (cont’d)

Natural sampling
x(t ) → xs (t ) = x(t ) pTS (t )

+∞ 2π
jn t
pTS (t ) = ∑ Pn ⋅e TS
n =−∞
2π nTS + TS /2 2π n
−j −j t
Pn =e 2TS
⋅ 1 ∫ pTS (t )⋅e TS
dt
Ts −TS /2 -fm fm
⋅sinc(nπ )=(−1) ⋅sinc(nπ )

− jnπ n
=e
⎛
+∞
⎞
{ } n
X S ( f ) = F x(t )⋅ pTS (t ) = ∑ Pn ⋅ X ⎜ f − ⎟
n =−∞ ⎝ TS ⎠ -fS -fm fm fS
30
Sampling process (cont’d)

Flat-top sampling
⎧ +∞
⎫
x(t ) → xs (t ) = ⎨x(t ) ∑ δ (t −nTS )⎬⊗ p(t )
⎩ n=−∞ ⎭
P( f ) = F { p(t )}=TS ⋅e − jπ fTS ⋅sinc(π f TS )
+∞
⎛ ⎞
X S ( f ) =⋅e − jπ fTS
⋅sinc(π f TS )⋅ ∑ X ⎜ f − n ⎟ -fm fm
n=−∞ ⎝ TS ⎠
Sampling rate is given in Samples/s

(S/s, kS/s, MS/s, GS/s); -fS -fm fm fS
31
Quantizing process
- analog signal approximation to the nearest discrete value:
x [ n ] → x q [n ] = q k ⇒ k , k ∈ 1, M , qk ∈QM
aM xq(t)
qM → M qM → M
Quant. ak Quantized
thresholds qk → k qk → k
values
ak-1
q2 → 2 q2 → 2
a1
q1 → 1 q1 → 1
a0
2 1 2 k M +δ/2
nq(t) t
t -δ/2
Quantization of non-sampled signal (continuous)
32
Sampling & quantizing process

Ts
ak
qk → k
ak-1
Quantization qk-1 → k-1 Quantized
thresholds values
a2
q2 → 2
a1
q1 → 1
a0
nsq(t)
Quantization ½ δ
noise -½ δ t
Analog signal
Sampled signal (sample & hold)
Quantized signal
• Quantization – uniform (constant step) – linear ADC

– non-uniform (variable step) – nonlinear ADC
33
Quantization
Truncating quantization qk = ak −1
n n
U qt = U ref ∑ 2 bi = δ U ∑ 2n −i bi = N t δ U
−i
i =1 i =1
Quantization noise p(nq)

∞
nqt =U −U qt =U ref ∑2 −i
bi
i = n +1 0 +δ nq
Noise mean value
∞ δ
1 δ
E{nqt } = ∫
−∞
p (nqt )nqt dnqt = ∫ nqt
0
δ
dnqt =
2
Noise variance (power)

2−2 n 2 δ2
σ = E{nqt } − [ E{nqt }] =
2
qt
2
= U ref 2
12 12 Ideal characteristic
34
Quantization (cont’d)
ak +ak +1
Rounding quantization qk +1 =
2
⎛ −n n
⎞
U qr = δ U ⋅ bn +1 + U qt = U ref ⎜ 2 bn +1 + ∑ 2− i bi ⎟
⎝ i =1 ⎠
= ( N t + bn +1 )δ U = N r δ U , bn +1 ∈{0,1}
Quantization noise
n
nqt =U −U qt =U ref (− 2 − ( n +1)
bn+1 + ∑ 2 − i bi )
i =n+ 2
p(nq)
Noise mean value -δ/2 +δ/2 nq

+δ / 2
1
E{nqr } =
δ
∫
− /2
nqr
δ
dnqr = 0 Ideal characteristic
δ2 2−2 n 2
Noise variance (power) σ 2
qr = E{nqr } − [ E{nqr }] =
2 2
= U ref
12 12
35
Round-ceiling quantization qk = ak
∞
U qm = δ U + U qt = U ref (2 −n
+ ∑ 2− i bi )
i =1
= ( N t + 1)δ U = N m δ U
Quantization noise
∞
nqm =U −U qm =U ref (− 2 + ∑ 2 − i bi )
−n
i = n +1
Noise mean value p(nq)

0
1 δ
E{nqm } = ∫
−δ
nqm
δ
d nqm = −
2 -δ 0 nq
Noise variance (power)

δ2
2−2 n 2
σ 2
= E{nqm 2
} − [ E{nqm }] =
2
= U ref
qm
12 12 Ideal characteristic
36
Noise value as: voltage (rms, p-p), LSB (rms, p-p), SNR;
Signal to quantization noise ratio (SNR)
Considering a periodic signal at input, with period T, having power:
T
1
Px = ∫ x 2 ( t ) dt = U x2_ ef
T 0
⎛P ⎞ ⎛ U x2_ ef ⎞ ⎛ 12 ⋅ U x2_ ef ⎞ ⎛ 2 n 12 ⋅ U x2_ ef ⎞
SNR ( n ) = 10 ⋅ log ⎜ x ⎟ = 10 ⋅ log ⎜ 2 ⎟⎟ = 10 ⋅ log ⎜⎜ ⎟⎟ = 10 ⋅ log ⎜⎜ 2 ⋅ ⎟⎟
⎜ Pn ⎟ ⎜ σ
⎝ δ
2 2
⎝ q ⎠ ⎝ q ⎠ ⎠ ⎝ U ref ⎠
⎛ U x _ ef ⎞
= 6, 02 ⋅ n + 10,8 + 20 ⋅ log ⎜
⎜ U ⎟⎟
[dB]
⎝ ref ⎠
Total SNR after quantization process:
For analog noisy signal, the total noise power is σ T = σ a + σ q
2 2 2
U x2_ ef ⎛ σ a2 ⎞
effective bit number : nef = log 4 = n − log 4 ⎜1 + 2 ⎟⎟
σ T2 ⎜ σ
⎝ q ⎠
37
U ref
Example: a full range sine wave input x ( t ) = A sin (ωt ) A≅
2
2
1 2
T
A 2 U
Px = ∫ x ( t ) dt =
ref
Signal power and rms value: = U x _ ef =
2
T 0 2 8
⎛P ⎞ ⎛ A 2 ⎞
⎛ 6 A 2
⎞ ⎛ 3 ⋅ U 2
⎞
SNRq ( n ) = 10 ⋅ log ⎜ x ⎟ = 10 ⋅ log ⎜ 2 ⎟ = 10 ⋅ log ⎜ 2 ⎟ = 10 ⋅ log ⎜
ref
⎜ 2σ ⎟ ⎜ ⎟⎟
⎜ Pn ⎟ ⎝ δ ⎠ 2 ⋅ 2 −2 n
U 2
⎝ q⎠ ⎝ q⎠ ⎝ ref ⎠
SNRq ( n ) = 6.02 ⋅ n + 1.76 dB (for sinwave quantization)
Smax
Dynamic range: DR = 20 ⋅ lg = 6, 02 ⋅ n + 1.76 dB=SNRq
S min
ENOB = ( DR − 1, 76 dB ) / 6.02
Example: S N R q (1 0 b it ) = 6 2 d B
A2 1 ⎛ σ a2 ⎞
total effective bit number: nef = log 4 2 + log 4 = n − log 4 ⎜ 1 + 2 ⎟⎟
σT 3 ⎜ σ
⎝ q ⎠
38
Non-ideality errors
Static errors
Offset error (linear error);
Gain error (linear error);
Full-Scale error (offset error + gain error) ;
Integrated nonlinearity error (INL);
Differential nonlinearity error (DNL);
Dynamic error:
Aperture error (due to the delay between
the clock signal of S/H block and the effective holding time)
For sin wave input x( t ) = Asin (ωt )
d x(t )
EA = TA < δ V ⇒ TA = n 1
dt 2 2 πf
39
Offset error
Gain error
Factor scale error
INL error DNL error
40
Effects of static errors and quantizing error (examples)
An ideal three-bit quantizer, with An ideal three-bit quantizer, with

+0.6 LSB offset error a gain of 1.25 instead of 1.00
.
An ideal three-bit quantizer, with INL An ideal three-bit quantizer, with
error caused by important DNL error INL error and small DNL error
41
Improving A/D conversion techniques

Antialiasing
Oversampling
Signal
filter Imagine
spectrum
spectrum
Quant.
OSR – oversampling ratio noise
fS fS
OSR = =
f S min 2⋅ f sig
SNRq (n) =6.02⋅n +1.76+10⋅log(OSR)
Dithering – adding a small amount

of random noise (maximum = 1/2·δU) Nyquist rate ADC Oversampling ADC
to the input before conversion (for constant
and slow varying analog signal).
LSB oscillates randomly between 0 and 1
in the presence of very low input levels.
42
Acronyms for A/D converter

SNR - Signal to (quantization) Noise Ratio;
THD – Total Harmonic Distortion (due nonzero INL) = the ratio of the
rms value of the fundamental signal to the mean value of the root-sum-
square of its harmonics (usually the first five harmonics); Specified in
dBc (decibels below carrier);
SINAD (dBc) - Signal-to-Noise Plus Distortion ratio (same as SNDR) =
ratio of the rms value of the fundamental signal to the mean value of
the root-sum-square of its harmonics plus all noise components;
SNDR - Signal to Noise + Distortion Ratio;
SFDR - Spurious Free Dynamic Range = the ratio of the rms value of
the signal to the rms value of the worst spurious signal (that may be or
may not be an harmonic of the original signal );
⎡ ⎛ U x _ ef ⎞⎤
⎢ SNR [dB] - 10,8 dB-20 ⋅ log ⎜ ⎟⎟ ⎥
⎢ ⎜ U
n=⎢ ⎝ ref ⎠⎥
ENOB - Effective Number of Bits: 6,02 ⎥
⎢ ⎥
⎢ ⎥
⎢ ⎥
FOM – ADC Figure of Merit : FOM = Power [Joule/level resolved]
2 ENOB fS
43
SFDR is an important specification in communications systems because it
Input Tone
input tone
harmonics
Quantization Noise
Other quantization impairments:

• SFDR intermodulation products
• Harmonics
• intermodulation products
44
A/D converter structures

Without integration
Without feedback
Time-stretch ADC (optical ADC)
Charged – coupled device ADC (CCD-ADC)
Time-interleaved ADC accuracy speed
Flash ADC (direct conversion)
Folding ADC (Two-step ADC)
Pipelined ADC (serial ADC)
With feedback
Successive approximation ADC (SAR)
Ramp-compare ADC
Delta-encoded ADC
With integration
Sigma-delta ADC
ADC with intermediate FM stage
Integrating ADC (single-slope, dual-slope, multiple slope)
45
Flash ADC
• bank of 2n -1 parallel comparators (high complexity);
• very fast - GHz sampling rates (limited only by
delays of comparators and logic network);
• references – resistor ladder
Digital
• few bits of resolution (4 – 8 bits, rarely 10 bits)
• high input capacitance Input DOUT
• expensive power / area (in IC)
backend
• are prone to produce glitches (clock skew –
comparators sample the inputs at different instants)
• high cost
• applications: video, wideband communications,
optical storage
clock
46
Flash ADC
Improving technique – track / hold
• T/H for good dynamic performance
• Offset correction in comparators
Input
Track / Hold
DOUT
Example: AD9066 Dual 6-bit, 60MSPS
Flash ADC
Key specifications:
• Input Range: 500mV p-p
• Input Impedance: 50kΩ || 10pF
• ENOB: 5.7 bits @15.5MHz Input Offset
correction
• On-Chip Reference
• Power Supply: Single +5V
• Package: 28-pin SOIC
• Ideal for Quadrature Demodulation
47
“Interpolating” Flash ADC

reduces the number of comparator
preamplifiers at the input of a Flash
converter by a factor of two;
substantially reduces the input
capacitance, power dissipation, area of
flash converters;
preserves the one-step nature of a Flash
architecture ( VLSI technology);
48
Time-interleaved ADC (TI-ADC)
• uses M parallel flash ADCs;

• ADC sample data every M-th cycle of
the effective sample clock;
• sample rate is increased M times;
• complexity is increased M times;
• requires correction of time-
interleaving mismatch errors;
• applications: video, wideband
communications, optical storage;
49
Folded Flash ADC (two steps) INPUT

FOLDING FINE
• Folding = technique that reduces hardware CIRCUIT ADC NF
• maintaining the fast nature of a full Flash

ADC; COARSE DIGITAL ADDER &
• An analogue pre-processing circuit ADC CORRECTION CIRCUIT
generates a residue which is digitised to NC

obtain the LSBs; DIGITAL OUTPUT
WORD
• The MSBs are resolved using a coarse
ADC that operates in parallel with the folding
circuit;
• increase latency;
• Folded ADC reduces latches and logic: Folding principle
NC+NF bits need 2Nc+2Nf-2 comparators;
• First stage determine the output sign;
• At every stage (except the last) the LSB
is wasted; NC + 1 bits NC bits N F bits
50
Serial/Parallel ADC (pipelined)

uses more steps of sub-ranging (with same bits number NC);
• one stage
• a coarse conversion is done
• amplifies the difference of the input signal (determined with a DAC), then go
to next stage
• fast conversion - GHz sampling rates;
• data latency greater than flash, but less than SAR
• high resolution with less complexity;
• ADC overload in next stage need Digital Error Correction;
NC + 1 bits NC bits NC + 1 bits NC bits
STAGE 1 STAGE 2
51
Serial/Parallel ADC (pipelined)

• Example: AD 9220/9221/9223 12 bits pipelined ADC
- Latency is four cycles;
- 1 bit overlap between adjacent stages
- accuracy of ADC in stages 1-4 needs 4
bits; 5-th stage needs greater accuracy;
- entire ADC accuracy established by 5-th
stage
Family Members:
• AD9221 (1.25MSPS), AD9223 (3MSPS),
AD9220 (10MSPS)
• Power Dissipation: 60, 100, 250mW,
Respectively
• FPBW: 25, 40, 60MHz, Respectively
• Effective Input Noise: 0.1 LSB RMS (Span =5V)
• SINAD: 71 dB
• SFDR: 88dBc
• On-Chip Reference
• Differential Non-Linearity: 0.3 LSB
• Single +5V Supply
• 28-Pin SOIC Package
52
Serial ADC (1 bit per stage)

• it uses the truncating
quantization in intermediate
stages.
• Example for bipolar case;
Single stage ADC
Obs: don’t confuse with serial

output ADC of other
technologies (flash, SAR,
folded flash, etc )
53
Successive approximation register ADC (SAR)

• SAR = Successive approximation register
• DAC = digital-to-analog converter
• EOC = end of conversion
• SAR = successive approximation register
• S/H = sample and hold circuit
• Vin = input voltage
• Vref = reference voltage
- use a binary search to converge on the

VAX
closest quantisation level
- Binary search:
- select middle element
- If too high select middle element of lower group
- If too low select middle element of upper group
- Repeat until 1 element remains
- Constant conversion time (n cycles)
54
Successive approximation algorithm
Bit 2 = 0
Bit 4 = 0
Bit 3 = 1
VDAC
Bit 1 = 1
Tconv = nT
⋅ CK
Slower than Flash, but far fewer comparators
4 Bit SAC
– allows for higher accuracy
55
Delta - encoded ADC (tracking ADC)

• an up-down counter feeds the DAC; R
_ Up/Dw Num. rev.
sensUP/DOWN
CK
+ CMP Counter
• CMP compares UX and DAC output; Ux [z]
n n
N
• CMP drives U/D counter sens ; I(N) n
DAC
CNA
• use a feedback to adjust the counter;
I(N) IR
• very wide range and high resolution;
• conversion time is dependent of the input signal level (has a guaranteed value
for the worst case);
• introduces granular noise for constant and very low frequency signals;
• can expect overflow error for rapid variable signal;
Granular
noise Overflow
56
Ramp Compare ADC

FC
EOC
• A comparison voltage V(N) is ramped up; CK
Ux
• When the comparison voltage matches +
_
CMP NUM
the sampled voltage (VA) the comparator n

z
SC
N
is triggered – the sampled voltage has
DAC
been determined; V(N)
CNA
VR
• Variable Conversion Time (depends

when ramp signal matches actual signal): UX
- Best case = 1 cycle V(N)
- Worst case = 2n cycles

• Slower than SAR, same accuracy;
57
Sigma-delta ADC
• the output is in the form of a 1 bit serial
bit stream;
• analog input variation proportional to
the duty of the output digital signal;
• Oversampling (sampling freq 16 – 512
times greater than Nyquist rate);
Sigma-delta ADC of the first order
• low complexity;
• presents “granular” noise for constants
and possible overflow error for fast
analog input;
• applications: typical low bandwidth
digital transmission 22KHz(voice in digital
telephone network); recently - ADSL
network access, 1-2MHz (multi-bit ADC
and multi-bit feedback DAC ); digital
audio equipment (16-24 bit resolution,
48kS/s);
Oversampling ADC (Σ-Δ ADC)
58
Sigma-delta ADC
• Quantization noise is
pushed out of the signal
band;
• digital filter eliminates
out of band noise ;
• very high SNR
Signal Quant. Noise
spectrum spectrum
59
Sigma-delta ADC
• better performances for high order
Σ-Δ ADC (second, third, etc.);
• changing LPF (integrator) →BPF we can
reduce the noise mDSP (N0) in band of interest; Second order Σ-Δ ADC
mDSP Spectral noise shaping SNR vs OSR (Σ-Δ)
60
Integrating ADC – single slope

• similar with ramp - compare ADC, but analog
devices
• contain: voltage comparator, digital counter,
sawtooth wave generator
Sawtooth
• Phases: wave gen.
0. Reset counter and sawtooth wave generator

1. Start conversion (SC) – start generator and
counter U
X
2. Finish conversion (FC) – When the comparison

voltage (analog input) matches the output
generator the conversion finish and stop the
counter:
N X = k⋅U X
• Variable Conversion Time (depends when ramp
signal matches actual signal):
- Best case = 1 cycle
- Worst case = 2n cycles
61
Integrating ADC – dual slope

T1 = 2 n TCK , T2 = N '⋅TCK
T1 T1 +t X
1 U t dt = 1
x( )
RC ∫0 ∫ V dt R
RC T1
U x (t ) t n
= x = Nn' ⇒ U x (t ) =VR ⋅∑bi 2 − i =VR ⋅N
VR T1 2 i =1
• Absolute values of R and C don’t affect operation

• Conversion time is given by:
Tconv =(2 n + N ')TCK ≤ 2 n+1TCK
• Digital output word gives average value of UX

during first integration phase
• Can be used to get resolutions exceeding 20 bits
but at lower conversion rates
62
Integrating ADC – dual slope with auto-zero
Phase:
• Phase 1 – auto zero
(K1=0, K2=0)
•Phase 2 – unknown
voltage integrating (K1=1,
K2=1)
•Phase 3 - reference
voltage integrating (K1=2,
K2=2)
63
UX
Dual slope ADC application: digital voltmeter
64
UX
Functioning principle – ICL7106

Switches Phase 0 Phase 1 Phase 2
(AZ)
INPUT open close open
+REF open open funct. of

Vin sign
-REF open open funct. of

Vin sign
AUTO- close open open

ZERO
65
ADC with intermediate FM stage

-UGI
• comprise
• a voltage-to-frequency converter
• a frequency counter to convert
frequency into a digital count
VP =V0 − 1 ∫U x (t )dt
R1C T2
V0 =Vp + 1 ∫U GI dt − 1 ∫U x (t )dt
R2C T1 R1C T1
V0
R
U x = 1 ⋅ 1 ⋅U GI ⋅T1 = K ⋅ f out
T1 +T2 R2
66
UX
Example U-f converter LM331
• Longer integration times allow

higher resolutions;
• the speed of the converter can be
improved by sacrificing resolution;
• few analog devices – high accuracy
• are very popular for low frequency
application with remote analog
sensor;
Vin RS 1
f out = ⋅ ⋅
2.09V RL Rt Ct
67
Application. Remote analog voltage measurement with LM331

(National Semiconductor)
linie lunga
(transmisie la distanta)
Remote transmission
Ux U-f f-U Ux
Vin R RL
f out = ⋅ S⋅ 1 Vout = f in ⋅2.09 ⋅ ⋅ Rt Ct
2.09V RL Rt Ct Tx Tx to
Catre f-metru
f-metru RS
68
Ultra-fast ADC
Pure electronic ADC: CCD-ADC;
Optical ADC : Time-stretch ADC.
• CCDs - ADC
Charged-Coupled device (CCD) - sampled analog clocked delay line that
memories the input voltage at the clock impulse (analogical memory);
Typically size – 512 stages (samples) and 100MS/s;
An slower ADC quantizes these analogical values;
For greater effective sample rate (400MS/s) are necessary several CCDs
in parallel with staggered clock drive.
Application – digital video signal capturing
69
Ultra-fast ADC
CCD matrix scheme
CCD output waveform
70
Ultra-fast ADC – electronic ADC

• CCD - ADC
Correlated double sampling (CDS) minimise
switching noise at output
71
Ultra-fast ADC – optical ADC
• Electronic (pure) real-time analog-to digital conversion is limited to onversion

rates of few GS/s;
• Communication, image processing and radar applications require extremely
fast real time A/D conversion;
• A way out of this conversion bottleneck may be the use of photonic concepts
for A/D conversion;
Concept for ADC optical conversion:
• Photonic time stretching converter;
• Self-Electro-optic Effect Device based all-optical A/D conversion;
• Optical folding-flash converter;
• Optoelectronic thyristor based photonic smart comparator;
72
Ultra-fast ADC – optical ADC (cont’d)

Absolute analog to digital conversion rate limits for a required SNRq
73
Ultra-fast ADC – optical ADC

• Time-stretch ADC (TS-ADC) Digitizes a very wide bandwidth analog
signal by time-stretching the signal prior to digitization using a photonic
preprocessor.
• Improvements:
• Effective sampling rate increased by M ;
• Effective Input bandwidth increased by M ;
• Reduce jitter noise ;
• Eliminates the need for samples interleaving ;
• Ideal for time-limited signals or fast time-varying signals ;
74

• Schematic photonic preprocessor for time-stretching
• Each ADC see the slowed-down signal;
• Full Nyquist sampling by each ADC;
• By allowing for finite overlap between segments, mismatch error can be
estimated from the signal itself;
Δλ1 x4 Digitizer
WDM
T
Δλ2
PRISM
Digitizer
x4
Δλ3 Digitizer
Time/ wavelength
Time x4
Δλ4
Δλ3
Δλ2 Δλ4 Digitizer
Δλ1 x4
T TI-ADCs
Time Stretch 4T
T
75

Photonic Time Stretch System
Stretched Signal
Wavelength
Input RF
Signal
Dispersion BWChirp Dispersion

Time
SC PD
Modulator
Source
L1 L2
SC Optical Pulse Chirped Optical Pulse
Stretch Factor = 1 + L2 / L1
Time Aperture = D x Δλ x L1
Baseband BW* = 1 /(8πβ 2 L1 )
Time BW Product* = Δf op / 2Δf RF
76

Mismatches in TS-ADC Arrays
Tseg
2π L −1
kωs
Offset
S (ω ) =
Ts
∑ Fk × δ (ω −
k =0 L
)
Mismatch sin
πkN
Analog Signal Fk =
1⎡ M −1
∑ bm exp(− j
2πkm ⎤
)⎥ × L ⋅ exp⎡− j πk ( N − 1) ⎤
⎢
L ⎣ m =0 M ⎦ πk ⎢ L ⎥
sin ⎣ ⎦
L
Gain
2π L −1
kωs
Mismatch S (ω ) =
Ts
∑ Fk ×δ (ω − ωo −
k =0 L
)
Clock 1 ∞
kω s
Skew S (ω ) =
Ts
∑
k = −∞
Fk × δ (ω − ω0 −
L
)
πkN
sin
1⎡ M −1
2πkm ⎤ L × exp ⎡− j πk ( N − 1) ⎤
Fk = ⎢ ∑
L ⎣ m=0
exp(− jω0 rmTs ) exp(− j )⎥ ×
M ⎦ sin πk ⎢
⎣ L ⎥
⎦
L
L=MxN: the period of distortion pattern
77

Mismatches in TS-ADC Arrays – Spectrum
Offset Error Gain Error or Clock Skew
Spurs at harmonics of Sidebands at multiples of
fsignal/(MxN) fsignal/(MxN) centered at fsignal
signal signal
spurs fs/(MxN)
-fsignal 0 fsignal Freq. -fsignal fsignal Freq
Overlap between segments

Slight redundancy in sampling could Digitizer 1 (S1) Digitizer 2 (S2)
(time overlaping) significantly improve
the ADC performance;
Overlap
78

•Time-stretch ADC (TS-ADC)
• ADC SFDR Improvements
RMSE SFDR RMSE SFDR
(before) (before) (after) (after)
Offset 4% -36dBc 0.3% -58dBc
Gain 4% -36dBc 0.35% -57dBc
Clock
8% -26dBc 0.45% -51dBc
Skew
• Conclusions:
• Signal is reconstructed based on segments, instead of the individual
samples;
• In each segment, the sampling is above the Nyquist sampling rate;
• Subject to the similar mismatch as the sample-interleaved counterpart;
79
Bibliography
S. Ciochina, Masurari electrice si electronice, 1999 ;
ham.elcom.pub.ro/iem;
Application notes - National Instruments;
J.G. Webster, Electrical Measurement, Signal Processing and Displays,
2004;
80

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Digital to Analog Converter

Analog to Digital Converter

Digital to Analog Converter

 Function: converts binary input number in analog output;

 Binary coding (sub-unitary, N<1)

 Natural binary (unsigned)

 Offset binary (signed)

 Binary coding (cont’d)

 Binary coded decimal (BCD) – 4 bits (nibble) used to

Binary codes conversion

Binary codes conversion

 Ideal characteristic for unipolar DAC :

 Ideal characteristic for bipolar DAC

δ U = U R ⋅ 2− n 0 1/8 4/8 7/8

Offset error Gain error

D/A converter – traditional data converter at Nyquist

- LPF is antialiasing filter (for extinction of image signal on fS ) ;

D/A converter – mathematical representation:

F { y sh (t )}=F ⎨ ∑ y(nTS )⋅δ (t −nTS )⎬ ⋅ F { p(t )}

For w = TS (practical DAC converter) -fm fm

-fS -fm fm fS 1/w

Binary-Weighted Resistor DAC

Using Tellegen’s theorem: 1

Vg ( N ) =VR ∑bi 2−i =VR ⋅N 1

Vg _min =Vg ( 0...0h) =0V δVg =Vg ( 0...1h) =2−n VR 0 R(N)

Vg _max =Vg ( F...Fh) =VR (1−2−n )

Binary-Weighted Resistor DAC (cont’d)

Steady state current command

Binary-Weighted Resistor DAC (cont’d)

• Larger bit numbers difficult due desired current changes being

R-2R ladder network DAC

R-2R ladder network resistor DAC (cont’d)

• Maintains constant current through all branches = no voltage

Stochastic DAC (without resistor network)

N sub-unitary number (N1 supra-unitary )

• binary code on digital input → command for controlled amplification /

• Industrial Control Systems

• Waveform Function Generators

Example 1: Digital to analog converter (8 bits) - DAC 08

Example 2: Inversion amplifier with digital adjustment gain

 Function: converts input analog signal into a digital signal;

 Mathematical representation of ADC Function:

A/D Converter – traditional data converter at Nyquist rate

Successive operations for AD conversion process.

Sampling process (remember)

Sampling process (cont’d)

x(t ) → xs (t ) = x(t ) pTS (t )

⋅sinc(nπ )=(−1) ⋅sinc(nπ )

Sampling process (cont’d)

P( f ) = F { p(t )}=TS ⋅e − jπ fTS ⋅sinc(π f TS )

Sampling rate is given in Samples/s

Sampling & quantizing process

• Quantization – uniform (constant step) – linear ADC

Quantization noise p(nq)

Noise variance (power)

Noise mean value -δ/2 +δ/2 nq

Noise mean value p(nq)

Noise variance (power)

For sin wave input x( t ) = Asin (ωt )

INL error DNL error

 Effects of static errors and quantizing error (examples)

An ideal three-bit quantizer, with An ideal three-bit quantizer, with

 Improving A/D conversion techniques

Function: converts binary input number in analog output;

Binary coding (sub-unitary, N<1)

Natural binary (unsigned)

Offset binary (signed)

Binary coding (cont’d)

Binary coded decimal (BCD) – 4 bits (nibble) used to

Ideal characteristic for unipolar DAC :

Ideal characteristic for bipolar DAC

Function: converts input analog signal into a digital signal;

Mathematical representation of ADC Function:

Effects of static errors and quantizing error (examples)

Improving A/D conversion techniques

Dithering – adding a small amount

Acronyms for A/D converter

A/D converter structures

“Interpolating” Flash ADC

Time-interleaved ADC (TI-ADC)

Folded Flash ADC (two steps) INPUT

Serial/Parallel ADC (pipelined)

Serial/Parallel ADC (pipelined)

Serial ADC (1 bit per stage)

Successive approximation register ADC (SAR)

Successive approximation algorithm

Delta - encoded ADC (tracking ADC)

Ramp Compare ADC

Integrating ADC – single slope

Integrating ADC – dual slope

Integrating ADC – dual slope with auto-zero

Dual slope ADC application: digital voltmeter

Functioning principle – ICL7106

ADC with intermediate FM stage

Example U-f converter LM331

Ultra-fast ADC – electronic ADC

Ultra-fast ADC – optical ADC

Ultra-fast ADC – optical ADC (cont’d)

Ultra-fast ADC – optical ADC

Ultra-fast ADC – optical ADC (cont’d)

Ultra-fast ADC – optical ADC (cont’d)

Ultra-fast ADC – optical ADC (cont’d)

Ultra-fast ADC – optical ADC (cont’d)

Overlap between segments

Ultra-fast ADC – optical ADC (cont’d)