Chapter 15

Digital Signal Processing

The trend today in receiver design is toward
digital signal processing. This powerful tech-
nique frees the receiver of drift problems in-
volving temperature and power supply
voltage excursions. Today, the small size of
large-scale integration digital integrated cir-
cuits makes it possible to deliver receivers that
could be only dreamed of a generation ago.
Although the goal is to get the analog-
to-digital converter (ADC) as close to the an-
tenna as possible, most receivers today fit the
schema shown in Figure 15.1. From the IF
amplifier two paths can be taken by the digi-
tal designer.
First, you could demodulate the IF sig-
nal and do the signal processing at audio. In
that way, a simple, low-cost ADC is used
(indeed, maybe even your computer’s
sound card). A digital-to-analog converter
(DAC) is used to convert the signal back to
audio. About the only thing that can be
done after the demodulator is filtering and
audio AGC.
Second, the processing takes place at the
IF frequency. The ADC must be considerably
better than in the audio case, but this permits
utilizing the digital circuitry to demodulate the
IF signal. It also permits using I-Q quadrature

A/D DIGITAL D/A AUDIO

DEMODULATOR
CONVERTER PROCESSING CONVERTER OUTPUT

IF
AMPLIFIER

A/D DIGITAL D/A AUDIO

CONVERTER PROCESSING CONVERTER OUTPUT

Fig. 15.1 Digital signal processing schema.

227
228 THE TECHNICIAN’S RADIO RECEIVER HANDBOOK

processing techniques. After the ADC, there

will be a digital processing stage and a DAC to +VMAX
reconvert the signal to audio.
3Q
It is worth noting that, in radar re-
2Q
ceivers, a significant increase in sensitivity is
available because we can integrate a number Q

of pulses (N). In coherent processing, the IF

is converted and the increase in sensitivity is -Q
N, but in noncoherent processing (after the -2Q
demodulator), it is N. -3Q
Another advantage of using the micro-
-VMAX
processor to control the receiver is that all
the tuning, bandwidth, gain, and control
functions can be implemented through the
microprocessor. The user’s decisions on
which of these to invoke are registered in the
microprocessor and relayed to the circuits ERROR
under control.

ADC NOISE
Fig. 15.2 Quantizing error of the signal.
All reception is a problem of signal-to-noise
ratio (SNR). The ADC must add minimally to
the noise produced in the receiver or the Table 15.1 Quantization Noise Voltage
design will fail. The sampling rate (number N Bit Decibels
of samples per second taken by the ADC) 6 −20
must be high enough to demodulate the 8 −41
bandwidth being handled. Nyquest’s theo-
10 −53
rem tells us that the data sampling rate must
be twice the nominal bandwidth being re- 12 −63
ceived, but because filters have no straight 16 −97
edges, the actual rate will be up to 2.5 times 20 −125
the bandwidth. The width of the sampling
pulse must be small compared to the period
of the highest frequency within the receiver comes too large, then there will be a hard
passband. clipping action taking place at ±NQ, and the
The ADC will add little inherent noise automatic gain control circuits must be bal-
of its own at the IF frequency, but as it gets anced to eliminate this problem. The root
closer to the antenna, with its smaller signal mean square value of the quantizing voltage
levels, the percentage of the total becomes is given in Table 15.1.
higher and higher. As a result, IF processing
probably will be the standard for some time
to come. RECEIVER ARCHITECTURES
Figure 15.2 shows the quantization er-
ror noise that will be encountered in the Figure 15.3 shows the layout of a simple
ADC. The top curve is an input/output single-conversion receiver based on digital
curve, whereas the bottom curve is a repre- techniques. The front end of the receiver
sentation of the error. Each step of the ADC consists of the bandpass filtering, RF ampli-
output is QV high. If the input signal be- fying, and mixing functions. It is driven by a

IF
FRONT END
AMPLIFIER
AGILE
FREQUENCY
SYNTHESIZER
MICROPROCESSOR
Fig. 15.3 Digital receiver block diagram.
number of signals. The RF signal from the
antenna drives the input of the front-end
circuitry.
There will be control signals for select-
ing the bandpass filtering and automatic gain
control for the RF amplifier. Sometimes, a
selectable attenuator will be in the circuit
as well.
Finally, there is the local oscillator cir-
cuit. In this case, the LO is an agile digital
frequency synthesizer controlled by the mi-
croprocessor.
The microprocessor also controls the IF
amplifier gain through an AGC function. The
IF amplifier produces an output signal that
almost fills up the ADC in the digital receiver
section when a strong signal is received at
the antenna. Finally, the digital receiver sec-
tion demodulates the signal and applies it to
the audio amplifiers for output to the loud-
speaker or earphones.
The microprocessor controls the front
end, the local oscillator (agile frequency syn-
thesizer), IF amplifier, and digital receiver
section. User inputs on the front panel of the
receiver determine which function is to be
used.
Figure 15.4 shows a block diagram of a
high-frequency, double-conversion digital re-
ceiver. The microprocessor controls are not
shown here but nonetheless are present. The
front end of the receiver consists of an atten-
Digital Signal Processing 229
DIGITAL AUDIO
AUDIO
RECEIVER OUTPUT
uator, low-pass or bandpass filter, and a
mixer/local oscillator. In this case, the LO is a
digital frequency synthesizer.
At the output of the mixer are a band-
pass filter and a noise blanker. The noise
blanker punches a hole in the signal at the
+10 dB amplifier whenever a noise impulse
is received. The output of the bandpass filter
feeds a +10 dB amplifier, and the output of
that amplifier is mixed with a signal from a
local frequency standard (which also serves
the digital frequency synthesizer). This pro-
duces the second IF signal, which is the high
gain (50–90 dB) stage.
Following the second IF is the ADC.
This stage outputs digitized signals to the
quadrature multiplier stage, which produces
the I and Q signals needed by the channel fil-
ter and demodulator stage. If the receiver is
to be used digitally, then the I and Q signals
are available as data out lines, but if an audio
output is required, the signal is fed to a DAC
to reform the audio.
Figure 15.5 shows a block diagram of a
somewhat more complex single-sideband re-
ceiver. Again, for the sake of simplicity, I do
not show the microprocessor that controls
the action of the receiver.
The front end consists of the preselec-
tor, mixer stage and a digital frequency syn-
thesizer. The preselector consists of an RF
amplifier and the bandpass or low-pass filter-
230 THE TECHNICIAN’S RADIO RECEIVER HANDBOOK

ANTENNA

NOISE
BLANKER

BANDPASS
LOW-PASS +10 dB
ATTENUATOR MIXER FILTER MIXER
FILTER AMPLIFIER
(15 KHz)

DIGITAL
FREQUENCY
FREQUENCY
STANDARD
SYNTHESIZER

I I
IF CHANNEL Q DATA
A/D QUADRATURE OUT
AMPLIFIER FILTER &
CONVERTER MULTIPLIER
(50 dB) Q DEMODULATOR

D/A AUDIO
CONVERTER OUTPUT

Fig. 15.4 Block diagram of a high-frequency, double-conversion digital receiver.

ANTENNA

IF IF
A/D IF
PRESELECTOR MIXER AMPLIFIER MIXER AMPLIFIER
CONVERTER TRANSLATOR
No. 1 No. 2

DIGITAL FIXED
FREQUENCY FREQUENCY
SYNTHESIZER OSCILLATOR

I DIGITAL
DECIMATION
SSB MIXER MIXER
FILTER
FILTER

BEAT
ENVELOPE D/A AUDIO
DETECTOR
FREQUENCY S CONVERTER OUTPUT
OSCILLATOR

Q DIGITAL
DECIMATION
SSB MIXER MIXER
FILTER
FILTER

D/A AGC
CONVERTER SYSTEM

Fig. 15.5 Block diagram of a complex single-sideband receiver.


ing needed to protect the receiver and im-
prove the intermodulation distortion perfor-
mance. IF amplifier 1 is at the first IF
frequency, which in HF receivers typically is
about 50 MHz. In VHF/UHF receivers, a first
IF of 70, 30, or 10.7 MHz may be used.
The second IF frequency is generated
by the mixer following the first IF amplifier
and the fixed frequency oscillator. This signal
usually is 10.7 MHz, 9 MHz, 8.83 MHz, or 455
kHz, depending on the frequency of the re-
ceiver and the design. The second IF ampli-
fier is the amplifier with the highest gain.
Digital Signal Processing 231
At the beginning of the digital receiver
section is the ADC. The output of the ADC
is fed to an IF translator stage, which pro-
duces the I and Q output signals. Following
the IF translator, the I/Q signals are fed to
decimation filters and a digital SSB filter.
Following the digital SSB filters are a set of
mixers and an envelope detector, which de-
velops the AGC voltage in a DAC circuit.
Finally, the signal is mixed with a beat fre-
quency, then combined to form the input to
the DAC. The output of the DAC is an audio
output signal.