PCS-985T Transformer Protection X Instruction Manual en Demostic General X R1.00 (En YJBH2601.0086.0001)

PCS-985T
Transformer Relay
Instruction Manual Supplement
for Project ECKF110355
NR Electric Co., Ltd.

Supplement for Project ECKF110355
Preface
This document is the supplement of the corresponding general instruction manual of the
equipment mentioned on the cover. It is dedicated to the specific project, and cannot be used in
other projects. If there are some differences between this supplement and the corresponding
general instruction manual, user must refer to this supplement for the designated project.
Copyright
Version: 1.00 NR ELECTRIC CO., LTD.
69 Suyuan Avenue. Jiangning, Nanjing 211102, China
P/N: EN_ YJBH5093.0086.0001.110355 Tel: +86-25-87178185, Fax: +86-25-87178208
Website: www.nrelect.com, www.nari-relays.com
Copyright © NR 2013. All rights reserved Email: NR_TechSupport@nari-relays.com
We reserve all rights to this document and to the information contained herein. Improper use in particular reproduction and dissemination
to third parties is strictly forbidden except where expressly authorized.
The information in this manual is carefully checked periodically, and necessary corrections will be included in future editions. If
nevertheless any errors are detected, suggestions for correction or improvement are greatly appreciated.
We reserve the rights to make technical improvements without notice.
PCS-985T Transformer Relay i

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ii PCS-985T Transformer Relay.

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Table of Content
Preface........................................................................................................................ i
Table of Content....................................................................................................... iii
1 Information about this Application ...................................................................... 1
2 Introduction............................................................................................................ 3
2.1 Protective Functions Configuration ............................................................................................ 3
3 Operation Theory................................................................................................... 5
3.1 HV Side Phase Overcurrent Protection ..................................................................................... 5
3.2 HV Side Ground Overcurrent Protection.................................................................................... 6
4 Hardware .............................................................................................................. 13
4.1 Plug-in Module Terminal Definition........................................................................................... 13
5 Human Machine Interface ................................................................................... 17

5.1 Understand the LCD Display .................................................................................................... 17
6 Settings ................................................................................................................ 21
6.1 General Settings....................................................................................................................... 21
6.2 Implicit internal Settings ........................................................................................................... 24
6.3 Protection Settings ................................................................................................................... 26
6.4 Device Setup ............................................................................................................................ 42
7 Manual Version History ....................................................................................... 47
PCS-985T Transformer Relay iii

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iv PCS-985T Transformer Relay.

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1 Information about this Application

The following table gives the information about the application of this supplement which must be
used with corresponding general instruction manual for the applied-specific project.
Project ECKF110355
SUBQ SUBQ00124177
Software version PCS-985T R1.00_ECKF110355
Corresponding general PCS-985T_X_Instruction Manual_EN_Domestic General_X_R1.00_

instruction manual version (EN_YJBH5093.0086.0001)
PCS-985T Transformer Relay 1

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2 PCS-985T Transformer Relay.

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2 Introduction
2 Introduction
2.1 Protective Functions Configuration
According to the requirement of this project, following protective functions are configured with the
protection relay, and the functions which are not mentioned in this section are not equipped for
user’s protection relay.
Table 2.1-1 Protective functions in PCS-985T
Protective function
Transformer biased current differential protection 87T
Transformer unrestrained current differential protection 50/87UT
Restricted earth fault protection of HV side 64REF
Restricted earth fault protection of LV side A 64REF
Restricted earth fault protection of LV side B 64REF
Stub differential protection 87S
Overexcitation protection 24
Voltage controlled phase overcurrent protection of HV side 50/51P
Negative-sequence overcurrent protection of HV side 50/51Q
Voltage controlled phase overcurrent protections of each branch at

50/51P
LV side
Ground overcurrent protections of LV side A(B) 50/51G
Stub overcurrent protection 50/51P
Residual overvoltage alarm of LV side A(B) 59G
Overload alarm 49
Cooling initiation function 49
On-load tap change (OLTC) blocking function during overload 49
CT saturation detection
Inrush current detection
Overexcitation detection
Harmonic blocking function
VT circuit failure supervision VTS
CT circuit failure supervision CTS

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2 Introduction
NOTE! Please replace the Table 1.2-1 in the Section 1.2 of the general instruction
manual with the above table in this section.

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3 Operation Theory
3 Operation Theory
3.1 HV Side Phase Overcurrent Protection
Voltage controlled overcurrent protection of HV side is replaced by negative-sequence

overcurrent protection of HV side, the operation principle of which is shown below.
3.1.1 Negative-Sequence Overcurrent Protection

Negative-sequence overcurrent protection is applied as backup protection of transformer, and two
stages are equipped. Negative-sequence current of HV side of transformer is adopted for the
protection calculation. Negative-sequence voltage is selectable to control negative-sequence
overcurrent protection to prevent maloperations during CT circuit failure.
 Logic
Two stages have similar logics and the logic of stage 1 is taken as an example shown below.
SIG U2>1V ≥1
SET [En_NegOV_Ctrl_NegOC_HVS]
SIG I2>[I_NegOC1_HVS]
BI [EBI_PPF_HVS] & &

[t_NegOC1_HVS] 0s
[Op_NegOC1_HVS]
SET [En_PPF_HVS]
SIG Flg_En_NegOC1_HVS
SIG FD_NegOC1_HVS
Figure 3.1-1 Logic diagram of stage 1 of negative-sequence overcurrent protection
Where
U2: the negative-sequence voltage of HV side.
[En_NegOV_Ctrl_NegOC_HVS]: the logic setting of enabling negative-sequence overcurrent

protection being controlled by negative sequence voltage.
I2: the negative sequence current of HV side.
[EBI_PPF_HVS]: the binary input of enabling the phase-to-phase fault backup protection of HV
side.
[En_PPF_HVS]: the logic setting of enabling the phase-to-phase fault backup protection of HV
Flg_En_NegOC1_Tr: the internal flag indicating that negative-sequence overcurrent stage 1 is

enabled by configuring the logic setting [TrpLog_NegOC1_HVS].
FD_NegOC1_HVS: the fault detector of stage 1 of negative-sequence overcurrent protection of

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3 Operation Theory
HV side picks up. The fault detector will pick up if negative-sequence current of HV side is greater
than the current setting.
[I_NegOC1_HVS]: current setting of stage 1 of negative-sequence overcurrent protection of HV

side.
[t_NegOC1_HVS]: time delay of stage 1 negative-sequence overcurrent protection of HV side.
[Op_NegOC1_HVS]: the operation flag of stage 1 negative-sequence overcurrent protection of

HV side.
3.2 HV Side Ground Overcurrent Protection
For the project, calculated residual current is fixedly used for the calculation of stage 1
definite-time ground overcurrent protection and neutral current is fixedly adopted for the
calculation of stage 2 definite-time ground overcurrent protection and inverse-time overcurrent
protection.
3.2.1 Definite-Time Ground Overcurrent Protection

Following functions of two-stage definite-time ground overcurrent protection relay can be selected
by configuring corresponding logic settings:
 Whether or not be controlled by directional element.
 Whether or not be controlled by residual voltage.
 Breaker(s) at what side or sides will be tripped.
Operation criterion of definite-time ground overcurrent protection
3I 0 _ Cal  [I_ROC1_Cal_HVS]
Equation 3.2-1
3I 0 _ NP  [I_ROC1_NP_HVS]
Where:
3I 0 _ Cal is the calculated residual current of HV side.
3I 0 _ NP is the neutral current of HV side.
[I_ROC1_Cal_HVS] is the setting of ground overcurrent protection with calculated residual current
of the HV side.
[I_ROC1_NP_HVS] is the setting of ground overcurrent protection with neutral current of the HV
side.
3.2.2 Inverse-Time Ground Overcurrent Protection

There are four inverse-time curves selectable for inverse-time overcurrent protection and they are

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3 Operation Theory
“IEC Normal inverse”, “IEC Very inverse”, “IEC Extremely inverse” and “IEC Long-time inverse”.
The inverse-time operating time curve is as follows. Neutral current is adopted for the calculation.
K  Tp
t 
 I  Equation 3.2-2
   1
 I set 
Where:
I set is the operating current, i.e. [Ib_InvROC_NP_HVS].
Tp is time multiplier setting [TMS_InvROC_NP_HVS].
K is a constant.
 is a constant.
The user can select the operating characteristic from four inverse-time characteristic curves by
setting [Opt_InvROC_HVS], and parameters of available characteristics for selection are shown in
the following table.
Table 3.2-1 Inverse-time curve parameters
Time Characteristic K α
IEC Normal inverse 0.14 0.02
IEC Very inverse 13.5 1.0
IEC Extremely inverse 80 2.0
IEC Long-time inverse 120 1.0
3.2.3 Residual Voltage Control Element (RVCE)

 Operation criterion of RVCE
3U 0  [ V_ROV_VCE_HVS] Equation 3.2-3
Where：
3U 0 is the residual voltage of HV side.
[V_ROV_VCE_HVS] is the setting of residual overvoltage element for controlling the ground
overcurrent protection of the corresponding side.
 ROC being controlled by RVCE of local side

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3 Operation Theory
The logic setting [En_VCE.ROV_Ctrl_ROC1_Cal(NP)_HVS] is used to select whether some stage

ground overcurrent protection is controlled by residual voltage control element. For example
[En_VCE.ROV_Ctrl_ROC1_Cal(NP)_HVS], if this logic setting is set to 1, ground overcurrent
protection will be controlled by the RVCE of HV side. Otherwise it will not.
 Zero-sequence voltage used by RVCE
Residual voltage from broken-delta VT of HV side is fixed as the voltage used by residual voltage
control element.
3.2.4 Residual Directional Element (RDE)

The logic setting [Opt_Dir_ROC_HVS] is used to select the direction of every stage of ground
overcurrent protection. If this logic setting is set to 1, the direction is transformer and reach angle
is 225º. If this logic setting is set to 0, the direction is power system and reach angle is 75º. Figure
3.2-1 shows operating characteristic of directional protection where the hatched area is operation
zone.
In addition, the logic setting [En_Dir_Ctrl_ROC1_Cal(NP)_HVS] is used to select whether the

corresponding ground overcurrent relay is controlled by directional element. If this logic setting is
set to 1, the corresponding ground overcurrent protection will be controlled by directional element.
Otherwise, it will not.
3I0
3U0 3U0
φRCA=255°
φRCA=75°
3I0
a) Direct to power system b) Direct to transformer
Figure 3.2-1 Operating characteristic of residual directional element
NOTE: The residual voltage and residual current used by directional relay are definitely
the calculated residual voltage and calculate residual current. The direction mentioned
above is based on the assumption that positive polarity of three-phase CT for calculating
residual current is at the side of busbar.
3.2.5 Influence of VT Circuit Failure on RVCE and RDE

The logic setting [Opt_VTS_Ctrl_ROC_HVS] is used to control performance of residual directional
element and residual voltage control element during VT circuit failure.
---When this logic setting is set to 1, if VT circuit failure of a side is detected, the residual voltage

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3 Operation Theory
control element and residual directional element cannot operate to release the residual
overcurrent relay.
---When this logic setting is set to 0, if VT circuit failure of a side is detected and the operation
criterion of residual voltage control element or residual directional element are met, the
corresponding element can still operate to release the protection at local side.
3.2.6 Logic
3.2.6.1 Logic of Definite-Time Ground Overcurrent Protection
Ground overcurrent protection with calculated residual current and the ground overcurrent
protection with neutral current have the same logic diagram and here ground overcurrent
protection with calculated residual current is taken as an example to show the logic diagram.
SIG 3U0>[V_ROV_VCE_HVS] &
SIG Flg_VTS_HVS ≥1
&
Flg_RVCE
SET [Opt_VTS_Ctrl_ROC_HVS]
≥1
SET [En_VCE.ROV_Ctrl_ROC1_Cal_HVS]
SIG Flg_Direction_ROC_HVS &
SIG Flg_VTS_HVS ≥1
&
Flg_RDE
SET [Opt_VTS_Ctrl_ROC_HVS]
≥1
&
[t_ROC11_Cal_HVS] 0s
[Op_ROC11_Cal_HVS]
SET [En_Dir_Ctrl_ROC1_Cal_HVS]
[t_ROC12_Cal_HVS] 0s
[Op_ROC12_Cal_HVS]
SIG 3I0_Cal>[I_ROC1_Cal_HVS]
BI [EBI_EF_HVS] &
SET [En_EF_HVS]
SIG Flg_En_ROC1_Cal_HVS
SIG FD_ROC1_Cal_HVS
Figure 3.2-2 Logic diagram of definite-time ground overcurrent protection with calculated residual current
Where:
3U 0 : the residual voltage of HV side.
3I 0 _ Cal : the calculated residual current of HV side.
[V_ROV_VCE_HVS]: the voltage setting of residual voltage control element of HV side.
Flg_VTS_HVS: the internal flag indicating that VT circuit failure of HV side is detected.
[Opt_VTS_Ctrl_ROC_HVS]: the logic setting of selecting how HV side ground overcurrent

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3 Operation Theory
protection responses when VT circuit failure is detected.
[En_VCE.ROV_Ctrl_ROC1_Cal_HVS]: the logic setting of enabling residual voltage control

element to control ground overcurrent protection of HV side with calculated residual current.
[En_Dir_Ctrl_ROC1_Cal_HVS]: the logic setting of enabling directional element to control ground

overcurrent protection of HV with calculated residual current side.
Flg_RVCE: the internal flag indicating the residual voltage control element picks up.
Flg_RDE: the internal flag indicating the residual directional element picks up.
Flg_Direction_ROC_HVS: the internal flag indicating that residual directional element decides the
earth fault is in the protection direction of ground overcurrent protection of HV side.
[EBI_EF_HVS]: the binary input of enabling the earth fault backup protection of HV side.
[En_EF_HVS]: the logic setting of enabling earth fault protection of HV side.
Flg_En_ROC1_Cal_HVS: the internal flag indicating that ground overcurrent protection of HV side
with calculated residual current is enabled by configuring the logic settings
[TrpLog_ROC11_Cal_HVS] and [TrpLog_ROC12_Cal_HVS].
FD_ROC1_Cal_HVS: the pickup of fault detector of ground overcurrent protection of HV side with
calculated residual current.
[t_ROC11_Cal_HVS], [t_ROC12_Cal_HVS]: two time delays of delay 1 and delay 2 of ground

overcurrent protection of HV side with calculated residual current respectively.
[Op_ROC11_Cal_HVS], [Op_ROC12_Cal_HVS]: two operation flags of delay 1 and delay 2 of

ground overcurrent protection of HV side with calculated residual current respectively.
3.2.6.2 Logic of Inverse-Time Ground Overcurrent Protection
IDMT
SIG 3I0_NP >[I_InvROC_NP_HVS] & &
[tmin_InvROC_NP_HVS] 0s
SIG Flg_InvROC_NP_HVS
BI [EBI_EF_HVS] & &

[Op_InvROC_NP_HVS]
SET [En_EF_HVS]
SIG FD_InvROC_NP_HVS
Figure 3.2-3 Logic diagram of inverse-time ground overcurrent protection with neutral current
Where:
3I 0 _ NP : the neutral current of HV side.
[I_InvROC_NP_HVS]: the picking up current setting of inverse-time ground overcurrent protection

of HV side with neutral current.

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3 Operation Theory
FD_InvROC_NP_HVS: the pickup of fault detector of inverse-time ground overcurrent protection

of HV side with neutral current.
[tmin_InvROC_NP_HVS]: the minimum time delay of inverse-time overcurrent protection of HV

side with neutral current.
[Op_InvROC_NP_HVS]: the operation flag of inverse-time ground overcurrent protection of HV

side with neutral current.

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3 Operation Theory

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4 Hardware
4 Hardware
Pin definitions of signal output modules NR1526A at slot 10 and NR1541A at slot 11 are
somewhat different to those in the corresponding general manual, and the detailed definition for
the project is shown below.
4.1 Plug-in Module Terminal Definition
NR1526A
Slot 10
NR1526A
BO_Diff 1002 1001 BO_Diff
BO_PPF_HVS 1004 1003 BO_PPF_HVS

BO_ROC_Cal/REF_ BO_ROC_Cal/REF_
1006 1005
HVS HVS
BO_EF_NP_HVS 1008 1007 BO_EF_NP_HVS
COM 1010 1009 COM
BO_OvExc 1012 1011 BO_OvExc
BO_ROC/REF_Br1 1014 1013 BO_ROC/REF_Br1
BO_ROC/REF_Br2 1016 1015 BO_ROC/REF_Br2
BO_Bak_Br11 1018 1017 BO_Bak_Br11
COM 1020 1019 COM
BO_Resv1 1028 1027 BO_Resv1
COM 1030 1029 COM
Figure 4.1-1 Pin definition of signal output module NR1526A at slot 10
The pin description of NR1526A at slot 10 is shown respectively.
Pin No. Symbol Description

1009 COM Common terminal
1009-1001 BO_Diff The signal output of operation of transformer differential protection
The signal output of operation of phase-to-phase fault protection of
1009-1003 BO_PPF_HVS
HV side
The signal output of operation of ground overcurrent protection
BO_ROC_Cal/REF_H
1009-1005 of HV side with calculated residual current or restricted earth
VS
fault protection of HV side
1009-1007 BO_ROC_NP_HVS
of HV side with neutral current
1019-1011 BO_OvExc The signal output of over excitation alarm

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4 Hardware

The signal output of operation of ground overcurrent protection of LV
1019-1013 BO_ROC/REF_Br1
side A or REF protection of LV side A
side A or REF protection of LV side B
1019-1017 BO_Bak_Br11 The signal output of backup protection of branch A1 at LV side
1029-1023 BO_Bak_Br21 The signal output of backup protection of branch B1 at LV side
1029-1027 BO_Resv1 The reserved signal output 1 for future application
1010-1002 BO_Diff The signal output of operation of transformer differential protection
The signal output of operation of phase-to-phase fault protection of
1010-1004 BO_PPF_HVS
HV side
BO_ROC_Cal/REF_H
1010-1006 of HV side with calculated residual current or restricted earth
VS
1020-1012 BO_OvExc The signal output of over excitation alarm
side A or REF protection of LV side A
side A or REF protection of LV side B

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4 Hardware
NR1541A
Slot 11
NR1541A
1102 1101
RLY01 BO_Diff
1104 1103
1106 1105
RLY02 BO_PPF_HVS
1108 1107
1110 1109
BO_ROC_Cal/REF_H
RLY03
VS
1112 1111
RLY04 1114 1113 BO_ROC_NP_HVS
RLY05 1116 1115 BO_OvExc
RLY06 1118 1117 BO_ROC/REF_Br1
RLY07 1120 1119 BO_ROC/REF_Br2
RLY08 1122 1121 BO_Bak_Br11
RLY09 1124 1123 BO_Bak_Br12
RLY10 1126 1125 BO_Bak_Br21
RLY11 1128 1127 BO_Bak_Br22
RLY12 1130 1129 BO_Resv1
Figure 4.1-2 Pin definition of signal output module NR1541A at slot 11
The pin description of NR1541A at slot 11 is shown below.

1101-1102 BO_Diff_1 The signal output 1 of operation of transformer differential protection
1103-1104 BO_Diff_2 The signal output 2 of operation of transformer differential protection
The signal output 1 of operation of phase-to-phase fault protection of
1105-1106 BO_PPF_HVS_1
HV side
The signal output 2 of operation of phase-to-phase fault protection of
1107-1108 BO_PPF_HVS_2
HV side
The signal output 1 of operation of ground overcurrent
BO_ROC_Cal/REF_H
1109-1110 protection of HV side with calculated residual current or
VS_1
restricted earth fault protection of HV side
The signal output 2 of operation of ground overcurrent
BO_ROC_Cal/REF_H
1111-1112 protection HV side with calculated residual current of or
VS_2
restricted earth fault protection of HV side
1115-1116 BO_OvExc The signal output of operation of overexciation
The signal output of operation of ground overcurrent protection or
restricted earth fault protection of LV side A.
The signal output of operation of ground overcurrent protection or
restricted earth fault protection of LV side B

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4 Hardware

The signal output of operation of backup protection of branch A1 at LV
1121-1122 BO_Bak_Br11
side.
The signal output of operation of backup protection of branch A2 at LV
1123-1124 BO_Bak_Br12
side.
The signal output of operation of backup protection of branch B1 at LV
1125-1126 BO_Bak_Br21
side.
The signal output of operation of backup protection of branch B2 at LV
1127-1128 BO_Bak_Br22
side.

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5 Human Machine Interface
5.1 Understand the LCD Display
5.1.1 Display When Tripping

All operation messages for the project are listed in the following table.
Table 5.1-1 Operation report list
No. Item Description
1 ManTrigDFR Oscillography function is triggered manually.
2 AlmTrigDFR Oscillography function is triggered by alarm signals.
3 FD.Pkp Any one fault detector picks up.
4 Op_InstDiff Unrestrained instantaneous differential protection operates.
5 Op_PcntDiff Biased differential protection operates.
HV side unrestrained instantaneous restricted earth fault (REF)

6 Op_InstREF_HVS
protection operates.
7 Op_PcntREF_HVS HV side biased REF protection operates.
8 Op_InstREF_Br1 Unrestrained instantaneous REF protection of LV side A operates.
9 Op_PcntREF_Br1 Biased REF protection of LV side A operates.
10 Op_InstREF_Br2 Unrestrained instantaneous REF protection of LV side B operates.
11 Op_PcntREF_Br2 Biased REF protection of LV side B operates.
Stage 1 of negative-sequence overcurrent protection of HV side

12 Op_NegOC1_HVS
operates.
Stage 2 of negative-sequence overcurrent protection of HV side

13 Op_NegOC2_HVS
operates.
14 Op_InstOC_HVS Instant overcurrent protection of HV side operates.
15 Op_DefOvExc Definite time overexcitation protection operates
16 Op_InvOvExc Inverse time overexcitation protection operates.
Delay 1 of HV side ground overcurrent protection with calculated residual

17 Op_ROC11_Cal_HVS
current operates.
Delay 2 of HV side ground overcurrent protection with calculated residual

18 Op_ROC12_Cal_HVS
current operates.
Delay 1 of HV side ground overcurrent protection with neutral current

19 Op_ROC11_NP_HVS
operates.
Delay 2 of HV side ground overcurrent protection with neutral current

20 Op_ROC22_NP_HVS
operates.

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Inverse time ground overcurrent protection with neutral current of HV

21 Op_InvROC_NP_HVS
side operates
22 Op_ROV11_HVS Delay 1 of stage 1 of HV side residual overvoltage protection operates
23 Op_ROV12_HVS Delay 2 of stage 1 of HV side residual overvoltage protection operates
Stage 1 of definite-time overcurrent protection of LV side branch A1

24 Op_OC1_Br11
operates.

25 Op_OC2_Br11
operates.
26 Op_InstOC_Br11 Instant overcurrent protection of LV side branch A1 operates.

27 Op_OC1_Br12
operates.

28 Op_OC2_Br12
operates.

30 Op_OC1_Br13
operates.

31 Op_OC2_Br13
operates.

33 Op_OC1_Br14
operates.

34 Op_OC2_Br14
operates.
36 Op_OC1_Br1 Stage 1 of definite-time overcurrent protection of LV side A operates.
37 Op_OC2_Br1 Stage 2 of definite-time overcurrent protection of LV side A operates.
38 Op_InstOC_Br1 Instant overcurrent protection of LV side A operates.
Stage 1 of definite-time overcurrent protection of LV side branch B1

39 Op_OC1_Br21
operates.

40 Op_OC2_Br21
operates.
41 Op_InstOC_Br21 Instant overcurrent protection of LV side branch B1 operates.

42 Op_OC1_Br22
operates.

43 Op_OC2_Br22
operates.
45 Op_OC1_Br23 Stage 1 of definite-time overcurrent protection of LV side branch B3

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operates.

46 Op_OC2_Br23
operates.

48 Op_OC1_Br24
operates.

49 Op_OC2_Br24
operates.
51 Op_OC1_Br2 Stage 1 of definite-time overcurrent protection of LV side B operates.
52 Op_OC2_Br2 Stage 2 of definite-time overcurrent protection of LV side B operates.
53 Op_InstOC_Br2 Instant overcurrent protection of LV side B operates.
54 Op_ROC1_Br1 Stage 1 of ground overcurrent protection of LV side A operates.
55 Op_ROC2_Br1 Stage 2 of ground overcurrent protection of LV side A operates.
56 Op_ROC1_Br2 Stage 1 of ground overcurrent protection of LV side B operates.
57 Op_ROC2_Br2 Stage 2 of ground overcurrent protection of LV side B operates.
58 TrpOutp1 Group 1 of tripping output contacts operate.

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6 Settings
6 Settings
6.1 General Settings
6.1.1 System Settings

Table 6.1-1 System settings list
No. Setting Item Range Description
1 Active_Grp 1~30 Current setting group.
2 Opt_SysFreq 0: 50Hz; 1:60Hz Select system working frequency.
Name of the protected primary equipment, such as

3 PrimaryEquip_Name Max 16 characters
transformer, line, etc.
 Setting path
Access path in menu is:
Main Menu -> Settings -> General Settings -> System Settings
6.1.2 Enable Settings
 Settings list
Table 6.1-2 Enable settings list
No. Setting item Range Description
Logic setting used to enable (1) or disable (0) transformer

1 En_Diff 0/1
differential protection
Logic setting used to enable (1) or disable (0) phase-to-phase

2 En_PPF_HVS 0/1
backup protection of HV side
Logic setting used to enable (1) or disable (0) earth fault

3 En_EF_HVS 0/1
protection of HV side
Logic setting used to enable (1) or disable (0) overexcitation

4 En_OvExc 0/1
protection
Logic setting used to enable (1) or disable (0) restricted earth

5 En_REF_HVS 0/1
The logic setting used to enable (1) or disable (0) backup

6 En_Bak_Br11 0/1
protection of LV side branch A1
The logic setting used to enable (1) or disable (0) backup

7 En_Bak_Br12 0/1
Logic setting used to enable (1) or disable (0) backup

8 En_Bak_Br13 0/1

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6 Settings

9 En_Bak_Br14 0/1

10 En_Bak_Br1 0/1
protection of LV side A

11 En_Bak_Br21 0/1
protection of LV side branch B1

12 En_Bak_Br22 0/1

13 En_Bak_Br23 0/1

14 En_Bak_Br24 0/1

15 En_Bak_Br2 0/1
protection of LV side B

16 En_EF_Br1 0/1

17 En_EF_Br2 0/1

18 En_REF_Br1 0/1
fault protection of LV side A

19 En_REF_Br2 0/1
fault protection of LV side B
Logic setting used to enable (1) or disable (0) stub differential

20 En_StubDiff_HVS 0/1
Logic setting used to enable (1) or disable (0) stub overcurrent

21 En_StubOC_HVS 0/1
Logic setting used to enable (1) or disable (0) VT neutral line

22 En_VTNS 0/1
failure supervision
Logic setting used to enable (1) or disable (0) debugging

23 En_TestMode 0/1
operation through PCS-PC software.
 Setting path
Main Menu -> Settings -> General Settings -> Enable Settings
6.1.3 Transformer System Settings
 Settings list

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6 Settings
Table 6.1-3 Transformer system settings list
No. Setting Item Range Step Unit Description
1 Sn 0.01~600 0.01 MVA Capacity of the transformer
2 U1n_HVS 0.01~2000 0.01 kV Rated primary voltage of HV side
3 U1n_Br1 0.01~600 0.01 kV Rated primary voltage of LV side A
4 U1n_Br2 0.01~600 0.01 kV Rated primary voltage of LV side B
5 U1n_VT_HVS 0.01~2000 0.01 kV Rated primary voltage of VT of HV side
6 U2n_VT_HVS 0.01~200 0.01 V Rated secondary voltage of VT of HV side
7 U2n_DeltVT_HVS 0.01~330 0.01 V Rated secondary voltage of broken-delta VT of HV side
8 U1n_VT_Br1 0.01~600 0.01 kV Rated primary voltage of VT of LV side A
9 U2n_VT_Br1 0.01~200 0.01 V Rated secondary voltage of VT of LV side A
10 U1n_VT_Br2 0.01~600 0.01 kV Rated primary voltage of VT of LV side B
11 U2n_VT_Br2 0.01~200 0.01 V Rated secondary voltage of VT of LV side B
12 I1n_CT_HVS 0~60000 1 A Rated primary current of CT of HV side
13 I2n_CT_HVS 1 or 5 A Rated secondary current of CT of HV side
14 I1n_BushCT_HVS 0~60000 1 A Rated primary current of bushing CT of HV side
15 I2n_BushCT_HVS 1 or 5 A Rated secondary current of bushing CT of HV side
16 I1n_CT_Br11 0~60000 1 A Rated primary current of CT of LV side branch A1
17 I2n_CT_Br11 1 or 5 A Rated secondary current of CT of LV side branch A1
24 I1n_BushCT_Br1 0~60000 1 A Rated primary current of bushing CT of LV side A
25 I2n_BushCT_Br1 1 or 5 A Rated secondary current of bushing CT of LV side A
26 I1n_CT_Br21 0~60000 1 A Rated primary current of CT of LV side branch B1
27 I2n_CT_Br21 1 or 5 A Rated secondary current of CT of LV side branch B1
34 I1n_BushCT_Br2 0~60000 1 A Rated primary current of bushing CT of LV side B

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6 Settings
35 I2n_BushCT_Br2 1 or 5 A Rated secondary current of bushing CT of LV side B
36 I1n_CT_NP_HVS 0~60000 1 A Rated primary current of neutral CT of HV side
37 I2n_CT_NP_HVS 1 or 5 A Rated secondary current of neutral CT of HV side
38 I1n_CT_Gap_HVS 0~60000 1 A Rated primary current of gap neutral CT of HV side
39 I2n_CT_Gap_HVS 1 or 5 A Rated secondary current of gap neutral CT of HV side
40 I1n_CT_NP_Br1 0~60000 1 A Rated primary current of neutral CT of LV side A
41 I2n_CT_NP_Br1 1 or 5 A Rated secondary current of neutral CT of LV side A
42 I1n_CT_NP_Br2 0~60000 1 A Rated primary current of neutral CT of LV side B
43 I2n_CT_NP_Br2 1 or 5 A Rated secondary current of neutral CT of LV side B
logic settings “1” - enable, “0” – disable
44 Yyy12_Conn 0/1 Connection group of transformer is Y/Y/Y-12
45 Ddd12_Conn 0/1 Connection group of transformer is Δ/Δ/Δ-12
46 Dyy11_Conn 0/1 Connection group of transformer is Δ/Y/Y-11
47 Ydd11_Conn 0/1 Connection group of transformer is Y/Δ/Δ-11
48 Dyy1_Conn 0/1 Connection group of transformer is Δ/Y/Y-1
49 Ydd1_Conn 0/1 Connection group of transformer is Y/Δ/Δ-1
 Setting path
Main Menu -> Settings -> General Settings -> Tr Sys Settings
6.2 Implicit internal Settings
These settings can not be seen on LCD of device and only can be viewed and configured on PC
through PCS-PC software. These settings are usually configured in factory or configured by field
commission engineer according to the design drawing and project requirement.
6.2.1 Internal Configuration Settings
 Settings list
Table 6.2-1 Internal configuration settings list
1 Cfg_Polar_CT 0~7FFF CT polarity definition
Logic setting of selecting three-phase current channel for CT of

2 Cfg_CT_HVS1 0~14
HV side 1

3 Cfg_CT_HVS2 0~14
HV side 2

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6 Settings
Logic setting of selecting three-phase current channel for

4 Cfg_BushCT_HVS 0~14
bushing CT of HV side

5 Cfg_CT_Br11 0~14
LV side branch A1

6 Cfg_CT_Br12 0~14
LV side branch A2

7 Cfg_CT_Br13 0~14
LV side branch A3

8 Cfg_CT_Br14 0~14
LV side branch A4

9 Cfg_BushCT_Br1 0~14
bushing CT of LV side A

10 Cfg_CT_Br21 0~14
LV side branch B1

11 Cfg_CT_Br22 0~14
LV side branch B2

12 Cfg_CT_Br23 0~14
LV side branch B3

13 Cfg_CT_Br24 0~14
LV side branch B4

14 Cfg_BushCT_Br2 0~14
bushing CT of LV side B
Logic setting of selecting zero-sequence current channel for

15 Cfg_CT_NP_HVS 0~8
neutral point zero-sequence CT of HV side
Logic setting of selecting zero-sequence current channel for gap

16 Cfg_CT_Gap_HVS 0~8
zero-sequence CT of HV side

17 Cfg_CT_NP_Br1 0~8
neutral point zero-sequence CT of LV side A

18 Cfg_CT_NP_Br2 0~8
neutral point zero-sequence CT of LV side B
Logic setting of selecting CTs for transformer differential

19 Cfg_CT_Diff 0~F
protection
Logic setting of selecting CTs for overcurrent protection of HV

20 Cfg_CT_OC_HVS 0~3
side
21 Cfg_CT_Abnor_HVS 0~3 Logic setting of selecting CTs for abnormal protection of HV side
Logic setting of selecting CTs for restricted earth fault protection

22 Cfg_CT_REF_HVS 0~7
of HV side

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6 Settings

23 Cfg_CT_REF_Br1 0~7
of LV side A

24 Cfg_CT_REF_Br2 0~7
of LV side B
Configuration setting of selecting which tripping outputs will

25 Cfg_Ext_TrpOutp 0~1FFFF
delay drop off
26 t_Ext_TrpOutp 0~0.45s The pulse width of tripping output to delay drop off
6.2.2 Label Settings
 Settings list
Table 6.2-2 Label settings list
No. Setting item Description
1 Name_Trp1 Label setting of tripping output 1
6.3 Protection Settings
6.3.1 Transformer Differential Protection Settings

 Settings list

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6 Settings
Table 6.3-1 Transformer differential protection settings list
Pickup current setting of biased differential protection

1 I_Pkp_PcntDiff 0.1~1.5 0.01 A
of transformer
Current setting of unrestrained instantaneous

2 I_InstDiff 2~14 0.01 A
differential protection of transformer
Current setting of transformer differential current

3 I_Alm_Diff 0.05~1 0.01 A
abnormality alarm
The first slope of sensitive biased differential

4 Slope1_PcntDiff 0.05~0.5 0.01
protection
The second slope of sensitive biased differential

5 Slope2_PcntDiff 0.5~0.8 0.01
protection
6 k_Harm_PcntDiff 0.1~0.35 0.01 Restraint coefficient of second harmonic
Tripping output logic setting of differential protection

7 TrpLog_Diff 0000~1FFFF
of transformer
logic settings “1” - enable, “0” - disable
Logic setting of enabling unrestrained instantaneous

8 En_InstDiff 0/1
differential protection of transformer
Logic setting of enabling biased differential protection

9 En_PcntDiff 0/1
of transformer
Logic setting for selecting the restraint blocking

principle.
10 Opt_Inrush_Ident 0/1
“0”: discrimination by harmonics
“1”: discrimination by waveform distortion
Logic setting of selecting whether biased differential

protection being controlled during CT circuit failure
“1”: the transformer biased current differential
11 Opt_CTS_Blk_PcntDiff 0/1
protection will be blocked and alarm will be issued.
“0”: alarm will be issued but transformer biased
current differential protection will not be blocked
 Setting path
Main Menu -> Settings -> Tr Diff Prot Settings -> Tr Diff Prot Settings
6.3.2 HV Side Restricted Earth Fault Protection Settings

 Settings list

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6 Settings
Table 6.3-2 HV side restricted earth fault (REF) protection settings list
1 I_Pkp_PcntREF_HVS 0.1~1.5 0.01 A Pickup current setting of biased REF protection of HV side
Current setting of unrestrained instantaneous REF

2 I_InstREF_HVS 2~14 0.01 A
Current setting for HV side REF protection operates to

3 I_Alm_REF_HVS 0.05~1 0.01 A
alarm
4 Slope_PcntREF_HVS 0.3~0.8 0.01 Restraint coefficient of HV side biased REF protection
5 TrpLog_REF_HVS 0000~1FFFF Tripping output logic setting of HV side REF protection
logic settings “1” - enable, “0” – disable
Logic setting of enabling unrestrained instantaneous REF

6 En_InstREF_HVS 0/1
7 En_PcntREF_HVS 0/1 Logic setting of enabling biased REF protection of HV side
 Setting path
Main Menu -> Settings -> HVS Prot Settings -> HVS REF Prot Settings
6.3.3 HV Side Phase-to-phase Backup Protection Settings
 Settings list
Table 6.3-3 HV side phase-to-phase backup protection settings list
Current setting of instaneous overcurrent

1 I_InstOC_HVS 0.05~100 0.01 A
Time delay of instaneous overcurrent protection

2 t_InstOC_HVS 0~10 0.01 s
of HV side
Tripping output logic setting of instaneous

3 TrpLog_InstOC_HVS 0000~1FFFF
overcurrent protection of HV side
Current setting of stage 1 of negative-sequence

4 I_NegOC1_HVS 0.05~100 0.01 A
Time delay of stage 1 of negative-sequence

5 t_NegOC1_HVS 0~10 0.01 s
Tripping output logic setting of stage 1 of

6 TrpLog_NegOC1_HVS 0000~1FFFF negative-sequence overcurrent protection of HV
side
Current setting of stage 2 of negative-sequence

7 I_NegOC2_HVS 0.05~100 0.01 A
8 t_NegOC2_HVS 0~10 0.01 s Time delay of stage 2 of negative-sequence

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6 Settings
Tripping output logic setting of stage 2 of

9 TrpLog_NegOC2_HVS 0000~1FFFF negative-sequence overcurrent protection of HV
side
Current setting of overload alarm element of HV

10 I_Alm_OvLd_HVS 0.05~20 0.01 A
side
Time delay of overload alarm element of HV

11 t_Alm_OvLd_HVS 0~10 0.01 s
side
Current setting of stage 1 of overload cooling

12 I_InitCool1_OvLd_HVS 0.05~20 0.01 A
initiation element of HV side
Time delay of stage 1 of overload cooling

13 t_InitCool1_OvLd_HVS 0~25 0.01 s
Current setting of stage 2 of overload cooling

14 I_InitCool2_OvLd_HVS 0.05~20 0.01 A
Time delay of stage 2 of overload cooling

15 t_InitCool2_OvLd_HVS 0~25 0.01 s
Current setting of overload block on-load tap

16 I_OvLd_Blk_OLTC_HVS 0.05~20 0.01 A
changing element of HV side
Time delay of overload block on-load tap

17 t_OvLd_Blk_OLTC_HVS 0~10 0.01 s
changing element of HV side
Logic setting of enabling stage 1 of overcurrent

18 En_NegOV_Ctrl_NegOC_HVS 0/1 protection of HV side being controlled by
voltage control elements
Logic setting of enabling overload alarm

19 En_OvLd_HVS 0/1
element of HV side
Logic setting of enabling stage 1 of overload

20 En_InitCool1_OvLd_HVS 0/1
cooling initiation element of HV side
Logic setting of enabling stage 2 of overload

21 En_InitCool2_OvLd_HVS 0/1
cooling initiation element of HV side
Logic setting of enabling overload block on-load

22 En_OvLd_Blk_OLTC_HVS 0/1
tap changing element of HV side
 Setting path
Main Menu -> Settings -> HVS Prot Settings -> HVS PPF Prot Settings
6.3.4 HV Side Earth Fault Protection Settings

 Settings list

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6 Settings
Table 6.3-4 HV side earth fault protection settings list
Voltage setting of residual overvoltage

1 V_ROV_VCE_HVS 2~100 0.01 V element for controlling ground overcurrent
Current setting of definite-time ground

2 I_ROC1_Cal_HVS 0.1~100 0.01 A overcurrent protection of HV side with
calculated residual current
Time delay 1 of definite-time ground

3 t_ROC11_Cal_HVS 0~10 0.01 s overcurrent protection of HV side with
Tripping output logic setting of delay 1 of

definite-time ground overcurrent
4 TrpLog_ROC11_Cal_HVS 0000~1FFFF
protection of HV side with calculated
residual current
Time delay 2 of definite-time ground

5 t_ROC12_Cal_HVS 0~10 0.01 s overcurrent protection of HV side with

definite-time ground overcurrent
6 TrpLog_ROC12_Cal_HVS 0000~1FFFF
protection of HV side with calculated
residual current
Current setting of stage 2 of definite-time

7 I_ROC1_NP_HVS 0.1~100 0.01 A ground overcurrent protection of HV side
with neutral current
Time delay 1 of stage 2 of definite-time

8 t_ROC11_NP_HVS 0~10 0.01 s ground overcurrent protection of HV side

stage 2 of definite-time ground
9 TrpLog_ROC11_NP_HVS 0000~1FFFF
overcurrent protection of HV side with
neutral current
Time delay 2 of stage 2 of definite-time

10 t_ROC12_NP_HVS 0~10 0.01 s ground overcurrent protection of HV side

stage 2 of definite-time ground
11 TrpLog_ROC12_NP_HVS 0000~1FFFF
neutral current
Operating current of inverse-time ground

12 Ib_InvROC_NP_HVS 0.5~20 0.01 A

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6 Settings
neutral current
Time multiplier setting of inverse-time

13 TMS_InvROC_NP_HVS 0.05~10 0.01 ground overcurrent protection with neutral
current
Minimum time delay of inverse-time

14 tmin_InvROC_NP_HVS 0~10 0.01 s ground overcurrent protection of HV side
Logic setting of selecting time

characteristic curve of inverse-time
neutral current
15 Opt_InvROC_NP_HVS 0~3
0: IEC Normal inverse
1: IEC Very inverse
2: IEC Extremely inverse
3: IEC Long-time inverse
Tripping output logic setting of

16 TrpLog_InvROC_NP_HVS 0000~1FFFF inverse-time ground overcurrent
protection of HV side with neutral current
Logic setting of enabling definite-time

ground overcurrent protection with
17 En_VCE.ROV_Ctrl_ROC1_Cal_HVS 0/1 calculated residual current being
controlled by residual voltage control
element

ground overcurrent protection of HV side
18 En_VCE.ROV_Ctrl_ROC1_NP_HVS 0/1
with neutral current being controlled by
residual voltage control element
Logic setting of enabling of definite-time

19 En_Hm_Ctrl_ROC1_NP_HVS 0/1
harmonic

20 En_Dir_Ctrl_ROC1_Cal_HVS 0/1
with calculated residual current being
controlled by residual directional element.

21 En_Dir_Ctrl_ROC1_NP_HVS 0/1
residual directional element

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6 Settings
Logic setting of selecting the direction of

“1”: the direction is transformer and reach
22 Opt_Dir_ROC_HVS 0/1
angle is 225º.
“0”: the direction is power system and
reach angle is 75º.
Logic setting of selecting how ground

responses when VT circuit fails.
“1”: when VT circuit failure at one side is

detected, directional relay and voltage
control element at the same side will be
disabled but overcurrent relay on the
23 Opt_VTS_Ctrl_ROC_HVS 0/1 same side can still be controlled by
voltage control elements of other side if
corresponding logic setting is set as “1”.
“0”: when VT circuit failure at one side is

detected, the overcurrent relay will
become an overcurrent relay without
directional element and voltage control
element.
 Setting path
Main Menu -> Settings -> HVS Prot Settings -> HVS EF Prot Settings
6.3.5 Overexcitation Protection Settings

 Settings list
Table 6.3-5 Overexcitation protection settings list
Overexcitation multiple setting for definite time

1 k_DefOvExc1 1~2 0.01
overexcitation protection operates to trip
2 t_DefOvExc1 0.1~3000 0.1 s Time delay of definite time overexcitation protection
Tripping output logic setting of definite time

3 TrpLog_DefOvExc1 0000~1FFFF
overexcitation protection
Overexcitation multiple setting for definite time

4 k_Alm_DefOvExc 1~2 0.01
overexcitation operates to alarm
Time delay for definite time overexcitation operates to

5 t_Alm_DefOvExc 0.1~25 0.1 s
alarm

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6 Settings
Upper limit overexcitation multiple setting of inverse

6 k0_InvOvExc 1~2 0.01
time overexcitation protection: n0
Time delay corresponds to upper limit overexcitation

7 t0_InvOvExc 1~3000 0.1 s
multiple: t0
Overexcitation multiple corresponds to the point n1 of

8 k1_InvOvExc 1~2 0.01
inverse time overexcitation curve
Time delay corresponds to the point n1 of inverse time

9 t1_InvOvExc 1~3000 0.1 s
overexcitation curve

10 k2_InvOvExc 1~2 0.01

11 t2_InvOvExc 1~3000 0.1 s

12 k3_InvOvExc 1~2 0.01

13 t3_InvOvExc 1~3000 0.1 s

14 k4_InvOvExc 1~2 0.01

15 t4_InvOvExc 1~3000 0.1 s

16 k5_InvOvExc 1~2 0.01

17 t5_InvOvExc 1~3000 0.1 s

18 k6_InvOvExc 1~2 0.01

19 t6_InvOvExc 1~3000 0.1 s
Lower limit overexcitation multiple setting of inverse

20 k7_InvOvExc 1~2 0.01
time overexcitation protection: n7
Time delay corresponds to lower limit overexcitation

21 t7_InvOvExc 1~3000 0.1 s
multiple setting: t7
Tripping output logic setting of inverse time

22 TrpLog_InvOvExc 0000~1FFFF
overexcitation protection
 Setting path
Main Menu -> Settings -> HVS Prot Settings -> OvExc Prot Settings

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6 Settings
6.3.6 Settings of Backup Protection of Each Branch of LV Side A

In this section, x=1~4 corresponds to LV side branch A1~A4 respectively
 Settings list
Table 6.3-6 LV side branch A1/A2/A3/A4 backup protection settings list
Setting of negative-sequence voltage controlled

1 V_NegOV_VCE_Br1x 1~20 0.01 V
element of LV side branch Ax
Setting of phase-to-phase undervoltage controlled

2 Vpp_UV_VCE_Br1x 10~100 0.01 V
element of LV side branch Ax
Current setting of instant overcurrent protection of LV

3 I_InstOC_Br1x 0.1~100 0.01 A
side branch Ax
Time delay of instant overcurrent protection of LV side

4 t_InstOC_Br1x 0~10 0.01 s
branch Ax
Tripping output logic setting of instant overcurrent

5 TrpLog_InstOC_Br1x 0000~1FFFF
protection of LV side branch Ax
Current setting of stage 1 of overcurrent protection of

6 I_OC1_Br1x 0.1~100 0.01 A
LV side branch Ax
Time delay of stage 1 of overcurrent protection of LV

7 t_OC1_Br1x 0~10 0.01 s
side branch Ax
Tripping output logic setting of stage 1 of overcurrent

8 TrpLog_OC1_Br1x 0000~1FFFF

9 I_OC2_Br1x 0.1~100 0.01 A
LV side branch Ax

10 t_OC2_Br1x 0~10 0.01 s
side branch Ax


12 En_VCE_Ctrl_OC1_Br1x 0/1 protection of LV side branch Ax being controlled by
voltage controlled element

13 En_VCE_Ctrl_OC2_Br1x 0/1 protection of LV side branch Ax being controlled by
Logic setting of enabling accelerating tripping of stage

14 En_OC2_SOTF_Br1x 0/1
2 of overcurrent protection of LV side branch Ax
Protection performance option if VT circuit fails.

15 Opt_VTS_Ctrl_OC_Br1x 0/1 “1”: when VT circuit failure is detected, voltage
controlled element of corresponding side will be

Date: 2013-01-22
6 Settings
disabled.
“0”: when VT circuit failure of one side is detected, the
overcurrent element of LV side branch Ax will not be
controlled by voltage controlled element.
 Setting path
Main Menu -> Settings -> LVS Prot Settings -> Br1x Bak Prot Settings
6.3.7 Settings of Backup Protection of Each Branch of LV Side B

In this section, x=1~4 corresponds to LV side branch B1~B4 respectively
 Settings list
Table 6.3-7 LV side branch B1/B2/B3/B4 backup protection settings list

1 V_NegOV_VCE_Br2x 1~20 0.01 V
element of LV side branch Bx

2 Vpp_UV_VCE_Br2x 10~100 0.01 V
element of LV side branch Bx

3 I_InstOC_Br2x 0.1~100 0.01 A
side branch Bx

4 t_InstOC_Br2x 0~10 0.01 s
branch Bx

5 TrpLog_InstOC_Br2x 0000~1FFFF
protection of LV side branch Bx

6 I_OC1_Br2x 0.1~100 0.01 A
LV side branch Bx

7 t_OC1_Br2x 0~10 0.01 s
side branch Bx


9 I_OC2_Br2x 0.1~100 0.01 A
LV side branch Bx

10 t_OC2_Br2x 0~10 0.01 s
side branch Bx

12 En_VCE_Ctrl_OC1_Br2x 0/1 Logic setting of enabling stage 1 of overcurrent

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6 Settings
protection of LV side branch Bx being controlled by


13 En_VCE_Ctrl_OC2_Br2x 0/1 protection of LV side branch Bx being controlled by
Logic setting of enabling accelerating tripping of stage

14 En_OC2_SOTF_Br2x 0/1
2 of overcurrent protection of LV side branch Bx

“1”: when VT circuit failure is detected, voltage
controlled element of corresponding side will be
15 Opt_VTS_Ctrl_OC_Br2x 0/1 disabled.
overcurrent element of LV side branch Bx will not be
controlled by voltage controlled element.
 Setting path
Main Menu -> Settings -> LVS Prot Settings -> Br2x Bak Prot Settings
6.3.8 Settings of Backup Protection of LV Side A

The current used in LV side A backup protection is derived from the LV side A bushing CT.
 Settings list
Table 6.3-8 LV side A backup protection settings list

1 V_NegOV_VCE_Br1 1~20 0.01 V
element of LV side A

2 Vpp_UV_VCE_Br1 10~100 0.01 V

3 I_InstOC_Br1 0.1~100 0.01 A
side A

4 t_InstOC_Br1 0~10 0.01 s
A

5 TrpLog_InstOC_Br1 0000~1FFFF

6 I_OC1_Br1 0.1~100 0.01 A
LV side A

7 t_OC1_Br1 0~10 0.01 s
side A

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6 Settings

8 TrpLog_OC1_Br1 0000~1FFFF

9 I_OC2_Br1 0.1~100 0.01 A
LV side A

10 t_OC2_Br1 0~10 0.01 s
side A


12 En_VCE_Ctrl_OC1_Br1 0/1 protection of LV side A being controlled by voltage
controlled element

13 En_VCE_Ctrl_OC2_Br1 0/1 protection of LV side A being controlled by voltage
controlled element

controlled element of LV side A will be disabled.
14 Opt_VTS_Ctrl_OC_Br1 0/1
overcurrent element of LV side A will not be controlled
by voltage controlled element.
 Setting path
Main Menu -> Settings -> LVS Prot Settings -> Br1 Bak Prot Settings
6.3.9 Settings of Backup Protection of LV Side B

The current used in LV side B backup protection is derived from the LV side B bushing CT.
 Settings list
Table 6.3-9 LV side B backup protection settings list

1 V_NegOV_VCE_Br2 1~20 0.01 V
element of LV side B

2 Vpp_UV_VCE_Br2 10~100 0.01 V

3 I_InstOC_Br2 0.1~100 0.01 A
side B
4 t_InstOC_Br2 0~10 0.01 s Time delay of instant overcurrent protection of LV side

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6 Settings

5 TrpLog_InstOC_Br2 0000~1FFFF

6 I_OC1_Br2 0.1~100 0.01 A
LV side B

7 t_OC1_Br2 0~10 0.01 s
side B


9 I_OC2_Br2 0.1~100 0.01 A
LV side B

10 t_OC2_Br2 0~10 0.01 s
side B


12 En_VCE_Ctrl_OC1_Br2 0/1 protection of LV side B being controlled by voltage
controlled element

13 En_VCE_Ctrl_OC2_Br2 0/1 protection of LV side B being controlled by voltage
controlled element

controlled element of LV side B will be disabled.
14 Opt_VTS_Ctrl_OC_Br2 0/1
overcurrent element of LV side B will not be controlled
by voltage controlled element.
 Setting Path
Main Menu -> Settings -> LVS Prot Settings -> Br2 Bak Prot Settings
6.3.10 Settings of Earth Fault Protection of LV Side A

 Settings list
Table 6.3-10 LV side A earth fault protection settings list
1 I_ROC1_Br1 0.1~100 0.01 A Current setting of stage 1 of ground overcurrent

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6 Settings
Time delay of stage 1 of ground overcurrent protection

2 t_ROC1_Br1 0~10 0.01 s
of LV side A
Tripping output logic setting of stage 1 of ground

3 TrpLog_ROC1_Br1 0000~1FFFF
overcurrent protection of LV side A
Current setting of stage 2 of ground overcurrent

4 I_ROC2_Br1 0.1~100 0.01 A

5 t_ROC2_Br1 0~10 0.01 s
of LV side A

overcurrent protection of LV side A
Voltage setting of residual overvoltage alarm element

7 V_Alm_ROV_Br1 5~100 0.01 V
of LV side A
Time delay of residual overvoltage alarm element of

8 t_Alm_ROV_Br1 0~10 0.01 s
LV side A
Logic setting of enabling residual overvoltage alarm

9 En_Alm_ROV_Br1 0/1
 Setting path
Main Menu -> Settings -> LVS Prot Settings -> Br1 EF Prot Settings
6.3.11 Settings of Earth Fault Protection of LV Side B

 Settings list
Table 6.3-11 LV side B earth fault protection settings list

1 I_ROC1_Br2 0.1~100 0.01 A

2 t_ROC1_Br2 0~10 0.01 s
of LV side B

overcurrent protection of LV side B

4 I_ROC2_Br2 0.1~100 0.01 A

5 t_ROC2_Br2 0~10 0.01 s
of LV side B

Date: 2013-01-22
6 Settings

overcurrent protection of LV side B
Voltage setting of residual overvoltage alarm element

7 V_Alm_ROV_Br2 5~100 0.01 V
of LV side B
Time delay of residual overvoltage alarm element of LV

8 t_Alm_ROV_Br2 0~10 0.01 s
side B
Logic setting of enabling residual overvoltage alarm

9 En_Alm_ROV_Br2 0/1
 Setting path
Main Menu -> Settings -> LVS Prot Settings -> Br2 EF Prot Settings
6.3.12 Settings of Restricted Earth Fault Protection of LV Side A

 Settings list
Table 6.3-12 LV side A restricted earth fault protection settings list
Pickup current setting of biased REF protection of LV

1 I_Pkp_PcntREF_Br1 0.1~1.5 0.01 A
side A

2 I_InstREF_Br1 2~14 0.01 A
Current setting for LV side A REF protection operates to

3 I_Alm_REF_Br1 0.05~1 0.01 A
alarm
4 Slope_PcntREF_Br1 0.3~0.8 0.01 Restraint coefficient of LV side A biased REF protection
5 TrpLog_REF_Br1 0000~1FFFF Tripping output logic setting of LV side A REF protection

6 En_InstREF_Br1 0/1
REF protection of LV side A
Logic setting of enabling biased REF protection of LV

7 En_PcntREF_Br1 0/1
side A
 Setting explanation
Please refer to Section 6.3.2 for details.
 Setting path
Main Menu -> Settings -> LVS Prot Settings -> Br1 REF Prot Settings

Date: 2013-01-22
6 Settings
6.3.13 Settings of Restricted Earth Fault Protection of LV side B

 Settings list
Table 6.3-13 LV side B restricted earth fault protection settings list
Pickup current setting of biased REF protection of LV

1 I_Pkp_PcntREF_Br2 0.1~1.5 0.01 A
side B

2 I_InstREF_Br2 2~14 0.01 A
Current setting for LV side B REF protection operates to

3 I_Alm_REF_Br2 0.05~1 0.01 A
alarm
4 Slope_PcntREF_Br2 0.3~0.8 0.01 Restraint coefficient of LV side B biased REF protection
5 TrpLog_REF_Br2 0000~1FFFF Tripping output logic setting of LV side B REF protection

6 En_InstREF_Br2 0/1
REF protection of LV side B
Logic setting of enabling biased REF protection of LV

7 En_PcntREF_Br2 0/1
side B
Please refer to Section 6.3.2 for details.
 Setting path
Main Menu -> Settings -> LVS Prot Settings -> Br2 REF Prot Settings
6.3.14 Stub Differential Protection Settings
 Settings list
Table 6.3-14 Stub differential protection settings list
Pickup current setting of stub biased differential

1 I_Pkp_StubDiff 0.1~1.5 0.01 A
protection
Current setting of stub differential current abnormality

2 I_Alm_StubDiff 0.05~1 0.01 A
alarm
Restraint coefficient of stub biased differential

3 Slope_StubDiff 0.3~0.8 0.01
protection
Tripping output logic setting of stub biased differential

4 TrpLog_StubDiff 0000~1FFFF
protection

Date: 2013-01-22
6 Settings
5 En_StubDiff 0/1 Logic setting of enabling stub differential protection
Logic setting of selecting whether stub biased

differential protection being controlled during CT
circuit failure
6 Opt_CTS_Blk_StubDiff 0/1 “1”: the stub biased current differential protection will
be blocked and alarm will be issued.
“0”: alarm will be issued but stub biased current
differential protection will not be blocked
 Setting path
Main Menu -> Settings -> Stub Prot Settings -> Stub Diff Prot Settings
6.3.15 Stub Overcurrent Protection Settings
 Settings list
Table 6.3-15 Stub overcurrent protection settings list
Current setting of instaneous overcurrent protection of

1 I_InstOC_Stub 0.05~100 0.01 A
stub
Time delay of instaneous overcurrent protection of

2 t_InstOC_Stub 0~10 0.01 s
stub
Tripping output logic setting of instaneous overcurrent

3 TrpLog_InstOC_Stub 0000~1FFFF
protection of stub

4 I_OC1_Stub 0.05~100 0.01 A
stub
5 t_OC1_Stub 0~10 0.01 s Time delay of stage 1 of overcurrent protection of stub

6 TrpLog_OC1_Stub 0000~1FFFF
protection of stub
 Setting path
Main Menu -> Settings -> Stub Prot Settings -> Stub OC Prot Settings
6.4 Device Setup
6.4.1 Device Settings

 Settings list

Date: 2013-01-22
6 Settings
Table 6.4-1 Device settings list
No. Setting Item Range Description
Select encoding format of header (HDR) file

1 HDR_EncodedMode GB18030, UTF-8 COMTRADE recording file. Default value is
“UTF-8”.
Select the caption language sent to SAS via

IEC103 protocol. Default value is 0.
2 Opt_Caption_103 0~2 0: Current language;
1: Fixed Chinese
2: Fixed English
3 Un_BinaryInput 24V, 48V, 110V, 220V Voltage level of binary input
1. [HDR_EncodedMode]
The setting is to select encoding format of header file .Default value of [HDR_EncodeMode] is
1(i.e. UTF-8 code) and please set it to 0(i.e. GB18030) according to the special requirement.
2. [Opt_Caption_103]
The setting is to select the caption language of IEC103 protocol. Please set it to “1” (i.e. Fixed
Chinese) if the SAS is supplied by a Chinese manufacturer.
0: Current language, i.e. the caption language changes with device LCD language.
1: Fixed Chinese, i.e. Chinese is fixedly selected as the caption language.
2: Fixed English, i.e. English is fixedly selected as the caption language.
3. [Un_BinaryInput]
The setting is used to set the voltage level of binary input module. 24V and 48V can be selected
when low-voltage BI module is equipped and 110V or 220V can be selected when high voltage
BI module is equipped.
 Setting path
Main menu -> Settings -> Device Setup -> Device Settings
6.4.2 Communication Settings

 Settings list
Table 6.4-2 Communication settings list
No. Settings item Range Description
000.000.000.000~
1 IP_LAN1 IP address of Ethernet port 1.
255.255.255.255

Date: 2013-01-22
6 Settings
000.000.000.000~
2 Mask_LAN1 Subnet mask of Ethernet port1.
255.255.255.255
000.000.000.000~
3 IP_LAN2 IP address of Ethernet Ethernet port 2.
255.255.255.255
000.000.000.000~
4 Mask_LAN2 Subnet mask of Ethernet port 2.
255.255.255.255
5 En_LAN2 0: disable, 1: enable Enable/disable the IP address of Ethernet port 2.
6 IP_LAN3 0: disable, 1: enable IP address of Ethernet port 3.
000.000.000.000~
255.255.255.255
9 IP_LAN4 0: disable, 1: enable IP address of Ethernet port 4.
000.000.000.000~
255.255.255.255
000.000.000.000~
12 Gateway Gateway of router
255.255.255.255
Enable/disable sending message in broadcast

13 En_Broadcast 0: disable, 1: enable
mode via network. (IEC103).
Communication address between the protective

14 Addr_RS485A 0～255 device with the SCADA or RTU via RS-485 serial
port 1.
4800,9600,19200,
15 Baud_RS485A Baud rate of rear RS-485 serial port 1.
38400,57600,115200 bps
Communication protocol of rear RS-485 serial port

1.
0: IEC60870-5-103
16 Protocol_RS485A 0～9
1: Modbus
2: Reserved
Others: Not available
Communication address between the protective

17 Addr_RS485B 0～255 device with the SCADA or RTU via RS-485 serial
port 2.
4800,9600,19200,
18 Baud_RS485B Baud rate of rear RS-485 serial port 2.
38400,57600,115200 bps

Date: 2013-01-22
6 Settings
Communication protocol of rear RS-485 serial port

2.
0: IEC60870-5-103
19 Protocol_RS485B 0～9
1: Modbus
2: Reserved
Others: Not available
4800,9600,
20 Baud_Printer 19200,38400, 51600, Baud rate of printer port
115200 bps
0: disable
21 En_AutoPrint Enable/disable automatic printing function
1: enable
Conventional
SAS Select the mode of time synchronization of
22 Opt_TimeSyn
Advanced equipment.
NoTimeSyn
The address of the external SNTP clock

000.000.000.000~
23 IP_Server_SNTP synchronization server sending SNTP message to
255.255.255.255
the equipment.
The local time zone also referred to as the hour

24 OffsetHour_UTC -12~12hrs
offset hour from UTC .
25 OffsetMinute_UTC 0~60min The offset minute of local time from UTC.
0: Tripping reports will not be uploaded via

communication port;
26 En_Maintenance 0/1
1: Tripping reports will not be uploaded via
communication port.
 Setting path
Main Menu -> Settings -> Device Setup -> Comm Settings

Date: 2013-01-22
6 Settings

Date: 2013-01-22
7 Manual Version History

In the latest version of the instruction manual, several descriptions on existing features have been
modified.
Manual version and modification history records
Manual
Software
Version Date Description of change
Version
Source New
PCS-985T
1.00 2013-01-22 Form the original manual.
R1.00_ECKF110355

Date: 2013-01-22

Date: 2013-01-22

PCS-985T Transformer Protection X Instruction Manual en Demostic General X R1.00 (En YJBH2601.0086.0001)

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PCS-985T Transformer Protection X Instruction Manual en Demostic General X R1.00 (En YJBH2601.0086.0001)

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PCS-985T

for Project ECKF110355

NR Electric Co., Ltd.

Version: 1.00 NR ELECTRIC CO., LTD.

69 Suyuan Avenue. Jiangning, Nanjing 211102, China

P/N: EN_ YJBH5093.0086.0001.110355 Tel: +86-25-87178185, Fax: +86-25-87178208

Website: www.nrelect.com, www.nari-relays.com

Copyright © NR 2013. All rights reserved Email: NR_TechSupport@nari-relays.com

We reserve the rights to make technical improvements without notice.

PCS-985T Transformer Relay i

ii PCS-985T Transformer Relay.

3.2 HV Side Ground Overcurrent Protection.................................................................................... 6

5 Human Machine Interface ................................................................................... 17

6.2 Implicit internal Settings ........................................................................................................... 24

6.3 Protection Settings ................................................................................................................... 26

6.4 Device Setup ............................................................................................................................ 42

7 Manual Version History ....................................................................................... 47

PCS-985T Transformer Relay iii

iv PCS-985T Transformer Relay.

1 Information about this Application

Software version PCS-985T R1.00_ECKF110355

Corresponding general PCS-985T_X_Instruction Manual_EN_Domestic General_X_R1.00_

PCS-985T Transformer Relay 1

2 PCS-985T Transformer Relay.

2.1 Protective Functions Configuration

Table 2.1-1 Protective functions in PCS-985T

Transformer biased current differential protection 87T

Transformer unrestrained current differential protection 50/87UT

Restricted earth fault protection of HV side 64REF

Restricted earth fault protection of LV side A 64REF

Restricted earth fault protection of LV side B 64REF

Stub differential protection 87S

Voltage controlled phase overcurrent protection of HV side 50/51P

Negative-sequence overcurrent protection of HV side 50/51Q

Voltage controlled phase overcurrent protections of each branch at

Ground overcurrent protections of LV side A(B) 50/51G

Stub overcurrent protection 50/51P

Residual overvoltage alarm of LV side A(B) 59G

Cooling initiation function 49

On-load tap change (OLTC) blocking function during overload 49

Inrush current detection

Harmonic blocking function

VT circuit failure supervision VTS

CT circuit failure supervision CTS

PCS-985T Transformer Relay 3

manual with the above table in this section.

4 PCS-985T Transformer Relay.

3.1 HV Side Phase Overcurrent Protection

Voltage controlled overcurrent protection of HV side is replaced by negative-sequence

3.1.1 Negative-Sequence Overcurrent Protection

BI [EBI_PPF_HVS] & &

Figure 3.1-1 Logic diagram of stage 1 of negative-sequence overcurrent protection

U2: the negative-sequence voltage of HV side.

[En_NegOV_Ctrl_NegOC_HVS]: the logic setting of enabling negative-sequence overcurrent

I2: the negative sequence current of HV side.

Flg_En_NegOC1_Tr: the internal flag indicating that negative-sequence overcurrent stage 1 is

FD_NegOC1_HVS: the fault detector of stage 1 of negative-sequence overcurrent protection of

PCS-985T Transformer Relay 5

[I_NegOC1_HVS]: current setting of stage 1 of negative-sequence overcurrent protection of HV

[t_NegOC1_HVS]: time delay of stage 1 negative-sequence overcurrent protection of HV side.

[Op_NegOC1_HVS]: the operation flag of stage 1 negative-sequence overcurrent protection of

3.2 HV Side Ground Overcurrent Protection

3.2.1 Definite-Time Ground Overcurrent Protection