Department of Electrical Engineering

Faculty Member:____________________
Date: ____________________
Course/Section:____________________
Semester: ________________

EE221: Digital Logic Design

Lab 12: Sequence Detector
Name
Reg. No.
Report/Pres
Viva

Total/35

Marks / 25
Marks /
10
EE241: Digital Logic Design Page 1
Lab12: Sequence Detector

This Lab Activity has been designed to familiarize the students with design and
implementation of a sequence detector that detects 10110 from an incoming binary stream
received serially. The students are expected to do the following:-

Complete the Sequential Design Method

Design the circuit using JK Flip-Flops

There are related questions at the end of this activity. Give complete answers. Use diagrams if
needed for clarity.
The students are required to complete Pre-Lab work before coming to the lab and submit lab report
before leaving.

Pre-Lab Tasks:

1. We wish to design a circuit with single input x, and a single output z, that detects an
overlapping sequence 10110 in a string of bits coming through an input line. We start it in the
initial state S0. In our design the detector circuit will only advance to the next state if some
valid bit of the specified sequence is received, otherwise will go back to either S0 or any other
state depending upon whether sequence breaks totally or partially. As and when complete
sequence is received, the detector circuit will output 1.

There are two FSM models for your design. Name these models and give advantages/
disadvantages of each? Which method you prefer and why? (1 Mark)

EE241: Digital Logic Design Page 2

Draw the Mealy state diagram for this sequence detector. How
many JK Flip-Flops
would you need for implementing this sequence detector and why?
(5 Marks)

2. List the State Table

(3 Marks)
Present Sate
Input

Next State

Output
Flip Flop Inputs

Q3
Q2
Q1
x
+
Q3

+
Q2

+
Q1
z
J3 K 3
J2 K 2
J1 K 1
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3. Obtain the simplified equations for Output z and Flip-Flop Inputs using map method.
(3 Marks)
EE241: Digital Logic Design Page 4
4. Draw complete circuit diagram for the sequence detector using JK flip flops and
external NAND gates . (3 Marks)
EE241: Digital Logic Design Page 5
Lab Tasks:

5. Implement the sequence detector in hardware and show results to your Instructor/Lab
Engr. (10 Marks)
EE241: Digital Logic Design Page 6