3 Intro2OPAMPS PDF

ADVELIN
Ann E. Dulay
Lecture 3: Introduction
to Operational Amplifiers
What is an operational amplifier?
 a very high gain direct coupled
amplifier in integrated circuit form that
uses external feedback networks to
control its response A
 used primarily to perform mathematical D
V
operations such as addition, E
subtraction, integration, and L
differentiation, hence the name I
N
operational.
 op-amps were previously constructed
with vacuum tubes using high voltages
Lecture 3: Introduction to Operational Amplifier

Prepared by: ANN E. DULAY 2
Symbol of op-amp
+Vss
V- -
Vo
A
V+ + D
V
-Vss E
L
I
The voltage at the inverting terminal shall be called V-, N
and the voltage at the non-inverting terminal shall be
called V+.
Most op-amps are powered with dual-supplies but there
are some that can be operated with single-supply.
Op-amp equivalent circuit
Ideal Practical
+
V- Vo 2Rcm
Ro A
Vd
Ri Vo D
Avd
V+ V
AVd
2Rcm E
L
- I
N
Vo  Av d
A – open loop gain
vd  v  v
Block diagram of a typical op-amp
intermediate level shifting output

input stage stage stage stage
A
•Input stage is usually a dual-ended input, balanced output D
V
diff-amp.
E
L
•The intermediate stage is a dual-input unbalanced output
I
differential amplifier N
•The level shifting stage can be an emitter follower with

voltage divider, a constant current bias or a current mirror
•The output stage is usually a complementary symmetry
push-pull amplifier
Schematic circuit of CA741
A
D
V
E
L
I
N
Active load Short circuit protection circuit

Differential pair
Current source Widlar current source/bias Emitter follower stage
6
Schematic circuit of LF356 op-amp
A
D
V
E
L
I
N
•National Semiconductor
•Bi-FET
7
Schematic circuit of TLC279
A
D
V
E
L
I
N
•Texas Instrument
•CMOS
8
Schematic circuit of OP-27 op-amp
A
D
V
E
L
I
N
Uses on-chip trimming to reduce offset.

By Analog Devices

Op-amp characteristics
Property Ideal Practical
Open-loop gain (Aol) Infinite  104
Open-loop bandwidth infinite Dominant pole (10 Hz)

(BW) A
D
Common-mode infinite  70 dB V
rejection ratio E
Input resistance (Ri) infinite  10 M L
I
Output resistance (Ro) zero < 500  N
Input currents (Bias zero < 0.5 A

current) IB
Offset voltages and zero <10mV, < 0.2nA
currents (Vio, Iio)

Comparison of different op-amps
741 LM108 AD611 AD507
Vio (mV)  5  2  0.5 5
IB (nA)  500 2  0.025  15
Iio (nA)  200  0.4  0.010  15 A
D
Aol (dB) 106 95 98 100 V
E
CMRR (dB) 80 95 80 100 L
Ri (M) 2 100 106 300 I
N
SR (V/s) 0.5 0.2 13 35
UBW(MHz) 1 1 2 35
741 – 2-stage architecture; LM108 – superbeta;

AD611-BIFET; AD507 - wideband
Op-amp Parameters
1. Input bias current (Ib)
- the average of the currents flowing into both
inputs. Ideally, the two input bias currents are
equal. This is the direct current required by A
the inputs of the op-amp to properly operate D
the first stage. +Vss
V
E
- generates error when Rc L
Rc
op-amp is operated in + Vo1
I
Vo N
high dc applications. - Vo2
Q1 Q2
V1 V2
I B  I B
IB 
V V
IEE
2 RE
-Vss

How to reduce or eliminate the effects of IB
 Install a dummy resistance at the (+)
terminal with a value equal to the
Thevenin’s resistance seen at the (-)
terminal. A
D
 Use superbeta transistors at the input V
stage (has a very thin base thus E
producing a very high gain). Ex. LM108 L
I
 Input current cancellation (dummy N
resistance is no longer required for this
type of op-amp). Ex. OP-07
 Use of op-amps with very low input bias
current (FETs and MOSFETs)
Op-amp Parameters
2. Input offset current (Ios)
- the difference of the two input bias currents.
- also generates error at high dc gain
applications. A
- can be eliminated by scaling down all D
resistances*. V
IB+ E
+ L
Ios  I B  I B IB-
Vo I
N
-
* Reducing resistances will increase power

dissipation and also generate harmonic distortion.
Op-amp Parameters
3. Input offset voltage
- because of transistor mismatches, the output
will not become zero when the input is zero.
- is defined as the voltage that must be A
applied to one of the input terminals to give a D
zero output voltage. V
E
L
Voltage I
transfer N
characteristic
of a practical
op-amp

Op-amp Parameters
Input offset voltage
 R2 
Vos  1  Vio A
 R1  D
V
E
If R1=R2 L
Vos  1  1 5mV   10mV

I
N
If R2=103R1
Vos  10 3  5mV   5V
Op-amp Parameters
4. Input voltage range (VCM)
- this is the range of input voltages
over which the op-amp will still
A
operate properly. D
V
- in BJT like 741, this is the range of E
input voltages for which each BJT L
I
still operates in the forward active N
region.

Op-amp Parameters
5. Output voltage swing (Vomax)
- depending on the load resistance, this the
maximum peak output voltage that the op-
amp can supply without saturation or clipping. A
D
VOL  Vo  VOH V
E
VOH  VCC  VEC13( sat )  VBE14(on)  VR 6 L
I
N
VOH  Vcc  0.2V  0.7V  0  Vcc  0.9V
VOL  VEE  VCE17(min)  VEB22(on)  VEB20(on)
VOL  VEE  2.1V

Op-amp Parameters
Output voltage swing
-CMOS op-amps can provide rail-to-rail
outputs, that is, their output range extends
all the way up to VCC and all the way down A
D
to VEE.
V
E
L
I
N
Rail-to-rail outputs
Op-amp Parameters
6. Output short circuit current (Iosc)
- the maximum output current that the op-
amp can deliver to a load.
- The short circuit protection circuit for 741 A
D
consists of Q15, Q22, R6, R7, and R11 V
(during sourcing) and Q14 during sinking. E
L
- these transistors are off under normal I
conditions; when a large current exists at N
the output, they conduct thus limiting the
current that would flow to the base of the
output transistors, Q14 (sourcing), Q20
(sinking)
Op-amp Parameters
7. Input resistance (Zi)
- the resistance “looking in” at either input with the
remaining input grounded.
- For 741, Riint = 2 M, Rcm = 200M 
- intrinsic resistance A
D
V
8. Output resistance (Zoi) E
- the resistance seen “looking into” the op-amps L
output. I
- For 741, Roint= 75  N
9. Supply current
- the current that the op-amp will draw from the
power supply.

Op-amp Parameters
10. Open-loop voltage gain (Aol)
- the ratio of the output to input voltage of the
op-amp without external feedback.
- the gain decreases with increasing frequency
A
D
V
E
L
I
N
22
Op-amp Parameters
11. Unity Gain bandwidth product (GBP)
- this is the frequency at which the open loop
voltage gain decreases to 1 or 0 dB.
A
GBW D
f max 
A vcl V
E
L
12. Common-mode rejection ratio (CMRR)- the
I
measure of the ability of the op-amp to reject N
signals that are simultaneously present at
both inputs. It is the ratio of the common-
mode input voltage to the generated output
voltage, usually expressed in decibels (dB).

Op-amp Parameters
13. Slew rate (SR)
- the time rate of change of the output voltage
with the op-amp circuit having a voltage gain
of unity.
A
D
V
E
L
I
N
Figure (a) and (b) show the effect on the output

waveform of the slew rate of the op-amp for square
and sine waves respectively.
Op-amp Parameters
14. Channel separation for packages
having one internal op-amp, a
certain amount of crosstalk will be
A
present. That is, a signal is applied D
to the input of the opamp section V
E
will develop a small but finite output L
signal in the remaining section(s), I
N
even though there is no input signal
applied to the unused section(s).

Loop Configurations
 Open-loop
 Used in comparison and oscillator
circuits
A
 Closed-loop D
V
 Used in amplifier and similar E
applications. L
I
 An external component is connected N
between the input and output of the
operational amplifier.

Two types of op-amp
 1. Compensated op-amp
 instability in amplifier circuits can be reduced by
internal compensation. This instability is caused
by undesirable lags in the feedback.
A
 if the total phase lag is 360 degrees, the circuit D
oscillates. V
 The compensation circuit is an RC circuit. E
L
However, internal compensation limits the high
I
frequency gain and the slew rate of the device. N
 Has a constant roll-off rate of –20dB/decade
from unity gain to fc.
 Examples: uA741, 4156

Two types of op-amp
 2. Uncompensated op amp
 requires an external RC circuit. This
could increase frequency range of
operation. A
D
 The frequency response is determined V
by the individual responses of several E
L
internal stages. I
N
 Examples: LM318

Frequency response
 shows how the voltage gain varies as
frequency changes.
Phase Avol A
shift Uncompensated
100 D
V
80 slope = -20 dB/decade >
E
2700
60 L
1800 I
40 N
90O
20
phase response
0
0
10 100 1k 10k 100k 1M 10M 100M frequency,
Hz

Frequency response
Phase Avol Compensated

shift
100
80 phase response A
2700 D
60 V
1800
E
40
90O L
20 I
0 N
0
10 100 1k 10k 100k 1M 10M 100M frequency,
Hz

Phase response
 A single RC network may produce a
phase shift of up to –900.
 Compensated op-amps offer more
A
stability because the phase lag does D
not exceed 900. V
E
 In an uncompensated op-amps, the L
phase lag increases as the number of I
N
stages increases. The total phase lag is
given by:
1 
f  1  f  1  f 
tot   tan    tan    ...  tan  
 1
fc  2
fc  n
fc
References
1. Millman, Jacob and Arvin Grabel
Microelectronics 2nd ed. New York:
McGraw-Hill, 1987.
2. Franco, Sergio Design with Operational
Amplifiers and Analog Integrated Circuits A
D
3rd ed. New York: McGraw-Hill, 2002. V
3. Savant, C.J.; Roden, Martin S.; and E
Gordon L. Carpenter Electronic Design: L
I
Circuits and Systems Redwood City, N
California: The Benjamin/Cummings
Publishing Company, Inc., 1987.
4. Gayakwad, R. Op-amps and Linear
Integrated Circuits 4th ed. Upper Saddle
River, New Jersey: Prentice Hall, 2000.

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ADVELIN

Lecture 3: Introduction to Operational Amplifier

intermediate level shifting output

•The level shifting stage can be an emitter follower with

Active load Short circuit protection circuit

Uses on-chip trimming to reduce offset.

Lecture 3: Introduction to Operational Amplifier

Open-loop bandwidth infinite Dominant pole (10 Hz)

Input currents (Bias zero < 0.5 A

Lecture 3: Introduction to Operational Amplifier

741 – 2-stage architecture; LM108 – superbeta;

Lecture 3: Introduction to Operational Amplifier

* Reducing resistances will increase power

Lecture 3: Introduction to Operational Amplifier

Vos  1  1 5mV   10mV

Lecture 3: Introduction to Operational Amplifier

VOL  VEE  VCE17(min)  VEB22(on)  VEB20(on)

VOL  VEE  2.1V

Lecture 3: Introduction to Operational Amplifier

Lecture 3: Introduction to Operational Amplifier

Figure (a) and (b) show the effect on the output

Lecture 3: Introduction to Operational Amplifier

Lecture 3: Introduction to Operational Amplifier

Lecture 3: Introduction to Operational Amplifier

Lecture 3: Introduction to Operational Amplifier

Lecture 3: Introduction to Operational Amplifier

Phase Avol Compensated

Lecture 3: Introduction to Operational Amplifier

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