Electronics Chapter 6

ECE 1231
Electronics
Dept. of Electrical and Computer Engineering

International Islamic University Malaysia
Chapter 5
The Field Effect Transistor
MOS Field Effect Transistor 1-3
 The metal-oxide-semiconductor field-effect transistor

(MOSFET) became a practical reality in the 1970s.
 The MOSFET, compared to BJTs, can be made very small,
i.e., it occupies a very small area on an IC chip.
 Since digital circuits can be designed using only MOSFETs,
with essentially no resistors or diodes required, high-density
very large scale integration (VLSI) circuits, including
microprocessors and memories, can be fabricated.
 The MOSFET has made possible the handheld computer,
the powerful personal computer.
 MOSFET can also be used in analog circuits.
© Electronics ECE 1231

MOS Field Effect Transistor 1-4
 In the MOSFET, the current is controlled by an electric

field applied perpendicular to both the semiconductor
surface and to the direction of current.
 The phenomenon used to modulate the conductance
of a semiconductor, or control the current in a
semiconductor, by applying an electric field
perpendicular to the surface is called the field effect.
 The basic transistor principle is that the voltage
between two terminals controls the current through the
third terminal.

Two-Terminal MOS Structure 1-5
 The heart of the

MOSFET is the metal-
oxide-semiconductor
capacitor.
 The metal may be
aluminum or some
other type of metal.
 In most cases, the metal is replaced by a high-conductivity

polycrystalline silicon layer deposited on the oxide.
 The parameter tox is the thickness of the oxide and εox is the
oxide permittivity.

 The physics of the

MOS structure can be
explained with the aid
of a simple parallel-
plate capacitor.
 An insulator material
separates two plates.
 With this bias, a negative charge exists on the top plate, a
positive charge exists on the bottom plate, and an electric
field is induced between the two plates.
 The capacitance of the parallel capacitor is C = εA/d, where
A = area, d = distance, ε = permittivity of the medium.
 A MOS capacitor with a p-type

semiconductor substrate: the
top metal terminal, called the
gate, is at a negative voltage
with respect to the substrate.
 Like parallel-plate capacitor, a
negative charge will exist on
the top metal plate and an
electric field will be induced.
 If the electric field penetrates
the semiconductor, the holes in the p-type semiconductor
will experience a force toward the oxide-semiconductor
interface and an accumulation layer of holes will exist.
 The same MOS

capacitor, but with the
polarity of the applied
voltage reversed.
 A positive charge now
exists on the top
metal plate and the induced electric field is in the opposite
direction.
 If the electric field penetrates the semiconductor, holes in
the p-type material will experience a force away from the
oxide-semiconductor interface.

 As the holes are pushed away

from the interface, a negative
space-charge region is created.
 Minority carrier electrons are
attracted to the oxide-
semiconductor interface.
 This region of minority carrier
electrons is called an electron
inversion layer.
 The magnitude of the charge in
the inversion layer is a function
of the applied gate voltage.
 The same basic charge

distribution can be obtained
in a MOS capacitor with an
n-type semiconductor
substrate.
 A positive charge is created
on the top metal plate if a
positive voltage applied to the top gate terminal and an
electric field is induced.
 In this situation, an accumulation layer of electrons is
induced.

 If a negative voltage is
applied to the gate terminal,
a positive space-charge
region is induced by the
induced electric field.
 This region of minority
carrier holes is called a hole
inversion layer.
 The magnitude of the
charge in the inversion layer
is a function of the applied
gate voltage.

n-Channel Enhancement-Mode MOSFET 1-12
● Transistor Structure
 The gate, oxide, and p-type
substrate are the same as
those of a MOS capacitor.
 There are two n-regions,
called the source and drain
terminal.
 The current in a MOSFET is
the result of the flow of charge
in the inversion layer, called A simplified cross section
the channel region, adjacent of a MOSFET with
to the oxide-semiconductor channel length L and
interface. channel width W

● Basic MOSFET Operation

 With zero bias applied to
the gate, the source and
drain terminals are
separated by the p-region.
 This is equivalent to two
back-to-back diodes.
 The current in this case is
essentially zero.

 If a large enough positive

voltage gate voltage is
applied, an electron
inversion layer connects
the n-source to the n-drain.
 A current can then be
generated between the
source and drain terminals.
 Since a voltage must be applied to the gate to create the inversion
charge, this transistor is called an enhance-mode MOSFET.
 Since the carriers in the inversion layer are electrons, this device
is called an n-channel MOSFET (NMOS).

Ideal MOSFET Current-Voltage 1-15
Characteristics – NMOS Device
 The threshold voltage of the

n-channel MOSFET, denoted
as VTN, is defined as the
applied gate voltage needed to
create an inversion charge.
 If the gate is less than the
threshold voltage, the current
in the device is essentially
zero.
 If the gate voltage is greater
than the threshold voltage, a
drain-to-source current is
generated.

 A positive drain voltage creates a reverse-biased

drain-to-substrate pn junction.
 So current flows through the channel region.
 Not through a pn junction.

● The iD versus vDS characteristics for small values of vDS.
 When vGS < VTN, the drain

current is zero.
 When vGS > VTN, the
channel inversion charge is
formed and the drain
current increases with vDS.
 With a larger gate voltage,
a larger inversion charge
density is created, and the
drain current is greater for
a given of vDS.

● In the basic MOS structure for

vGS > VTN with a small vDS:
 The thickness of the inversion
channel layer qualitatively
indicates the relative charge
density.
 Which for this case is
essentially constant along the
entire channel length.

 When the drain voltage vDS
increases, the voltage drop across
the oxide near the drain terminal
decreases.
 It means that the induced inversion
charge density near the drain also
decreases.
 The incremental conductance of the
channel at the drain then decreases.
 It causes the slope of the iD versus
vDS curve to decrease.

 As vDS increases to the point where the
potential difference, vGS - vDS = VTN, the
induced inversion charge density at the
drain terminal is zero.
 The incremental channel conductance
at the drain is zero, means that the
slope of the iD versus vDS curve is zero.
 So,
or
where vDS(sat) is the drain-to-source
voltage that produces zero inversion
charge density at the drain terminal.

 When vDS becomes larger than

vDS(sat), the point in the channel at
which the inversion charge is just
zero moves toward the source
terminal.
 In the ideal MOSFET, the drain
current is constant for vDS > vDS(sat).
 This region of the iD versus vDS
characteristic is referred to as the
saturation region.

 The region for which

vDS < vDS(sat) is known
as the nonsaturation or
triode region.
 The ideal current-voltage
characteristics in this
region are described by
the equation:
, Kn = conduction parameter

 In the saturation region,

the ideal current-voltage
characteristics for the
vGS > VTN are described
by the equation:
where
μn = mobility of electrons.
and
Cox = oxide capacitance
per unit area.  Can be written in the form:
where k′n = μnCox


p-Channel Enhancement-Mode MOSFET 1-25
● Transistor Structure
 The substrate is now n-type
and source and drain areas
are p-type.
 The channel length, channel
width, and oxide thickness
parameter definitions are the
same as those for NMOS
device.
Cross section of p-channel enhancement-mode MOSFET

● Basic MOSFET Operation

 The operation of the p-
channel device is the same
as that of the n-channel
device.
 Except the hole is the
charge carriers rather than
the electron.
 A negative gate bias is required to induce an inversion layer

of holes in the channel region directly under the oxide.

 The threshold voltage for

the p-channel device is
denoted as VTP.
 Since the threshold voltage
is defined as the gate
voltage required to induce
the inversion layer, VTP < 0
for the p-channel
enhancement-mode device.
 Once the inversion layer has been created, the p-type
source region is the source of the charge carrier so that
holes flow from the source to drain.
 A negative voltage drain

voltage is required to
induce an electric field in
the channel forcing the
holes to move from the
source to the drain.
 The conventional current
direction for the PMOS
transistor is into the source
and out of the drain.
 The conventional current direction and voltage polarity for
the PMOS are reversed compared to the NMOS.
Characteristics – PMOS Device
 The ideal current-voltage characteristics of the PMOS device are

essentially the same as those as the NMOS device, but the drain
current is out of the drain and vDS is replaced by vSD.
 The saturation point is given by vSD(sat) = vSG + VTP.
 For the p-channel device biased in the nonsaturation region, the
current is given by:
 In the saturation region, the current is given by:

The drain current exits the drain terminal.

Characteristics – PMOS Device
 The parameter Kp is the conduction parameter for the p-channel

device is given by:

where W, L, and Cox are the channel width, length, and oxide
capacitance per unit area.
The μp is the mobility of holes in the hole inversion layer.
 Can be written in the form: where k′p = μpCox
 For a p-channel MOSFET biased in the saturation region, we

have:

Circuit Symbols and Conventions 1-31
 The NMOS Transistor:

(Conventional & simplified
circuit symbols)
 The PMOS Transistor:

(Conventional & simplified
circuit symbols)

MOSFET DC Circuit Analysis 1-32
● Common-Source Circuit
 The source terminal is
at ground and common
to both input and output
portions of the circuit.
 The CC acts as an open
circuit to dc but it allows
the signal voltage to the
gate of the MOSFET.
 In the dc equiv. circuit, since the gate current into the transistor is
zero, the voltage at the gate is given by a voltage divider principle:
Assuming that VGS > VTN.

 Since the transistor is biased in the saturation

region, the drain current:
 The drain-to-source voltage:
 If VDS > VDS(sat) = VGS – VTN, then the transistor is biased in the
saturation region.
 If VDS < VDS(sat), then the transistor is biased in the nonsaturation
region.


● Common-Source Circuit with PMOS

 The dc analysis is essentially the same as for
the NMOS circuit.
 The gate voltage:
 The source-to-gate voltage:
 Assuming that VGS > VTP, or VSG > VTP , we have:

and
 If VSD > VSD(sat) = VSG + VTP, then the transistor is biased in the
saturation region, if VSD < VSD(sat), it is in the nonsaturation region.

Load Line and Models of Operation 1-36
 The load line is given by:
or
 Two end points of the load line

determined in usual manner:
If ID = 0, then VDS = 5 V;
If VDS = 0, then ID = 0.25 mA.
 The Q-point of the transistor is
given by the dc drain current
and drain-to-source voltage.
 If the VGS < VTN, the drain

current ID = 0 and the Q-point
is in cutoff.
 As the VGS becomes just
greater than VTN, the device is
on and is biased in saturation
region.
 As VGS increases, the Q-point moves up the load line.

 The transition point is the boundary between the saturation and
nonsaturation regions, where VDS = VDS(sat) = VGS – VTN.
 As VGS increases above the transition point value, the transistor
becomes biased in the nonsaturation region.

Example
Determine the transition
point parameters for a
common-source circuit,
considering VTN = 1 V
and Kn = 0.1 mA/V2.

1-39
The MOSFET Amplifier
● Common-Source NMOS Transistor with Small-Signal Equivalent

Circuit:
where and ro = small-signal output resistance.

1-40
● A Basic Common-Source Configuration:
Assume that the transistor is biased in the saturation region by

resistors R1 and R2, and the signal frequency is sufficiently large
for the coupling capacitor to act essentially as a short circuit.

1-41
 The output voltage:
 The gate-to-source voltage: , Ri = R1║R2
 So the small-signal voltage gain:

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ECE 1231

Dept. of Electrical and Computer Engineering

 The metal-oxide-semiconductor field-effect transistor

© Electronics ECE 1231

 In the MOSFET, the current is controlled by an electric

© Electronics ECE 1231

 The heart of the

 In most cases, the metal is replaced by a high-conductivity

© Electronics ECE 1231

 The physics of the

 A MOS capacitor with a p-type

 The same MOS

© Electronics ECE 1231

 As the holes are pushed away

 The same basic charge

© Electronics ECE 1231

© Electronics ECE 1231

© Electronics ECE 1231

● Basic MOSFET Operation

© Electronics ECE 1231

 If a large enough positive

© Electronics ECE 1231

 The threshold voltage of the

© Electronics ECE 1231

 A positive drain voltage creates a reverse-biased

© Electronics ECE 1231

● The iD versus vDS characteristics for small values of vDS.

 When vGS < VTN, the drain

© Electronics ECE 1231

● In the basic MOS structure for

© Electronics ECE 1231

© Electronics ECE 1231

© Electronics ECE 1231

 When vDS becomes larger than

© Electronics ECE 1231

 The region for which

© Electronics ECE 1231

 In the saturation region,

© Electronics ECE 1231

© Electronics ECE 1231

Cross section of p-channel enhancement-mode MOSFET

© Electronics ECE 1231

● Basic MOSFET Operation

 A negative gate bias is required to induce an inversion layer

© Electronics ECE 1231

 The threshold voltage for

 A negative voltage drain

 The ideal current-voltage characteristics of the PMOS device are

 In the saturation region, the current is given by:

© Electronics ECE 1231

 The parameter Kp is the conduction parameter for the p-channel

 For a p-channel MOSFET biased in the saturation region, we

© Electronics ECE 1231

 The NMOS Transistor:

 The PMOS Transistor:

© Electronics ECE 1231

© Electronics ECE 1231

 Since the transistor is biased in the saturation

 The drain-to-source voltage:

© Electronics ECE 1231

© Electronics ECE 1231

● Common-Source Circuit with PMOS

 The source-to-gate voltage:

 Assuming that VGS > VTP, or VSG > VTP , we have: