Professional Documents
Culture Documents
X1 8
D0 – D7
CRYSTAL X2
8
A0 – A7
Vcc
Gnd 8
8085 A8 – A15
CPU
RESET
RESET OUT RD
WR
IO/M
LOGIC DIAGRAM
Vcc
AD0 – AD7
X1
Lower 8 - bit Address/Data Bus.
X2
RESET IN
READY A8 - A15
RST 7.5
ALE
RST 6.5 8085 RD
RST 5.5
WR
INTR
IO/M
INTA
S1
HOLD
S0
HLDA
RESET OUT
SID
CLK OUT
SOD
Gnd
DEMULTIPLEXING AD BUS
SIMPLIFIED ARCHITECTURE
B C INTERRUPT
CONTROL SERIAL I/O
D E CONTROL
H L
IR W Z
INCREMENTER/
A M_TMP
DECREMENTER
CRYSTAL SP
M2
PC
ALU M1
X1 X2
F COUT C3 M0
TIMING
and
CONTROL UNIT FLAGS
C0 C1 C2 Cn
AR (H) AR (L) DR
8 8 8
A8 – A15 A0 – A7 D0 – D7
INTERNAL ARCHITECTURE
FLAGS
b7 b6 b5 b4 b3 b2 b1 b0
SF ZF X AC X PF X CY
SF ZF X AC X PF X CY
23 = 0 0 1 0 0 0 1 1
15 = 0 0 0 1 0 1 0 1
38H 0 0 1 1 1 0 0 0
X X
Result is NON- ZERO ,
ZF = 0.
No CARRY from MS There are 3 1s, PF = 0.
bit, CY = 0.
69 = 0 1 1 0 1 0 0 1
18 = 0 0 0 1 1 0 0 0
81H 1 0 0 0 0 0 0 1
X
Result is NON- ZERO ,
ZF = 0.
No CARRY from MS There are 2 1s, PF = 1.
bit, CY = 0.
CB = 1 1 0 0 1 0 1 1
E9 = 1 1 1 0 1 0 0 1
1 1 0 1 1 0 1 0 0
Result is NON- ZERO ,
ZF = 0.
There is a CARRY There are 4 1s, PF = 1.
from MS bit, CY = 1.