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Mode 3: Thyristors T 3 and T 4, and all four-diodes are now conducting so that
the load is effectively connected in parallel with both commutating capacitors.
This RLC circuit undergoes a transient response during which the load current
falls to zero and reverse. When a load current attains a value I, diodes D1 and
D2 become reverse biased. This terminates Mode 3 and completes the commutation
process.
Mode 4: For the next half-cycle, the source current I is flowing through T 3,
D3, the load, D4, and R 4. Note that the capacitor voltage is now EL , as shown in
Fig. 9.3(d), and the capacitor hold this voltage until the next commutation.
The d.c. current source delivers a unidirectional current I to the inverter, and
when the inverter feeds a reactive or regenerative load, the d.c. supply current
cannot reverse as it did in the case of a VSI. However, the feedback diodes of
VSI have been removed, allowing the d.c. link voltage to change polarity and
permitting a return of energy to the d.c. link by virtue of a reversal of d.c. link
voltage rather than a reversal of d.c. link current. When T 3 and T4 are gated to
initiate Mode 2, the inverter input voltage, Edc, goes negative, as shown in Fig.
9.3(e), and remains negative throughout this interval. Hence, the input power
Edc. I is also negative, indicating that power is being returned to the d.c. current
source.
2 3 È 1 1
iA = I Ísin w t sin 5w t sin 7w t
p Î 5 7
1 1 ˘
+ sin 11w t + sin 13w t L˙ (9.3)
11 13 ˚
Thus, the fundamental component of a.c. line current has an amplitude of
2 3I p , and RMS value of 6 I /p or 0.78I.
The unique relationship between input and output voltage magnitudes for the
six-step VSI has its counterpart in the unique relationship between input and
output current magnitudes for the current-fed inverter. If the CSI feeds the
balanced delta-connected load of Fig. 9.6(a), the phase current has the six-step
waveform of Fig. 9.6(b), which is characteristic of the line-to-neutral voltage
for a balanced star-connected load fed by a six-step VSI. By Fourier analysis:
2 È 1 1
iR = I Ísin w t + sin 5w t + sin 7w t
p Î 5 7
1 1 ˘
+ sin 11w t + sin 13w t + L˙ (9.4)
11 13 ˚
Clearly, the current waveforms delivered by the six-step CSI have pronounced
low order harmonics. In an a.c. motor drive, these harmonics give rise to pulsating
torques and irregular shaft rotation at low speeds, as in the case of six-step VSI
drive.
When an electrical load is fed from an a.c. current source, the terminal voltage
waveform is determined by the response of the load to the applied current. The
di di
voltage across the inductor L is L , where is the rate of change of current.
dt dt
Consequently, the idealised current waveforms of Figs 9.5 and 9.6 cannot be
realized with practical inductive loads because the instantaneous step changes in
current would develop voltage spikes of infinite amplitude. In practical circuits,
the rate of change of load current must be limited to keep the terminal voltage
within the peak voltage capability of the inverter thyristors. The commutation
interval, during which load current is transferred from phase-to-phase, must be
sufficiently long to reduce the rate of change of current to an acceptable value.
This constraint does not drive in a VSI because the feedback diodes provide a
path for inductive load currents to charge the d.c. link capacitor. This arrangement
prevents rapid interruption of load current and clamps the inverter output voltage.
In a CSI, however, there are no reverse current paths because the feedback
diodes are removed, and the commutation interval can only be shortened at the
expense of increased voltage stresses on the inverter devices.
Fig. 9.5 ASCI (a) Circuit diagram: (b), (c), (d) idealized a.c. line current
waveform; and (e) thyristor gating sequence
Induction Motor Voltage Waveforms: For an induction motor load, the terminal
voltage waveform is determined by the impedance presented to the fundamental
and harmonic components of the inverter output current. At harmonic frequencies,
the input impedance of the motor is effectively the sum of the stators and rotor
leakage reactances. The reactances are large at harmonic frequencies but are
relatively small at fundamental frequency. Consequently, fundamental and harmonic
effects can be separated and the induction motor represented by the approximate
equivalent circuit of Fig. 9.7(a), in which the total leakage inductance per phase,
L, is placed in series with each of the fundamental phase voltage sources, Ea, Eb ,
and Ec. When the induction motor is fed from a current source, the terminal
voltages are obtained by superposition of the fundamental voltages, Ea, Eb and
di
Ec, and the L voltages developed across the leakage inductances.
dt
Commutating circuit analysis The ASCI has a relatively simple circuit, but an
analysis of the commutating action is complicated due to the fact that the
commutating phase interacts with the other two phases and the motor load.
Figure 9.8 shows the CSI feeding a star-connected induction motor. Inverter
operation is assumed to be in a steady state condition with motor speed constant.
The commutating cycle proceeds as follows:
Mode 1: In this mode, the inverter is in the normal operating mode between
commutations. Assume thyristors T 1 and T2 have been conducting for sometime,
so that phases A and C carry current but phase B does not. The resulting current
path is shown in Fig. 9.8(a). Capacitors C1, C3 and C5 are assumed to be charged
with the voltages EL , zero, and EL , respectively. When the inverter is first
switched ON, the capacitors must be precharged with a voltage distribution of
this nature, but the auxiliary precharging circuit is not needed subsequently.
Mode 2: When thyristor T 3 is triggered, T 1 is reverse-biased by the voltage on
capacitor C1, and turn-off. As shown in Fig. 9.8(b), the current I, which was
flowing in T1, is now flowing through T3, the capacitor bank formed by C1 in
parallel with C3 and C5, and diode D1. During this charging interval, the constant
source current, I, linearly charges the capacitor bank. The outgoing thyristor, T 1,
is reverse-biased until the motor phase currents have the same values as existed
during Mode 1. This charging mode ends when diode D3 starts to conduct.
Mode 3: This is the current transfer mode during which motor current transfers
from phase A to phase B, as shown in Fig. 9.8(c). When diode D3 conducts, the
upper capacitor bank is connected in parallel with the motor through diodes D1
and D3. The resulting LC circuit resonates, and in one quarter of the resonant
period the oscillatory current reduces the phase A current from I to zero, and
increase the phase B current from zero to I. Diode D1 then blocks, and the
commutation cycle is complete.
Mode 4: The source current I is now feeding phases B and C through thyristors
T 3 and T 2, as shown in Fig. 9.8(d). This condition lasts until T 4 is gated to initiate
the next commutation. Because D3 is the only conducting diode in the upper
group, the upper capacitor group retains its charge until the next upper group
commutation.
The duration of transfer Mode 3 determines the rate of change of motor phase
di
current and the magnitudes of the resulting L voltage transients developed across
dt
the motor leakage inductances. These voltage spikes appear in the output voltage
waveform, as discussed previously and shown in Fig. 9.7. A large value of
commutating capacitance prolongs transfer Mode 3 and thereby limits the voltage
stresses on the inverter devices. The increased commutating time is, therefore, of
adequate duration to permit the use of low-cost, converter-grade thyristors rather
than expensive, inverter-grade devices with fast turn-off characteristics.