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Chapter 1: Digital Background
Chapter 2: Semiconductor backgro
Index
Chapter 3: CMOS Processing
Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8 Chapter 4: CMOS Basics
STA & SI
Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics Chapter 5: CMOS Layout Design

Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6

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DFM Introductio Parasitic Interconnect Corner (RC Manufacturing Effects and Their Dielectric Process Other
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Implant P+ Impurities: CMOS P
5)
Monday, March 28, 2011
Implant P+ Impurities: CMOS Process
Chapter1 Chapter2 Chapter3 Chapter
"Time Borrowing" : Static Timing Analysis (STA) basic (Part 2)

STA & SI:: Chapter 2: Static Timing Analysis

2.1 2.2 2.3a 2.3b 2.3c 2.4a
Basic Concept Of Basic Concept of Setup-Hold Examples:S-H
Timing Paths Time Borrowing Timing Path Delay
Setup-Hold Violation Time/Violation
2.4b 2.4c 2.5a 2.5b 2.6a 2.6b
Interconnect Delay Delay - Wire Load Maximum Clock Calculate “Max Clock Freq”- Fix Setup-Hold
Fix Setup-Hold Violation-1
Models Model Frequency Examples Violation-2 Vlsi expert
2.6c 2.7a 2.7b 2.7c 2.8 Like Page 5.3k like

Fix Setup-Hold Incr/Decr Delay Incr/Decr Delay 10 ways to fix Setup-Hold

Incr/Decr Delay Method-3
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Static Timing analysis is divided into several parts:

Part1 -> Timing Paths

Part2 -> Time Borrowing
Part3a -> Basic Concept Of Setup and Hold Blog A

Part3b -> Basic Concept of Setup and Hold Violation ► 20

Part3c -> Practical Examples for Setup and Hold Time / Violation ► 20
► 20
Part4a -> Delay - Timing Path Delay
► 20
Part4b -> Delay - Interconnect Delay Models
► 20
Part4c -> Delay - Wire Load Model VLSI EXPERT (vlsi EG)
google.com/+Vlsi-expert ► 20
Part5a -> Maximum Clock Frequency
Bridging Gap Between ► 20
Part5b -> Examples to calculate the “Maximum Clock Frequency” for different circuits. Acdamia and Industry ▼ 20
Part 6a -> How to solve Setup and Hold Violation (basic example) ►
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Part 6b -> Continue of How to solve Setup and Hold Violation (Advance examples) ►
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Part 6c -> Continue of How to solve Setup and Hold Violation (more advance examples) ►

Part 7a -> Methods for Increase/Decrease the Delay of Circuit (Effect of Wire Length On the Slew) ►

Part 7b -> Methods for Increase/Decrease the Delay of Circuit (Effect of Size of the Transistor On the Slew) ▼
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Part 7c -> Methods for Increase/Decrease the Delay of Circuit (Effect of Threshold voltage On the Slew)
Part 8 -> 10 ways to fix Setup and Hold Violation.
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In a ASIC there are majorly two types of component. Flip-flop and other is Latches. Basically Here we will discuss about Latched based timing
analysis.
Before this we should understand the basic differences between the latch based design and flip-flop based design.
Edge-triggered flip-flops change states at the clock edges, whereas latches change states as long as the clock pin is enabled.
The delay of a combinational logic path of a design using edge-triggered flip-flops cannot be longer than the clock period except for Subscribe To VLSI EXPERT

those specified as false paths and multiple-cycle paths. So the performance of a circuit is limited by the longest path of a design.
Posts
In latch based design longer combinational path can be compensated by shorter path delays in the sebsequent logic stages.So for
higher performance circuits deisgner are turning to latched based design. Comments

Its true that in the latched based design its difficult to control the timing because of multi-phase clockes used and the lack of "hard" clock edges at
which events must occur. Popular Posts

The technique of borrowing time from the shorter paths of the subsequent logic stages to the longer path is called time borrowing or cycle "Timing Paths" : Static
Timing Analysis (STA) ►
stealing.
basic (Part 1)
► 20
Lets talk about this. Please See the following figure. Basic of Timing ► 20
Analysis in Physical
Design
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Example of Latched based design. Delay Models" : Static
Timing Analysis (STA)
basic (Part 4b)

There are 4 latches (positive level sensitive). L1 and L3 are controlled by PH1 and L2 and L4 are controlled by PH2. G1, G2, G3 and G4 are combinational "Time Borrowing" :
logic paths. For now assume a library setup time is zero for the latches and zero delay in latch data-path in the transparent mode. Static Timing Analysis
(STA) basic (Part 2)
Now if assume that if designs using edge-triggered flip-flops, the clock period has to be at least 8 ns because the longest path in G1 is 8 ns. Now as the clock
pulse is 5ns , there is a voilation at L2. On the other hand, if the design uses latches , L2 latch is transparent for another 5ns and since the eighth (8th) ns is 10 Ways to fix SETUP
within the enabled period of L2, the signal along path1 can pass through L2 and continue on path2. Since the delay along path2 is 2 ns, which is short enough to and HOLD violation:
compensate for the overdue delay of path1, this design will work properly. In other word we can say that path1 can borrow sometime (3ns) from the path2. Static Timing Analysis
(STA) Basic (Part-8)
Since the sum of path1 and path2 is 10ns, which is the required time of L3, there will be no voilation in either of the Latches.
For the same reason, path3 can borrow some time (1ns) from path4 without any timing violation. 5 Steps to Crack VLSI
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Note: A latch-based design completes the execution of the four logic stages in 20 ns, whereas an edge-triggered based design needs 32 ns.

Lets see this in a more complex design. Its self explanatory. Recent Visitors

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19 comments: Followers

Anonymous January 5, 2012 at 3:41 AM

Hi, the example you have provided is an out of phase clock triggered latches. But in "Few Important things" you mentioned time borrowing occur for the
same phase of the same clock. Could you please clarify or provide a different example with single clock.
Reply