CONTENTS

/ TK I / No. 3373E CHAPTER 1 GENERAL

1. CONSTRUCTION OF THE CCD COLOR IMAGE
SENSOR ...•........•........•... 1-1
CHAPTER 2 ·CAMERA
I VM-E10A 1. RELATED CIRCUITS ..................... 2-1
2. SIGNAL PROCESSING CIRCUIT .... ; ...... 2·2
2. COf\JFIGURATION OF CIRCUITS ........... 4-3
3. CYUNDER SERVO ...................... 4-3
4. CAPSTAN SERVO .................•..... 4-4
CHAPTER 5 VIDEO
1. VIDEO SIGNAL INPUT/OUTPUT CIRCUITS .. 5-1

SERVICE MANUAL 3. AUTOMATIC FOCUS CONTROL CIRCUIT ..• 2-14

MANUAL RELATED TO THE VM-E10A
MODEL/TITLE
VM-E10A Technical Data
4. ELECTRONIC VIEWFINDER ............•. 2·16
CHAPTER 3 SYSTEM CONTROL
1. GENERAL DESCRIPTION ................ 3-1
2. POWER SUPPLY ...•................... 3-2
3. DATA COMMUNICATION ................. 3-4
4. KEY INPUT .•...•..•.......•..........• 3-5
Manual No. 5. TAPE/TROUBLE DETECTOR ..•........... 3-5
3372E 6. LOADING MOTOR CONTROL .•..........• 3-7
7. ASSEMBLE RECORD CONTROL CIRCUIT .•. 3-8
8. MICROPROCESSOR PIN FUNCTIONS ....•. 3-9
CHAPTER 4 SERVO
1. GENERAL DESCRIPTION ................. 4·1
2. RECORD AMPLIFI ERS/PREAMPUFIERS •... 5-2
3. LUMINANCE SIGNAL PROCESSING
CIRCUITS ........................ 5-3
4. CHROMINANCE SIGNAL PROCESSING
CIRCUITS .......................• 5-1 O
5, 47+1 /4fH SIGNAL I fsc (3.58MHz) SIGNAL
GENERATORS .................... 5-12
CHAPTER 6 AUDIO
1. GENERAL ............................. 6-1
2. AUDIO SIGNAL INPUT/OUTPUT CIRCUITS .. 6-2
3. AUDIO SIGNAL PROCESSING CIRCUITS ... 6-3
CHAPTER 7 MAECHANISM
1. GENERAL DESCRIPTION ................ 7-1
2. OPERATIONS IN ALL MODES ............. 7-2

CHAPTER 1 GENERAL
Table 1-1 Specifications of the CCD Color Image
1. CONSTRUCTION OF CCD COLOR Sensor
IMAGE SENSOR (Fig. 1-1) Item
Chi Size mm
Table 1-1 shows specifications of the CCD color image
sensor, ICX026BK Ima e Size mm
Effective Picture Elements

O tical-black
Color Filter

510C27COBJ)

~----------
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------ -- --- ----------- --- ----., I

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(13(00))
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SPECIFICATIONS AND PARTS ARE SUBJECT TO CHANGE FROM IMPROVEMENT OUTPUT 11 ' HORIZONTAL SHIFT REGlSlER I

L_ 13 ----~------------------------L-
18 19
______ J
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Fig. 1-1 Construction of CCD Color Image Sensor

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 -::· . ,· .. •
CHAPTER 2 CAMERA
1.. RELATED CIRCUITS (Figs. 2·1 and ~-2) 2) Horizontal Drive Pulses - . , " · ·:
* Horizontal shift register clock pulses (H1 and H2), ·
1-1. CCD Color Image Sensor Driver(Fig. * Resetpulse (R) ·· ·· 1

2-1) . . . . 3) Signal Processing Pulses. · -

This consists of a driVe pulse generator,.vertical driver
and horizontal dfiver.
1~M. Drive.Pulse Generator {IC1202: DRIVE
PULSE GEN) . . . . . .. . 1~1~2. Vertical Driver {IC1201: VERT. PRIVEFl) ·., .
A crystal oscillator (X1201: 19.07MHz) connectedb.e-
tween pins 1 (OSC OUT) and 2 (OSC IN). forms ayolt-
age controlled oscillator and generates a _19.07MHz
signat :Th.is·.· reference· signal ·is· comp_ared. with the
horizontal drive (CHO) putse supplied from a sync gen-
erator (IC1211: SYNC GENf Jhe error sign_al at pin 46
(LPF) is fed back to ~ vari~cap diode (01206)./arid the
reference signal synchronized with the CHO pulse is ob-
tained. The reference signal is divided by 2 to generate
a 9.5MHz reference signal. This 9.5MHz reference sig-
nal is supplied to the CCD 1H delay circuit from pin 4.
IC1202 generates the 9.5M Hz sensor drive pulse and sig-
nal processing pulses. IC1201 accepts 4-bit digital data
(SHUT.1 to SHUT.4) from a system control sub micro-
processor (IC1901: S-µ.P) and changes the shutter
speed.
Output Pulses
1) Vertiqal Drive Pulses
* Vertical shift register-clock pulses (V1to V4), ·
* Electric charge transfer pulses (CH1 and CH2),
* Overflow dr?in pulse (SUB)
*Horizontal optical-black pulse {HOB);
*· Preblanking pulse (P.BLK), ···
* Line sequential pulse (fH/2);. · ..
* Sampling pulses (SH1 and,SH2) :
This generates four vertiea! shift register :c.l()ck p~lses
{<j>V~ to <f>V4) with four phases V{.ithfour input, pulses, V1
to V4; and two input pulses, Cf:i1 a·nd CH2; and·~~pplie~
them to a sensor. (l,C1001 :.SENSOR).Jhe <f>Y1. a119 fV3
pulses have three:v61tages (h.!gh, ~.iddle aiic:.f loirl)~ ·High
voltage is approx. 15V(at pin 20) •..at.middl~_vgl~ge_, pin
15 is grounded (OV), and loVfvoltag~ is appr,o~.~9V (at
pin 18). The qN2 and <I>V4 pulses have two voltages "(mid-
dle and low), and middle voltage is OV (at pin 15) and low
voitage is -9V (at pin 18). The V.SUB pulse also has two
voltages (high and low); high voltage is 15V (at pin 20)
and low voltage is -9V (at pin 18).
1-1-3. Horizontal Driver {Q10031o Q1006: DRIVER)
Two pulses, <j>H1 and <j>H2, are directly supplied to
1c1001. The pulse, ¢R. is supplied tolC1001 through the
driver composed of 01003 to 01006.
1-1.:.4.. Drive.Pulses-~frlcf Biases of IC.1oof .-:·:-:: :, ,.::".'.
(1) · Vertical·Shift·Register ClockPtirses {~v1 fo. ·ctN4)
These are supplied:t,o th~ ,verticat·s~iftregi~er·~nd time
the transfer of charges fro~th_e.pictwe~el~rnent~..to the
• ;~ ~
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• • ,,• •• • :,,' : • •• 1 ' ., .' .' /.r'< 'r

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!C1001
SENSOR
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 vertical shift register and their mixing during the vertical
blanking period and transfer of charges from the vertical
shift register during the horizontal blanking period.
(2) Overflow Drain Bias (V.SUB)
This sets the voltage of the overflow drain. The overflow
drain is provided between each picture ele!'Tler:i~ to.-
reduce blooming by preventing charges from entering·
the adjacent vertical shift register when excess charge· :
occurs due to a very bright subject.-; · . : _ . 2 of IC42AF. - These .two-voltages are compared with
This voltage is generated by a bias generator (01007, · . reference voltagesat-pins s (approx. 3.7V) and 3 (ap~
01008: BIAS GEN) wtththeaidofRT1201 (SENSOR SUB
VOLTAGE). The overflow drain (SUB) pulse is superim-
posed on this voltag~. This pulse Is used to sweep out
unnecessary charges When the shutter is operated;
(3) Horizontal Shift_Register Clock Pulses (<j>H1 and
~~ ' -
These are supplied to the horizontal shift register and
time the transfer. of charge from the horizontal shift
register to the output circuit during the horizontal scan-
ning period. - •.
(4) Reset Pulse (<j>R) · angle direction. When: the telephoto switch is pressed;
This is supplied to the output circuit and timethe reset-
ting of charge which remains in the output circuit after
the previous scanning before charge istransferred from
the horizontal shi~ register to the output circuit during
the horizontal scanning period. - pressed.
(5) Biases
*Reset drain (RD, pin 15), ·
*Output gate (VGG, pin 12),
* Protection transistor bias (VL, pins 7 and 16),
* Output source (VSS, pin 13)
WIDE
5'13--Wr--E°'C>-..--t--.;,_-<
Fig. 2-2 Zoorn Motor Driv~r
2. SIGNAL PROCESSING CIRCUITS (Figs.
2·3to2-9)
2·1. Preprocessing Circuit (Figs. 2·3 to-
2-6)
The output signal from the sensor (IC1001: SENSOR) is
supplied to the CDS circuit in the preprocessing circuit
(IC1202: PAEPROCESS) through a buffer (01001: BUF}
and pin 6.
2-1-1. CDS Circuit (Fig. 2-4)
IC1001 generates a noise portion (A period) and a sig-
11•11•ii'li"'"Wil-ii?l1Pil""il:lJ'llYll-Tll'TI·:m1-11·:- - - - - - · ·.--·-··--...-•.--------·-------------..----3 ·-------
1-2. Zoom Motor Driver (Fig. 2-2)
The zoom motor is driven by two comparators (IC42AF:
COMPA.) and a motor driver (JC41AF: MOTOR DRIVER).
_The. zoom_ direction-Js- determined by pr.essirig--the
telephoto switch or wide-angle switch. When_ neither
switch has been pressed, a voltage of approx. 2.SV which ·-
is divided by R40AFand R41 AF is supplied to pins s and
prox. 1.4V) and they are within the range of two reference
voltages, 3."N to 1AV. As a result, t_wo comparators out~
put "lo" at pins 7 and 1, and the zoom motor does not
turn. When the wide-angle swhch is pressed, the 5V3
power source is supplied to the two comparators, and
.the output atpin Tg9es "Hi:' and the other output at 'pin
1 goes"Lo"; Asaresult,adecoder(DECODE) inlC41AF
detects tbe voltages at pins 7 and 8, and cjetermines the
motor direction, controls driver (DRIVER) and turns the
zoom motor connected between pins 2and 3 in the wide~
both pins 5 and 2 of the two comparators· are grounded,
the output at pin 7 goes "Lo" and the other output at pin
1 goes "Hi". Thesevoltages are detected by the decoder
in the same way as when the wide-angle switch is
·· ·
The speed ~f rotation of the motor is determined by the
voltage at pin 5 (SPEED CONT.) and in this model the
voltage at pin 5 ls set to approx.1.4V, and it takes about
8 seconds to zoom from end to end. . ..
-The reference voltage generator(V.REFGEN) gene~~tes
the reference voltage to pin 6 {2.5V) only.when either or
both inputs goes "Hi". ' ·
--- R48AF R49AF
(4.7k) (5.8k)
I • I
1c41'Af"_":'.;..:.;.;; _.J
MOTOR ORll/ER -
na~ portion including noise (B period) alternately. The
no1s~ ca.us~ by 1c1001 is m~inly low frequency.noise
that 1s superimposed on the signal; affecting t<Hhe sig-
nal-to-noise ratio (S(N)~ The CDS ·(Correlated Double
Samp~ing) ~ir~~~-r~f11C)~~s_ -~~If{ freqyerycy no.ise. by
~lan:ii:J.ing ~~e noise portion (A period) to a rated voltage··
and produce a continuous signal by replacing the noise':
: _portion with:the signal portion. It is composed of clamp-
. _.1ng and ~i:nple~hold circuits, and an amplifier.
(1) Clamping Circuit (CLAMP)
This clamps the noise portion (A period) of the signal (1)
to the rated voltage to remove the low frequency noise
when the SH1 pulse (2) is supplied. _ _. . . ·-
2-2
ti
(2) Sample-Hold Circuit (S/H)
Th~s samples the signal portion (B period) including the
noise (4) and holds it until the noise portion (A period)
when the SH2 pulse Is supplied. This produces the con§
tinuous signal (5) by replacing the noise portion with the
signal portion.
(3) _Amplifier (AMP)"_
This inverts and amplifies the continuous signal (5) and
supplies it (6) tci the AGC circuit and iris detector.
SH2
® level that serves as the reference level and the blanking
. @AMP@
lr-IPUT 1--11---l~- OUTPUT
:0.A..i ,
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Fig. 2-4 CDS (Correlated Double Sampling) Circuit
2-1-2. AGC Circuit
This consists of an AGC detector and amplifier and con-
trols a11 output signal level to keep it constant regardless
of the input signal level. This is the same as the AGC cir-
cuit. in the· processing circuit of previous models,
-however, .the AGC circuit is installed in the _stage follow-
ing the CDS circuit_ to Improve the S/N in this model.
·(1) • AGC Detector (AGC DET)
This iriplits the luma signal from pin 34 of a signal
processing .circuit (IC1206:_ PROCESS), compares its
level with areference voltage, generates an error voltage
(AGC voltage) that corresponds to the input signal level
and is-held by a capacitor (C1211) 9onnected to pin 10,
and supplies it to the amplifier as a gain control signal.
This normally operates as an average detector, however,
it operates as a peak value detector to prevent the out-
- put level frqm rising ex:cessively when the input signal
level exceeds a rated level. It also has a gate function to
rerriove .the reference (REF) pulse superimposed in the
blanking period:
(2) Amplifier (AGC)
This has characteristics such that its gain is inversely
proportional to the control signal level and the gain con-
trol range ls set to 2dB to 20dB. This gain is set to a min-
imum when "Hi" AGC KILLER signal is supplied from the
iris control circuit (IC1207: AIC).
2-3
2·!·3. Blanking/Clipping Circuit (BLANK/CLIP)
This blanks the input signal using the preblanking
(P.BLK) pulse, clips the white level more than a rated
level (900m.V) and add~ the REF pulse. The output sig-
nal Is supplied to a horizontal aperture correction circuit
(HORIZ. APERTURE CORRECT) and color separation
clrcutt·(COLOR SEPA.) through sample·hold circuit 1
(S/H1) .
2-1-4. Feedback Clamping Circuit (FB CLAMP)
This fixes the black level to match the levels of the black
level. This sample-holds the level of the black level of the
blanking output signal when the horizontal optical black
(H.08) pulse is supplied, compares its level with the level
of the blanking- period of the signal and generates an
error voltage. This error voltage is fed back to the input
signal supplied to the AGC amplifier, thus the DC level of
the black level is fixed.
2-1-5. Horizontal Aperture Correction Circuit
This emphasizes those parts of edges where black chan-
ges to white or vice versa in the horizontal direction and
CO?Sists Of a 170ns delay line, phase compensation cir§
c~it, subtracter, mi~erand differential amplifier. The input
signal is branched into two parts; one is supplied to the
170nsdelay line and the other is supplied tothe subtrac-
ter.
(1) 170ns Delay line (DL1201: 170ns DELAY)
This delays the signal by 170ns and supplies it to the
phase co,mpensation circuit and subtracter. This also
adds the double-delayed signal (340ns delayed) that is
reflected due to unmatching impedance with the 170ns
delay line and subtracter, to the input signal and
generates a sum signal.
(2) Pllase ~ompensation Circuit (PHASE COM PE.)
The phase distortion occurs (phase is delayed in the
edge emphasizing signal) if subtraction is performed.
T_herefore, this advances the phase of the 170ns delayed
signal to compensate phase distortion in the edge emf
phasizing signal.
(3) Subtracter (SUBTRACT)
This subtracts the sum signal from the 170ns delayed
signal and generates the edge emphasizing signal.
(4) Mixer
This adds the 170ns delayed signal and edge emphasizr
ing sig_nal and generates the edge emphasized signal.
(5) Differential Amplifier (Q1207: DIFF. AMP)
!hi~ input~ the A~C voltage held by C1211 and amplifies
it d1fferent1ally with a reference voltage of approx. 1 .4V.
Ther~for:. when th~ AGC voltage falls (rises} as the in·
comr~~ hg~t falls (n?es), the amount of the edge emf
phas1z1~g signal at pin 13 is decreased (increased).
The horizontal aperture corrected signal with the vertical
edge has been enhanced Is supplied to 4MHz lowpass
filter through the amplifier (01213, 01214: AMP).
2-1-6. 4MHz Lowpass Filter (DL 1202: 4MHz LPF)
This limits the bandwidth below than 4MHz and
generates a luma signal. The luma signal is supplied
through a buffer (01215: BUF) to the signal processing
circuit (IC1206: PROCESS).
3
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IC1206
01242
COMPA. PROCESS
2.!lV

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CAMERA ON

:'"'"""D
PHASE INV
SYNC COMPE.
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1Cf<l02
12
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CHARACTER'{-;;;...
C~t:A, L. - _ _ _,

Fig. 2-3 Signal Processing Circuit

2-4 2-5
--rrr-wrr1mnr-·. -·--·
 2-1-7. Color Separation Circuit {Fig. 2-5)
This consists of sample-hold circuits 1 to 6 which
separate the dot sequential signal that contains Informa-
tion of each picture element, mixers, 1H delay circuit and
gain control circuit.
(1) Sample-Hold Circuit 1 to 6 (S/H1 to S/H6)
1) Sample-Hofd Circuit 1 (S/H1)
· This sample-holds the input signal (non-delayed) when
the SH2 pulse is supplied. It generates an (Mg+ Cy) sig-
nal and (G +Ye) signal sequentially in the first horizontal
line (nH), and a (G +Cy) signal and (Mg+ Ye) signal in
the next horizontal line ((n + 1)H) (1).
2} Sample-Hold Circuit 2 (S/H2}
This sample-holds the input signal (1 H delayed) when
the SH2 pulse is supplied. It generates a {G +Cy) signal
and (Mg+ Ye) signal sequentially in the first horizontal
line (nH), and an (Mg +Cy) signal and (G +Ye) signal in
the next horizontal line ((n+1)H) (2).
3) Sample-Hold Circuit 3 (SfH3}
This sample-holds the Input signal when the SH1 A pulse
is generated. It generates an (Mg+ Cy) signal in the first
horizontal line and a (G +Cy) signal in the next horizon-
tal line (3).
4) Sample-Hold Circuit 4 (S/H4)
This sample-holds the·input signal when the SH1 B pulse
is supplied. It generates a (G+ Ye) signal in the first
horizontal line and an {Mg+ Ye) signal in the next
horizontal line (4).
5) Sample-Hold Circuit 5 (SJH5)
This sample-holds the input signal (1 H delayed) when
the SH1A pulse is supplied. It generates a (G+Cy) sig-
SH2
nal in the first horizontal Iine and an (Mg+ Cy) signal in
the next horizontal fine (5).
6} Sample-Hold Circuit 6 (SJH6}
This sample-holds the Input signal (1 H delayed) when
the SH1B pulse is supplied. It generates an (Mg+Ye)
signal In the first horizontal line and a (G +Ye) signal in
the next horizontal line (6).
These four color separated signals, (3) to (6), are sup-
plied to two mixers and a multiplexer (MULTIPLEX).
(2) Mixers 1 and 2 (MIX1 and MIX2)
Mixer 1 mixes two non-delayed signals, (3) and (4), and
supplies them to the AGC detector, feedback clamping
circuit and vertical enhancer. Mixer 2 also mixes two 1H
delayed signals, (5) and (6), and supplies them to the
AGCdetector, feedback clamping circuit and vertical en-
hancer.
(3) 1H Delay Circuit (IC1204: CCD 1H DELAY)
This delays the input signal· (1) by exactly 1H using the
9.SMHz CLOCK pulse that has the same frequency as
the horizontal drive pulse in the sensor.
(4) Gain Control Circuits
The DC level and amplitude of the non-delayed signal
and 1H delayed slgna1·vary because of the 1H delay
operation. If these signals are color separated as they
are, the color reproduction would deteriorate and color
moire would be Introduced. To avoid this, the DC level
and amplitude of the non-delayed and 1H delayed slg~
na!s are adjusted by the gain control circuits which con-
sist of feedback clamping circuit, AGC detector and AGC
amplifier. .
1) Feedback Clamping Circ11it (FB CLAMP)
SH!A
@

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l CLOCK I
I 1 3
'2s 5'"c"'Co ,;;1,
G1217 l SH2 SH1A MULTIPLEX
BUF>-=289-1__. ®
L.~!:.~.J
: IC1204
______ J
©

CD Mgl-Cy G•Vt Mg+Cy G+Y• ~ G+Yt •Vt G+cy

® I G+eyf;+vrj G-K) !Mivr j-G+Cy b+vr Ii~ f'iii+cy IG+Y+9"'"cv IG+Y• §+cv\
© I Mg-t-Cy I M<;J+Cy I Mg+Cy II\ I G-tey I G-tCy I I
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© I G+Yt I G•Yt I }} I Mg+Yt I Mg+Yr I ENHANCER
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I I G~Cy. I 5~ I I I I
© G+Cy G+Cy Mg-t-Cy Mg+Cy '-.+-...:.,--< LUMA.I_,
t.... __________

© [ Mg+Y• I Mg~v. I I G+Yt I G+'llP

· Color Separation

Fig. 2-5 Color Separation Circuit and Vertical Enhancer

dim LI
 This accepts two input signals; one is a non-delayed sig-
nal supplied from mixer 1 and the other is the 1H delayed
signal supplied from mixer 2. It compares the DC levels
of the two signals when the H.OB pulse Is supplied and
generates an error voltage corresponding to the level dif-
ferences. This errorvoltage ls fed back to the 1H delayed
signal input to the AGC amplifier to match the DC levels
of the non-delayed and 1H delayed signals.
2) AGC Detector (AGC DET)
This accepts two input signals, non-delayed and 1H
delayed, the same as the feedback clamping circuit,
compares the levels of the REF pulses that are superim-
oosed on the blanking period in the signal, and
generates an error voltage (AGC voltage). This AGC
voltage is held by C1210 connected to pin 12 and it is
supplied to the AGC amplifier.
3) AGC Amplifier (AGC)
The gain of this amplifier is proportional to the AGC volt-
age. Its gain is changed by the level of the AGCvoltage
to match the level of the REF pulse in the 1H delayed sig-
nal with that of the non-delayed signal.
2-1-8. Vertical Enhancer (VERT. ENHANCER, Fig. 2-
5)
This enhances those edges where black changes to
white or vice versa in the vertical direction and consists
of a subtracter, base noise clipping circuit and mixer.
(1) Subtracter
This subtracts the 1H delayed signal from the non-
delayed signal supplied from the corer separation circuit,
and generates an edge enhancing signal.
(2) Base Noise Clipping Circuit (BASE NOISE CLIP)
This removes base noise contained in the vertical edge
enhancing signal and generates an inverted vertical
edge enhancing signal. This also removes base noise
contained in the horizontal aperture correction signal
supplied from pin 26 and generates it with the vertical
edge enhancing signal.
(3) Mixer
This adds the edge enhancing signal to the horizontal
aperture corrected signal and generates the vertical
edge enhanced signal.
2-1-9. Multiplexer (MULTIPLEX, Fig. 2-6)
This produces the color signal using line interpolation,
improves the color reproduction and reduces color
moire. This supplies four signals from the sample-hold
circuits (SH3 to S/H6) to four switches (SW1 to SW4)
which are controlled bythe fH/2 pulse (1) and selects the
signals. · R = (Wr+Gr)-(Wb+Gb)
(1) SW1
fH/2 pulse is "Hi": the (Mg +Cy) signal of the signal
(2) is selected,
fH/2 pulse is "Lo":. the (Mg+ Cy) signal of the signal
·(4) is selected
As a result, a continuous (Mg+ Cy) signal (6) is
generated at pin 17 as the Wb signal.
{2) SW2
fH/2 pulse is "Hi": the (G +Ye) signal of the signal
(3) is selected,
fH/2 pulse is "Lo": the (G +Ye) signal of the signal
(5) is selected
2-7
• ' 1 •I I '' - / 0 ,. I"'°':-., I
10
As a result, a continuous (G +Ye) signal (7) is generated signal to pass only during the "Hi" period, according to the luma signal. The frequency of this trap is determined
at pin 18 as the Gr signal. the window gate 01'/G) pulse supplied from pin 5. There- by the voltage supplied to pin 11.
(3) SW3 fore, the top of the screen (approx. 1/3), and right and
fH/2 pulse Is "Hi": the (G +Cy) signal of the signal left of the screen viewed by this unit are cut off to prevent 2-2-4. Phase Compensation Circuit (PHASE EQ)
(4) is selected, the iris from closing unnecessarily when a very bright This compensates the delay time characteristics of the
fH/2 pulse is "Lo": the (G +Cy) signal of the signal subject like the sun is shot. luma signal caused by the 9.SM Hz trap.
(2) is selected (3) Detector (DET) and Lowpass Filter (C1216,
As a result, a continuous (G + Cy) signal (8) is generated 2-2-5. Gamma Correction Circuit (GAMMA)
R1341: LPF)
at pin 20 as the Gb signal. The gamma characteristic value of the CCD image sen-
These circuits integrate the iris detection signal to detect
(4) SW4 sor is 1 while that of the color receiver is 2.2. So, the cir-
Its average level for one field. The detected level is sup-
fH/2 pulse is "Hi": the (Mg+ Ye) signal of the signal cuit amplifies the luma signal non-linearly in order to set
plied through pin 7 to the non-inverting input of the driver
(5) is selected, the overall gamma characteristic value to 0.45 (-y
(DRIVER).
1/2.2).
fH/2 pulse is "Lo": the (Mg +Ye) signal of the signal (4) Motor Driver (MOTOR DRIVER)
(3) Is selected The input voltage is proportional to the iris detection sig- 2-2-6. Dark Clipping Circuit (DARK CLIP)
As a result, a continuous (Mg+ Ye) signal (9) is nal level. A reference voltage set up by RT1209 (AIC) is This clips the black level that seNes as the reference level
generated at pin 21 as the Wr signal. supplied to the inverting input (pin 8) of the driver_ With of the signal. The output signal is supplied to the luma
signal compensation and automatic white balance cir-
These four signals are supplied to a matrixing circuit this, the output voltage (pin 9) of the driver falls as the
cuits.
(R1266 to R1279, R1407: MATRIX) through buffers iris detection signal level falls. The iris motor operates
(01210, 01212, 01243, 01244: BUF). according to the difference between the C9V power
2-2-7. Luma Signal Compensation Circuit (LUMA
source and the motor drive voltage (pin 9). If the iris COM PE.)
detection signal level falls (rises), the iris motor works to
This improves the color reproduction of red when the
open (close) the iris. An electromotive force is induced
@ camera is shooting a subject under low-light conditions.
in the iris motor control coil according to the position and
This inputs the R-YL signal from the chroma noise
speed of an Iron piece in order to apply negative feed-
reducer (IC1211(2/4): CNR), clamps the R-YL signal,
@ back to the driver so ihat the iris moves smoothly. The
S/H 0 generates a compensation signal and adds it to the luma
4 Gr CG•Ye) output of the driver is also supplied to the AGC killer signal. This compensation signal has the opposite
(AGC KILLER). polarity to the red component and tt reduces the level of
© ®
~
(5) AGC.Killer (AGC KILLER) the red portion of the luma signal. By this, the gain of the
Gb(G•Cy)
When the output level of the driverfalls to a reference
Lo-..J ) red component of the chroma signal is artificially in-
® voltage (V.REF: 3V) as the iris detection signal level falls, creased. Therefore, color reproduction is improved.
SW4Hl._.f ® the output (pin 12) of the AGC kil!er becomes open. As
Co__ •I
Wr(Mg+Ye) The luma signal is output at pin 34 and is supplied to the
a result, the AGC voltage output (pin 1O) of IC1202 be- character mixer (IC1210: CHARA. MIX).
comes open, and the gain of the AGC circuit (AGC) is
r--fH---j
controlled by the AGC voltage (V.AGC). When the out- 2-3. Chroma Signal Processing Circuit
© put level of the driver rises above the reference voltage (Fig. 2·3)
@ [M9'+'CYJ]I IMg+Cy I G+Cy I II I G+Cy IMg+Cy I I (V.REF) according as the Iris detection signal level rises,
the AGC KILLER voltage ("Hi") is output via pin 12. As a The color separated and multiplexed four signals f:Nr,
® ~+Ye lMll+Ye//Mll•Y• lMg+Ye l 13+-Ye( result, the gain of the AGC circuit in IC1202 is set to min- Gb, Gr and Wb) are supplied to the matrixing circuit.
imum by the AGC KILLER voltage.
© ~l I G +Cy I Mg+Cy I t IMg +Cy I G +Cy I (
(6) Low Light Detector (LOW LIGHT OET)
2-3-1. Matrixing Circuit and Differential Amplifier
(1) Matrixing Circ.uit (R1266 to R1279, R1407:
@ IMg+Y• /Mg+Ye jMg+Ye l G +V• j G +Ye I G +Ve lMg+Ve) The AGC voltage generated by the AGC detector in MATRIX)
IC1202 is also supplied to the low light detector and Its This is a resistance matrixlng circuit and converts four
@ ~ IMg-tCyjMg+cvl % JMg+cvlMg+Cyj) level is compared with a reference voltage supplied to
signals fY'/r, Gb, Gr and Wb} to the three primary color
pin 13 (approx. 2.SV). When the.level of the AGC volt- signals (A, G and B). The three primary color signals are
@) [iii\IG+Ye l G+Ye j G+Ye(l G+Vel G+Ye I G+ve(
age becomes lower than the 2.8Vasthe luma signal falls, output with positive and negative polarities and a dif-
® ~/ I G -tCy I G +Cy Iu G +Cy I G +Cy I( this generates a "HI" LOW LIGHT DET signal which is ferential amplifier in the following stage converts them as
supplied to the system control sub. microprocessor follows.
@ jr.tqtVe \\Mg+Ve- jMg+Ye JMg +ve\}Mg+Ye jMg+Ve lMll+Ye \ (IC1901: S-µ.P). As a result, the shutter speed display in
the EVF screen begins to blink.
Fig. 2-6 Multiple>ier = (Mg+Ye)+(G+Ye)-(Mg+Cy)-(G +Cy)
2-2. Luma Signal Processing Circuit (Fig. =R
2-1~10. Automatic Iris Control Circuit (IC1207: AIC, 2-3) G = {Gb+Gr)-(V\/b+Wr)
Fig. 2-3). . . . = (G+Cy)+(G+Ye)-(Mg+Cy)-(Mg+Ye)
· The output signal from the .CDS circuit is supplied to the The luma signal is first supplied to a setup circuit.
=G
iris detector. 2-2-1. Y Setup Circuit (RT1213: Y SETUP) B = (Wb+Gb)-(Wr+Gr)
(1) Iris Detector (IC1202: IRIS DET) This adjusts the setup level of the luma signal.
This gamma corrects the signal to match the characteris.. = (Mg+Cy)+(G+Cy)-(Mg+Ye)-(G +Ye)
tics of the iris control in this model with that in the pre- 2-2-2. Feedback Clamping Circuit (FB CLAMP) =B
vious model and supplies it to the gate circuit in IC1207. The operation is the same as that in IC1202. (2) Bias Generator (01216: BIAS GEN)
(2) Gate Circuit (IC1207: GATE) This generates a bias voltage for resistor matrixing and
2-2-3. 9.5MHz Trap (9.SMHz TRAP)
This clips the signal during the "Lo" period to permit the also determines the amount of the -B signal via RT1202
This eliminates 9.5MHz sensor drive pulses remained in (MATRIX).
2-8
 (3) Differential Amplifier (IC1205: DIFF. AMP)
A3-channel chroma amplifier is provided.
1) R Channel
Adifferential amplifier produces the Rsignal from the +A
and -R signals.
2) G and B Channels
The G and B signals are produced in the same way as
the A signal. · The levels of two color difference signals are controlled
AT1204 (RED GAIN) connected across pins 13 and 14
and RT1203 (BLUE GAIN) connected across pins26and
27 control the gain of respective differential amplifiers to
adjust the white balance.
The three primary color signals are supplied to IC1206
through buffers (01218to 01220: BUF).
The configuration and operation of the chroma signal
processing circuit are basically the same as those in the
lumasignaJ processing circuit (9.SMHztrap, gamma cor-
rection, dark clipping circuits). The differences are as
follows.
2·3-2. Feedback Clamping Circuit (FB CLAMP)
The operation of the feedback clamping· circuit in the
green channel is the same as that in the clamping circuit
in IC1202. However, the feedback clamping circuits in
the red and blue channels are different.
The level of the output signal from the 1MHz lowpass fil-
ter is sample-held and its level is compared with the out-
put of a comparator (01241 : COMPA.), and an error
voltage is generated: This error voltage is fed back to
the Input signal through pin 3 when the H.08 pulse is
supplied. The red signal Is input to 01241, its level Is
compared with a reference voltage· of approx. 2.5V and
"Hi" is generated when the level of the red signal goes
lower than 2.SV. That is, the black level is fixed by this
operation.
2-3-3. White Balance Control Circuit (WHITE BAL)
This is an amplifier whose gain is variable within 15dB
according to the white balance control voltage
generated by the automatic white balance circuit (AUTO
WHITE BAL). The voltage vs. gain characteristic of the
R channel is inverted with respect to that of the Bchan-
nel. That is, gain rises with voltage in the A channel but
gain falls as voltage rises in the B channel. The circuit
maintains white balance in the .color temperature range
of 2,500K to 1O,OOOK.
2-3-4. YL Matrixing Circuit (YL MATRIX)
This generates the YL signal which is used to generate
the color difference signals from the A, G and B signals
which have undergone gamma·correction.
2-3-5. Color Difference Signal Matrixing Circuits (R-
Yl./B-VL MATRIX)
These generate the R-YL color difference signal from the
A and YL signals and 8-YL color difference signal from
the B and YL signals.
2-3-6: 1MHz Lowpass Filter (1MHzLPF)
This limits the bandwidth by removing high frequency
components hlghenhan 1MHz.. The .limiting of the
bandwidth is performed .for the three primary color sig-
nals In the previous model, however it is. performed for
the color difference signals in this model, to Improve
2-9
.-.. . . nszzm± · n snsm ·--··-·----~----~· . .--~-. ···
smear. The frequency of this lowpass filter is deter-
mined by the voltage at pin 35.
2~3-7. Gain Control Circuit (GAIN CONT.)
· This inputs the following three signals and controls the
gain of two color difference signals.
(1) Chroma Level Adjustment Voltage
by the voltage supplied to pin 44. · The gain is inversely
proportional to the voltage that is adjusted by RT1205
(CHROMA GAIN).
(2) low light Compensation Signal
The AGC voltage is input to the low light compensation
(01240, 01237: LOW LIGHT COMPE.) circuit, its level is
compared with a reference voltage (approx. 3.0V) and a
low light compensation signal is generated. This signal
is supplied through pin 44 with the chroma level adjust-
ment voltage and it reduces the color difference signals
with low light.
The output signal are supplied to the chroma noise
reducer and the automatic white balance circuit.
2-3-8. Chroma Noise Reducer (IC1211 (2/4): CNR)
This red.uces random noise to Improve the S/N.
It consists of the 1H delay circuit and mixer. The non-
delayed color difference· signal Is added .to the 1H
delayed color difference signal by the mixer to generate
an average color difference signal,. thus improving the
S/N by approx. 3dB. The SC1 (fsc)signal is input to drive
the CCC 1H delay circuit.
The R-YL signal output at pin 21 and B~YL signal output
at pin 23 are supplied to IC1210 through the setup cir-
cul · 2.5V
2-3-9. Setup Circuit (RT1214, RT1213: R-YLJB-YL
SETUP)
These adjust the setup voltage of the R-YL and B-YL sig-
nals. '
2-3-10: Automatic W~ite Balance Circuit (AUTO
WHITE BAL, Figs. 2-7 and 2·8) .
This generates the gain cGntrol voltages oi the R and 8
signals from two color difference signals and feeds them
back to the gain control circuits of the R and. B signals
' so that a white sllbjectis seen as white (R = G = B)
regardless of the light source. (col or temperature).
(1). Operation of CircuifElements . . .
This· circuit has two. channels for the.R-B signal and Mg-
G signal, however the Operation and configuration are
basically the same. The R-YL and 8-YL signals are sup-
plied to the subtracter and adder~ and the luma signal is
supplied to the white level setting circuit (WHITE LEVEL).
1) .Mode ·Detector (MODE DET) . 01211
The mode of this circuit is set by a voltage at pin 20 and
is "AUTO" asJhe voltage fa set to approx. 1.4V. The
automatic white balan~e operation is performed at high
speed for 4 seconds i,yhen the power Is first turned on
and after that; the speed is chang9d to low {1/16)
automatically.
2) Subtracter. . COLOR
This subtracts the s~YL signal .from the R-YL signal and
gen.erate~ the color temperature dete.ction (R-8) signal.
. (A-YL) ·~ (B-YL) = R~B .. . . . . . . . Fig. 2-7 Aurtomatic White Balance Control Circuit
~r
::i;:
1£.
,.r~~r:r~;m
3) Adder (ADD). been clipped by a low clipping circuit (01211: LOW
This adds two color difference signals, the R-YL and B- CLIP), compares the level of the luma signal with the R-
YL signals, and generates the Mg-G (A+ B-2YL) signal. YL signal. By this, the level of the luminance Is normal-
(R-YL) + (B-YL) = R+B-2YL = Mg-G ly set to the level of higher than 3rd step. However, if the
This contains an artificial light source component such level of the R-YL signal goes "Hi", the level of the
as fluorescent lamps, etc. luminance is shifted to the level higher than 6th step.
4) Feedback Clamping Circuit FB CLAMP) The AGC voltage of which the higher level has been
This detects the black level of the input signal when the clipped by a high clipping circuit (01246: HIGH CLIP) is
H.BF pulse is supplied, compares Its level with a supplied to the white gate circuit (GATE). Therefor, the
reference voltage, generates an error voltage, feeds it input voltage at pin 31 becomes approx. 2.1 V, and the
back to the input signal and frxed the black level. The white detection area is determined by the output of the
error voltage is held by C1359 connected to pin 28 (or white detection pulse generator. However, the input
C1355 connected to pin 32). voltage at pin 31 becomes approx. 4.0V under low light
Tile output is supplied to the white detection pulse gen- condition, and the white detection area is expanded.
erator and gate (GATE). The white detection pulse is supplied to the gate circuit.
5) White Detection Pulse Generator (WHITE DET 6) Gate Circuit (GATE)
PULSE GEN), Luma Level Setting Circuit (LUMA This passes only the input signal in the white detection
LEVEL) and White Gate (GA TE) area according to the white detection pulse.
This extracts awhite detection area which is aligned with 7) Integration Circuit (INTEGRATION)
the color temperature axis by comparing the level of the This inversely integrates the charged voltage at C1358
R-B and Mg-G signals with reference levels, extracts part connected to pin 26 (at C1357 connected to pin 27) for
of the white detection area, the level of which is higher one field and holds it.
than the rated lum.a signal level, and generates the white R > B (or Mg > G): more than 2.SV,
detection pulse. R = B (or Mg = G): 2.5V,
The luma level setting circuit detects the high luminance R < B (or Mg< G): less than 2.5V
subject as awhite, because the white subject has higher The Integration is performed by the reference voltage
reflection ratio than that of the colored subject normally. (V.REF) in the Mg-G channel and in the R-B channel in-
The rated luma signal level is determined by the luma tegration is performed by a color temperature detection
level setting circuit which inputs the luma signal and low signal supplied from pin 24 to make the integration soft.
level cilpped R-YL signal the lower revels of which have The integrated and held voltage is reset every field by the
01222
csv 3.4V
COMPA.
01225
SW
R
LUMA
I
I R1319
I
I
I
I
B I
I
I
_________________ J I
JO------ - - -
27
LOW CLIP l<;1357
2.3Y
R·Y
csv IHL V.AGC ,
OC1211·21)
/
*
B·Y
1EMP€RA1URE
,WHITE
OF.T AREA '
2-10
hw-smwwtrerm
 RESET pulse. The integrated voltage Is compared with
areference voltage and then the result is supplied to the
8-bit counter.
In the R-B channel, the integrated and held voltage is also
supplied to two comparators (01222/01226, 01245:
COMPA.) and its level is compared with two reference
voltages of appr9x. 3.4V and approx. 1.BV. When its
level is within the range of 3.4V to 1.8V, two outputs go
"Hi", and a switch (01225: SW) keeps off. As a result,
the automatic white balance operation will be performed.
However, when its level becomes higher than 3.4V or
lower than 1.av, the output becomes "Lo". Therefore,
01225 turns on, generates "Hi" and supplies it to the
mode detector. As a result, the mode is changed to
"HOLD" and the previous counter data is held. After that,
the integrated voltage will be within the range of 3.4V to
1.SV by changing the color temperature of the subject,
01225 turns off, and the mode will be changed to the
"AUTO". At this time, the operation Is performed by the
high-speed mode and after that, the operation is shifted
to the low-speed mode in the same way as when the
power is first turned on.
8) 8-Bit Counter (B-BIT COUNTER)
This counts up or down according to the signal input
from the integration circuit ( ± 128 steps). This counter
is controlled by the CLOCK pulse.
R > B (or Mg > G): counts down,
R = B (or Mg = G): counts stop (hold),
R < B (or Mg < G): counts up
9) Digital-to-Analog Converter (DIA CONV.)
This converts the 8-bit digital data (256 steps) to an
analog voltage.
10} Center Shift Circuit (CENTER SHIFT)
This does not work in this model and the signal is simp-
ly passed through this circuit as input pin 18 is opened.
This means the center of the color temperature is set to
approx. 4,500K.
11) Axis Control Circuit (AXIS CONT.)
This converts the analog voltage to two control voltages
that control the gain of the white balance control circuits
1 2 3
FV (pin 22) n.JlJlIL_JlIIJlJlJl..J1JU1JUL.nn ____ fU11l ___ fL
: : ! :
:
I
: !
I
R-8 lnte.
(pin 26)
1 I
1.5V I t
(WHITE BAL). This voltage becomes 3V when the
power on reset is performed. The ratio of the control volt-
age between the R-B and Mg-G channels is set to 5: 1.
12) Color TemperatlJre Detector (COLOR TEMPE. DET)
This compares the.level of the R-8 control voltage with
the reference voltage and detects the color temperature.
This output is supplied to the. integration circuit for the
R-8 signal.
(2) Actual Operation (Example)
When the power is first turned on, the voltage (1.4V)
rises, and the mode is set to the "AUTO". When the volt-
age (1.4V) exceeds 1.0V, the counters are reset and the
data of the counters are set to center (129). As a result,
the control voltages at pins 14 and 15 are setto 3V. The
R-YL and 8-YL signals corresponding to the color
temperature of the subject are supplied to the automatic
white balance control circuit as voltages to control the
gains of the Rand B signals.
Now, if the R-B signal Is R > B and Mg-G signal is Mg =
G (lower color temperature), the following will be per-
formed.
1) The Integrated voltage of the R-B signalbecomes
more than 2.SV as the R signal is more than. the B signal
and the Integrated voltage of the Mg-G signal becomes
2.5V as the Mg signal equals the Gsignal. Therefore, the
8-bit counter. of the R-B channel starts down counting
and the 8-bit counter of the Mg-G channel holds its data.
2) 6-bit counter counts down every field, and the count
data decreases {129-1-128-127-). Therefore, the gain
of the A signal is decreased and the gain of the B signal
is increased as the control voltage is decreased.
3) If the gain of the R signal equals the gain of the B sig-
nal, integrated voltage becomes 2.5V, and the 8-bit
counter stops down counting and holds its data.
These operations are performed for a 256-field period
(approx. 4.27s). After that, the operation mode is shifted
to low-speed to stabilize operation. The Integration and
counting are performed every sixteen fields (approx.
267ms) in the low-speed mode, however, the operation
is the same as in the high-speed mode.
127 128 129 256 272 273
: : :: : : :: ; ! : This always adds the positive BF pulse as the nega-
:
:
!
I !
I !: ! :..
3.SVr.·-~-·-,-,--·--:---·-
:: : : :
I I . !~ 2.5VI I I • I I
I I f ' ' ' '
2·4. Character Mixer (IC1210: CHARA.
MIX, Fig. 2-3)
The luma signal from IC1206 and two color difference
signals, R-YL and B-YL, from IC1211 (2/4) are supplied to
IC1210.
2-4-1. Luma Signal Processing Circuit
(1) Clamping Circuit (CLAMP)
This fixes the DC level of the luma signal.
(2) Negative/Positive Inversion Circuit (SW1)
This switch does not work and the positive luma signal
is always generated as the negative/positive inversion
Input (pin 19) is grounded.
(3) Character Signal Mixer (SW2)
This switch does not work and the signal is simply
passed through this switch. The Iuma signal is supplied
to the gamma correction circuit.
(4) Gamma Correction Circuit (IC1211 (3/4):
GAMMA)
This corrects the gamma characteristics of the luma sig-
nal and supplies it to an encoder (IC1214: ENCODER).
2-4-2. Chroma Signal Processing Circuit
Two color difference signals (R-YL and B-YL) are sup-
plied to the clamping circuits (CLAMP). Before being
supplied to the clamping circuit, a phase compensation
is applied to the 8-YL signal to correct'the phase of the
chroma signal. ·
(1) Phase Compensation Circuit (PHASE COMPE.)
This consists of a high clipping circuit (01203: HIGH
CLIP), adder and amplifier (01202, 01201: AMP).·
The high clipping circuit clips the R-YL signal higher than
a reference voltage of approx. 3.0V. This clipped R-YL
signal is mixed to the s~YL signal and it Is amplified and
supplle<:f to the clamping· circuit. Then two color dif-
ference signals are processed by clamping circuits and
character mixers (SW3 and SW4) which do not work and
simply pass the signal before being supplied to the burst
flag adder. · · ·
(2) Burst Flag Adders (BF ADD)
1) In the R-YL Channel
This does not work and the signal is simply passed
through this circuit and supplied to the encoder.
2) In the B-YL Channel
tive/positive inversion input (pin 1O) is grounded. The
output is supplied to the encoder.
limit the white level within the specified range and linear
clipping during the blanking period In which
synchronous noise remains so that noise is removed and
the black level is limited.
(3) Luma/Chroma Mixer roe MIX)
This mixes the CHARACTER signal generated by a
character signal generator (IC1902: CHARA GEN) with
the luma signal.
(4) Fade Circuit (FADE)
The level of the luma signal output is controlled by three
signals as follows.
1) FADE Signal
The FADE signal is integrated by a time constant circuit
and supplied through a buffer (01233: BUF). When the
voltage increases, the luma signal output decreases and
then stops (FADE OU"T), and when it decreases, the luma
signal increases and outputs via pin 18 (FADE IN).
2) CAMERA ON Signal
This is inverted by an inverter {01236: INV) and supplied
through 01233. This signal goes "Lo" during recording
and it goes "Hi" in modes other than camera recording.
3) BACKGROUND Signal
The BACKGROUND signal generated by IC1902 and
supplied through the OR gate (D1203) sets the level of
the CHARACTER signal and also reduces the luma level
of the background of the CHARACTER signal, because
the pulsewidth of the BACKGROUND signal is wider than
that of the CHARACTER signal to improve the edges of
the CHARACTER signal.
(5) Mixer
This mixes the C.SYNC signal with the luma signal to
generate a composite luma signal which is supplied
through a buffer (Q1230: BUF) to the video circuit.
2-5-2. Chroma Signal Processing Circuit
Two color difference signals (R-YL and 8-YL) are
prncessed by the clamping (CLAMP) and clipping (CLIP)
circuits before being supplied to the balanced
modulators.
(1) Balanced Modulators (BAL MOD) and Mixer
These modulate the R-YL signal with SC2 (90°) and 8-YL
signal with SC1 (0") then mixes them to generate a
3.58MHz chroma signal.
(2) Fade/Gain Control Circuit (FADE/GAIN CONT.)
The operation of this circuit is the same as that in the
luma signal processf ng circuit. The output is supplied to
a base noise clipping circuit.

ov- ,' :: !; :! : : : {3) Blanking Mixer (BLANK MIX)

Mg·Glnte.
: I: :I : : :

(pin 27)
2.SV ; ----: : : ! : ...... -:-:-·---1- · - - - 2·5. Encoder (IC1214: ENCODER, Fig. 2·3} This mixes the C.BLK pulse with the BF pulse to generate
ov-l , : , : : :! ,: ; : l l a control signal which controls subcarrier amplifiers so
2·5-1. Luma Signal Processing Circuit that SC1 and SC2 are not supplied to the balanced
Mode (pin 20)
:
1.~_n::·-·:
: : : :
::
I I 4

: -·--:-,-,-----:-·-·-
I I I :

(1) Clamping Circuit (CLAMP)· modulators (BAL MOD) during the blanking period ex-
~
1

: : I : : : : : l This fixes the DC level of the luma signal when the CP cept forthe burst flag period.
I I : : : I I 4 I

:::;_,./~·-~: pulse is supplied. (4) Base Noise Clipping Circuit (01247 to 01249:
R Gain (pin 14) r-...... •
I 1·1
! (2) Blanking/Clipping Circuit (BLANK/CLIP)
kr:
I : I 'I

3V I I
1
I ! f-!----~ . BASE NOISE CLIP)
I II I' •..__ High level noise originating from the sensor drive pulses, This eliminates base noise contained in the 3.58MHz
I : : : : : :: : : I : : I

::~:~, .. ·: 11
etc. is mixed with the luma signal during the vertical and chroma signal.
S Gain(pin 15)
3V;+t-t···; ··-~---~--- horizontal blanking periods.
On the other hand, If the video si_gnal level exceeds. a
(5) 3.58MHz Bandpass Filter (L1210, C1367:
3.58MHz BPF)
: : : : f-Hold-j :--1sFVs....; ::':,
specified level, the picture might deteriorate due to amal- This extracts the chroma signal components (3.58MHz
function of the VCR. To eliminate such· synchronous ±500kHz). The output is supplied through a buffer
noise, the C.BLK pulse is mixed with the luma signal. (01231: BUF) to the video circuit.
Fig. 2-8 Automatic White Balahce Control Operation
After this, the clipping circuit performs linear clipping to

2-11 2-12
 2..s. Programmed Automatic Exposure value Is determined by RT121 O(AE1) which sets the sen-
Control Circuit (Fig.· 2·9) sitivity of the iris detector.
(3) Amplifier (IC1208(2/2): AMP)
This describes the operation of the. signal input/output
Thisampliflesthe output voltage (F.DET signal) of the iris
circuit which is the interface with ttie system control sub
detector. RT1211 (AE2) which sets the offset voltage of
microprocessor (IC1901: S-µ.P) (Refer to the "CHAPTER
the amplifier, Is connected to the noninverting input (pin
3 SYSTEM CONTROL" for details of the automatic AE 5).
control operation).
(4) F.DET1 Detec1or (IC1:215(2/2): F.DET1 DET)
2-6-1. Operation of the Programmed AE This compares the F.DET signal with the reference volt-
When the power ls turned on, 1he shutter speed is age at pin 5 and generates the F.DET1 signal. The out-
automatically set to the AE: 1/60 second. Then, the shut- put is supplied through a matrix circuit (01905: SW) to
ter speed is automatically selected by the F.DET1 and IC1901.
F.DET2 signals. The reference voltage is selected by the SHUT.1 signal
(1) F.DET1 Signal at pin 43 of IC1901. When it goes "Hi" (at 1/60 second),
This is a result of com parlsons made with the level of the switch (01227, 01229: SW) turns off, and the voltage be-
output from the iris detector (IRIS DET). The shutter comes approx. 1.9V. When it goes "Lo" (at 1/120 and
speed is increased when the F.DET1 signal changes to 1/250 second), switch turns on, and. the voltage be-
"HI" from "Lo". comes approx. 1.SV (F7.2).
(2) F.DET2 Signal (5) F.DET2 Detector (IC1215(1/2): F.DET2 DET)
This is also a result of comparisons made with the level This compares the F.DET signal with the reference volt-
of the output from the iris detector. The shutter speed is age at pin 2 and generates the F.DET2 signal. The out-
decreased when the F.DET2 signal changes to "Hi" from put is also supplied through 01905 to IC1901.
"Lo". The reference voltage is selected by the SHUL4 signal
These two signals, F.DET1 and F.DET2, are supplied to
at pin 40 of IC1901. When it goes "HI" (at 1/60and1/250
IC1901 to determine the shutter speed as follows. second), switch (01228: SW) turns on, and the voltage
becomes approx.1.9V (F3.2). When It goes "Lo" (at 1/120
F.DET1: Hi F.DET1: Hi . second), switch turns off, and the voltage becomes ap-
1/60 Second +--+ 1/120 Second +- -+ 1/250 Second prox. 2.SV (F2).
F.DET2: Hi F.DET2: Hi
2-6-3. Actual Operation
2-6-2. Circuit Operation (1) 1/120 Second to 1/250 Second
(1) Iris Detector (IRIS DET: Hall device)
Since the shutter speed ls 1/120 second, both the
This Iris detector Is mounted near to the iris in the iris SHUT~ 1and SHUT.4 signals are "Lo", the reference volt-
motor and it detects the iris opening and generates a
age at pin 5 is approx 1.5V (F7.2) and the reference volt-
voltage for detecting the F value. The detected voltage age at pin 2 is approic. 2.5V (F2). When the subject
atTP1201-7is3.0Vwhenthe iris is fully opened and 1.0V brightness Increases, the iris. closes and the F.DET sig-
when the iris is closed.
nal decreases. If the F.DET signal goes lower then
(2) Bias Generator (IC1208(1/2): BIAS GEN)
reference voltages, the output at pfn 7 goes "HI" and the
1his generates a bias current for the iris detector; Its
output at pin 1 goes "Lo". When the output goes "Hi",
CSY C5Y
IC1901
r-----,
I
S-µP
I integrated by capacitors connected to the output ac-
I I
-:11>----'"~3 SHlJT.1 I SUBJECT
I I
I -1 I I
01905 turns on, and the F.DET1 signal is supplied to
IC1901. As a result, the shuttr speed is changed to 1/250
second from 1/120 second.
(2) 1/120 Second to 1/60 Second
Since the shutter speed Is 1/120 second, the reference
voltage at pin 5 is approx. 1.5V (F7;2) and the reference
voltage at pin 2 is approx. 2.SV (F2) . When the subject
brightness decreases, the iris opens and the F.DET sig-
nal Increases. If the F.DET signal goes higher then
reference voltages, the output at pin 7 goes "Lo" and the
output at pin 1 goes "Hi". When the output goes "Hi",
01905 turns on, and the F.DET2 signal is supplied to
IC1901. As a result, the shuttr speed Is changed to 1/60
second from 1/120 second.
(3) 1/60 Second to 1/120 Second and 1/250 Second
to 1/120 Second
These operations are similar to those descrivbe above.
3. AUTOMATIC FOCUS CIRCUIT (Figs. 2-10
and 2·11)
3-1. Principle of Automatic Focusing (Fig.
2·10)
The automatic focus control system Is an external focus-
ing system operating on_ the principle of triangulation
using the reflection of infrared rays. Infrared rays emitted
by two infrared LEDs pass through a projection lens and
reach the subject. The infrared rays reflected from the
subject come back to a sensor via the receiving lens.
The sensor is composed of two photodiodes, A and B.
The focusing lens Is moved until two photodiodes
receive an equal amount :if reflected infrared rays (the
receiving lens moves , ..;cording to the movement or the
focusing lens).
The distance "y'' to the subject is given by:
y =I Xf/x
This twin beam system uses one Infrared LED ·with a
prism which· divides the infrared ray Into two. The twin
beam system can bring two subjects into focus at the
same time. In case of the single beam system, the beam
passes through between two subjects. This means that
the probability of achieving focus is improved.
PROJECTION
LENS
the integrated A-B signal to a differential amplifier (DIFF.
3·2. Circuit Operations (Fig. 2-11)
3-2-1. Power Circuit
(1) Automatic Focus Switches .
When the FOCUS switch (SWS 1AF) is set to the "AUTO"
position or when the switch is pressed with SW51AF set
to the "PUSH AUTO" position, the C9V power source is
supplied to an autofocus switch (Q51AF, Q52AF: AF
SW), and the ai.Jtofocus switch turns on and supplies the
A6V power source.
(2) 5V Regulator (IC12AF: 5V REG)
This regulates and supplies the AFSV power source to a
signal processing circuits, and automatic focusing is
started.
3-2-2. Sensor (D01AF) and Preamplifier (IC01AF:
PREAMP)
Infrared rays of 9kHz reflected from the subject are pick-
ed up by D01AF and they are converted to current and
supplied to IC01AF which converts the current to volt-
age. The outputs come from pins 5 (A signal) and 6 (B
signal) and, after passing through C04AF and C03AF and
pins 24 and 23, enters the automatic focus processing
circuit.
IC01AF Includes circuits that remove DC components
arising from external light.
3-2-3. Automatic Focus Processing Circuit (IC11AF:
AUTOFOCUS PROCESS}
(1) 9kHz Bandpass Filter (9kHz BPF)
A highpass filter Is formed by a capacitor (C04AF) and
the Input impedance of the IC. The highpass filter forms
a 9kHz bandpass filter with the characteristics of an
amplifier. It picks up infrared signals resulting from
reflections, etc., removing infrared noise components.
The output Is supplied to an adder and a subtracter.
(2) Adder {ADD) and Subtracter (SUBTRACT)
These generate the sum signal A+ B and the difference
signal A-B from the A and B signals. The output is sup-
plied to a pulse detection/integration circuit (PULSE
DET).
(3} Pulse Detection/Integration Circuit (PULSE DET)
The Input signals are detected synchronously with a
9kHz SYNC signal from a logic circuit (LOGIC) to remove
external Infrared components. The detected signals are
cording to the amount of Incident light. The integrated
A+B signal is supplied to a comparator (COMPA.) and

l ':"" . !
1 1
IRIS o-- - + - - - - . - - - - - - - ' AMP).
DET. I
I I The integration time of the A + B signal is inversely

·;--0 i
L..- -.J
proportional to the amount of light striking DO 1AF. That
is, the more (less) light, the shorter (longer) the integra-
tion time.
J I I The Integration time of the A-B signal is also proportion-

01905
51
I
KEV2 :
I
I
RECEIVING
al to the difference of A and B but the output is as shown
SW I I LENS in Table 2-1, depending on the relation between them.
R1360 I I Table 2-1 Integrated Signal of A-B
(5.Gk) ~11---"'------'4~0 SHUH. I Fig. 2-10 Priciple of Automatic Focusing
I._ _____ JI f QQ_ut Relation Out_Q_ut Volt~e Focusi1!9_
A>B Lower than 2. -rv Focused nearer
A=B 2.7V In focus
Fig. 2-9 Programrried Automatic Exposure Control A<B Higherthan 2.7V Focused farther
Circuit
2-13 2-14
llo"""'mWf ?
1
·r•TF?~?"'F"ZE:-·· . ···. · ·. ··w·-~-·-·-·o-···- ... ...
~ ~-"·-·"·-~-,.r·•·"'·· .
~·~w-·n->-·--~··-~· ·····-··--:z··-7-gz:-~-- ..,,.. . ..,,..,____ ·cy -·---·- . --·iiff··· ···-· · . hzavrst:r:d
 VR12AF (A+ B OFFSET) connected across pins 4 and 5,
and VR11 AF (A-B OFFSET) connected across pins 2 and
3, adjust the offset voltages of the pulse detectors so that
there are no output if no signals are Input.
(4) Comparator (COMPA.) and Differential Amplifier
(DIFF. AMP) . the integration,. holding the integrated voltage. Also, it
These compares the integrated A+ B and A~B signals
with a reference voltages (2.2V and 2. 7V) produced by a
reference voltage generator ('I.REF. GEN).
1) Comparator (COMPA.) .
This compares the Integrated A+ B signal (serving to
make A-B which represents how much the camera Is out
of focus Independent of the distance and refl ectlvity) with
a divided reference voltage (2.2V). The output Is "Hi"
when the Integrated A+ B signal Is as 2.2V.
2) Differential Amplifier (DIFF. AMP). . If the camera is judged to be in focus, autofocus opera·
This compares the integrated A-B signal (representing
how much and In which way, farther or nearer, the
C'.amera is out of focus) with 2. "N. The output is as shown
in Table 2-2.
Table 2-2 Outpl.Jt of the Differential Amplifier
ln_Qut Relation Out_Qut
A>B "Lo"
A-B Offset volt~e
A<B "HI"
SYNC, MODE, infrared LED drive and motor drive sig-
nals.
1) Judging Focus · . · (6) Reference Voltage Generator (V.REF GEN)
If the A+ Bsignal becomes "Hi" within 28ms after the start
of measurement, it inverts the MODE signal and stops
judges whether or not the camera is in focus. Judgment
is done by comparing A-8 and a reference voltage (K)
supplied to pin 9 as shown in Tab~e 2-3.
Table 2-3 Judgment of Focusing Condition
Jud ment
In focus
Out of focus
· (021AF,Q22AF: LED DRIVER)tomakethe LED emit in-
tion Is reset for about 350ms then starts again. If the
camera is judged to be out of focus, the direction in
which the motor should be driven and the duty ratio of
the motor drive signal are determined from the A-B sig·
nal. The duty ratio of the motor drive signal will be set at
100% ("Hi") or 62.5%, depending on the A-8 signal and
the Input supplied to pin 10. The duty ratio Is 0% ("Lo")
when the camera is ln focus.
If the A+ B·signal does not rise to "Hi" within 28ms, the
current. The constant drive current is 100rnA with "Hi"
logic circuit determines that no light Is coming in and
Is mechanically pressed by the lens. Pin 20 falls to "Lo" The autofocus motor is driven by IC31AF according to
and autofocus operation stops for 350ms. the FAA ON signal (output at pin 13) and the NEAR ON
signal (output at pin 12) of IC11AF. The duty of the motor
Receiving the AF5V1 power source through pin 14, this drive signals are changed 'from 62.5% to 0% from 100%
generates V.REF(2.7V), 2.71/ and 2.2V;
depending on the distance to the subject (near end or
(7) Oscillator (OSC) far end to bring into focus). Table 2-4 shows the states
This generates a clock signal of approximately 35kHz, of IC21AF.
determined by C14AF and R14A.c: connected to pin 11.
The SYNC signal of 9kHz, the infrared LED drive signal Table 2-4. States of IC21AF (MOTOR ORNER)
and the motor drive signal are generated from the clock Input (Pin) Output (Pin) States of the Motor
signal. 8 7 3 2
3-2-4. Infrared LEO Drive Circuit 0 0 OPEN OPEN Stop
This drives the infrared LED (D21AF). 1 0 Hi GND Far:ILoadfiJgl
The signal output from pin 15 drives two LED drivers 0 1 GND Hi Near]UnloadilJ.91
1 1 GND GND Stop(Brakij_
frared rays of about 9kHz. The infrared LED drive cur-
rent Is varied In two steps according to the LED drive
signal (pin 15) and feedback ·signal (pin 16). 4. ELECTRONIC VIEWFINDER (EVF) (Fig.
When the lens should move to bring a close subject into 2·12)
focus, the drive current is "Lo" in order to prevent satura-
tion of the preamplifier which strong infrared rays would The video signal from the luma signal processing circuit
cause. The drive current is "Hi" when the lens moves to (IC201: LUMA PROCESS) is supplied to the EVF
bring a rnore·distance subject into focus. Pin 17 is the processing circuit (IC801: EVF PROCESS).
negative feedback input to drive 021 AF with a constant
4-1. Video Circuit

I
generates a motor drive signal (100%: "Hi") which drives and 60mA with "Lo". The fuma signal is first clamped to fix the DC level and is
The output is supplied to the logic circuit where it is the motor to move the lens until the far end is reached. then supplied to an amplifier (6dB). The amplifier
3-2-5. Motor Driver (IC31AF: MOTOR DRIVER)
judged.· . 2) When it is detected that the Far End has been
(5) Logic Circuit (LOGIC) . . ~ IC201
reached. . !~ ~~_P3~CESS
On receiving the comparator's .output, this judges It is detected that the far end of the lens movement has :~; I I

,
'~
whether or not the camera is in focus and generates the been reached when the far end switch (S1 AF: FAR END) ~; : ~'3=-8---~-+I
I I
I
L----..J
I l
I
VR12AF
IC11AF U A•B A6V I
ArU.!.O!~~S_P~~fS,? _ - 4 - 5- ~~:_r__ - - -- - - - .., I

I
.1
I
' IC1902
CHARA.GEN
LIU lI l--ilf+.....,_~------vERT.

1---:z.l~l-tot MB : r---l I r->1-:..~)".--AJl,...-~~5~

15
l
I
~'19=-----~9'----1--~
I
SVNC 1
16 I I
MOOE I l.----.J

A•B
•,,
I
I
I
20
FAR ENO
SlAF
~FAREND
LOGIC csv csv

FAR ON

NEAR ON

I
I
I RT805
·1 lC1901 BRIGHT
I S·uP
I ..-----., 0803
I
L-----------.l
I l :
DRIVER
I REC LEO~o-----~®it-'---,
Fig. 2-11 ·AUtomatlc Focus Processing Circuit I
I
1
I
~m ~
L..----.J.

Fig. 2· 12 Electronic FViewfinder

2-16
II
 CHAPTER 3 SYSTEM CONT.ROL
amplifies the luma ·signal. and supplies it to a driver (4) Switches the shutter speed. character generator (IC1902).
(0802: DRIVER) through pin 16. The luma signal is then 1. GENERAL DESCRIPTION (Fig. S-.1) (5) Transfers character and display position data to the
supplied to grid 1 of the EVF CRT.
Two microprocessors (IC901: M-µ.P and IC1901: S-µ.P) IC1901
I
4-2. Vertical· Deflection Circuit control the circuits and mechanism as follows. MECHA STATE I COMMUNICATION
.C9.~.~0L : COllTROL l+---------.i~g~~ICAT!ON
The clamped luma signai Is supplied to the sync 1-1. Roles of M·µ.P --------.£.--------
CASSETTE, TAPE, I SW30HzlSWl5Hz FUNCTION KEY
separator (SYNC SEPA.) through a lowpass filter (LPF) !ROUBLE I GEN
PG SENSOll
(OISP!.AV, RESET.
MATRIX KEY

which removes high frequency components. The sync (1) Receives operation key data detected by S-µ.P and DETECTION r-------- a_!c;)~,! ___ _
- - - - - - - -1 ARTIFICIAL
separator separates the composite sync signal from the transmits operation and backup data to S-µ.P I V.SYNC GEN
LUMA/CHROMA
CIRCUIT SHUTTER SPEED IMAGE SENSOR
DRIVER
POWER ON/OFF. r-:...- 7-.- - - - CONmOL
luma signal and supplies It to a vertical sync signal through the communication lines. WAKEUP/BACKUP I
(2) Controls the loading motor to switch the operation CONTROL I CYL-FG SENSOR
separator (VERT. SYNC SEPA.) and a phase detector I INDICATOR POWER. TALLY
(PHASE DET) in the horizontal deflection circuit. mode of the mechanism. --- -----i CYLJHOER CONTRO.L INDICATOR
REGULATOR
The vertical sync signal separator separates the vertical (3) Monitors the outputs of the sensors in the I SPEED/PHASE
EDIT( REC PAUSE) I CONTROL
sync (V.SYNC) signal from the composite sync signal. mechanism to detect the type of cassette, opening ·BACKUP OET. &
RESET CONTROL BACKUP DETECTOR
CONTROL :
Triggered by· the V.SYNC signal, a vertical oscillator or closing of the cassette holder, tape transport and I
CYLJNOER
DRIVER
(VERT. OSC) generates a vertical sawtooth signal with the operation states of motors. - - ______ J ___ - - - -- -
OISPLA Y OATA
MUTE /SOUELCH : TRANSFER
the aid of C815 connected to pin 4 and R815 connected (4) Transfers commands and function data to the video CONTROL I CFG SENSOR CONTROL
to pin 3. signal processing IC (IC201 ). --------1
BACKUP DATA :
The vertical driver (VERT. DRIVER) amplifies the saw- (5) Receives data according to the EJECT and CONTROL I CAPSTAN REGULATOR

tooth signal and the output is supplied to pins 8 and 6. VTR/CAMERA switch inputs, short-circuit detection - - - - - - - _, SPEED/PHASE
CPERAT JON DATA : CONTROL
The deflection current comes from a vertical deflection input and presence/absence of battery connection TRANSFER I

yoke (VERT. DEF. YOKE) back to the vertical driver via to control power on/off. --------: CAPSTAN OR I VER

RT802 (VERT. SIZE) which varies the amount of feed-
back or the gain of the vertical driver to adjust the verti-
cal size.
4·3. Horizontal Deflection Circuit
The phase detector compares the phases of the
separated H.SYNC signal and the horizontal drive pulse
generated by a horizontal oscillatqr (HORIZ. OSC) and
feeds the error voltage back to the horizontal oscillator
via pin 13, lowpass filter composed of C818 and R819,
and pin 12 so that the horizontal drive pulse is syn-
chronized with the H.SYNC signal.
The horizontal drive pulse output from pin 1ois supplied
to a driver (0801: DRIVER), and drives a horizontal
deflection yoke (HORIZ. DEF. YOKE).
Ahorizontal linearity circuit consisting of L802, R801 and
C805 improves the linearity of current flowing through
the horizontal deflection yoke .. The horizontal drive
(H.SYNC) pulse at pin 9 is also supplied to a character
generator (IC1902: CHARA GEN) to generate a charac-
ter signal.
4-4. High Voltage Circuit
After receiving the horizontal drive pulse produced by
0801, the high voltage circuit generates high voltages
required by the CRT.
Pin 9: supplies approx. 2.3kV to the anode.
Pin 5: supplies approx. 1kV to AT803 and the resistor
divider.
(1) AT803 (FOCUS): adjusts the focusing volt-
age supplied to grid 3.
(2) Resistor Divider (R803 to R805): generates
approx. 333V supplied to grid 2.
Pin 1: supplies approx. 49.SVto RT805 (BRIGHT) and
the video driver (0802).
RT805 (BRIGHT): adjusts brightness by varying
the cathode voltage.
Pins 7 and 8: supply the flyback pulse to the filament.
(6). Switches the operation mode (recording or play) of
.the preamplifier circuit of the video heads.
(7) Generates a SW30 Hz signal from the TACH(PG)
signal and uses this to time the start of recording
and erasing and to select pilot signals for ATF
during recording and play. . OPERATION MOOE, I PERIOD CONTROL ·
(8) Starts the cylinder and capstan motors.
{9) Controls the video and audio outputs.
(10) When pause Is instructed during recording, M-µ.P
detects the amount of tape transported so the
amount of overlapping is minimum.
(11) Controls the bias oscillation (on/off) of the flying
erase head.
(12) Receives cylinde.r FG, TACH(PG) and vertical sync
signals to control cylinder servo.
(13) Receives capstan FG signal and ATF error voltage
to control capstan servo.
(14) Receives the battery terminal voltage, measures it
· and converts it to display data.
(15) Detects the inputs of operation switches (PAUSE,
EJECT etc.) on the top panel.
(16) Generates an artificial V sync signal during search
or pause mode and applies it to the video output.
(17) Controls the turning-on time of the recording cur-
rent.
(18) Transfers the overdischarge detection reference
voltage and switching point to the EAROM (IC905)
in the test mode. M-µ.P reads the data when the
power is turned on.
-1·2. Roles of S·µ.P
(1) Transfers data on the positions and functions of the
operation switches to M-µ.P through communication
lines with M-µ.P, and receives data on the operation
from M-µ.P.
(2) Detects the Inputs of switches on the side panel via
a niatrix switch.
(3) Driv~s the power and tally indicators.
________,
iO~N~~CJl~~ CIET 1
OPERATION ,_ _______ _
KEY OET (AIOJ : PILOT SELECTION
_--------1 CONTROL
SHORT & OJ~ r,- - -- -
BATTERY
LEVEL DET. I
CH1 /CH2
___ .;..., ____ ;RECODING
HCAO PREAMP
HOO SW CONTRCX. I
(M-,uP)
Fig. 3-1 System Control
2. POWER SUPPLY CIRCUIT (Fig. 3·2)
2-1. Features
(1) Relay-less power switch circuit. The state of power
(on/off) is maintained by M-µ.P.
(2) Data of date, time and counter is held by S-µP and
adjustment data of switching point (PG shifter) and
overdischarge reference data are held by EA ROM
(IC905). Power (5 V or 3 V) is always supplied to
S-µ.P regardless of the power switch setting to hold
the data. When the 6 V battery or AC adapter is
removed from the camcorder, a 3V lithium battery
supplies power to S-µ.P. The EAROM (IC905) can
hold the data when the power supply is removed.
(3) M-µ.P monitors the output voltage of the 6 V battery
when the power is turned on. The output voltage is
displayed in the EVF as a bar graph (E--F). When
the voltage drops below 5.6 V, M-µP switches off.
(4) Three power supplies (C16V, C9Vand C-8V) for
image sensor driver are supplied from DC-DC
cmwertei.
2·2. Power Supply Operations
2-2-1. When only a 3V Lithium Battery is con-
nected.
Only S-µ.P Is initialized and enters backed up state, and
M-µP does not operate.
ATF ERROR O€T
RECi°RE"F"Pilor-
GEN
---
HEAO REC AMP
(5-µP)
The power from the 3 V lithium battery is supplied to the
reset signal generator (IC910) and power input (pin 39)
of S-µP through a battery switch/backup detector circuit
(IC904).
When the power voltage reaches approx. 2.SV, IC91 o
generates a reset pulse (Lo) and supplies it to the reset
input (pin 20) of S·µ.P through an amplifier (0903, 918)
to initialize S-µ.P.
IC904 monitors the voltage at the power input (pin 8) to
switch the power (3V/5V) to be supplied to S-µ.P and dis-
crimiate between different batteries (3V or 6V battery).
When only a 3V lithium battery is connected, IC904 pin
a is OV, therefore the switch (S1) in IC904 selects 1he
power of the 3V ltthium battery connected to pin 4. To
reduce the power consumption of IC904 in the backup
mode, the discrimination of the battery is synchronized
with the Input to S·µ.P. S-µ.P outputs "Hi" to pin 28 ap-
prox. every 500 ms and supplies It to the backup detec-
tor (BACKUP DET) in IC904 via pin 7. The backup
detector is activated when pin 7 ls "Hi". When only a 3V
battery is connected, IC904 pin 8 goes oV, therefore the
backup detector outputs "Lo" at pin 3 and supplies it to
the backup mode input (pin 32) of S-µP. While pin 32 is
"Lo", S-11P is set to the backup mode. In the backup
mode, the frequency of the S-µP's clock pulse becomes
32 kHz (generated by a crystal oscillator (X1901) be-
tween pins 18 and 19) to reduce power consumption of
the 3V llthium battery.

2;_17/ 3-1
3-2
 2-2-2. When a 6V Battery or AC Adapter is con- VfR, VTR power control output (VCR ON: pin 17) goes value. TheA/D converted voltage data is compared with M) line goes "lo" when data is communicated between
nected. "Hi". When the VTR/CAMERA switch is set to CAMERA the data corresponding to the bar graph display (E-F, S-µP and M-µ.P. M-µ.P requests S-µ.P to transmit data
M-µ.P is initialized and then enters the backup state. and POWEASAVE/ON switch is set to on, VTR, camera E-, E-) and the data corresponding to the over-dis- (Lo to Hi) and informs that the data has been received
The power supply (6V) from the 6V battery or AC adapt- and Image sensor driver power control outputs (VCR charge level (approx. 5.6V); and the data to be displayed (Hi to Lo) through the REQUEST(M-S) line.
er is supplied to a SV regulator (IC907). through a fuse ON, CSV SW and CMR ON at pins 17; 16 and 11) are set . is selected and over-discharge is detected.
(F052) and ls converted to SV (this output Is called the to Hi. The VCR ON signal at pin 17 turns an the switch M-µP also detects shortcircutts in the cylJnder and 3·2. Communications between S·µP and
AfJ V). A5 V is supplied to the power Input (pin 72) of M- (S 1) in the regulator circutt and the power switches capstan motors from this Input to pin 45. Since the out- Character Generator (IC1902)
µ.P and power input (pin 8) of the battery switch/backup put of the switches (0901, 0002) is supplied as the
(0901, 0902) of the cylinder/capstan motors and S-p.P transmits the data of characters to be displayed in
detector (IC904). Receiving AfSVat pin 8, IC904 performs power supply to the motors, M·µ.P measures this volt-
generates the power supplies (SV-1, SV-2, 5V-3, the EVF or on the monitor screen and the data instruct-
the two operations. First, it selects 5V at pin 8as a power age, and when a shortcircuit (OV) continues for more
B+ (CYL) and B+(CAPST)) required by the VfR signal ing their position, to the character generator (IC1902).
supply to S-µ.P. Secondly, it Inverts the output of the than so ms, M-µ.P judges that a shortcircuit ·has oc-
processing circuit. IC1902 calculates the coordinates of the picture to be
backup detector from "Lo" to "Hi" to activate S-µ.P. curred.
The CSV SW signal at pin 16 turns on the switch (S2) in displayed using the horizontal and vertical sync signals
When S-µ.P is activated, the frequency of S-µ.P's clock · The division errors of the divider (R919, R920) are dif-
the regulator circuit and generates the CS V power supp- and converts the character codes corresponding to the
pulse is switched from 32kHz to 4MHz (determined by ly required by the camera signal processing circuit. ferent depending on the units. When the test mode is
the crystal oscillator (X1902) between pins 21 and 22). performed, the over-discharge detection level can be coordinates to a TV signal. S-µ.P and IC1902 are con-
The CMR ON signal at pin 11 turns switch (S3) in the nected via four communication lines, CLOCK(S-CG),
S-µ.P then generates a reset pulse (Lo) via pin 27 regulator circuit when external equipment Is not con- corrected automatically according to the division error.
(RESET(M)) and supplies it to the reset input (pin 32) The over-discharge detection level is written to the DATA(S-CG), STROBE(CG} and CS(CG). DATA(S-CG)
nected to the !W input/output jacks (de~ectecl by pin 24 is a data line. The serial data is transferred,
of M-µ.P through an inverter (0915) to initialize M-µ.P. EAAOM (IC905).
which goes "Hi" on when nothing is connected) in the synchronized wtth the clock pulse on the CLOCK{S-CG)
2-2-3. When the EJECT, VTR or CAMERA Switch is camera mode (pin 19 is "Lo"). Switch (S3) supplies 6V line. STROBE(CG) goes "Hi" immediately after S-µP
1urned on. to the camera power supply generator (C9V, C15V, C.. 3. DATA COMMUNICATIONS (Fig. 3-3)
completes data transfer to IC1902 and latches the data
M-µ.P becomes active and instructs that power.should 9V GEN) to activate the Image sensor.. S-µ.P transmits data (commands, function and charac- in IC1902. CS(CG) Is "Hi" while S-µP is transferring data
be supplied to each circuit. 2-2-4. Battery Terminal Voltage Detector (Fig. 3-2) ter data, etc.) to M-µP and the character generator to IC1902.
When the EJECT button is pressed or the VTR/CAMERA M·JJ.P detects the voltage at the battery terminal and dis- (IC1902) and M~µ.P transmits data to S-µ.P, and EAROM
switch is set to VTR or CAMERA, the start input (pin 40: plays it in the EVF using a bar graph (E.;..F). When the · (IC905). 3-3. Communications between M·µP and
WAKEUP (Lo)) of M-µP goes "Lo" which operates the voltage reaches an over-discharge level Oessthan5.6V), Video Signal Processor (IC201)
internal clock oscillator (the oscillation frequency of M-µP stops operation, sets th.e. mechanism to the· stop 3·1. Communication Lines between M-µP
which is set to 16MHz by a crystal oscillator (X901) be- mode and then turns the power off. and s. µ.p M-µ.P transfers the commands (play, Input selection,
tween pins 34 and 35). M-µ.P then checks the inputs etc.) and functions (PALJNTSC, etc.) to the video signal
M-µP receives the battery.voltage at the A/Dlnput (pin S-µ.P and M-µP communicate data with each other.
(pins 19 to 21) of the above switches. When the EJECT processor (IC201) through data lines. M-µP and IC201
45 via a divider (A919, R920) and converts it to a digital They are connected via 5 communication lines, DATA(S-
button is pressed or the VTR/CAMERA switch is set to are connected via three communication lines,
M), DATA(M-S), CLOCK(S-M), CS(S-M) and RE- CLOCK(M-YC), DATA{M-YC) and CS(YC). DATA(M-YC)
QUEST(M-S). DATA(S-M) is a data line from S-µ.P to is a data line. The serial data Is transferred,
M-µP and DATA(M-S) Is a data line from M-µP to S-µP. synchronized with the clock pulse on the CLOCK(M-YC)
The serial data is transmitted/received, synchronized line. CS(YC) is "Hi" while M-µP is transferring data to
wlththe clockpulseontheCLOCK(S-M) line. TheCS(S- IC201.

~~~"----·· ~c~~----, µ:~~----,

I I I I I I
IC909 II I - . . ,39
CLOCK(S-M)~3!..1 I - - - _ _ : . - - - - - - - - - - - - - - + - - - 12'1 CLOCK(5-ro) I
..:!.:!..l
2
r- -, 1 1
: ~~I OATA(S-M) l30 37 4 DATA(S-CG) :
L. 3_J
5V-1-5V-3
TO SYSlEM COtolT. ~
OATA(M-S) 1
20
f
38
I :I
A5V (~ff"MAIC!roolAJ
CS(S-M)l
26
1
36
! :
.- I
.
CYL SERVO
(IC901·68)
B•(C'll.)
REQUEST("4-SJ /
I
35
f
15
I
I I
I

1 I I I
I
I iI I
I
IC905
r-------.
I
I
I
I
I :
I CS(ROMi
!13
I 0900
31. I :I IC201
:
I
I
CAPSt SERVO I OATA(ROM·M)~ I r-----; I
1 I I I l I
OATACM-ROM)~ 42
(IC90H7) 24
I 51 I 1DATA(M·V/C) I I
I I I
I ClOCK(M-ROM) j43 ) •
23
kLOCK(M·Y/CJ I I

BATT.vot.TAGE INOICATION
: I : L_____ J : I :
I I I EAROM I I I
U· E··-F I I CS('f/C)~11~.:........,1-..-------22---o;~CS('f/C) I I
I I 1 1 I I
e.H5.g E-· I L------...1 L ______ .J I 1,
I M·µP LUMA PROCESS
M·5.7 "E':. 25
S7AOBE(CG) 3 STROBE(CG) I
5.6 POWEil OFF
CS(CG)
133
I
·
11
I
CS(CG) lI
I I I J
L----..;....;..J L-----...l
1
S- JJ p CHARACTER GEN
i._
Fig. 3-2 Power Supply Fig. 3-3 Data Transfer

a.
I~·. I • • • ' • • 1, I. I.
r
• : • ' ~ I I •• .,, \ , •' 1, • ' "· r ·, • I 1 • • • I • : ( ·,' ~ "' • • ' r ~ • 11 • ' • / • • • '', '
 3-4. Communications between M·µ.P and M-µP detects operations of the keys on the top panel
abnormalities in the tape transport system. The dew
(EJECT, VTR/CAMERA, etc.). M-µ.Pdetectstheseopera- frequency of the pulse to detect any abnormal reel disk
EAROM(IC905) sensor and .cassette holder sensor (S093) detect the speed (reel lock). IC901 uses the Inputs from both the
tions from three direct inputs (pins 19 to 21) and one AID
The EAROM(IC905) holds four types of adjustment data mechanism state. The tape thickness sensor (5092), reel sensors and the information on tape thickness input
convertion Input (pin 47). Pin 19 is a camera power input safety tab sensor (5091-1), MP/ME cassette sensor
(switching point data, reference voltage data for over- which goes "Lo" (OV) when trie VTR/CAMERA switch Is to pin 44 to calculate the remaining tape time.
discharge detection, slow tracking data· and artificial (5091-3) and HMP cassette sensor (S091 ~2) detect the
set to CAMERA and the POWERSAVE/ON switch Is set
V.SYNC phase data). The switching point data and to ON. Pin 20 detects the VTR position of the
type of cassette and the recorded condition. The tape 5-3 Dew Sensor
reference voltage data for over-discharge detection are thikness, safety tab and HMP cassette sensor outputs
VfR/CAMERA switch. Pin 21 Is an EJECT switch input. are applied via ND converter to M-µ.P. The dew sensor characteristics are· such that its Im-
written when shipped from the factory. To change the This camcorder Is provided with an input (pin 40: WAKE pedance is several kiloohms when the relative humidity
data after parts are replaced, etc., the camcorder must UP) which starts M-µ.P when these keys are oper:ated is 60% and several hundred kiloohms when it Is 80%.
be set to the test mode; the data is automatically cor- 5-1. Tape End Sensors (0091, Q094)
during power off.. When these keys are pressed, pm 40 The voltage drop thus produced is applied to pin 46 of
rected. goes "Lo" and a 16MHz clock pulse starts to be The take-up (suppiy) ·tape end. is detected when IC901. When the input voltage at pin 46 reaches 0.45V
M-µP and IC905 are connected via four communication generated and then the inputs at pins 19 to ~i are photot;ansistor 0091 (0094) receives light emitted by or higher, IC901 sets the camcorder to the stop mode,
lines DATA(M-ROM), DATA(ROM-M), CLOCK(M-ROM) detected. Pin 47 receives a voltage corresponding to the LEO (0091) through the leader at the end of tape. causes the power indicator to flash and inhibits any
and 'cs(ROM). DATA(M-ROM) Is a data line through seven operation keys (PAUSE, STOP, REW, F.FWD, 0091 is driven by the pulse output at pin 18 of IC901 at operation key input.
which M-µ.P transfers command and address codes to REC, AV DUB, PLAY). This voltage is ND converted and 60Hz to prevent erroneous detection due to external
IC905 and DATA(ROM-M) is a data line through which compared with the data corresponding to each key, thus light. The output of 0091 (0094) is applied to pin 49 (50) 5·4. Cylinder Lock
IC905 transfers data to M-µ.P. Data is transferred, the key which has been operated is detected. of IC90t IC901 monitors the inputs at pins 49 and 50,
synchronized with the clock pulse on the CLOCK(~­ synchronized with the light emission of 0091. IC901 receives the cylinder FG signal {CYL.FG) via pin
S-µ.P detects the operation keys (RESET, DISPLAY, 61 from pins 12and13 of the cylinder driver (IC603) and
ROM) line. CS(ROM) Is "Hi" while data is being commum~ TITLE, TIME LAPSE, AV DUB, ADV, SEL, SHUTIER,
cated between M-µ.P and IC905. REVIEW FADE DATE/TIME, etc.) on the side panels 5-2. Reel Sensors (Q092, Q093) monitors any change in frequency. When there is no

4. KEY INPUT (Fig. 3-4)

through~ matr~ circuit. S-µ.P has 4-phase outputs (pins The take·up (supply) phototranslstor 0092 (0093)
change In frequency, IC9o1 judges that cylinder lock has
occurred and sets the camcorder to the stop mode.
8 to 11 :· PHASEO to PHASE3) and 5-phase Inputs (pins receives the light reflected by the eight reflective plates,
The operation keys on the panels are detected by M-µ.P 3 to 7: KEYO to KEY4) to form a matrix circuit. attached to the back of the reel disk at equal intervals, 5·5. Cassette Holder Sensor (S093)
and S-µ.P. and detects the reflection frequency tojudge the speed
of rotation of the reel disk. The light source is an LED in Switch S093 detects whether the cassette holder Is up
r--------,
JC901 (M-tJP)
the same chip as the reel sensor. The output of the reel or down and applies the result of this detection to pin 22
: CST ~'22=----------0 ~ CAssmE S!J sensor is shaped by comparator IC907 and then the out- oflC901. When the cassette holder is closed, pin 22 goes
I I
I I put of 0093 (0092} is applied to pin 56 (55) of IC901. •to" from "Hi"; fC901 drives the loading motor and
I REC START ~=--"'."""""r-t-----o
25
REC START /STOP SN
IC901 counts the pulses generated by the take-up reel switches the mechanism from the unloading stop mode
I I Gr to the loading stop mode. The output of 5093 is also ap-
: CMR~l'IER~~-_,_H----1 ~-----,o
119 sensor to detect the amount of tape transported and the

lI EJECT
=:'--.
.}J
--t-H-1--<E~rlr ON-~SAVE CMR-o=F-VTR
PCJNER
lC901 (M-uP)
,-------;
JC603
r----;
I
I
1
20
v~~~R~-.-1-~+-----------:-~ II ""L·FG !61
'-'
!
-----------.;cvLD:l!VEl
o.o..,
I 12 FG N'.Pl
I I 5093 I I L. ____ ..J
i 1

:
I
WAKEUP 'D
i 0909, 0916
I )£~qi ____ .,
m
~o-o---71.,~CST.SW

23 I
II
: .

I
CEW(A/0)~45 '//,
t
SV .

DEW SENSOR
®. I
I
I I
I
I
1
f 1
3~---------,
8
. - - - - - - --vME/MP
~I TAPE OET
I
J;.
rtr

l
: 0091
J I I I
SV ---INr--t-__,-_,....--,--"91 {A/OJ I 2·3Y . ~TAKEUP END SENSOR
I ~ 2~9 ------, I 9 _ _ _ _ _ _.._I-JI
REW.·EN01~64:::.
I I I PHASE 110
I I I 1~----- 5092 I I SY
I
I
I
~I 11
I
I
I a~--~
I I
5091 l.ti~- li~_Jl)_j
;).;' t t .
1 1,l FWO El'IOt,50 I I j

~·· :1 1~::
2.3V 0094 SUPPLV END SENSOR
I I
LOW
LIGHT ~~RESET MP:ON TAB:ON THICKNESS I I 0910 0091 ••
HMP: ON
~~VCR
"I j FADE ~uroeR AV DUS DISPLAY
13pm : ON I
I
11.L_ "
ENO LA.MP ~·-----er--
""-- - .qL:___ SY

~
KEV I I IS HMP SW TASSW THICK SW VOl.1AG£(V) I I 60Hz PULSE ENO LAMP 0092
471 1 1 r-·--:
1 t t 11 i i
J, l,
_Ji
!, 15 35 KEY 2 F. DET 1 REVIEW ADV. 5091-(2) 5091-(1) 5092 (PIN40 I I ·

PLAY AV DUB REC FF REW STOP PAUSE

L_____
J
<:
4
F.OET2

-
SEL

DO.'IEITJME TITLE
OFF

ON
OFF

OFF
OFF'

OFF
4.2-5.0

3.17-4.2 I
I
I
I
I
I
T.REEL \>""SS..__ _-c;,_ SY

(3.9V) (3.GV) (3.3V) (2V) (1.7¥) (U.V) (1.1V) I I OFF I

ON OFF t9 -2.15
I I SY TAK'i::UP REEL SENSOR
l
I
'ON ON OFF t64-t9
I
I
I I I
L.------J
(S-uP)
OFF OFF ON 2.49·3.17 I CASSETTE TAPE(EIOTTOM)
ON OFF SUPPLY REEL SENSOR
Fig. 3-4 Key Input ON 2.16-2.49

5. TAPE/TROUBLE DETECTION (Fig. 3-5)

This circuit detects abnormalities In the tape transport
system, the mechanism state, type of cassette and the
and recorded contents from abnormal operations and
malfunctions.
The supply and take-up end sensors (0091, 0094), reel
sensors.(0092, 0093) and cylinder lock sensor detect
OFF

ON
ON:HMP
OFF: HMP
()<l

....ON

~~ OFF:10um
ON:CLOSE
ON
ON

ON:13um

CFF:Ol'EN
1'5-164

0 -i.45

- '"'" '" :"~

rRl " ""
TAB ME/MP THICKNESS

recorded condition, and protects the tape, mechanism.

Fig~ 3~5 Trouble Sensor - ·• ·

,
.. • • I
0 ;t
_, '
•
I

' - •' ' •

1
\ : • ._ < ; <," • \I , • I I -.1 ~I 'j ', I' I ' ' I ' , , ' I
 plied to pin 40 (WAKEUP) of IC901. When the cassette age table In the diagram} 7. ASSEMBLE RECORDING CONTROL of the SW30Hz signal. When the rise.of the SW30Hz
holder Is closed during power off, IC901 turns the power signal is detected, M-µP sets the "FE ON" signal out-
on and starts the loading motor; 5-9. ME/MP Cassette Sensor (5091 ·3) CIRCUIT
put via pin 7 to "Hi" and the "PRECONT" signal out-
Switch S091-3 detects the opened/closed state of the This camcorder uses a flying erase head and controls put via pin 8 to "Lo". The "FE ON" signal causes the
5-6. Tape Tthickness Sensor (S092) tape type (metal or evaporated) detection hole and ap- the section overlap-recorded over the previously erase current to ilow to the flying erase head to start
Switch S092 detects the opened/closed state of the tape plies the result to pin 23 of IC901 .. When pin 23 ls "Hi", recorded video track so that it is minimum (within about erasing. The PRECONT" signal causes the opera-
thickness detection hole and applies the result to pin 44 IC901 judges that. it is an evaporated tape (ME), and one track), thus a high-quality assemble-recorded pic- tion of preamplifier to stop.
of IC901 through a DIA converter circuit. The.d.etection when pin 23 is "Lo", icoo1 judges that it Is a metal tape ture with no noise atthe joint is obtained. (3) Alter the flying erase head is operated, M-µP sets
hole of a 13µ.m tape is closed and that of a 10µ.m tape (MP). When the pause button is pressed during recording, the the CH-1 recording control output (pin 77: CH1
opens. IC901 judges the tape thickness from the volt- following operations are performed. REC) to "Hi" at the fall of the next SW30Hz signal
age input to pin 44 (see the voltage table in the diagram). 6. LOADING MOTOR CONTROL CIRCUIT (1) When M-µP receives the operator's pause com- a11d the CH-2 recording control output (pin 76: CH2
mand, it resets the internal capstan FG counter REC) to "Hi" at the rise of the fallowing SW30Hz sig-
(Fig. 3-6) (CFG counter) to make the count number zero. The nal to start recording.
5·7. Safety Tab Sensor (S091·1) M-µPcontrolstheoperation mode (REW/REV, PLAY/FF, capstan FG counter counts the CAPST.FG pulses
LSTOP, ULSTOP or EJECT) of the mechanism via the input via pin 69, and when the count number 8. AE (Automatic Exposure) Control (Fig.
Switch 5091-1 detects the opened/closed state of the reaches approx. 84, it monitors the rise of the
miserasure prevention hole (or safety tab) on the cas- loading motor. M-µ.P applies the loa~ing motor cont~ol 3-7)
outputs at pins 63 to 65 to motor dnver IC906 to drive SW30Hz signal. When the rise of the SW30Hz sig-
sette and applies the result to pin 44 of IC901 through a nal is detected, the "FE ON" signal output via pin 7
D/A converter. Recording is possible when the detec- the loading motor until the commanded mode match~s Six shutter speeds (1/60, 1/120, 1/250, 1/1000, 1/2000
the operation mode of the mechanism. The output at pin goes "Lo", stopping the supply of the erase current and 1/10000-second) are provided. lhese shutter
tion hole is closed and is not possible when.the hole is flowing to the flying erase head.
opened. IC901 judges whether recording is possible or 65 goes "Hi" for approx. 3 seconds from the beginning speeds can be selected manually and three of these
when the mechanism mode is switched from LSTOP to (2) After the erase current flowing to the flying erase speeds (1/60, 1/120 and 1/250) can be switched
not from the voltage Input to pin 44 (see the voltage table
ULSTOP and .decreases the unloading speed. This head is stopped, M-µ.P sets the CH-2 recording con- automatical!y according to the iris value (F number).
in the diagram). trol output (pin 76) to "Lo" at the fall of the next
matches the amount of slack tape and the amount of S-µP (IC1901) is responsible for this control. S-µ.P
5-8. Hi-Band MP (HMP) Cassette Sensor tape to be taken up at the beginning of unloading. SW30Hz signal and the CH-1 recording control out-
put (pin 77) to "Lo" at the rise of the following
receives three signals (F.DET-1, F.DET-2 and FY) from
($091-2) The diode (0904) turns off in modes other than loading the camera circuit described before and detects the
and unloading to reduce the power consumption of the SW30Hz signal. operation angle of the Iris meter and vertical scanning of
Switch 5091-2 detects the opened/closed state of the Zener diode (Z0903). (3) M-µ.P sets the VTR to the reverse play mode until the image sensor to determine the appropriate shutter
HMP cassette detection hole of the cassette and applies The mechansim state.switches SHo S3 detect the opera- the CFG counter counts 1260 pulses (for approx. speed. S-µ.P then outputs four signals (SHUT 1 - SHUT
the result to pin 44 of IC901 through a DIA converter. The tion mod.e of the mechanism and apply it to pin 48 of 1.5 seconds) to provide a tracking period (for ap- 4) to drive the image sensor. S-µP receives the results
detection hole of a HMP cassette is open and that of a IC901 via D/A converter. prox. 1.2 seconds) immediately before assemble of comparison between the output voltage of the Hall
normal MP cassette is closed. IC901 detects the type of (see the voltage in the diagram} . recording is started. During reverse play, the device which detects the operation angle of the iris meter
cassette from the input voltage at pin 44. (see the volt- "REVERSE" signal from pin 4 of M-µ.P goes "Lo" and and the reference voltage corresponding to each F num-
reverses the direction in which the capstan rotates. ber (F2.0, F3.2 and F7.2), vla the F.DET-1 and F.DET-2
IC901 (M-uP)
.---------, (4) M-µ.P sets the preamp mode control output (pin 8: pins. F.DET-1 is input as a command to switch to a higher
I
I
I
I
LOADING
MOTOR
PRECONT) to "Hi" until recording is started to ac- shutter speed when the F number becomes as large as
I LOAD/ 63 tivate the preamplifier. This causes the pilot signals F3.2 (at 1/60-second speed) or F7.2 (at 1/120-second
I BRAKE
1 played back in the reverse and assemble periods speed) as the amount of icident light increases. When
I UNLOAD/ 64
I BRAKE (described la.ter) to be supplied to the ATF control the F.DET-1 signal is input (pins 11 and 5 of S-µ.P are
I IC601. short-circuited by Q1905), a shutter speed one step
OUTPUT
MECHA I (5) When the CFG counter reaches a count of 1260, M- higher than that set currently is selected (1/60 to 1/120,
STATE
LOAD UN- LM- I
µ.P resets the "REVERSE" output at pin 4 from "Lo"
LOAD SLOW I 1/120to 1/250). F.DET-2 isinputasacommandto switch
lDADING H L H I to "Hi" and runs the tape forward for approx. 0.3 to a lower shutter speed when the F number becomes
GV I
UNUW)START L H L
D904 I seconds (252 CAPST.FG pulses). Through this as Iowas F3.2(at1/250-second speed) or F2.0(at1/120-
I I
UNLOAO L H H
I I
operation, the tension of tape,ls corrected. second speed) as the amount of Incident light
BRAKE H H H I
I
·1
(6) Th~ "CAPST.ON" signal output from pin 30 of M-µP decreases. When the F.DET-2 signal is iaput (pins 11
I ZD902
STOP L L H I (2.7Vl I goes "Lo" which stops the capstan motor. The pres- and 4 of S-µP are short-circuited by 01905), the shutter
r-----..1·

~j""'-----_,,,~l] ?~.:lONJ I sure roller is compressed against the capstan for 5 speed one step lower than that set currently is selected
CM-SLOW I minutes maximum until pause is released. (1/250 to 1/120, 1/120 to 1/60). The reference voltages
SV I
I When pause is released, the following operations are per corresponding to each F number (F2.0, F3.2 and F7.2)
I I J-IECHA SW POSITION VOLTAGE OPERA Tl ON formed.
I 39k I STATE S3 52 51 (PH< -'S) MODE are selected by the shutter speed outputs (SHUT 1 and
I
MECHA STATE ~4 =-
8
---+------,,.--r-, I REW/REV OFF· OFF ON 3.17- 4.2 REWIND,
R.SEAACH
(1) The "CAPST.ON" signal at pin 30 goes "Hi" to start SHUT4).
(AID) ·
ov-sv 100k 47k 27k : PB. REC,STl!.L, the capstan motor. After the pause button is If the shutter speed were changed instantaneously, the
PLAY/FF ON OFF ON 1.64- 1.9 F.FWD
r- - ---- - - - - - - , I pressed, the assemble period ls set until recording change In the amount of Incident light would be faster
I · I I REC, PAUSE.
I ON is started (for approx. 1.2 seconds, 1,008 CAPST.FG
I I ·I··· I . I ~--'. L STOP OFF OFF 1.9·2.15 REC STBY than the change of the iris meter, causing over-exposure
I L_ -1-s1_ -r-s.L _J_sJ J UL.STOP OFF ON ON 2.15·2.49 POWER OFF pulses). During this period, the cylinder motor is or under-exposure. To prevent this, approximately one
I rotated, synchronized with the V.SYNC signal and
I l EJECT, ON ON ON 0·1.45 EJECT second is provided for switching the shlrtler speed to
I rtr the ATF servo controls the capstan motor so the match the follow-up speed of the iris meter. During the
I ROTARY MECHANISM STATE
I SWITCH video tracks are synchronized with the scanning of shutterspeed switching period, SHUT 1 goes "Hi", SHUT
IL ________ JI the video heads. 2 and SHUT 3 go "Lo" and SHUT 4 is a 60 Hz PWM out-
(2) When the CFG counter counts 1,008 CAPST.FG pul- put. The image sensor driver recognizes this period from j
Fig. 3-6 Mech. State Control .. ses (counts down to zero), M-µ.P monitors the rise the SHUT 1 - SHUT 3 levels and sets the operation mode

~ , I ' f

IT
1
" 'I• I ~ '/~~~
Elm - I
3-7
1 ' ,'' ~,. ~ 1 11 ~ • J' , ~ \ J ' 1
•'
TT 7 - 7E w- Hi
3-8
=zr
' j
mrumrat·r~
of the image sensor to the storage mode when SHUT 4 is switched to 1/120~ The storage period is 16.6 ms (256H Pin VO Active Abbreviation Function
components) at 1/60 and 8.3 ms (128H components) at No. Level
is "Lo" and the discharge mode when it is "Hi". The fre-
19 I Lo POWER SW Power switch input in the camera mode.
quency and phase of the PWM signal at the SHUT 4 pin 1/120. The difference of the storage period is 128H com- J.CAMERAl
are synchronized with the vertical sync signal (FV) to be ponents. When the storage period (Lo) is reduced by 20 I Lo POWER SW Power switch Input In the vrR mode.
synchronized· with the vertical scanning of the image 2H components for every field, the storage period (8.3 JYIR)_
sensor. Since a shutter speed switching period of ap- ms) of the objer.t is reached after approx. one second 21 I Lo EJECT SW Eiect switch ~eration in.2_ut.
(2H x 60fields), thus the 1/120 shutter speed codes 22 I Lo STAGE SW Detec1s that the cassette holder Is closed.
prox. one second is provided, the discharge period is in- 23 0 Hi/Lo ME/MP Discriminates between metal~~ and ev¥rated1Mt;l_ t~es.
creased or decreased at 2H Intervals when 1/60 ·is (SHUT 1 and SHUT 4 are "Lo" and SHUT 2 and SHUT 3 24 I Lo ANIN Detects the connection of the /W i'1E_Ut/outputjacks.
switched to 1/120 and at 1H intervals when 1/120 is are "Hi") are obtained. 25 I Lo REC START/ Detects the record starVstop switch operation in the camera mode.
switched to 1/250. The following is an exmple when 1/60 STOP SW
26 I Hi TEST When 'Hi" is applied, the headswitching point and over-<lischarge detection level are adjusted
r------------------------------------------1
I REFER TO CAMERA CIRCUIT· I
~uto- matical.!Y,
27 0 Lo SP/LP 1Notusech_
I I 28 0 Lo PB PHASE OFF {Notusefil
I I 29 0 Hi CYLON (Not used)
: SYNC IMAGE SENSOR . :
I GEN DRIVER I 30 0 Hi CAPSTON Reduces the~wer consum_2!ion of the motor driver when the ca_E_stan motor is stqQQ_ed.
I
I
I
I
31 - Connected to_g_round.
32 I Lo RESET Receives the reset command from S-.!!f to initialize M:J}.P.
I I
I I 33 B+ Connected to the SV_Q_ower source.
I I 34 I PULSE XTAL Generate a 16 MHz clock pulse.
I I 35 I PULSE EXTAL
I I 36 I Lo CSlMAINl Communicate data with IC902 (S-µP).
l
l
I 37 I Hi DATAIS-MI
I I
38 0 Hi DATAJ_M-~
L--------------- ----------- ------ ---- -- ____ J 39 0 PULSE CLOCKlS.Ml
~c;;\;~os;L;i.j I . 40
41
I
I
Lo
Hi
WAKEUP
DATAJ.ROM-Ml
Starts the 16MHz clock pulse_generator.
Receives data from the EAROM;

.----~-~~1~-~~-1 ___ ~J~ 431l

1
42 0 Hi DATA]M·YQl Transler operation data to the luma/chroma circuit.
SHUTTER SPEED CODE 37___ 4£_, 43 0 Lo CLOCKlM·YC}
1150 11120 1/:ZSO TFWlSIT
I KEY3 PHASEO KE\'2 FV 1 2 3 4 I 44 I 0-SV CSTDET (ND) Receives data on the opening/closing of the detection holes in the cassette (HMP, TAB,

SHUT
1 H L L H
I
I
SHUT iI 45 I 0-&J BATilA/Ql.
THICKNESSJthrou_g_h the D/A converter.
Measures the_power voltag_e of the batte_ry_and displays_ the remaini1'!9._ level in the EVF.
SHUT I I 46 I 0-&J DEW(_A/DJ_ Detects condensation.
2 H H H L
.I 47 I ().&/ VCR KEY (AID) Measures the voltage corresponding to each operation key to detect the key which has been
SHUT 11250
H H L t I IC1901 (S-µP) <?.E_erated.

ili
3
SHUT H .L H 60Hz L __ - - - - - - - - - - - - - 1120 48 i 0-SV MECHA SW (!\ID) Measures the voltage corresponding to the operation mode of the mechanism to detect the
4 PWM I
mode.
:I ,1160;I
I. 49 I Hi REV END Detects the end of t~e durin_g_ rewind and reverse search.
F2 F3'.2 F7.2 50 I Hi FWD END Detects the end of t~e durin_g~aybac~Lrecordirig and fast forward.
51 I 0-&I ATFERAOR Receives the ATF error volt~e from ATF IC to control the capstan_E_hase.
Fig. 3-7 Automatic Exposure (AE) Control 52 GND Connected toground.
53 AID REF Receives a reference volta_ge for /lJD conversion Inside the µ.P.
54 B+ Connected to 5V.
55 I PULSE T.REEL 1. Detects defective take-up of the take-up reel.
9. MICROPROCESSOR PIN FUNCTIONS 2. Used as the clock pulse of the tape counter.
3. Calculates the ta__mi remalnln_g_time.
9·1. M·µP(IC901) 56 I PULSE S.REEL Calculates the t1!2_e remaining_ time.
57 I Hi S EDIT IN INot usedl
Pin 1/0 Active Abbreviation Function 58 I PULSE C.SYNC Converted to a reference slg_nal ]/2 V.SYNCj for~inder_Q_hase control durin_g_recordi119::
No. Level . . 59 I PULSE TACH]FGl Video head_Q_Osition data for~nder_m,ase control
1 0 PULSE BLANK Blanks each 6H.f>~riod before and after the artificial V ~c pulse. 60 I Hi VIDEODET Detects the non-recorded section of the taPJ' to stQQ. the liner counter.
2 0 PULSE SW30Hz Switches the video heads, FM frequency and pilot signals, and suppresses audio switching 61 I PULSE CYLFG 1. Cylinder rotation data for cylinder speed control (720 Hz).
noise. 2. Detects~nder lock.
3 0 Hi PB Sets the luma/chroma and audio circuits to the..E!~ack mode. 62 I PULSE CFG Ca_Q_stan rotation data for ca_E_stan ~eed control (840 Hz in the SP model
4 0 Lo REVERSE Reverses the ca_Q_stan motor. 63 0 Hi LOAD Control the direction of rotation of the loadin_g_motor.
5 0 Hi MUTE Mutes the audio sls_nal duri11g_loading. 64 0 Hi UNLOAD
6 0 Hi SQUELCH · Sg_uelches the video outQ_ut. 65 0 Lo LMSLOW Decreases the loading motor speed for 3 seconds alter the mechanism starts unloading in
7 0 Hi FEON Activates the flying_ erase head duri1'!9._recordin_g_ and dubbil}S, the· L STOP mode to align the 1ape take-up operation with the operation speed of the
8 0 Hi PRECONT 1. Sets the preamplifiers of tho video heads to the playback mode. mechanism.
2. Sets the ATF control IC to the J!!~ack mode. · 66 0 Hi REC Sets the video sl9_nal_Qrocessil}g_ circuit to the record mode.
9 0 Lo fH CORRECT-2 (Not used). OT 0 PWM CAPST.SERVO Ou!e_uts a 15kHz PWM signal for caJ?_stan sj:)_eedle_hase control.
10 0 Hi fH CORRECT-1 68 0 PWM CYLSERVO Outp_uts a 15kHz PWM sig_nal for_Q}lljnder ~eed[Q_hase control.
11 0 Hi CMRQN/REF210 1 . Activates the camera signal processing circuit. . 69 I PULSE CFG Used as a clock pulse to determine the back space amount of tape during recording pause
· 2: OU!Quts a 210 Hz reference sl9!1al in the test mode. and also used as a _pulse for the linear time counter.
12 0 Hi S.EDIT Controls the_Q_ause mode of the VTR via the AN i!l.Q_ut/outputjacks during_ dubbi~ 70 - - Connected to 5 V.
13 0 Lo CSlEAROM}_ Activates the EAROM when the back~EAROMldata ls i~ut and output~·· 71 - -
14 0 Lo CSJY.C_l Activates the memo_!iwhen transmitting_ operation data to the luma/chroma circuit. 72 - -
15 0 Hi REQUEST].M-~ Re_g_uests S-..l!J' to transfer data.
csvsw Activates the CSV i:>_ower s~ circuit for camera_Q!ocessil'!fl_ circuit.
73
74
-
-0
- Connected tc_g_round.
Connected to 5 V.
16 0 Hi
17 0 Hi VCR ON Activates the VTR e_ower s~circuit. 75 Hi HEAD SW INot use~
18 0 PULSE ·END LED Drives the tl!Q_e end sensor indicator intermittently~ ·· 76 0 HI CH2REC Determines the turnirig-on time of the recordil}g_ s_ignal flowing_ to the CH-2 video head.

3-9 3-10
-· -·-·-SEP.
 Pin VO Active Abbreviation Function
No. Level recorded video track precisely with the scanning of the maintains the relative speed of the rotary video heads
77 0 Hi CH1 REC Determines the tumi'!9._-on time of the recordil'!fl. sjg_nal flowing to the CH-1 video head. video heads while rotating the video heads accurately at and the video tracks constant, absorbs uneveness in
78 0 PULSE ARTIFICIAL Generates a vertical !lyl'lC si9_nal durin~ still slow and search. the rated speed {1800 rpm). To control the above, speed rotation and minimizes variations in the time axis. The
V.SYNC control and phase control are applied to the capstan
79 Hi
phase control optimizes the tracking. Table 4-1 shows
0 PLT SEL2 Select pilot signals during recording and playback.
Hi
motor which drives the tape and the cylinder motor the reference signals and feedback signals used for each
80 0 PLT SEL 1
which drives the rotary video heads. The spe~ control control.
9-2. S·µ.P (IC1901)
Table 4-1 Signals used in the Servo System
Pin 1/0 Active Abbreviation Function
No. Level Motor S_ystem Mode Reference Sig_nal Feedback Signal
1 - Connected to 5 V. Cylinder Phase Recordi!!9_ 1/2VSYNC TACH(PG) pulse
2 I - PIC!Y_back REF30 Hz
3 I KEY4 These pins form a matrix switch circuit which detects the operation of switches on the side Speed Common ]}ilinder FG(CYLFG: 720 HZ)
4 I KEY3 panel. Capstan Phase Recording REF210 Hz Capstan FG (CAPST.FG/4:
5 I - KEY2
210 Hz)
6 I - KEY1
Pl~back 4-fr~uen~lot s_ignals
7 I - KEYO
8 0 - PHASE3 Speed Common Ccm_stan FG(CAPST.FG: 840 Hz)
9 0 - PHASE2
IC901 ( M-t.1P)
10
11
0
0
PHASE1
PHASEO
,.------------------------.,
I I
I I
12 Connected to 5 V. lC603(112l I I
13 QQ_en ...__ _ _
a1 <>--<o1 62 840Hz
14 0 PULSE REC RUN I
es
15 0 PULSE TALLY LED Outputs a 500 Hz pulse during REC (CAM) and a 500 Hz pulse containing a 0.5-sacond blank
when the battf!JY is dischara_ed.
16 0 PULSE POWER LED Outputs a 500 Hz pulse during power on and a 500 Hz pulse containing 0.5-second blank
when trouble occurs.
17 Vss Connected to_g_round.
18 XT1 Generate a 32 kHz clock pulse.
19 XT2
20 I Lo RESET Initializes S-.J!,f when the_..Q.ower volt~e exceeds 2.5 V.
21 - X1 Generate a 4 MHz clock pulse.
22 - - X2
23 0 Lo csisRAr.,ft Not used
24 0 Lo CS]jT'=fil_ Not used. I
I
25 () PULSE STB(CG) Goes "Hi' when data is being transferred to the character generator and goes "Lo" when I

~·
--0 Lo CSIMJ_
transfer is completed.
Oes_jg_nates M-µ.P as an 01?.1.ect to which data is transferred.
I
I
I
27 0 Hi RESET (M) Initializes M-J.1.P when a 6V battim1_is connected. I
28 0 PULSE BATTCHK Activates the backl!Q_detector in IC904 eve_ry_ 500 ms in the backup mode. I
29 I PULSE DATA}A-S} Receives data from M::1!f. I
I
3{) 0 PULSE DATA1S-M} Transmits data to M::Hf. I
31 0 PULSE CLOCK}S-M} ~chronizes data transfer. I
68
32 Lo BACKUP Sets S-_g._P to the backt1Q mode when the &I..PSJwer suf)f>ly Is disconnected. l--"----i.::.::"-C.SYNC
I
I
33 I Hi CS (CG) Designates the character_g_enerator as an oblect to which data is transferred. ----------8~PRECONT(PB,ASBL: Hi) :
34 - Not used.
L______E~~-=~2~1~~'.:: ________ J
35 I Hi REQUEST (M-S) Receives the data request command and the acknowledgement that data reception has
been completed form M:1!_,P. · Fig. 4-1 Servo Control
36 I Hi BLCSW Backlight correction switch ~eration l'lQ_ut
37 I PULSE V.IN ]inchronizes the shutter control ou!Q_ut.
38 - Not used. (1) 1/2 V. SYNC
39 - Reference signal for cylinder phase control during
the CH-2 video head on the upper cylinder. The frequen-
40 0 Hi SHUT.4 These swi1ch the shutter speed. cy of the TACH(PG) pulse is 30Hz when the cylinder
recording. This is obtained by dividing the vertical sync
41 0 Hi SHUT.3 motor rotates at 1800 rpm.
42 0 Hi SHUT.2 signal separated from the video signal by two.
(5) Cylinder FG (CYLFG)Pulse
43 0 Hi SHUT.1 {2) REF30Hz
44 I Hi SHUTIERNM Determines the shutter switch Ir![ mode. The signal used to detect the speed of the DD cylinder
Reference signal for cylinder phase control during play.
motor. This is generated from the FG sensor circuit
This is obtained by dividing the 16MHz clock pulse down
to30Hz. board attached to the lower cylinder which detects the
(3) REF21 OHz passing of the magnet fitted to the rotor shaft of the DD
CHAPTER 4 SERVO cylinder motor. The frequency of the cylinder FG pulse
Reference signal for capstan phase control during
(1800 rpm) to keep the length of video tracks constant, is set as follows.
1. GENERAL DESCRIPTION (Fig. 4-1) recording. This Is obtained by dividing the 16MHz clock
moreover, it matches the position. of the· rotary video pulse down to 21 OHz.
During recording, the servo circuit makes the magnetic head precisely with the phase of the vertical sync signal (4) . TACH(PG) pulse Recording/playback: 720 Hz ,
tape run at precisely the specified speed (1.4345 cm/s) in the video signal to be recorded; thus aligning the starts Feedback signal for cylinder phase control. This Is Still play: 716 Hz,
to maintain the specified video track pitch (20.5µm), and of video tracks at positions 6H before the vertical sync generated from a magnetic sensor on the FG sensor cir- Forward search: 742 HZ,
rotates the·video heads accurately atthe rated speed signal. During playback•. the servo circuit aligns the cuit board attachedto the lower cylinder which detects Reverse search: 698 Hz
the passing of the magnet installed approx.. 109.5° before
3-11/ 4-1
 (6) Capstan FG (CAPST.FG) Pulse
The signal used to detect the speed of the DD capstan
motor. This is divided by 4 to generate a feedback sig-
nal for capstan phase control· during recording. The
CAPST.FG pulse Is generated from an FG sensor at-
tached to the chassis which detects the passing of the
magnet fitted to the rotor shaft of the DD capstan motor.
When the rated tape speed Is maintained, the frequen-
cies of the CAPST.FG pulse are set as follows.
Recording/playback: 840 Hz,
Forward search (X9): 7,785 Hz,
Reverse search (X7): 5,700 Hz,
Fast forward (Xi 5): 13,293 Hz,
Rewind (X15): 11,861 Hz
(7) 4-Frequency Pilot Signals
Feedback signal for capstan phase control during play.
One of 4-frequency pilot signals is selected,
synchronized with the head switching signal (SW30 Hz),
in the specified orderfor each field during recording, and
is recorded together with other RF signals. ·
During playback, the main RF signal component and the
pilot signal components from both adjacent tracks are
reproduced by the rotary video heads which are 25µm
wide, about 1.2 times wider than the video track pitch,
and the phase of the capstan is controlled so the levels
(crosstalk components) of the pilot signals reproduced
by both adjacent tracks are always equal.
The frequencies of pilot signals are speclfiedas fl = 6.5
fH, f2 = 7.5 fH, f3 = 10.5 fH and f4 = 9.5 fH; f1 and f3
are recorded by the CH-1 video head, and f2 and f4, by
the CH-2 head.
FG FREQ.
REC IPB : 720Hz
STILL : 716Hz
F.SEARCH:742Hz
A.SE:ARCH:697Hz
Fig. +2 Cylinder
4-3
ii
2. CONFIGURATION OF CIRCUITS (Fig. 4-1)
The servo circuit consists of four ICs (IC901, IC601,
IC603 and IC604}.
IC901: Controls the speed and phase of the cylinder
motor, controls speed and recording phase of
the capstan motor, selects the pilot signals and
generates a SW30 Hz signal and an artificial
V.SYNC signal.
IC601 : Controls the playback phase of the capstan
motor (ATF) and generates pilot signals.
IC603: Amplifies the CYLFG signal and drives the
cylinder motor.
IC604: Amplifies the CAPST.FG signal and drives the
capstan motor.
3. CYLINDER SERVO
3-1. Cylinder Speed Control (Fig. 4-2)
M-p.P is responsible for speed and phase control of the
cylinder motor. M-µP receives feedback signals
(C'r'LFG, TACH(PG), C.SYNC) necessary for cylinder
speed-/phase~control, detects speed/phase errors. The
PWM signal Is smoothed, amplified by a switching
regulator and converted to a power supply which drives
the cylinder motor. M-µP generates a SW30Hz signal
from the TACH(PG) signal and generates the following
control signals, synchronized with SW30Hz.
(1) Artificial V.SYNC signal,
(2) A~cording period control signals (CH1 REC,
CH2REC),
(3) Pilot rotation control signals (PLT SEC 1, PLT
SEC2) .
The cylinder FG (frequency generator) which generates
r--------,I
I
REGULATOR
I I
I 11
134 I I
L _______ J
~~~z
PG091
I .
·
158
c:smc·
(IC201-2S)
se'w6 Control
CYLFG pulses is under the lower cylinder and detects
the passing of the magnet fitted to the rotor shaft using
the printed coll attached to the lower cylinder. The fre-
quencies of the CYL FG pulse are set as follows.
Recording/playback: 720 Hz,
Still play: 716 Hz,
Forward search: 742 Hz,
Reverse search: 697 Hz
The CYLFG pulses are supplied to pins 10 and 11 of FG
amplifier/cylinder driver IC603 and are amplified and
shaped to the amplitude necessary for processing in
IC901 in the subsequent stage. The amplified CYL.FG
pulses are output at pins 12 and 13 and supplied to the
speed error detector (SPEED ERROR DET.) in IC901.
The speed error detector compares the frequency of the
CYLFG signal and the reference frequency (720 Hz in
recording/playback, 716 Hz In still play, 742 Hz in for-
ward search and 697 Hz in reverse search) to detect
speed error data.
The speed error data, is added to the phase error data
(described later) and is then supplied to the 15kHz PWM
circu~ which changes .the duty of the 15kHz PWM signal
in proportion to the level of the speed error data. When
the cylinder speed becomes slower than the rated
speed, for example, the level of the detected speed error
data becomes higher, the duty ratio of the 15kHz PWM
signal becomes higher to increase the smoothed volt-
age, thus increasing the cylinder speed. The speed-
/phase-error data converted to a PWM signal is output
from pin 68, smoothed bya lowpass filter arid is supplied
to the duty control input of the 500kHz PWM generator
(SOOkHz PWM) through buffer (IC908, IC912) and pin 1O
of the regulator. The 500kHz PWM generator becomes
active when the VCR ON signal input via pin 2 is "Hi" and
controls the duty of the SOOkHz PWM signal according
to the cylinder speed/phase error voltage. The output of
the SOOkHz PWM generator is smoothed by a lowpass
filter (LPF), out put at pin 11 and is supplied to the drive
I
I coil power input (pin 4) of the cylinder driver (IC603).
I
I fixed to approx. 4. 7H. The artificial V.SYNC signal is out-
I
I 3-2. Cylinder Phase Control
A magnetic sensor for detecting TACH(PG) pulses is at-
tached to the lower cylinder and detects the passing of
the magnet approx. 109.5° before the CH-2 video head.
This output is supplied to the shaper (ICS-02).
IC602 amplifies and shapes the TACH(PG) pulse and
prevents malfunctions due to noise which ls input while
the TACH(PG) pulse is not "Hi". When the TACH(PG)
pulse is "Hi", C630 is charged through 0604. When the
TACH(PG) pulse goes "Lo" r-Jcc/2), the levels at pins 2
and 3 are inverted and the output of IC602 goes "Lo" until
the next TACH(PG)pulse is input. This operation
prevents malfunctions due to noise while the TACH (PG)
pulse is "Lo".
The amplffied and shaped TACH(PG) pulse passes
through a shaper (0605) and ls supplied to the
SW30/SW15 generator (SW30/SW15 GEN) in IC901 via
pin 59. The SW30/SW15 generator sets the duty ratio of
the TACH (PG) pulse precisely to 50% and also the. CH-
1 pulse to "Lo" and the CH·2 pulse to "Hi" (this output sig-
nal is called "SW30Hz"). ltalsodividestheSW30Hzsignal
by two to generate a SW15Hz signal. The phase of the
SW30Hz signal is adjusted automatically when this
model is set to the test mode and the alignment tape is
played.
In the test mode, the time (t) between the TACH (PG) and
V.SYNC signals is detected, subtracted 6H (381s) from
(t) and is written to the EAROM (IC905). The time (t' =t-
6f:J) is read from the EAROM (IC905) during power on.
Ttien, during recording/playback, the calculation of time
is started afteraTACH(PG) signal is detected, and when
the time reaches t', the level of the SW30Hz signal Is in-
verted. This operation sets the phase of the SW30Hz sig-
nal to SH before the V.SYNC signal. Since the time (t)
between the TACH(PG) and V.SYNC signals is different
in each camcorder, the test mode should be executed
wtien the cyfinder, EAROM (IC905), etc. are replaced.
The SW30Hz signal is supplied to the phase error detec-
tor (PHASE ERROR DET), artificial sync generator (AR-
TIFICIAL SYNC GEN), recording current control circuit
(REC PERIOD CONT) and pilot signal control circuit
(PILOT ROTATION CONT).
The PHASE ERROR DET compares the phase of the
SVV30Hz signal and 30Hz reference signal (1/2 V SYNC
or REF30Hz) to detect phase error data.
The 30Hz reference signal is different in the record and
play modes. During recording, the V.SYNC signal is
separated from the composite sync signal input via pin
58 and is divided by two create the 1/2 V.SYNC signal
which Is used for reference. During play, the 16MHz
clock pulse generated in the IC is divided down to 30Hz
and this REF30Hz s!gnal is used.
The phase error data is added to the speed error data
and ls supplied to the 15kHz PWM circuit described pre-
viously.
The ARTIFICIAL SYNC GEN operates during trick play
including search and pause, etc. to compensate for the
degradation of the V.SYNC signal during trick play. The
phase of the artificial V.SYNC signal is set to approx. 6H
from the edges of each SW30Hz signal and its width is
put from pin 78 and supplied to the luma/chroma circuit.
The REC PERIOD CONT controls the turning-on time of
the recording current supplied to the CH-1 and CH-2
video heads during recording. The PILOT ROTATION
CO NT generates signals (PLT SEL 1, PLT SEL 2) to
switch pilot signals (f1 to f4) during recording and play.
Refer to the capstan phase control during play for details.
4. CAPSTAN SERVO
4-1. Capstan Speed Control (Fig. 4-3)
M-µ.P is responsible for speed control and recording
phase control of the capstan motor.
The CAPST.ON signal from pin 30 of M-µP controls the
opening and closing of the capstan speed control loop.
When the capstan motor is stopped, the CAPST.ON sig-
nal ~oes "Lo", opening the loop. Since the CAP ST.ON
signal goes "Hi" in the loading, fast forward, rewind, play
and record modes, the loop is closed. The CAPST.FG
which generates CAPST.FG pulses Is at the back of the
4-4
-· . ........ - ,, ... .. .. ,..,..... iiii'"CEffi7l.1iiTiT- .
chassis and a· magnetic sensor attached to the chassis
detects the passing of a magneron the circumference of
the rotor. The frequencies of the CAPST.FG pulse are
set as follows.
Recording/playback: 840Hz,
Forward search (X9):. 7.788 Hz,
Reverse search (X7): 5,700 Hz,
Fast forward (X15): 13,293 Hz,
Rewind (X15): 11,861 Hz
The detected CAPST.FG pulses are supplied to pins ·1 o
and 11 of IC604 and are amplified to an amplitude which
can be processed by IC901 in the. subsequent stage.
The amplified CAPST.FG pulses are supplied to the
speed and phase error detectors (SPEED ERROR DET,
REC PHASE ERROR DET) through IC604 pin· 12 and
IC901 pins 62 and 69.. The speed error detector com-
pares the frequency of the CAPST:FG signal and the
reference frequency (840Hz in recording/playback,
5,700Hz in reverse search, 7,788Hz in forward search,
13,293Hz in fast forward and t1,861Hi in rewind) to
detect the speed error data. . The tape speed Is setto 9 (7) times the normal play during
The speed error data is added to the phase error data
and is then supplied to the 15kHz. PWM circuit which
determines the duty ratio of the 1SkHz PWM signal in
proportion to the level of the speed error data. The
speed error data converted to a 15kHz PWM signal is
output from pin 67, smoothed by a lowpass filter and is
supplied to the duty control input of the 500 kHz PWM
generator (SOOkHz PWM) through buffer (IC908, IC912)
and pin 12 of the regulator. . .
The SOOkHz PWM generator becomes active whe.n the
VCR ON signal input via pin 2 is "Hi" and controls the duty
of the SOOkHz PWM signal according tO the cylinder
speed/phase error voltage. The. output of the output at
pin 13 and Is supplied to the drive coil power input (pin
4) of the capstan driver (IC604) .. The motor driver uses
the "REVERSE'! signal input via pin 18 to determine the
direction of rotation.
4-2. Capstan Phase Control
The capstan phase Is controlled in different ways in the
record, play and search modes.
4-2-1. During Recording
The phases of the CAf>ST.FG signal (210 Hz) divided by
four and 21 OHz reference signal are. compared to detect
phase errors which are converted.to a 15kHz PWM sig-
nal and. smooth.ad to date.ct the phase error voltage.
4-2·2. During Play
Four pilot signals (f1 to 14) were previously recorded
together with the audio and video signals while being
switched every field (track).· During play, the levels of the
pilot signals reproduced from both adjacent tracks of the
main playback track are compared to detect the phase
error voltage (ATF error voltage).
4-2·3. During Search
for\vard (reverse) search so the number of noise bars on
the TV screen Is the same In both· modes. Moreover, the
ATF error voltage at the center of the screen is sampled
to control.the capstan phase so that the noise bar is fixed
at the center of the screen. · ·,
4-3. Capstan Phase Control during
Recording (Fig. 4-3)
The 840Hz CAPST.FG pulse Input via pin 62 of M-µP is
divided by four and.supplied to the phase error detector
(REC PHASE ERROR DET). The phase error detector
compares the· phases of the 21 OHz reference signal and
the CAPST.FG pulse divided by four (CAPST.FG21 OHz)
to detect the phase error data. This data is selected by
switch ($1), added to the speed error data and is then
supplied to the 15kHz PWM generator described in the
capstan speed control section. .
4-4. Capstan Phase Control (ATF) during
Play (Figs. 4-3 to 4-6)
4-3-1. General Description of ATF
The capstan phase during play is. controlled by the
specified ATF servo system. The ATF servo system uses
pilot signals recorded on each track to optimize track-
ing. The ATF servo compares the.amount of crosstalk
In the pilot signals reproduced from the two tracks ad-
jacent to the main playback track and uses the difference
as an error component to control the capstan phase.
There are fourpllot signal frequencies, .f1 to f4. The pilot
frequencies are specnied so the difference in frequency
of the pilot signal reproduced· from the main playback
track and one (the other) adjacent track ls fH (3 fH) ln the
long wavelength area (about 100 to 160 kHz) where there
is no azimuth loss and also an offset of 0.5 fH is provided
to avoid flyback pulse interference. The recording level
of the pilot signal is $pecifloo as approx..•14 dB with
respect to the chroma level.
Fig. 4-4 ·(a) shows the rotation of pilot signals during
recording, (b) shows the relationship of 4 pilot frequen-
cies and (c) the allocation of pilot signals on the video
tracks. Pilot signals (f1 and 13) are recorded by the CH-
1 video·. head on the video tracks, and f2 and f4 are
recorded by .the CH-2 head. The pilot signal is switched
to f1, f2, f3, f4 and back to f1 countercJockwise as shown
in .Fig. 44. (a) for every field, synchronized with the
SW30Hz and SW15Hz head switching signals, and thus
the specified pilot pattern shown in (c) ls obtained. Since
the relationshlp between the· pilot frequencies is
specified as shown in (b), the difference in pilot frequen·
cies Is fH between f1 and f2, and f3 and f4, and 3 fH be-
fH and 3 fH alternate wfth each other every field.
During play, the rotary video heads with a width (25µ.m)
1.2 times the specified video track pitch 20.3µ.m play
back the pilot signals on both tracks adjacent to the main
playback track. Although 1he CH-1 video head has an
azimuth of + 10° and the CH-2 video head has an
azimuth of -10° (a total of 20°) to eliminate crosstalk in
the luma signal, the frequency of the pilot signal is low,
therefore there is almost no azimuth loss and the pilot
signals are always reproduced from the playback tracks.
During play, the ATF servo mixes the pilot signals
reproduced from the tracks before and after the main
playback track with the reference pilot signals (f1' - f4')
to detect difference frequency pilot signal components
(fH, 3 fH). The outputs of these components are com·
pared to detect the ATF error voltage. The reference
pilot signals are rotated so the difference frequency pilot
signal component between the pllot signal reproduced
from the track before (after) the main playback track and
the reference pilot signal is !H (3 fH). When the video
tracks on which the f1 to 14 pilot signals are recorded be
played back in sequence in the forward direction, for ex·
ample, the reference pilot signals corresponding to each
track are in the order f1, f4, f3 and f2 (be careful as the
direction of rotation is reverse to that In recording):
· (c) 20.Sµn

tween f2 and f3,· and f4 and f1, that ls. the differences of Fig. 4-4 Pilot Signal Rotation

LUMA/CHROMA

To
VIDEO HEAD

FM AUOlO

~ ;i;
J78fH
(5.9,755MHz)

DIFFERENCE FREQUENCY
REF PB PILOT
PILOT ti 12 13 t'
fl - fH ('!H) 3fH

r2 fH - nH (2fH)

PI LOT SELECTION CODE 13 (UH) 3fH - fH

PB REF PILOT
~M,:i-~
PILOT
TRACK PB/SRCH STILL Sl~AL
~TL-1
1-80) 14 3fH (2fH) fH -

11 11. 11 11 H H : 2fH ANO 4fH COMPONENTS ARE

NO! USED
12 " 12 H L
13 12 13 L H

14 12 . 11 14 L L

· Fig. +5 Rec/Ref Pilot Signal Generator

4-5 4-6
--7 T - .. " ....
mrrnrtmnw
 4-3-2. Pilot Signal Generator (Fig. 4-5) servo control.
IC601 uses a 378fH (5.947552MHz) crystal oscillator be-
4-4. Capstan Phase Control during Search due to the azimuth effect is small. During search, the 4-
The AGC gain is determined by the voltage obtained by (Fig. 4-3, 4-6, 4-7) wave pilot signals are reproduced twice in sequence in
tween pins 14 and 16 to generate a 378fH clock signal. smoothing the ATF error voltage. The output of the AGC
This clock signal is divided by the four divider circuits one.field period. therefore theATF error output becomes
circuit is supplied to the two difference frequency pilot The search speed is set to the 9 (7) times the normal play
(DIVIDER) to become four pilot signals with frequencies a wave with two cycles in one-field period. M-µP
component detectors (fH BAL MOD. 3 fH BAL MOD). speed so the number of the noise bars on the screen is
f1, f2, f3 and f4. The following shows the division ratios samples the ATF error voltage (a 120Hz sine-wave
The fH BAL MOD and the fH SPF in the subsequent stage the same (5) in both modes. The phase of the capstan
and frequency of each pilot signal. during search) Input via pin 51 at the center of the
mix the playback pilot signals (f1 to f4) and reference motor is controlled so that three of five noise bars ap-
playback period of the CH-2 video head. M-µ.P selects
pilot signals (f1' to f 4') to detect the fH difference frequen- pear on the effective area of the screen in both modes.
f1 = 378 fH/58 = 6.5 fH (102.544 kHz), the reference pilot signal corresponding to the noise bar
cy pilot signal component (equivalent to the playback This phase control allocates the three noise bars, one at at the center of the screen so that the three noise bars
f2 = 378 fH/50 = 7.5 fH (118.951 kHz), level of the video track before the main playback track). the center and two at symmetrical positions in the upper appear at the center and at symmetrical positions in the
f3 = 378 fH/36 = 10.5 fl-i (165.21 OkHz), The 3 fH BAL MOD and the 3 fH SPF In the subsequent and lower halves of the screen. During search, one scan- upper and lower halves of the screen. The noise bar at
f4 = 378 fH/40 = 9.5 fH (148.689 kHz) stage detect the 3 fH difference frequency pilot signal ning of the video heads causes nine video tracks to be the center appears when the video track on which the f1
component (equivalent to the playback level of the video reproduced in sequence and continuous playback sig- or f3 pilot signal was recorded is being played back. M-
The 4-frequency pilot signals are supplied to the pilot track after the main playback track). The reference pi!ot nals are formed. If the azimuths of the video head and µ.P selects the f4 (f2) reference pilot signal for the video
selector circuit (PILOT SELECTOR). The pilot selector signals are selected so the difference frequency com- track do not match, noise would occur in the picture track on which f1 (f3) pilot signal was recorded.
receives two pilot select signals (PLT SEL 1, PLT SEL 2) ponent between the main playback track and the track played back from that track. In this model, five of nine The same capstan phase control circuit Is used during
output from pins 79 and 80 of M-µP, via pins 21 and 23, before it Is fH and that between the mafn playback track video tracks would cause noise. On the other hand, play and search, but the sample timing and the rotation
and selects the pilot signals during recording and and the track after It.ls 3 fH. The detected fH and 3 fH since the pilot signal has a low frequency, attenuation of reference pilot signals are different.
playback. M-µP generates the PLT SEL 1 and PLT SEL difference frequency pilot signal components are output
2 signals, synchronized with the SW30Hz and SW15Hz from pins 30 and 31, reenter IC601 via pins 32 and 33 CH 1 CH2 CHI CH2
signals generated internally. The recording pilot signal and are supplied to the comparator (A 1) through switch
is output from pin 24 and mixed with the FM audio sig- (S1). S1 is controlled by the voltage applied to pin 37.
Since pin 37 Is fixed at "Lo" in this model, the signals
nal, down-converted chroma signal and frequency-
modulated luma signal through a lowpass filter (LPF) and shown In the diagram are selected and supplied to A1.
is supplied to the video heads. A1 compares the fH and 3 IH difference frequency pilot
signal components to detect how the video heads are 28

4-3-3. ATF Phase Control Circuit (Fig. 4-6) drifted to the tracks before and after the main playback 27

The ATF. processor IC601 is responsible for phase error track. Pin 39 applies an offset voltage to A1 when the 26

detection (ATF error) during playback. tape transport system is adjusted to shift the tracking 25

point, thus simplifying checking of variations in the FM 2,

The playback pilot signal input via pin 40 Is supplied to 23
the AGC circuit (AGC) through an amplifier, pins 43 and envelope. The output of A1 Is supplied to pin 51 of M- DISPLAY

44. The AGC circuit (AGC) controls the amplitude so that µ.P through switch (S2: always on), pins 6 and 11, com-
the sum of the pilot signals reproduced from the tracks parator (A2) and pin 12. M-p.P converts the ATF error
before and after the main playback track are always the voltage at pin 51 to a digital value and adds it to the speed
same. This is to prevent level variations caused by chan- error data and then supplies it to the 15kHz PWM gener-
ges in tape tension, the difference of head projection and atvi' described in the speed control section.
variations In playback speed from affecting the ATF

,!.C.§.0.!.(!j:::if.L_.,
I I
I I
I I
I I 11
I I
10
I I
7
i.---'F---1-'....:-os PLT SEL2 I
eo
1
PLTSEL1 l
I I
I
I
I
REF
PILOT ~ru.-1 ~Tili
L: i!
I fl H H
I
I 12 H L
I
13 L H
I
I I 14 L !..
DIFFERENCE FREQUENCY
I I
33 I
REF PB PILOT I I ENVELOPE
PILOT fl f2 r3 f4
134 I
11 - fH (4fH) 3fH
57
~--r-----.....,------'1 AT,F LOCK
9---11-------' 14 I
12 11 · - 31H (2fH)
11
I•.
. ·, I
·I REF PILOT
13 (4fH) 3fH ·- fH ,, ./_ _A_ri=_ERRO_R_v_ot:_:rAG_E_ _-f'l12....___ _s~1 ATF ERROR

14 3!H (2fH) !H
s' 2
I .
I ~SW30Hz . AFT ERROR
2rH ANO l,fH COMPONENTS ARE
NOT USED
;J;. i I :t._______ ..J
VOLTAGE

L----------------------.1 " !1 12 13

· · .. Fig:f~6 .. Caps_tan Phase Control. Fig. 4-i Search Operation

4-7 j

w
' ;• I••,', I' ,r•I' \•\' • ~ ""~•' '~, "~ I: ~·
I .'I I ~ • ' f ,' ': ·: '' ' f,.'' •' , 'l ", •; 't ' ,.' .. ; ' ' ~' •' , · · .' 'I ' 1,
,__"""""'_~--~"""'""'".,""'"'·""'''"''•···;:
-T TFF PETr-7
4-8
 CHAPTER 5 VIDEO
formation signal has been mixed, generated at pin 28 is 1-2-4. Milling Circuits
1. VIDEO SIGNAL INPUT/OUTPUT 1-1-3. SW6 in IC202 supplied through pin 30 and clamping circuit (CLAMP) There is three muting circuits and they are controlled by
CIRCUITS (Fig. 5-1) This is controlled by a voltage at pin 29. The OR gate to the lumaJchroma mixer rr;c MIX) which mi:xes the the BLANK signal.
(0902) inputs two signals, CAMERA ON and AV IN (Lo), chroma signal with the luma signal to generate a com- (1) Information Mixer (INFOS MIX) in IC201
The input signals of the video signal processing circuit and generates "HI" voltage during camera recording. posite video signal. This mixes the INFOS character signal with the camera
are as follows. (1) During Camera Recording . The composite video signal is supplied through SW15 luma or AV IN video signal and also mutes the signal.
(1) Composite luma signal {LUMA) and 3.58MHz SW6 is set to the. "CAMERA REC" position, and the (PB/S-REC); video amplifier (VIDEO AMP) and pin 38 to When the BLANK signal supplied to pin 29 goes "Hi", the
chroma signal (CHROMA) from camera, camera chroma signal supplied to pin 44 is selected. both pin 4 of the AV connector and EVF (lC801: EVF EE luma slgnal, EE video signal or playback luma signal
(2) Composite video signal from AV connector (2) During. AV IN Recording · PROCESS). is muted.
The video signal input/output circuits control . the SW6 is set to the "PB/AV IN REC" position, and no sig· (2) Chroma Signal (2) Muting Circuit (MUTE) in IC202
input/output of the above signals; nal is selected. The camera chroma signal from a buffer (01231: BUF) This mutes the EE or playback chroma signal when the
is supplied through pin 44 of IC202. The camera chroma "Hi" BLANK signal is supplied to pin 37.
1-1. Input Signal Selection Switches 1-1-4. SW1 in an 1.nput Signal Selecti.on Circuit
signal is supplied through SW6, pin 32 and pin 5 of IC201 (3) SW2 In IC211
(IC211: INPUT SELECT)
to the comb filter (COMB FILTER) which simply passes This is also controlled by the BLANK signal supplied to
1-1-1. SW1 in the Luma Signal Processing Circuit This is controlled by the PB.signal supplied to pin 2.
(IC201: LUMA PflOCESS) the chroma signal during camera recording. The pin 4. When it goes "Hi", SW2 ls changed to the "Hi" posi-
(1} During Recording
The mode is detected by a system control main micro- camera chroma signal is supplied through SW7, tion, and the chroma signal is muted.
SW1 is set to the "PB (Lo)" position, and the .camera
processor (IC901 : M- J.LP) and transferred to a mode 3.58MHz bandpass filter (3.58MHz SPF) and pin 13 to
chroma signal supplied to pin 1 is selected. pin 30 of IC202. The camera chroma signal is then 2. RECORDING AMPLIFIERS/PRE-
detector (MODE DET) in IC201. The· mode detector (2) During Playback recorded on the tape. AMPLIFIERS (Fig. 5-2)
changes SW1 depending on the transferred mode. SW1 is setto the "PB" position, and the playback chroma
(1) During Camera Recording The EE chroma signal from 01231 is supplied to pin 1 of
signal supplied to pin 3 is selected. IC211. Two recording amplifiers (IC210: CH1 REC AMP, IC209:
SW1 !s set to the "CA~AERA" position, and the camera
During recording, the PB signal goes "Lo" and the CH2 REC AMP) and two preamplifiers (IC206: CH1
luma signal supplied to pin 34 Is selected. 1-2. Signal Route PREAMP, IC208: CH2PREAMP) are provided. The fol-
(2) During AV IN Recording camera chroma. signal supplied to pin 1 is selected by
1-2-1. During Camera Recording SW1 . This camera chroma signal is supplied through lowing signals are used to control this circuits.
SW1 is set to the "AV IN" position, and the AV IN video
(1) Luma Signal SW2 which is a muting circuit and pin 7 to the luma/ (1) CH1 REC Signal (Pin 1 of IC210)
signal supplied to pin 32 Is selected.
The camera luma signal from a buffer (01230: BUF) is chroma mixer in IC201. This goes "Hi" during CH1 track recording and activates
1·1-2. SW1 in the Chroma Signal Processing Circuit supplied through pin 34 of IC201, SW1 (CAMERA), SW2 IC21 Oto form the recording circuit.
1-2-2. During AV IN Recording
(IC202: CHROMA PROCESS) (AGC OFF), clamping circuit (CLAMP) to the comb filter (2) CH2 flEC Signal (Pin 1 of IC209)
This is controlled by a voltage supplied to pin 39, The composite video signal from pin 7 of the AV connec-
(COMB FILTER) which simply passes the luma signal This goes "Hi" during CH2 track recording and activates
however in this model. pin 39 is grounded. Therefore, tor is supplied through pin 32 of IC201, SW1 (AV IN),
during camera recording. The camera luma signal is IC209 to form the recording circuit.
SW1 is set to the "Lo" position, and the chroma signal video AGC circuit (VIDEO AGC) and SW2 (REC) to the
then recorded on a tape. (3) PRE CONT. (Lo) Signal (Pins 1 of IC206 and
clamping circuit. The clamped AV IN video signal is sup- IC207)
supplied to pin 30 is always selected. An EE (Electric-to-Electric) luma signal, to which an in· plied to the comb filter which separates the luma and
The PRE CONT. signal is inverted by an inverter (0246:
chroma signals from the AV IN video signal. The AV IN
INV). This goes "Lo" during playback and activates
luma signal is then processed and recorded on the tape,
IC206 and IC207 to form the playback circuit.
the same as in recording.
(4) SW30Hz Signal (Pins 8 of IC206 and IC207)
The AV IN chroma signal is supplied through SW7,
This selects the CH1 or CH2 head output signal during
3.58MHz bandpass filter and pin 13 to pin 30 of iC202
play to form a continuous signal.
and recorded on the tape, the same as in camera record-
ing. 2-1. Recording Operation
The EE video signal from the clamping circuit is supplied
through the information mixer (INFOS MIX), pins 28and 2-1-1. Mixer {0218: MIX)
30, clamping circuit, SWS (REC), video amplifier and pin This mixes 1he recording chroma signal with the record-
38 to both the AV connector and EVF. ing audio and recording pilot signals. The recording
I level is adjusted by RT215 (REC CHROMA LEVEL).
I 1-2-3. During Playback
I 2-1-2. Mixer
PB
I (1) Luma Signal
r-
1sw1
1
.1;
1------., ·
!~2 1 5
____ .JI The playback luma signal (PB LUMA) is supplied through
SW2 (PB), clamping circuit, information mixer, pins 28
This mixes 1he recording luma signal with the recording
chroma/audio/pilot signal to generate the composite
1rn, 1
_..o''!....--1---1-----------------' and 30 and clamping circuit to the luma/chroma mixer video signal.
1c211
~~L~lT !PB l_J rti-· • l
-.....,-,:..1
to generate the composite video signal. The composite 2·1-3. Recording Amplifier (0245, Q243: AMP)

L-H+-"
;--------~-----------,
15
. I~~ I video signal is supplied through SW15 (PB/S-AEC},
m ~ ;tc801 -~ .: This amplifies the recording signal and supplies it to a
~PB EVF AV video amplifier and pin 38 to both the AV connector and transformer (CP206) which transfers the signal to its
I ~~£~~ j CONNECTOR
EVF in the same way as in camera recording.
BLANK 132. secondary side. On the secondary side, a positive signal
(2) Chroma Signal . Is generated at pin 4 and a negative signal is generated
The playback chroma signal (PB CHROMA) is supplied at pin 6. The positive signal and the negative signal are
through a muting circuit (MUTE), playback killer (PB supplied to both IC21 Oand IC209. A playback switch
KILLER) and pin 38 to pin 3 of IC211.
(0234: PB SW) connected to the input of the amplifier
During playback, the Pe· signal goes "Hi", and the
turns on and mutes the recording signal during play.
playback chroma signal at pin 3 is selected by SW1 and
supplied through SW2 and pin 7 to the luma/chroma .
mixer in IC201.
Fig. 5-1 _. Vide_o. Sfgna!lnputtputput Circuits

5-1 5-2
TF"STT"'...F"-WT7TT- HllliF 1··-··---··· .. ·-·-····- ·-· ----·- --·· -- - -··- ·--·· . -·-· . ----- --- -- PCT -· ··1 -···--- ·--·-1···--- . ····- WW. -TTil 2 - CT W f'E?TE??P? r=F7E LE ii rmrn•·=
 2·1-4. Recording Amplifiers (IC210: CH1 REC AMP,
IC209: CH2 REC.AMP)
These amplify the CH1 and CH2 recording signals and
supply them to the CH1 and CH2 head independently.
2·2. Playback Operation
2·2-1. Preamplifiers (IC206: CH1 PREAMP, IC207:
CH2 PREAMP)
The signals reproduced from the CH1 and CH2 heads
are amplified independently by the preamplifiers (PRE)
and supplied to continuous signal generation switches
which are controlled by the SW30Hz signal supplied to
pin 8.
2-2-2. Continuous Signal Generation Switches in
IC206 and IC207
These switches tum on when the input is open and turn
off when the Input go "Lo" or "Hi". Therefore, the signals
are generated from pins 7 and 6 of IC206 when the
SW30Hz signal goes "Lo" and the signals are generated
from pins 7and 6 of IC207 when the SW30Hz signal goes
"Hi".
2-2-3. Mixer (0228)
This mixes two signals, positive signal from pins 7 of
IC206 and IC207 and negative signalfrom pins 6 of IC206
and IC207, and generates a playback signal (PB SIG-
NAL).

5V3
TP215
REC LUMA
(0236)

REC CHROMA
(0219)

REC AUDIO/
REC PILOT

PS SIGNAL
(0229)

PRE CONT.
(1C901-8)
0246
!NV

Fig. 5-2 Record Amplifiers!Preamplifiers

3. LUMINANCE SIGNAL PROCESSING
CIRCUITS (Figs. 5-3 to 5-8)
3-1. Luminance Signal Recording Circuit
(Figs. 5-3 to 5-8)
The luma signal from the camera is supplied to pin 34 of
the luma signal processing circuit {IC201: LUMA
PROCESS) and the video signal from the AV connector
is supplied to pin 32.
3-1-1. Input Signal Selection Switch (SW1)
This selects the camera luma signal or the AV IN video
signal. SW1 is controlled by the output of a mode detec-
tor {MODE DET) which inputs 24-bit serial data from a
system control main microprocessor {IC901 : M-µ.P) and
changes switches in the IC.
During camera: Camera luma signal,
During AV IN: AV IN video signal
3-1-2. Input Signal Selection Switch (SW2)
This selects the signal that has been gain controlled by
the AGC circuit or not as follows.
During camera recording: SW2 is set to the "AGC
OFF" position, and the luma signal that has
not been gain controlled is selected,
During AV IN recording: .SW2 ls set to the "REC"
position, and the video signal that has been
gain controlled is selected

..
z~ '"'""""'~"'E""'"Z-7
5-3
77 .. .. . . ,. . . . . . . -,,.,----.. . ______,__ ,_._. ._.,~---"" ·~-~----·-·-··-.~•••
Jiiiii"J~-,. ~···-.·, ,,~·-·---~··"~"··-- ·~---,·~,-. ~~,.,~ ,,.~, ~, ···•11<••·•1••---------·;m"·. ..•
- .•·~~.-.........,. - - - - - - - - - - - - - - -..•••·..... ~ -.liiiPFii?dfP--:-iii'lililll
 TP220
33 _ _ _ _ _
I!!
--,
. I
CAMERA

61
-,
I
I
I
I
I
r--t-t--i-~__._~~~~~~~~~~~~~__,I
_ _ _J

'0--t----<r~-..__REC LUMA
<RTZOI>

CORRE. 1-<.>--""-,6~3~~MA

NOR
I
-,SWIO
I

~0--~

IC201
LUMA PROCESS

C.S'fNC

- -.,
CAM~ER~ 1:N . I
t----------<)"•o=-~~~;,HROMA
REC CHROMA
IQl.2311 OQ02

!C211
,---- ..., q

TP210
INPUT I HiS,.~6-t" I
SELECT
I I 32 I Slo'30Hz

I LoL _J L ~ _ _ .:_ :i!!---9-e-

« I

SW7

IC202
CHROMA
PROCESS

38

P8
L-----'------------ 31- 37- - --,

BLANK
~c~~~~~~1-~-<>---~;.;..;:;.i.;.;_...;...;,;-+---,___,
Q23Q I
IN\/ o------' +
BF
uc2oz-ze1
+I!!- 4!!-

5111

Fig. 5-3 Video Signal Processing Circuit

5-4 5-5
·-n:&aii · LI I ·rnrw--rwma
 3-1-3. Video AGC Circuit (VIDEO AGC)
This consists of the AGC amplifier (VIDEO AGC), AGC
detector (AGC DET), clamping circuit (CLAMP), sync
separator (SYNC SEPA.) and key pulse generator, and
controls the output level making It constant regardless
of variations in the input level.
(1) AGC Detector (AGC DET) - ·
This adds the KEY pulsetothe.clamped video signal. The
AGC detector detects the level difference between the
peak values of the KEY pulse and sync tip t0- generate
an AGC voltage 01.AGC). The AGC voltage acts on the . This··corrects the delay_ time characteristics of the
AGC amplifier so that the output level of tfie video signal .
is fixed. · relative delay time characteristics w~h' respect _to tl'!e ..
(2) Clamping Circuit (CLAMP)
This fixes the DC voltage of the signal. The output is sup-
plied to the AGC detector, syrlc.separator and informa-
tion mixer (INFOS MIX). The outpl,Jt is also supplied to
SW13 through different paths in camera recording or AV .
IN recording.
(3) Sync Separator (SVNC SEPA.)
This separates the sync signal from the luma or video
signal. The sync signal is supplied to the key pulse gen-
erator and is also output at pin 25.
(4) Key P~lse·Generato~ (~EV GEN)
This delays the horizontal sync signal (H.SYNC) supplied
from the sync separator to create the KEY pulse at afixed
level (100% white level).
- This consists of the sub preemphasis circuit and a main
3-1-4. During Camera Recording
The signal selection switches (SWS, SW11, SW13 and
SW15) are set to the "$-REC" positions. The camera
luma signal is supplied through SW11 to the equalizer.
Equalizer (EQ)
This equalizes a dfelay time characteristics of the inter-
output of SW13 is supplied through pin 7 to the 6.0MHz .
lowpass filter. The 3.58MHz trap. (CP209: 3;saMHz · ·
TRAP) connected to pin 7 attenuates :the luma signal
components at the chroma signal band during record-
. ing. -.. . .. . . . .. . . preemphasis in the conventional VHS system.
· 3-1-6. · 6•. oMHz Lowpass Filter (CP201 :'6.0MHzl.PF)
This limits the bandwidth the Ium.a signal below than ·
.6.0MHz: ..
_3-M. Delay Equalizer (CP201: 1sons DELAY)
·6.0MHz lowpass tilter to prevent ringing~ corrects the
chroma signal. The output is supplied through:a buffer
. (0206 to 0208, 0247, 0248: BUF) which works as the
buffer during recordin·g to the input signal s.election cir-
·cult.
3-1-8. Input.Signal Selection Circuit (IC203: INPUT
SELECT) . . ..
This selects the signal supplied to pin 1 during. record-·
of
Ing and supplies It to amplifier (AMP), the gain which
. is selected by SW2, however-In this :model, gain _control
input (pin 2) is grounded, therefore the amplifier works
as a buffer. The output is supplied through. a clamping
circuit (CLAMP) to the sub preemphasis circuit.
3-1~9~ Preemphasis Circuit (PREEMPHA., Fig. 5-4)
preemphasis circuit. As high frequency components are
suscepti.ble to noise, they are preemphasized before
being recorded. During play, high.frequency comonents
are attei:iuat~ by the reverse characteristics to those in
recording.to improve the S/N.
(1} ~ub Preemphasis Circuit (SUB PREEMPHA.} 3-1-11. Frequency Modulator Controls (RT129 to
·. This provides ·non-line~r _emphasis, th.e emph~sis of RT'131)
' which is Increased asJhe input level is lower and the fre- 'the deviation of the frequency mOdulator is .~ontrolled
. quency is higher, which is the same as the dynamic to 1.2MH2 by RT129 (DEV. Fo ADJ) ;and the carrier fre-
quency is contro!le<I to 4.2MHz by RT130 (Fo ADJ) .
(2) Main_ Preemphasis Circuit {MAIN PREEMPHA.)
3-1-12. Frequency Modulator (FM MOD, Fig. 5-6)
This applies fixed emphasis which emphasizes high fre- This changes the oscillation frequency according to the
quency components regardless of the input signal. The ..
DC level of the input signal and frequency modulates the
overall .characteristics of the preemphasis Circuit are luma signal;- applying carrier interleaving as follow.
shown in. th_e· Fig. 5-4. The output
is supplied through .
Sync tip: 4.2MHz, ·
a
~W16 (REC) to dark/white clipping Circuit.
White peak: SAMHz
a-:Mo. Darkiwhite Clipping Circuit (D/W CLIP, Fig. Carrier Interleaving
5-5) . . The frequency modulator uses the SW30Hz signal input
.As the preemphasized luma signal has its high frequen- to pin 51 to offset the FM carrier frequency for every field
cy components empJiasized, it has large shoot com-
. ponents (overshoots and undershoots) at its leading and
(raising the CH1 carrier frequency by 1/2fH), thus pre-
venting beat interference from the adjacent tracks during
trailing edges. If the signal with large shoot components play.
-were to be simply frequency modulated, over-modula-
. tionwould occur and result in black-and-white inversion
during playback. To preventthis, the dark/white clipping
\I/HITE PEAK
circuit clips shoot components with a level higher than
specified.
White clip: 220%,
-----r --- - - -----
Dark clip: 100%,
The white clipping circuit clips overshoots and the dark
.. clipping circuit clips undershoots. The output is supplied
· to the frequency modulator through pin 57, frequency
4.2 5.4 (MHz l
modulator controls and pin 54.
MODULATION FREQUENCY
OVERSHOOT Fig. 5-6 FM Modulation
r·-----1-~--- -----·::~-E-::~~-~-11/HITE CLIP LEVEL
3-1-13. Limiter (LIMIT)

lt·---
16.
nal lowpass filter. The output is supplied through SW12 ,. 2 This limits the amplitude of the FM luma signal and sup-
(NOR) to SW13 ($-REC),. . . . - -· . . - . .. I
plies it to the recording equalizer through SW18 (REC)
3-1-5. During AV IN Recording
In the AV IN recording mode, the output of the clamping ~
14

12

10
'.
~
v -20d8

100%
ff x
SYNC TIP
and pin 43.
3-1-14. Recording Equalizer (0242: REC EQ, Fig. 5-
m
circuit is supplied through SW3, dropout compensation . ·~ l- -IOdB J.. _____ ---------------- ------ ----DARK CLIP LEVEL 7)
switch (SW4) which Is fixed to the "NOR" position.during z
<i vr v-1 The luma signalis trapped before being supplied to the
recording, to SWS (REC/PB).
(1) Mode Switch. (SW5)
.<:>
4
Ivr i-- -3d8
UNDERSHOOT

Fig. 5-5 Dark/Wf1ite Clip

recording equalizer.
(1) Trap
This selects the AV IN video signal in AV IN recording
_£ H
The lower sideband of the frequency modulated luma
and the C.SYNC signal In camera recording; and sup- 0
~ signal is expanded to low frequencies. If the signal is
IOK IOOK IM IOM.
plies it to a mixer 1. · ·· · TP201
FAEGUENCY(Hz).
(2) Mixer 1 (MIX1)
This does not work in AV IN recording and the signal is SU8(t)YNAM!C)

simply passecj through the circuit. · .. _

The AV IN video signal is supplied to t~e 1H delay circuit - · 251-,__1I++-lct+H1C--!---t--t-Hi+lt---t-++-t-H-t+ll- -29d8 : -
and mixers in the comb.filter. The video signal supplied .
to the comb filter Js:,separated into the luma slg11aLand 01-+-++1+!++!--+-H-+w1t-V1~r:--1+--+_+H-ttt-
~ ~-
- scta 1
. IC3eo
chroma signal. The luma signal frorri the mixer 2 (MIX2)
is supplied through SW11 (REC), equalize.r (EQ), SW12 .
iii".
~.
15
II
, -l/U1• 111.'--t-1-1-i-H+f~ -. IOdB

. vj;1 r-- ·h I- - 6d8 I

5VI

and mixer 4 (MIX4) to SW13 (REC) and the chroma sig- ~ 101---+-+++++H+--+.,_, /;yfl'f~+l1H+H---+-4;H-++H+!t---- 3d 8 ~E~ 1 ~1LOT ' - - ; i - - - - - - +
nal from the mixer 3 (MlX3) is supplied to the chroma sig-
nal processing circuit (IC202: CHROMA PROCESS) I JI:
through SW7 (CORRE.), 3.58MHz bandpass filter
(3.58MHz BPF) and pin:.13. The.chroma signaUs also.
l .
v
_QL...-c~~.u.LJ.JJ-~_-_u_..u..w.ll--_~_-'-'.J...LJ.~
C
REC CHROMA
!C202-40l
L216
Q216
MIX
r---~--------t TP213
10~ IOOK IM IOM
supplied to SW9 (REC). (See "3-2-1 O. Mixer, Dropout
Compensation Circuit, Comb Filter and Vertical Correla-
tion Detector'' for details on the signal separation). Th~.
. FAEOUENCl'(Hz)
OVERALL
h RT215
REC CHROMA
LEVEL

Fig. 5-4 Characteristics of Preempha~ls Fig. 5-7 Recording Equalizer

5-6 5-7
 recorded without any processing, it would interfere with
the FM audio signal (1.5MHz ± 100kHz) and the down-
converted chroma signal (743kHz ±500kHz). To
prevent this, the 1.5MHz trap composed of l204 and
C208 attenuates the frequency components at around
1.5MHz and the 743kHz trap composed of l205 and
C380 attenuates the frequency components at around
743kHz. The output is supplied to recording equalizer
through RT201 (REC LUMA LEVEL) which adjusts the
recording FM luma signal level.
(2) Recording Equalizer (0242: REC EQ)
This matches the characteristics of the recording FM
luma signal to an optimum value. The output is supplied
through a buffer (0236: BUF) to a mixer which mixes the
luma signal with the recording pilot, audio and chroma
signals. The recording signal is amplified by amplifier
(0245, 0234: AMP) and supplied to CP206. The input of
the amplifier is muted by a switch (0234: PB MUTE)
during playback.
3-2. Luminance Signal Playback Circuit
(Figs. 5·8 and 5·3)
The playback signal from a buffer (0229) is supplied to
a playback equalizer..
3-2-1. Playback Equalizer (Fig. 5-8)
The playback signal is first supplied to traps.
(1) Traps (L233 to l235, C351 to C353, L217, C360)
There are four traps which eliminate the pilot, audio sig-
nals and high frequency components higher than ap-
prox. 11 MHz and extract only the luma ·and chroma
signals.
The output is branched into two through a buffer (0230:
BUF). Fart is supplied through the trap composed of
L236 and C354 which attenuates the down-converted
chroma signal (743kHz ±SOOkHz). The other part is
supplied to the lowpass filter composed of L218, l219,
C291 to C293 and C387, which attenuates the luma sig-
nal higherthan approx. 1.3MHz.
(2) Playback Equalizer (Q231: PB EQ)
The high frequency components of the playback signal
from the preamplifier are attenuated due to the charac-
teristics of the heads, playback loss, etc. The playback
equalizer corrects this. It raises the high frequency com-
ponents of the FM lurna signal to flatten the overall fre-
quency response.
PB CHROMA -
(!C202-42l
Fig.·5-8 Playback Equalizer·
(3) Phase Compensator (Q232: PHASE EQ)
This corrects the phase distortion to reduce distortion of
the waveform during demodulation. Phase distortion
occurs with the luma signal the amplitude characteris~
tics of which are· equalized by the playback equalizer.
The output is supplied through a buffer (0233: BUF) and
pin 41 to the FM AGC circuit in IC201. ,
3-2-2. FM AG'C Circuit (FM AGC, Fig. 5-3)
This corrects any deviation in video head playback out-
put between the channels and variations In level to con~
trol the output level so it is constant.
The output is branched into ti.No. ·Part. is through SW18
(PB), pin 43 and amplifier (0201: AMP) to a limiter. The
other part is supplied to the dropout detector (DO DET).
3-2-3. Limiter (0201: LIM1n
This limitsthe amplitude variations in the FM luma signal
and supplies it to the double limiter through a buffer
(0202: BUF) and pin 45.
3-2-4. Double Limiter (DOUBLE LIMIT)
As the recording wavelength is .short in high density
recording and much preemphasis is applied, the lower
sideband level becomes higher than the FM carrier level.
If this signal is simply demodulated, black. and white
would be inverted. The double limiter therefore suppres·
ses lower sidebands.
3-2-5. Frequency Demodulator (FM DEMOD)
This voltage converts the FM input signal to demodulate
It into a luma signal.
3-2-6. Lowpass Filter (LPF)
This limits the bandwidth of the playback I uma signal and
supplies it to the phase compensation circuit through pin
47 and a buffer (0203: BUF).
3-2-7. Phase Compensation Circuit (0204: PHASE
EQ)
This corrects the phase distortion occurred by lowpass
filter. The output is amplified by an amplifier (0205; 0241,
0249, 0250: AMP), the gain of which is controlled .by
RT133 (PB LUMA LEVEL A). The output is supplied
through pin 50 and SW17 (PB) to a main deemphasis cir-
cuit.
3-2-8. Main Deemphasis Circuit (MAIN DEEMPHA.)
This has the opposite characteristics to the main preem-
phasis circuit in recording. It attenuates ~igh frequency
5VI
I
i
·····ya lilf "~
. . .... Ttfiffltrz?j
 components emphasized during recording to improve
the S/N.
3-2-9. Sub Deemphasis Circuit (SUB DEEMPHA.)
This Is switched to the reverse characteristics tO those in
recording. It attenuates the low level and high frequen-
cy components that were· emphasized through the
preemphasis operation to improve the SIN. The output
is supplied through SW3 (PB) to SW4 (NOR).
3-2-10. Mixer, Dropout Compensation Circuit,
Comb Filter (COMB FILTER) and Vertical
Correlation Detector (CORRELATION DET)
These circuits use the 1H. delay signal generated by the
CCD 1H delay circuit concurrently to perform each
process.·
(1) Mixer 1 (MIX1)
This mixes the C.SYNC signal with the camera chroma
signal in camera recording and simply passes the AV IN
video signal in AV IN recording. This also mixes the luma
signal with the chroma signal during playback. The out-
put is branched into two. Part is supplied through pin 21
to the CCD 1H delay circuit. The other is supplied to the
mixers in the comb filter.
(2) 1H Delayed Signal Generation Circuit
This uses the CCD 1H delay circuitwlth the 4fsc signal
to delay the video or luma signal accurately by '1 HIn the
baseband.
1) CCD 1H Delay Circuit (IC204: CCD 1H DELAY)
!C204 is activated when the PRE.CONT. signal goes "Hi"
or when the CAMERA ON signal goes "Lo". That is,
IC204 works only in AV IN recording and playback.
The luma or video signal from the mixer 1 is supplied
through pin 21 to IC204 and is delayed by 1H. The Clock
pulse for the CCD 1H delay circuit is the 4fsc signal which
is obtained by multiplying the fsc signal (3.58M Hz) sup-
plied from IC202 by 4 using the clock generator (CLOCK
GEN) in the IC.
2) 5.5MHz Lowpass Filter (CP202: 5.5MHz LPF)
This eliminates the clock frequency components remain-
ing In the 1H delayed signal.
3) Phase Equalizer (0211, 0212: PHASE EQ)
This corrects the phase distortion that occur due to
CP202. RT123 (COMB FILTER PHASE) control the
phase of the 1H delayed signal.
The output is branched into two. Part is supplied through
pin 17 to an amplifier (AMP) and amplified. The
amplified 1Hdelayed signal is trapped by the fsc trap (fsc
TRAP) which eliminates the 3.58MHz chroma signal
components and extracts the luma signal components.
The luma signal is then clamped and supplied through
SW6 to SW4 (DO) for dropout compensation. The other
part is supplied through pin 19 to an amplifier (AMP) and
amplified. RT125 (COMB FILTER GAIN2) connected to
the amplifier via pin 20 control the level of the 1H delayed
signal to match it with that of the non-delayed signal for
the comb filter. The output is supplied to the comb filter.
(3) Dropout Compensation Circl!it
This detects dropout of signals originating from
scratched tape, uneven magnetic coating, dust, etc. and
replaces dropout with the signal that occurs 1H before.
The dropout compensation circuit consists of the
5.,.9
zrm
dropout detector (DO DET) and SW4. .The dropout
detector receives the frequency modulated luma signal,
detects dropout of the signal and generates the DO pulse
until the dropout is recovered to supply it to SW4. SW4
is normally set to "NOR" and the playback iuma· signal
simply J)asses through the circuit. When dropout oc-
curs, the dropout detector outputs the DO pulses during
the dropout period and SW4 is set to "DO". Therefore;
dropout of the luma signalis replaced with the playback
signal that occurs 1H before.
(4) Comb Filter (COMB FILTER)
With the NTSC color TV signal, the chroma signal is fre-
quency interleaved with· the luma signal and is trans-
mitted together, therefore, the high frequency
components of the luma signal and the chroma signal
interfere with each other, causing dot interference and
cross color interference. To realize high resolution, only
the chroma signal must be attenuated without attenuat-
ing the high frequency components of the luma signal,
and to prevent cross color interference, luma compo-
nents must not remain In the chroma signal. The ener-
gy distributions of the luma_ and chroma signals
composing the NTSC composite video signal are inter-
leaved as follows.
Luma signal: Integral multiples of fH,
Chroma signal: Odd multiples of fH/2
The chroma signal (chroma subcarrier: fsc) is set as fol-
lows.
fsc = 455 x fH/2-
The fsc signal is. set to an odd multiple of fH/2. This
means that only the phase of the fsc signal is inverted
every scanning line. With this principle, when an original
signal and the signal that has passed through the 1H
delay circuit are added, only the chroma components
with phase reversed every H are canceled, and when the
delayed signal is subtracted from the original signal, only
the luma components with the same phase every H are
canceled. This consists of the addere, subtracters, fsc
traps.
The signal paths and operations are different depending
on the mode.
1) During Camera Recording
Luma Signal
The camera luma signal is directly .supplied to CP201
through SW11 (S-REC),equalizer,SW12, SW13 (S-REC)
and pin 7.
Chroma Signal
The camera chroma signal at pin 32 of IC202 is supplied
through pin 5 to the mixer 1. As SW5 is set to the "S-
REC" position, the C.SYNC signal is mixed with the
camera chroma signal.
This signal is only supplied to pin 30 of IC202 through
SW7 (REC-NO CORRE.), 3.SBMHz bandpass filter and
pin 13.
2) During AV IN Recording
The luma signal and the chroma signal are separated
from the AV IN video signal.
' AV IN Luma Signal
The AV IN luma signal is obtained by adding the original
signal and 1Hdelayed signal. The AV IN luma signal with
the odd multiple components of fH attenuated
-wrnz ··--··~ · ·-· · - - - - --- ·-· -· -
throughout the bandwidth Is supplied to a mixer 4 (MIX4)
through sw11 (REC} equalizer and SW12. The mixer 4
I
inputs two signals, luma signal and chroma signal with
the chroma signal band has been attenuated, mixes two
signals and generates the AV IN luma signal with the
chroma signal components at the chroma signal band
has been attenuated.
.4Y IN Chroma Signal
The AV IN chroma signal is obtained by subtracting the
1H delayed signal from the original (non-delayed) signal.
The AV IN chroma signal with the Integer multiple com-
ponents of fH attenuated throughout the bandwidth is
branched into two. Part is supplied to pin 30 of IC202
through SW7 (CORRE.), 3.58MHz bandpass filter which
limits the bandwidth of 3.58MHz ± SOOkHz and pin 13 if
the non-delayed and 1Hdelayed signals has vertical cor-
relation. If there is no correlation, SW7 is changed to the
"REC-NO CORRE." position, and the AV IN video signal
is passed through SW7 (REC-NO CORRE.) and supplied
to the 3.58MHz bandpass filter which extracts the
chroma signal by removing the luma signal. The other
part is supplied through ·SW9 (REC) and fsc trap (fsc
TRAP) which attenuates the chroma signal at the chroma
signal band, to the mixer 4.
3) During Playback
Luma Signal
The played back luma signal from the sub deemphasis
circuit is branched into three through SW3 (PB) and SW4
(NOR). Part is supplied to the CCD 1H delay circuit for
dropout compensation through the mixer 1 which mixes
the playback chroma signal. The second is supplied to
a mixer 5 (MIX5) through SW10 (NOR), SW11 (PB),
equalizer and SW12 (NOR). The third is supplied to a
mixer 6 (MIX6) which subtracts the 1Hdelayed video sig-
nal from the non-delayed luma signal. The output is the
chroma signal and is supplied through SW9 (PB) to the
fsc trap which attenuates the chroma signal compo-
nents atthe chroma signal band and extracts the chroma
signal components without the chroma signal band. The
output Is then limited, attenuated and. supplied to the
. mixer 5. At the mixer 5, the chroma signal components
without the chroma signal band is subtracted from the
non-delayed luma signal, and the luma signal with the
chroma signal components attenuated is obtained. The
playback luma signal is supplied through SW13 (PB) and
pin 7toCP201. The playback video signal from the mixer
1 is also supplied to the mixer 2 which adds the non-
delayed and 1H delayed video signal and generates the
luma slgnal with the crosstalk components of the chroma
signal. This luma signal Is then supplied through SWS
which is fixed to the "EDIT (Lo)" position and pin 11 to
IC202.
Chroma Sfwial
The played back chroma signal at pin 32 of IC202 is sup-
plied through pin 5 and mixer 1which mixes the playback
luma signal, to the mixer 3 and CCD 1H delay circuit.
The mb(ar 3 subtracts the i H delayed video signai from
the non-delayed video signal and generates only the
chroma signal. This playback chroma signal is supplied
through SW7 which is fD<ed to the "CORRE." position in
k playback, 3.58MHz bandpass filter and pin 13 to IC202.
~
I
#·1... __,._ ;=;=·-··-.. . . ,.- · - ·1--illii\o ... --
(5) Vertical Cooelation Detector (CORRELATION
DET)
This holds the differences of the amplitudes of the
original signal and 1H delayed signal, and when there is
more than a specified difference in the ampmude, it
judges no correlation and outputs "Lo" at pin 9. The no
correlation pulse (Lo) is also supplied to SW7.
3-2-11. 6.0MHz L<>wpass Filter (CP201: 6.0MHz LPF)
The application is the same as in recording.
3-2-12. Delay Equalizer (CP207: 180ns DEU\Y)
The application is the same as in recording.
3-2-13. Phase Eq1Jalizer (Q206 to 0208, Q247,
0248: PHASE EQ)
This is activated by the "Hi" PB signal during playback
and it corrects the phase distortion.
3-2-14. Input Signal Selection Circuit (IC203: INPUT
SELECT}
As SW1 in the IC is set to the "Hi" position by "Hi" PB sig-
nal supplied to pin 6, the input signal supplied to pin 4 Is
selected. RT135 (PB LUMA LEVEL2) connected to pin
4 adjust the output luma signal level to 1.0Vp-p at the
output terminal. The output Is supplied through the
amplifier which works as"the amplifier (6dB) as pir:i 5 is
connected to the 5V1 power source and pin 7 to the
clamping circuit and a noise canceler.
3-2-15. Noise Canceler (NOISE CANCEL)
This eliminates high frequency noise components in the
playback luma signal to improve the S/N. This inputs the
luma signal from the clamping circuit as the main signal
and luma signal through highpass filters from pins 1 and
2. The luma signal at pin 1 is subtracted from the luma
signal at pin 2 and the noise components are extracted.
These noise components are then subtracted from the
luma signal supplied from the clamping circuit. As a
result, high frequency noise components are eliminated.
The output Is supplied through SW2 and clamping cir-
cuit to the output circuit. (See "1. VIDEO SIGNAL
INPUT/OUTPUT Cl RCUITS" for the operations of the out-
put circuit.) ·
4. CHROMINANCE SIGNAL PROCESSING
CIRCUITS (Figs. 5-3 and 5-7 to 5·9)
4..1. Chromina11ce Signal Recording
Circuit (Figs. 5-3, 5·7 and 5-9)
The camera chroma signal from 01231 is supplied
through pin 44 of the chroma signal processing circuit
(IC202: CHROMA PROCESS) to an input selection
switch (SW6).
4-1-1. Input Signal Selection Switch (SWS)
This selects the input signal by the CAMERA ON or AV
IN (Lo) signal supplied to pin 29 through the OR gate
(0902).
Hi: Camera chroma signal is selected,
Lo: AV IN chroma signal Is selected
The camera chroma signal is output at pin 32 and sup-
plied through pin 5 to the comb filter in IC201. The
.... -····- •..... ··- -·- - ···-----~ ... ·-· ··-~ ~ T . ·a:razzc=n
5-10
 camera chroma signal or the AV IN chroma signal that
is extracted by the comb filter from the AV IN video sig-
nal, generated at pin ·13 is supplied through pin 30,
amplifier (4dB), input signal selection switch (SW1)
which is fixed to the "Lo" position as pin 39 is grounded,
and SW2 to the ACC circuit.
4-1-2. ACC Circuit (ACC)
This consists of the ACC amplifier and ACC detector
(ACC DET) and controls the burst level of the recording
chroma signal so it is .constant regardless of the input
signal level. it extracts the burst signal from the chroma
signal, timed by the burst gate (BG) pulse, detects the
burst signal level, and controls the gain of the ACC
amplifier to keep the burst level constant.
(1) Horizontal Sync Signal Gate Circuit (1/21H IN-
HIBln
This extracts the fH pulse from the C.SYNC signal sup-
plied from the sync separator in IC201 by removing
equalization pulses.
{:2) Burst Gate Pulse Generator (BG GEN)
The fH pulse· triggers a monostable multivibrator to
generate a BG pulse synchronized with the burst signal.
- bandpass filter.
f\
~ I/
i-i-..1\
~
1--
0
-600
+-+---
+- .......
-100
Fig. 5-9 Characteristics of Chroma Preemphasis
4-1-4. Burst Preemphasis Circuit (BURST PREEM-
PHA.)
Tl1is emphasizes the burst signal by 6dB when the BG
pulse is supplied to reduce color irregularities and noise
during recording and playback.
4-1-5. Recording Balanced Modulator (REC BAL.
MOD)
This down-converts the 3.58M Hz chroma signal with the
aid of a 4.32MHz subcarrier signal supplied from the
pllase inverter (PHASE INVERT). The following chroma
bandpass filter removes the sum components
(3.58MHz + 4.32MHz = 7.90MHz) from the output to ex-
tract the down-converted chroma signal (4.32MHz-
3.58MHz = 743kHz).
4-1-6. Record Killer (REC KILLER)
This is controlled by the KILLER signal generated by the
color killer detector~ When "Hi" is supplied, the output is
inhibited and when "Lo" is supplied, a down-converted
chroma signal is generated.
C<>lor Killer Detector (KILLER DET)
When chroma signal components enter the luma signal,
color noise occurs. The color killer detector us·es the BG
5;..11
iiiiiii"''"$"""~77"""1i1 f'" . ra-~s·wv·-····""'···,············· ..., "'~"'"''W•-·"'l'"''""~~-•.~,--,···-~·~·"""· ·~·-......,,,,_.
4-1-3. Chroma Preemphasis Circuft (CHROMA
PREEMPHA., Fig. 5-9)
This emphasizes !cw-level sideband components during
recording so that the S/N can be improved when em-
phasized components are deemphasized during play.
The amount of emphasis is varied depending on the
input level and frequency deviation.. Namely, when the
input level is low (high), the amount of emphasis is large
(small) for components having large frequency devia-
tions.· · C293, C387: 1.3MHz LPF, Fig. 5-8)
The chroma emphasis circuit consists of the 3.58MHz
trap (CP205: 3.58MHz TRAP) connected to pin 28, limiter
and an adder. CP205 attenuates the chroma signal as
the frequency deviation is smaller. The attenuated
chroma signal Is supplied through pin 28 and limited.
The adder adds the original chroma signal and the at-
tenuated chroma signal. As a result, the chroma signal
is emphasized as the frequency deviation is greater. The
resonance frequency of the chroma preemphasis is
shifted when the BG pulse is supplied from an inverter
(0239: INV). Also, pin 28 Is grounded by a playback
switch (0240: PB SW) during playback.
V1 t-- -20dB
--} t - -10d8
/
v plied through pin 34 to a mixer.
-10 tO
(3.58MH:z)
+10
y ~
+100
-
+600
FREQUENCV (kH2)
pulse to extract the burst period and 3.58MHz signal
generated by the fsc voltage controlled crystal oscillator
(fsc VCXO), and detects the presence or absence of the
burst signal by synchronous detection. When no burst
signal Is present (a black-and-white signal), it generates
a "Hi" KILLER signal. . (PHASE INVERn. It not only balanced-modulates the
4-1-7. Chroma Bandpass Filter (l216, C284:
CHROMA BPF, Fig~ 5-7)
This removes the sum components· (4'.32MHz +
3.58MHz == 7.90MHz) and extracts only the down-con-.
verted chroma signal (4.32MHz - 3.58MHz = 743kHz).
The 1.6MHz trap (CP210: 1.6MHz TRAP) connected to
the output of the chroma bandpass filter attenuates the
chroma signal at around 1.6MHz which is the audio sig-
nal band. The output is supplied through buffer (0219:
BUF) to a mixer. · · ··
4-1-8. Mixer (0218: MIX)
This mixes the down-converted chroma sigriai with the
recording. pilot/audio signal and also equalizes the
characteristics of the signal. AT215 (REC CHROMA
LEVEL) connected'to the collector of.0218 adjusts the
chroma signal level. · ·
0
•••- - ····-··-·-··""""S7F-
·····-·~· ..
The output of recording chroma, pilot and audio com-
bined signal is then mixed with the luma signal.
4·2. Chrominance Signal Playback Circuit
(Figs. 5-8 and 5·3}
The reproduced video signal from a buffer (0230: BUF)
is supplied to the 1.3MHz lowpass filter.
4-2-1. 1.3MHz Lowpass Filter (L218, L219, C291 to
This eliminates the luma and audio signals higher than
1.3MHz and extracts the chroma signal. The chroma
signal is supplied through a buffer (0265: BU F), pin 42
of IC202 and SW2 to the ACC circuit.
4-2-2. ACC Circuit (ACC)
The application is the same as in recording.
4-2-3. Playback Balanced Modulator (PB BAL. MOD)
This demodulates the down-converted chrorna signal
(743kHz ± 500kHz) to the 3.58MHz chroma signal using
the 4.32MHz subcarrier signal supplied from the phase
inverter.
The output ls supplied through pin 36 to the 3.58MHz
4-2-4. 3.SSMHz Bandpass Filter (CP204: 3.!iSMHz
BPF)
This eliminates the sum components (4.3.2MHz +
743kHz = 5.06MHz) and extracts only the 3.58MHz
chroma signal (3.58MHz ±SOOkHz). The output Is sup-
4-2-5. Feedback Switch and Mixer
(1) Feedback Switch (FEEDBACK SW}
This provld es two channels for two :nput signals supplied
to pins 20 and 21. These switches are controlled by the
correlation pulse generated by the vertical correlation
detector in IC201 and supplied to pin 18. When the cor-
relation pulse goes "Hi" that means there is correlation
the crosstalk components are simply passed through
these circuits. When it goes "Lo", fixed voltages are
generated.
(2) Input Signal Selection Switch (SWS)
This selects the input signals supplied to pins 20 and 21.
However in this model, a control input (pin 25} is
grounded, and the switch is fixed to the "Lo" position and
the crosstalk components supplied to pin 20 are always
selected.
(3) Mixer
This subtracts the crosstalk components from the
original chroma signal to eliminate crosstalk com-
ponents. The output is supplied through SW7, SW5 (Lo)
and pin 32 to the comb filter in IC201.
a 4-2-6. Burst Deemphasis Circuit. (BURST DEEM-
PHA.)
The chroma signal generated by the comb filter in IC201
is supplied through pin 30 and amplifier tc t11e burst
deemphasis circuit which attenuates the burst level,
which has been emphasized by 6cf B during recording,
by 6dB to restore the original level,. timed by tlie BG
pulse.
4-2-7. Chroma Deemphasis Circuit (CHROMA
DEEMPHA.)
This attenuates the sideband components of the chroma
signal which has been emphasized during recording to
~estore ~he original level to improve the S/N. The output
is supplied through SW5 to the muting circuit.
4-2-8. Muting Circuit (MUTE)
This mutes the playback chroma signal when "Hi" BLANK
signal supplied to pin 37 goes "Hi".
4-2-9. Playback Killer (PB KILLER)
The application is the same as the record killer. The out-
put is supplied through pin 38 to the input signal selec-
tion circuit.
4-2-10. Input Signal Selection Circuit (IC211:
INPUT SELECT)
(1) Input Signal Selection Switch {SW1)
!his is controlled by the PB signal supplied to pin 2 and
It selects the playback chroma signal supplied to pin 3
during playback.
(2) Muting Switch (SW2)
This is controlled by the BLANK signal supplied to pin 4.
When the BLANK signal goes "Hi", SW2 is set to the "Hi"
position, and the playback signal is muted and when it
goes "Lo", SW2 is set to the "Lo" position, and the
playback chroma signal Is output at pin 7. The playback
chroma signal is then supplied to the luma/chrorna mixer
in IC201.
5. 47+1/4fH SIGNAL/fsc (3.58MHz) SIGNAL
GENERATORS (Fig. 5-3)
5·1. 47+1/4fH Signal Generator (Fig. 5-3)
5-1-1. During Recording
Th~ 47+1/4fH signal generator is responsible for sup-
plying the 743kHz carrier signal (47+1/4fH) to the
4.32M~z balanced modulator (SUB BAL MOD) during
recording to balanced-modulate the3.58MHz carrier sig-
nal to the 4.32MHz subcarrier signal. The 4.32MHz sub-
carrier signal is phase-inverted in synchronization with
both the fH and SW30Hz signals by the phase inverter
3.58MHz chroma signal to the 743kHz down-converted
chroma signal in the record balanced-modulator but also
Inverts the phase of the chroma signal by every H for
CH2. The phase of tile subcarrier signal is inverted to
eliminate crosstalk interference from adjacent tracks
during p~ay.
The 47+1/4fH signal generator forms a closed loop
together with the 378fH voltage controlled oscillator
(378fH VCO) and 378fH phase comparator (fH PHASE
COMPA.) during recording. This closed circuit
generates the 743kHz carrier signal (47+1/4fH) that is
synchronized with the phase of the fH signal in the luma
or video signal and supplies it to the phase inverter. The
phase inverter inverts the phase of the 743kHz carrier
signal and supplies it to the record balanced-modulator.
The phase comparator compares the phases of the fH
signal and 1/378 divided output signal, generates an
error signal and feeds it back to the 378fH voltage con-
5-12
 trolled oscillator, and the oscillation frequency of the
378fH voltage controlled· oscillator locks tothe phase of
thefH signal. The oscillation output Is divided by the 1/8
divider to the 743kHz signal (47+1/4fH) and is supplied
to the 4.32MHz balanced-modulator.
5-1-2. 4.32MHz Balanced-Modulator (SUB BAL
MOD)
This produces the 4.32MHz carrier signal which is used
to balanced-modulate the 3.58MHz chroma signal to the
743kHz down-converted chroma signal. The 4.32MHz
subcarrler signal is obtained by mixing the 47+1/4fH
{743kHz) signal and the 3.58MHz carrier signal. The dif-
ference components (3.58MHz - 743kHz = 2.87MHz)
are removed by the 4.32MHz bandpass filter (CP203:
4.32MHz BPF} connected between pins 2 and 4.
5-1-3. Phase Inverter (PHASE INVERT)
This inverts the phase of the 743kHz carrier signal every
H for CH2 track to prevent crosstalk interference from
the adjacent tracks during play. The phase inverter
receives two signals, SW30Hz and fH, for this control.
celed by the closed loop, and an accurate 3.58MHz
chroma signal is generated. · (3) Or a conventional flxed head may be used to
5-1-6. Removal of Crosstalk interference from Ad·
jacent Tracks
The phase inverter inverts the phase of the 743kHz down-
converted chroma signal every Hfor the CH2 during play
in the opposite way to recording, returning to the original
phase. Therefore, the down-converted chroma signal is
demodulated to the 3.58MHz chroma signal and the
phase is also returned to the original. As a result, the
main signal component in the playback chroma signal is
returned to the state where it has the same phase every
H in the same way as the signal before being recorded,
but the crosstalk components from the adjacent tracks
have the phase with 180° opposite every H. This signal
is supplied to the comb filter in the subsequent stage
which eliminates only the crosstalk components. There-
fore, the main signal components are simply output, but
the crosstalk components cancel each other out.
5-2. fsc (3.58MHz) Signal Generator (Fig.
record the audio signal near t.he edge of the tape.
However, this unit employs the first method: multiplex-
ing the FM audio signal with the video heads (called
FM audio signal recording).
The FM audio signal recording system provides one
channel of monaural sound. The FM carrier frequency
is 1.5MHz and frequency deviation is ± 1OOkHz.
A noise reduction system is provided like that in a Hi-Fi
VCR. It is 2-to-1 compression-expansion type noise
reduction which is basically the same as that in VHS Hi-
Fi. The audio signal is compressed to 1/2 (in decibels)
during recording and expanded two times during
playback. At the same time, fixed emphasis is applied
to reduce high frequency noise.
REC/PB
INPUT
~-----T--. REc ouTPVT
_ ___...,,...
PB
2. AUDIO SIGNAL INPUT/OUTPUT
CIRCUITS (Fig. 6-2)
2-1. Input Circuit
The audio signal from a built-in microphone (MIC) is sup-
plied through a buffer (0001: BUF), highpass filter (HPF),
buffer (0002: BUF), microphone amplifier (IC001: MIC
AMP) and pin 1 to an input signal selection switch (SW1)
in an audio signal processing circuit (IC401: AUDIO
PROCESS).
2-1-1. Microphone Switch (SW001: MIC)
This reduces wind noise (low frequency components of
several hundred Hz) from the microphone. When
SW001 is set to the "WIND" position, the highpass filter
is activated.
2-1-2. Input Signal Selection Switch (SW1)
This selects the input signals depending on the leve: of
the signal input to pin 6 as follows.
CAMERA ON signal "Hi": Microphone signal is

5-1-4. During Playback 5-3) 75u selected,

The 47+1/4fH signal generator is responsible for not
only supplying the 4.32MHz carrier signal to the
playback balanced-modulator to turn the 743kHz down-
converted chroma signal to the 3.58MHz chroma signal
but also for removing time base errors of the chroma sig-
nal during playback. The phase of this 4.32MHz subcar-
rier signal is shifted in the opposite way to recording in
synchronization with the SW30Hz and fH signals. The
4.32MHz subcarrier signal inverts the phase of the
chroma signal every H for CH2 track, thus returning to
the original phase. Through this phase inversion, the
crosstalk interference from the adjacent tracks can be
eliminated by the comb filter in the subsequent stage.
5-1-5. Removal of Time Base Errors
5-2-1. During Recording ~ 19u
CAMERA ON signal "Lo": External audio signal sup-
plied from the AV connector is
EMPHASIS (1)
A closed loop Is formed by the 3.58MHz voltage control- selected
led crystal oscillator (3.58MHz VCXO) and record phase
comparator (REC PHASE COMPA.) and the. oscillation 2-2. Output Circuit
frequency of the 3.58MHz voltage controlled crystal os-
cillator Is locked to the burst signal in the chroma signal.
PB OUTPUT This supplies the EE or reproduced audio signal to the
earphone jack (JK001 : EAR) or the AV connector. To
The record phase comparator receives two signals, the
burst signal in the chroma signal and the 3.58MHz car- monitor the audio signal through the AV connector, con-
Fig. 6-1 Priciple of the Noise Reduction nect the AV output cable or RF converter to the AV con-
rier, to activate this control.
The record phase comparator compares the phases of nector.
the burst signal in the chroma signal with that of the
3.58MHz carrier signal and generates an error signal that
is fed back to the 3.58MHz voltage controlled crystal os-
0001 0002
cillator so that its oscillation frequency Is locked to be in BUF BUF

The frequency of the playback chroma signal is varied, phase with the burst signal. MIC
REC SIGNAL
affected by jitter, etc. To eliminate such variations, a 5-2-2. During Playback (02.18)
closed loop of 378fH voltage controlled oscillator Is The closed loop is released and the 3.58MHz voltage
formed.to compare the phases of the burst signal in the controlled crystal oscillator becomes a 3.58MHz fixed
playback chroma signal with that of the 3.58MHz carrier crystal oscillator. The accuracy of the oscillation frequen-
signal which is free from frequency variations and trans- cy is that of the cf'Ystal. The output of the 3.58MHz ear-
mit the frequency variations to the 4.32MHz subcarrier rier signal is also supplied to pin 12.
signal.
The playback phase comparator compares the phase of
the burst signal in the playback chroma signal with that
of the 3.58MHz carrier signal and generates an error sig- JOOl
nal that is fed back to the 378fH voltage controlled oscil- EAR
lator, and its oscillation frequency of the 378fH voltage IC901 I
controlled oscillator locks to the phase of the burst sig- ~:.JJ!. __ 1 : MUTE
nal in the playback chroma signal. ·That is, time base CHAPTER 6 AUDIO I I I
error components such .as· jitter, etc. in the playback I MUTE
5
0"-1--------?'~MUTE
chroma signal are transferred to the 378fH signal. 1. GENERAL (Fig. 6-1) I I I
I PB 93 12
9 PB/~B
The playback balanced-modulator balanced-modulates I·
the 743kHz down-converted chroma signal to the
There are three methods of recording audio signals in an l I1 5I
CAMERA o•tJ0'._- - - - 1 ~-----sw1
8mmVCR. . · 1.
1.. ____ _J
I 0905
BUF
3.58MHz chroma signal using the 4.32MHz subcarrler (1) The FM (frequency modulation) audio signal can be FADE
signal that includes time base error components. SVl --«>--'-9--..._..., I
recorded by multiplexing it with the video signal. I I
(4.32MHz+aij-(743kHz+Aij = 3.58MHz (2) PCM (pulse code modulation) audio signal record- L---------------- ---- -------- ·---------J
That is, time base components such as jitter (A~ are can- ing is also possible.
Fig. 6-2 Alldio Signal Processing Circuit

5"'.'13/ 5-1
..
i*"""''"T"'~·"~ --,~1,~M-··7 p-gr-z;M-·-·'-~"····"·""····-~.,,, ......... ~~--·,~~-······-··-~·~·--r~- ·· ~-.~~-·----., . ,. --··------··---~~-=·-M--·-~z·- er
6-2
 Muting Circuits (MUTE) 3-3-2. Limiter (LIMIT) . The video tape is wound around the cylinder by 221° motor, (2) Capstan motor and (3) Loading motor. The
These mute the EE or reproduced audio signal when the This limits the FM. audio signal amplitude before (with a model which enables PCM recording). 180° is for cylinder motor is built into the cylinder and is used ex-
MUTE signal supplied to pin 4 is "Hi". demodulation to.remove AM noise. recording video signals Including ±5° of overlap and 3° clusivelyto drive the cylinder. The capstan motor is used
for allowance and 30° Is for PCM recording. to drive the tape. The loading motor provides torque to
3-3-3. FM Demodulator (FM DEMOD) Since the cylinder diameter is 40 mm and the track width slide the subchassis and is also used as a drive source
3. AUDIO SIGNAL PROCESSING CIRCUITS This is the PLL FM demodulator and the voltage control- is 20.5 microns, the tape speed is 14.345 mm/s which is for loading. Both the take-up and supply reel disks have
(Fig. 6-2) ling the oscillation frequency is taken as the audio out- slower than VHS. The relative speed of the cylinder and slip mechanisms and are driven by torque transmitted
put when the output frequency of the voltage controlled tape is 3.8 m/s. The CH-1 and CH-2 video heads are at- by these slip mechanisms during play and unloading.
3-1. IC401 oscillator is locked at twice the input FM audio signal fre- tached to the cylinder at points 180° apart. The angle of Flexible wires are used to connect the motors and
quency. azimuth for CH-1 Is -1 o• and for CH-2 it is +10° (as seen switches.
IC401 includes recording and playback circuits and they
3-3-4. Hold Amplifier (HOLD AMP) from the front of the heads). The flying erase (FE) head
are selected by the PB signal supplied to pin 12.
This holds ttie signal amplitude before dropout or before is attatched at 90° from the CH-1 head in the direction of
3-2. Recording Circuit head switching, to compensate for the dropout and rotation. The flying erase head has no angle of azimuth.
pre\/ent switching.noise~.The output signal is supplied Fig. 7-1 is a diagram showing the basic locations of the 2. OPERATIONS IN ALL MODES (Figs. 7-2
3-2-1. AGC Circuit through SW2 to the 20kHz lowpass filter. video heads. A tach magnet is attached at 70.5° delayed 10 7·10)
This consists of the AGC amplifier (AGC) and AGC detec- (1) Dropout Detector (DO DET) from the CH-1 head. During recording, the flying erase
tor {AGC DET). The AGC detector detects the mean head first erases two tracks of signals and then video sig- This section describes operations of each part of the
The inputs the FM audio signal, detects the dropout and
value of the input signal and controls the gain of the AGC nals are recorded in the order CH-1 then CH-2. A weight chassis in detail.
generates the dropout pulse with a width of approx. 1ms
amplifier to fix the audio output signal. or less. The dropout pulse is supplied through the OR is attached beside the tach magnet to maintain balance
Fade Function with the flying erase head. 2-1. Diagram Showing Locations of Major
gate to the hold amplifier.
This fades the audio signal in and out, synchronized with (2) Head Switching Detector (HEAD SWITCH DET) The tape is loaded by a loading motor exclusively for Components - Top View of Mechanism
the fading in and out of the video signal during camera This inputs the SW30Hz signal through pin 8, detects the loading, using the parallel loading method. The upper (Figs. 7-2 to 7-4)
recording. The FADE signal supplied to pin 2 changes edge of the head switching signal and generates a pulse cylinder rotates in the same direction as that in which the
Fig. 7-2 shows the top view of the mechanism. The fol-
the smoothed voltage of the AGC detector to control the with a width of approx. 1O!J.S. This is also supplied tape runs.
lowing describes the operation and purpose of each
gain of the AGC amplifier. throu~h the OR gate to the hold amplifier. The chassis section is a dual layer structure consisting component along the tape running path.
3-2-2. 20kHz Lowpass Filter {20kHz LPF) of a sliding subchassis section and a main chassis sec-
3-3-5. 20kHz Lowpass FiHer (20kHz LPF) tion. A top-loading type cassette holder is built on top 2-1-1. Supply Reel Disk
This extracts the audio signal components under 20kHz. The application is the same as in recording. of the main chassis so that it can rotate freely. When a The supply reel disk incorporates a slip mechanism
3-2-3. Compressor/Expander (COMPRESS/EX- · 3-3-6. Compressor/Expander (COMPRESS/EX- cassette is loaded and the holder is depressed, the which is used to take up the tape during unloading and
PANO) PAND) holder is locked in the specifried position. While the tape reverse search.
This compresses the signal to 1/2 over the entire frequen- This has characteristics reverse to those of the compres- is being pulled out of the cassette by the torque of the Atthe bottom of the disk isa reflective plate which is used
cy range and then applies emphasis. sor during recording. The audio signal compressed to loading motor, the subchassls slides forward to wind the for the rotation detection. It generates eight sine-wave
1/2 (in decibels) during recording is expanded two times, tape around the cylinder. The tape drive mechanism is pulses per revolution. The supply reel disk consists of a
3-2-4. Limiter (LIMIT)
in order to expand the dynamic range, improve the S/N a major component mounted on the subchassis and the gear at the bottom to which torque is transmitted from
This limits the audio signal amplitude to under the max-
and prevent deterioration of high frequency com- loading mechanism is a major component on the main the reel drive gear and a pedestal at the top which is in·
imum frequency deviation before frequency modulation
ponents. The. output signal is supplied through SW3 to chassis. serted Into the reel hub of the cassette through the slip
to prevent overmodulation.
the muting circuit. There are three motors as the drive sources. (1) Cylinder mechanism. Since the torque from the reel drive gear is
3-2-5. FM Modulator (FM MOD) transmitted to the gea!' at the bottom, all operations
This frequency modulates the input signal with afrequen- 3-3-7. Muting Circuit (MUTE) (rewind, reverse search, unloading, etc.) are performed
cy deviation of within ± 1OOkHz and a carrier of 1.SMHz. This mutes the reproduced audio signal by the MUTE by torque transmitted by the slip mechanism. The ten-
The operation of the FM modulator is stopped when the signal and an output fromthe muting detector. sion band is wound round the pedestal at the top to con-
"Hi" MUTE signal is· supplied. Muting Detector (MUTE DET) trol the tension of the tape to be supplied.
This i11puts the dropout pulse and generates a muting
3-2-6. 2MHz Lowpass Filter (2MHz LPF) pulse when the dropout continues for 1.1 ms or more. 2-1-2. Tension Arm
This limits the bandwidth of the recording audio signal The tape is wound around the tension pin on the tension
to 1.SMHz ± 1OOkHz. The output signal at pin 14 is arm. The force of the spring hooked to the other end of
mixed with the recording pilot signals (REC PILOT) and the arm balances with the tension at which the tape
then supplied to a mixer (0218} in the luma/chroma sig- winds around the pin to control the tension of tape. The
nal processing circuits. tension of tape can be adjusted by changing the posi-
tion where the spring Is hooked. One end of the tension
3-2-7. Muting Circuit (MUTE)
band is attached on the tension arm so that It can rotate
This mutes the EE signal when "Hi" MUTE signal is sup- CHAPTER 7 MECHANISM freely. Although the other end of the band is fixed to the
plied from the OR gate. chassis, the hole in which the band is attached is long,
1. GENERAL DESCRIPTION (Fig. 7-1) therefore the attachment position can be adjusted. This

H_l:
3-3. Playback Circuit
This mechanism is for recording video and audio signals adjustment is done by comparing the adjustment hole in
The playback signal from a buffer (0229) is supplied on metal or evaporated tape which is hef d in a cassette the guide roller arm and the edge of the tension arm (see
through pin 18 to the 1.SMHz bandpass filter in IC401. 95 mm long x 62.5 mm wide x 15 mm high. Tape width Fig. 7-5).
3-3-1. 1.5MHz Bandpass Filter (1.5MHz SPF) is 8 rnrn. Tapes have thicknesses of: 13+1 microns (90
This extracts the 1.5MHz ± 1OOkHz reproduced audio minutes) and 1CH 1 microns (120 minutes). Selection 2-1-3. Supply Guide Roller (2)
signal by removing the luma, chroma and pilot signals. according to whether the tape is metal or evaporated and A brass ring is attached to the top of this roller to increase
CHZ CHI FE
The output signal is supplied to both the limiter and according to the thickness are done automatically by the the efficiency of inertia, thus suppressing jitter occurring
dropout detector (DO DET). tape~sel~ct ~~itc~es. Fig. 7-1 Video Headkrangement due to variations in the tape tension and speed.
;
[·~
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;:-1.'J

r·~"~"~liiiiftai' hw·:rsmr-ntrz:rws
 2-1-4; Guide Rollers and Slant Poles· The.shaft at the bottom of guide roller is threaded, there- parallel to the capstan shaft without a perpendicularity
These rollers and poles have the same structures as fore the height of roller can be adjusted by turning its top adjustment.. This structure moves the tape In an even
·those in .conventional VHS VCRs. •. They :change the using a special screwdriver. The angle of the slant pole line without pulling It up or down.
direction of tape running and regulate the height of tape. is fixed and it is not necessary to adjust It.
2-1-8. Take-up Reel Disk
··SUPPLY GUIDE. ROLLER 11 l SUPPLY SLANT POLE (I I TAKE UP GUIDE ROLLER (I I
The take-up reel disk operates In the same way as the
supply reel disk and takes up the tape supplied from the
capstan while slipping the torque using the slip
mechanism inside in the take-up and forward search
TAKE UP ;SI.ANT POLE 121 ' modes. At the bottom of the take-up reel disk is a reflec-
CAPSTAN MOTOR tive plate for outputting 8 pulses per revolution which is
PRESSURE ROLLER . used to detect rotation and display the remaining time.
A gear is provided on the circumference to drive the take-
up reel disk.
PRESSURE ROLLER SPRING
2-1-9. Reel Drive Gear (Swing Gear)
Torque from the capstan motor is transmitted by a
PRESSUR ROLLER ARM Cll
square belt to the reel drive gear through the center gear. PIN6
HS/NORMAL
The reel drive gear turns clockWise or counterclockwise
NO SENSOR
as the capstan rotates and transmits torque to the take·
up and supply reel disks. .......
TENSION BAND
TAKE UP REEL OISK
NO HOLE NO ON ( ) OFF t-'-l
=:J
!WITH SLIP MECHANISM I 2-1-10. Take-up Reel Brake I I METAL POWDER TAPE METAi. EVAPORATED TAPE
2 2 NOT USED NOT USED
TAPE SELECT SWITCH Brake torque is transmitted to the gear under the slip
3 3 13µ THICKNESS
mechanism of the take-up reel disk to apply braking to . 10µ THICKNESS

the reel disk through the slip mechanism. The take-up 4 4 - -

5 5 NORMAL
reel brake is provided with a brake shoe which applies HMP
6 6 REC
INHIBIT ARM TAKE UP REEL BRAKE or releases braking to/from the take-up reel disk depend- REC INHIBIT

ing on the direction of rotation of the reel disk. When the

Fig. 7-2
2-1-5 •. Cylinder {Fig. 7-3)
Fig. 7-3 s.hows the structure of the cylinder. The signals
picked by the video heads are supplied to .the circuit
boards through a rotary transformer. The upper cylinder
is pressed onto the shaft and is supported by two ball
bearirigs which allow it to rotate. Since a drive motor is
provided in the upper cylinder, the cylinder as a whole. is
compact and lightweight.. The upper. cylinder is driven
directly by the motor, therefore the vibration is less than
with conventional cylinders, causing an advantage in im-
proving jitter.. A convex bulge is provided on the circum-
ference of the lower cylinder to reduce jitter. As the
whole c~lnder assembly is dynamically balanced, vibra-
tions are greatly reduced w~en compared to convention-
al cylinders, to Improve jitter. . , · · ·. ··
The upper cylinder has two25µm-widevideoheadswith
azimuths of +10° arid -10°. Since the track pitch is
20.5 µ:m In, the .amm
system, OV01V{riting of 4;S~m occurs.
{,ARTH . BRUSH
MOTOR MAGNET.
. LOWER. dLINDER •
BOTTOM. ROTOR.
. Fig~ ·7_3 ~linder Structure
Top View of the Mechanism
The flying erase head is attached at 90° advanced from
the CH-1 head. This head ls 43µm wide and has no
azimuth. Therefore, when the flying erase head turns by
one turn, it erases two signal tracks. .A counterweight is
attached opposite to the flying erase head to balance the
head. The flying erase head erases two signal tracks
before the CH-1 video head anCJ then the CH-2 head
record video signals. To do this, there is a step dif-
ference of 13µ..m between the flying erase head and the
video heads.
2-1-6. Capstan
A 2.001 mm diameter DD capstan motor is driven by a
6-poledrive coil. Amagnetic ring for generating capstan
FG pulses on the circumference of the flywheel has 740
magnetic poles. This allows the flywheel to generate 370
CAPST.FG pulses in one revolution. Since the tape
speed is 14.345mm/s in the 8mm system, the capstan
shaft rotates at a speed of 2.270 rps (14.345/2.001) and
840 (370x2.270) pulses are generated.
Since the shaft is supported by oil-less metal bearings at
the top and bottom, with the section in contact with the
pressure roller sandwiched, a comparatively thin shaft
gives a sufficiently strong structure. The gear on the
CAPST.FG magnetic ring engages with the center relay
gear and transmits the torque of the moto.r to the center
gear. •
2-1-7. Pressure Roller
The pressure roller has the same structure as in conven-
tional table-top VCRs. It has a ball bearing at the center
and uses the play.of the ball bearing to pus.hthe roller in
tape is to be pulled out from the take-up reel disk in the
loading stop mode, for example, the take-up reel disk
turns counterclockwise which turns the take·up brake
shoe clockwise.
2-1-11. Supply Reel Brake
This brake is applied to the gear at the bottom of the
supply reel disk in the same way as the take-up reel
brake, therefore the brake torque is applied to the supp-
ly reel disk through the slip mechanism. When the stop
button Is pressed, the loading motor turns clockwise
which turns the loading cam gear through each relay
gear. This operation turns the supply brake gear
engaged with the loading cam gear clockwise. The pin
of the brake control arm on the subchassis is inserted
into the cam groove in the supply brake gear. Therefore,
the brake control arm turns clockwise. The plate spring
caulked to the brake control arm turns the supply reel
brake counterclockwise and applies braking to the supp- .
ly reel disk.
2-1-12. Inhibit Arm
This arm is engaged with the take-up. brake drive arm.
During leading, the Inhibit arm turns clockwise and in-
hibits the movement of the reel driVe gear so that the reel
drive gear Is not: engaged with the take-up. reel· disk for
take-up operation. - · · switch through loading gears (1) to (3). Since the
2·1-13. Tape Select Switches (Fig. 7-4)
Two tape select switches are·provided on the subchas-
sis and detect the safety tab and the thickness and type
of tape. (Refer to Fig. 7-4 forthe role of each switch. )
Fig. 7-4 Tape Select Switches
2-2. Diagram showing Locations of Major
Components in the Subchassis (Figs.
7·5 and 7-6)
Fig. 7-5 shows the top view of the subchassis. The sub·
chassis section drives the tape. The following describes
the operations of Its major cornponents.
2-2-1. Subchassis Slide Mechanism (Figs. 7-5 and
7-6)
When an Bmm cassette is inserted into the cassette
holder and the holder is depressed, the subchassis is
pushed to the front by the torque of the loading motor
and the tape is wound around the cylinder by the load-
ing mechanism on the main chassis (shown in Fig. 7-6).
The following is the detailed explanation. Three guide
pins on the main chassis are inserted into three subchas-
sis guide grooves In the subchassis and the guide hole
on the side of the main chassis engages with the pin on
the side of the subchassis, to slide the subchassis back-
wards and forwards. This sliding operation is performed
by the torque of the loading motor. The torque of the
loading motor is transmitted to the .mechanism state
mechanism state switch shows which mode the mecha-
nism is set tc, It should be assembled whiie the phase of
of
the switch m9(ie is aligned with that the machanism
mode. The torque passing through the mechanismstate
switchis transmitted to the loading cam gear. The p!n
of the subchassis drive. arm on the main chassis ls in-
serted. into the groove In the.loading cari gear. the As

7-4
•' .: .., l' : ,1 ii '.t • ,',~ 1
•:,: ~- :.~•:j 1
, " ~'1, • '
1
' 1 ,
 loading cam gear turns, It drives the pin provided on the
other end of the subchassis drive arm. This pin on the
subchassls drive arm is Inserted into the subchassis
slider stopper which is fixed to the subchassis and
moves the subchassis backwards and forwards to per-
SUPPLY GUIDE GROOVE
TENSION POLE
TENSION POLE
ADJUSTMENT HOLE
TENSION SPRING'
SUB CHASSIS SLIDE STOPPER
Fig. 7-5 Sub Chassis of the Mechansim
LOADING MOTOR
LOADING GEAR Cl
LOAD ING GEAR (2)
MECHA STATE SWITCH
SUPPLY BRAKE GE AR
LOADING RELAY GEARll
Fig. 7-6 MainChassis of the Mechanism
2-3. Diagram showing Locations of Major
Components in the Main Chassis
(Figs. 7~6 and 7-7) · Fig 7-7 is a diagram showing the operation principle of
Fig. 7.0 shows the locations of major components in the
main chassis; This chassis is responsible for the 1.oad-
lng and main brake drive operations. The left side of the
chassis Is for the loading operation and the right side is
for the perssure roller.drive operation..·The slide gear at
the center of the main chassis Is engaged with: the supp-
ly/take-up 16adlng gear which Is attached to the main
chassis so it can rotate freely and tums the take-up load-
7-5
liiiii'-"""""'W??tTtl• Ea777EF"''·••• .,.-... ~-·'-"'g-···.,·~--·~·~•-1'>',_,n,.,,,,,.,.~,.7-5"--·-·-·
form loading and unloading .. Since the subchassls slide gear (2). ·A groove is cut In the take-up loading gear
stopper regulates the distance by which the subchassis iAKE UP· L.OADING GEAR engaged with loading relay gear (2) ·and the pin of the
moves, Its position should be adjusted· when it is as- loading operation arm is insert into this groove. A plate
sembled. spring Is caulked to the loading operation arm and the
end ofthe spring is in contact with the drive pin of pres-
sure roller arm (2) (shown in Fig. 7-8). As the subchas-
sls advances and the take-up loading· gear turns during
TAKE UP SLANT POLEC2) CASSETT DAMPER
loading, the loading operation arm (shown in Fig. 7"6)
GUIDE PIN . turns and presses the pressure roller against the capstan
TAKE UP GUIDE ROLLER
. shaft. Then, the drive pin is pushed further, therefore the
pressure roller spring is pulled by the roller spring and
the compression force of the pressure roller is
generated. Since the guide pole beside the pressure
SUPPLY GUIDEROLLER ASSY !TOP VIEW) roller is pushed against pressure roller arm (1) by a tor-
Fig. 7-7 Supply/Take-up Loading Gear Drive. sion spring, it moves as the pressure roller moves.
Mechanism
GUIDE POLE
PRESS URE ROLLER
2-4. Loading Mechanism (Figs. 7·6 and \
7-7)
Torque from the loading motor is transmitted to loading
gear (3) through loading gears (1) and (2): A guide
groove ls provided in the back of loading· gear (3) and a
pin of the arm which drives supply slant pole (2) and
TAKE UP REEL BRAKE TA KE UP BRAKE DRIVE ARM
supply guide roller(2) (shown In Fig. 7-2) is inserted Into
this groove. This pin is Inserted lntothETgroove provided DRIVE PIN
at the bottom of the arm to which supply guide roller (2)
and supply slant pole (2) (shown in· Fig; 7~2) are attached·
and drives the arm. Since loading gear (3) also drives
th~. :mechanism·. state ,swlt9h, their,. phases. should: be
matched. w~en they a~e assembled. They should be as-
sembled whiie.tne hole in the. chassis-ls aligned.with the
hole in loading gear (3). Torque passing via the
mechanism state switch ls transmitted to the loading
cam gear.~ A'groovefor loading is provided in the load~ · Fig .. 7-8 Pressure Roller Drive Mechnisfr! . ·
.
CAPSTAN MOTOR
Ing cam gear a'"!C! the. pin_ of the sl.lde gear dri'l!e arm is
Inserted ~nto this groove. Asthe load Ing carri gear turns,
CENTER RELAY GEAR
the .slide ·gear dr!Ve· arm·tums counterdockwise.. The 2-6. Supply/Take-up ~eel e·rake Operation
PLATE SPRING plate spring at the end qf the ·st.Ide gear drive arm moves .. . Mechanisni (Fig. 7-:9) · · - ·
RELAY BELT
the slide gear backwards as loading 'progresses~ . The
supply and take-up leading geara"are"ehgaged with the The· pin of the brake control arm Is inserted into the cam
LOADING OPERATION ARM
slide ·gear. Whenthe slide gear moves backwards, tlie groove In the supply brake gear(shown in Fig. 7-6). A's
TAKE UP LOADING GEAR supply loading gear turns clockwise and the take-up loading progresses from the unloading stop mode to the
loading gear turns counterclockwise to push the supply loading stop mode, the sµpply brake gear turns counter-
and take-up guide roll~r. assel'l'.1blies against the: arm . clpck\vise. This turns the brake control arm clockwise
stoppers. The force with 'b\fhich_the supply guide roller via the c:arn groove which turns the supply reel brake
assembly is pushed against the arm stopper is given by counterclockwise to apply braking tOthe suppy reel disk.
the plate spring of.the- slide. gear drive arm._ The force Whe11 loading Is accessed from.the l0ading stop mode
with which the ta~e-up guide rollerassemb.ly Is pushed ... to the play mode, the supply reel brake turns clockwise
ing gear counterclockwise and the supply loading gear against the arm stopper is generated by the spring in the · ·via the cam groove' In the supply reel brake to release
clockwise to perform loading. link arm. When l,oading.is.compieted, the mechanism _.braking Jrom ttie supply reel disk: On the take-up side,
the pin of the take~up brake drive arm is in contact with
state switch detects the ~No . 5 position and stops the·
loading motor. : · the loading operatiorfar.rit:.(sMwn :in Fig. 7-6) and is
the take-up and supply loading gears. The supply guide
roller assembly advances along the guide groove as driven. hi the unloading stopi'node,.the take-up brake
loading progresses and Is pushed into the arm stopper 2-s. Pressure .Roller :compression ·.driVe arm .is· pushed In. the _clockwise direction by a
·spring.· This pushes the take:UP re.el brake counterclock-
by the plate spring attached to the slide gear drive arm
pushing the supply loading link directly. The force with
Mechan~~'!I. ~~i~~~~.!'i~ ~.na_ 1:ar ·. :wise so that it'is separated-from 'tlie take-up reel disk.
which the take-up guide roller assembly ls pushed into When the loading cam-gear at the ceoter_ of the main When loading is acc¢ssea to tl)e loading stop mode, the
the arm stopper is generated by the coil spring of the chassis Is turned ~l~k\_Yi~e:~Y ~h~ tg~cjlJ~ <?.f t~e l~ding_ take-up drive_ arm Is ·turned. cloc~wise by the loading
take-up loading link. motor, loading relay gear-(1) engaged with the loading operation arm which. turns th.e: take-up reel brake
cam gear tums and transmitsJorque·to Joadlng relay . . -counterclockwise fo apply braking to the take-up reel
:1
·- • • "'ilii'"""""'"''''"""'~·· _"J nmrnrrwrc::::r•
 disk. A take-up brake shoe as well as a take-up reel
brake Is attached to apply the brake on the take-up side.
When the take-up brake drive arm Is held by the loading
operation arm at the neutral position between the load-
Ing and unloading conditions In the playback and
reverse modes. the take-up reel disk turns counterclock-
wise. This turns the take-up IJrake shoe clockwise and
also tums the take-up reel brake clockwise to apply brak-
SUPPLY REEi. DISK
PIN
ing to the take-up reel disk. When the take-up reel disk
turns clockwise, the take-up reel brake turns counter-
clockwise and .Is released from the take-up reel disk.
That ls, when the tape Is to be pulled out of the take-up
reel disk In a specific mode (for example, In the loading
stop made). the take-up reel disk turns counterclock- ·
wise and ls braked.
the idler is swung to the take-up side so the reel drive
gear is not engaged with the take-up reel disk by the
groove In the panel and the inhibit arm. During unload-
ing, the Idler is swung to the supply side to remove slack
tape and the Inhibit arm is not used. When eject is in-
structed, the cassette holder should be locked by the
operator after depressing it After the cassette is ejected,
therefore, the loading motor turns In the loading direc-
tion so the mechanism state switch detects the UL STOP
position and enters the standby state. Since the eject
arm ls In the UL STOP mode at this time, then the cas-
sette holder can be locked. When still play Is instructed
and five minutes have elapsed, the mechanism returns
to the L STOP position to protect the tape and heads.
When the pause button is pressed during recording, the
capstan motor stops rotation and the mechanism enters
the record pause mode. When five minutes have
elapsed in the record pause made, the mechanism is
shifted to the L STOP mode. The tension arm is returned
slightly so the tape is slackened a little and the pressure
roller is released from the capstan shaft, causing the
mechanism to enter the standby mode.

TAKE UP BRAKE St;iOE

Fig. 7-9 Take-up/Supply Reel Brake Mechanism

2·7. Eject Mode (Fig. 7-6)
When the EJECT button is pressed, the loading motor
turns clockwise to transmit torque to the mechanism
state switch through loading gears (1) to (3). Torque of
the loading cam gear is transmitted to the take-up load-
ing gear through loading relay gears (1) and (2). Tile
take-up loading gear has a guide groove Into which the
pin of the loading operation arm is inserted and the arm
Is driven. The other end of the loading operation arm Is
In contact with the end of the eject arm. When the load-
ing operation arm turns, the eject arm turns clockwise.
One end of the eject arm pushes the lock arm of the cas-
sette holder backwards to complete the eject operation.
When eject should be completed, the other end of the
eject arm presses the mlcroswitch to stop the loading
motor.
2-8. Mechanism Timing Chart {Fig. 7-10)
Fig. 7-1 oshows a timing chart of the 8mm chassis. The
Idler Inhibit arm prevents the reel drive gear from turning
during loadi11g and unloading. If the reel drive gear were
engaged with the take-up reel disk during loading and
unloading, the tape would be wound onto the take-up
reel disk. The Inhibit arm inhi.blts this. During loading,

EJECT UL.SlOP LOADING L.STOP pS/FF ~EW/REV

SUB CHASSIS
--r-
I
TENSION ARN

TAKE UP REEL BRAKE ON

(ONE WAY CLUTCH) OFF
MAIN BRAKE
(SUPPLY SIDE) ~
IDLER INHISlT
TAKE UP SIDE

FR IDLER
.:
I
. I

Fig. 7-10 Mechanism Timing .Chart

7-7
7-8
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 ~HITACHI
HITACHI SALES COFIPORATION OF AMERICA Hitachi Sales Centroamerlcana, S.A.
Eastern Regional Office San Rafael de Escazu, (Apartado 10272), San Jose,
1290 Wall Street West, Lyndhurst, New Jersey 07071, U.S.A. Costa Rica
Tel. 201-935-8980 . Tel. 28-20-·11, 28-00·37
Mid-Western Regional Office Hitachi Sales Corporation de Panama, S.A.
1400 Morse Ave., Elk Grove Village, Ill. 60007, U.S.A. Nuevo Reparto ~I Carmen, Calle Ramon Arias y Calle B
Tel. 312-593-1550 Edificio Brasil 100, (Apartado 7657) Panama 5
Panama City, Rep. of Panama
Southam Regional Office
Tel. 61-6100, 61-4305
510 Plaza Drive, College Park, Georgia 30349, U.S.A.
Tel. 404-763-0360 Hitachi Sales de Chile Cia., Ltda.
Av. Mexico, 0183, Casilla 9793, Correo Central
Western Regional Office
401 West Artesia Boulevard, Compton, California 90220 U.S.A. Santiago, Chile
Tel. 774165
Tel. 213-537-8383
HITACHI SALES CORPORATION OF HAWAII. INC.
3219 Koapaka Street. Honolulu, Hawaii 96819, U.S.A. HITACHI SALES CORPORATION. TOKYO JAPAN
Tel. 808-836·3621 Head Office: THE HITACHI ATAGO BLDG.
No. 15-12, 2-Chome Nishi·Shinbashi
HITACHI (HSC) CANADA INC.
Minato-Ku, Tokyo 105, Japan
3300 Trans-Canada Highway, Pointe Claire, Quebec,
Tel. Tokyo (03) 502·2111
H9RU181, Canada
Tel. 514-697-9150

VM-E10A TK No .. 3373E TOKAI

Copyright © Hitachi, Ltd. 1990. All rights reserved. Printed in Japan (K)
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