EE 598

Digital Design using Verilog

Lecture 1: Overview

Prof. Bo Yuan
Electrical Engineering, CCNY
Slides adapted from Mingjie Lin, Arvind, Krste Asanovic
 Agenda
 Course Info. and Admin.
◦ Information;
◦ Administration.

 Course Content
◦ Definition;
◦ Content.

 Why we need to learn this course?

◦ Motivation;
◦ Learning Outcomes.
 Agenda
 Course Info. and Admin.
◦ Information;
◦ Administration.

 Course Content
◦ Definition;
◦ Content.

 Why we need to learn this course?

◦ Motivation;
◦ Learning Outcomes.
 Who am I
Instructor: Bo Yuan
 Email: byuan@ccny.cuny.edu
 Campus Phone: (212)-650-5615
 Office location: ST 530
 Office hour: 12:45pm-1:45pm 5pm-6pm
Tuesday (or appointment)
 Research and Teaching interests:
-- HW/SW Co-Design for Signal Processing System
-- HW/SW Co-Design for Machine Learning System
-- Error-Resilient Computing
-- Ultra-High Density Storage System
 Communication
A lot of info. will be on the blackboard
 Syllabus
 Lecture notes
 Homework & solutions
 Sample exam papers & solutions
 Reading materials & handouts
 Any update & notification
Check your emails frequently
 Timely notice will also be sent via emails
 Contact with me via email for any request
 Text
Textbook
 Advanced Digital Design with the Verilog
HDL
 2nd edition
 By Michael D. Ciletti
Other materials
 Handouts
 Reading materials
 Class Make-up
 Time conflict with the class schedule may
occurs when I attend technical or research
conferences etc.
 Manners to resolve the potential conflicts:
--Reschedule class to other date and time
--Adjusting the date of midterm exams
--Compensate by substitute instructor
 Any class conflicts due to my travel will be
announced both in class and on Blackboard.
 Grading
 Homework 15%
 In-class Midterm-1 25%
 In-class Midterm-2 25%
 Term Project 20%
 Final exam 25%

Date of exams will be announced in

class, on the blackboard, and via email
 Homework Policy
 Posted on the Blackboard
 No late homework (unless I am notified
before it is due for special circumstances).
 10 % penalty per day for late homework
(including weekends).
 No late homework once the solutions are
posted on the Blackboard.
 See syllabus for other details.
 Exam Policy
 Closed book for all exams
 One-page formula sheet (8.5’’x11’’, both sides)
is allowed
 No makeup exams will be given except in
provably extreme circumstances:
-- Notify me 24 hours prior to the exam
via e-mail or telephone
-- For medical-related reasons, a note from
a physician is a must.
 Plenty of notice will be announced about the
exam date (in class, blackboard, email)
 See syllabus for other details.
 Agenda
 Course Info. and Admin.
◦ Information;
◦ Administration.

 Course Content
◦ Definition;
◦ Content.

 Why we need to learn this course?

◦ Motivation;
◦ Learning Outcomes.
Digital Design using Verilog
 EE 598 is about “Digital Design”
-- “Hardcore” of EE&CE Program
-- Fundamental for many graduate-level courses

 Verilog is a HDL language for digital design

--HDL: Hardware description language
--other ways for digital design: schematic etc.
--HDL is the most convenient method
Modern Digital System
 Different Design Sytles
 Full-Custom (every transistor hand-drawn)
– Best performance: Intel CPU, memory

 Cell-Based ASICs (Only use cells in standard

library)
– High volume: most digital ICs

 Field Programmable Gate Arrays (FPGAs)

– Early Prototype, fast change: datacenter
 Full-Custom Design
 Designer is free to do anything, anywhere
– Each design team usually imposes some
discipline
– Most time consuming design style
 Reserved for very high performance or
very high volume devices
– Intel microprocessors, RF power amps
– Requires complete customization of all
layers of wafer
Example of Full Custom
Design
 Standard Cell Design
 Fixed library of cells plus memory generators

 Cells can be synthesized from HDL, or entered in

schematics

 Cells placed and routed automatically

 Currently most popular hard-wired ASIC type

Example of Standard Cell
Design
Standard Cell Design (ctd)
Standard Cell Design (ctd)
Field Programmable Gate
Arrays (FPGAs)
 Each cell in array contains a programmable logic
function
– Array has programmable interconnect
 Arrays mass-produced and programmed by
customer after fabrication
– Can be programmed by blowing fuses, loading
SRAM bits, or loading FLASH memory
 Overhead of programmability makes arrays
expensive and slow
– but startup costs are low, much cheaper than
ASIC for small volumes
Xilinx Configurable Logic
Block
ASIC/FPGA Design Flow
EE598 in Curriculum
Application
Algorithm CS220
Programming Language CS113,EE259
Operating System/Virtual Machines CS332
Instruction Set Architecture (ISA)
EE344
Microarchitecture
Gates/Register-Transfer Level (RTL) EE598
Circuits EE464, 457
Devices EE441
Physics EE339,454
 Agenda
 Course Info. and Admin.
◦ Information;
◦ Administration.

 Course Content
◦ Definition;
◦ Content.

 Why we need to learn this course?

◦ Motivation;
◦ Learning Outcomes.
Why we need to learn this
course (Academia)
 “Hardcore” of comp. engineering track
 Basis for many advanced courses/topics
-- (Advanced) computer architecture
-- Digital VLSI system design
-- Computer Network
-- Parallel GPU computing
…
Why we need to learn this
course (Industry)
 Basicskill for job in semiconductor industry
 A typical Job ad. from Intel.com
 https://forums.anandtech.com/threads/an-in-depth-look-at-google%E2%80%99s-first-tensor-processing-unit-
tpu-developed-in-2015-2016.2506216/
 Learning Outcome
 Clear Picture on Different Design
Approaches

 Verilog Programming

 Synthesizable Verilog Programming

 Common Digital Module Design

 ……