Hyperlynx Bhat PDF

Model, Simulate & Correlate PCB
designs using Mentor Graphics

analysis tools
Shreyas Bhat
Senior Applications Engineer

Mentor Graphics
Shreyas_bhat@mentor.com
(248) 223-5814
Contents
1. Signal integrity analysis using Hyperlynx SI
2. Power integrity analysis using Hyperlynx PI
3. EMI DRC checking using Hyperlynx DRC
4. System simulations using SystemVision
© 2010 Mentor Graphics Corp. Company Confidential

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Integrated PCB Simulation
Behavior Digital Integrity

Signal/
Power
HyperLynx SI/PI/DRC Digital Buffers
PCB Traces
Power Delivery
ModelSim / Questa Digital Logic
SystemVision
Analog
SystemVision Transistor Component AMS Analog Functional Block
Sensors
Actuators
Baseband Analog
SPICE
Level
SystemVision
Power Converters
Custom Digital
SPICE
Level
IC
Eldo RF / ADMS
RF Front-end
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Hyperlynx SI/PI: The 4 areas of analysis
Signal Integrity (SI) Power Integrity (PI)

Linesim (Planning) Linesim (Planning)
Boardsim (Post route) Boardsim (Post Route)

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Model digital signal integrity using Hyperlynx SI
Signal Integrity Concerns
Traditional signal integrity

— Crosstalk, overshoot, timing,
impedance mismatches
DDRx design
— Timing, ODT selection
Multi-gigabit SerDes
technologies
— Loss management, via
design, length matching,
impedance discontinuities

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People
Process Tools
The Generic Design Process Education
Data sheet rules

Data sheet rules
“There’s power
for signal integrity
info in there?”
Schematic Capture
Rules
PCB Layout
Thermal lab Signal integrity Power delivery EMC chamber

testing lab testing lab testing testing

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People
Process Tools
Improved Process & Tools Education
HyperLynx HyperLynx
Signal Integrity Power Integrity
DxDesigner
Constraint
Editor System
Expedition PCB
HyperLynx HyperLynx HyperLynx

Hyperlynx DRC
Thermal Signal Integrity Power Integrity
Thermal lab Signal integrity Power delivery EMC chamber

testing lab testing lab testing testing

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Components of a Simulation
Driver Interconnect Receiver
IC modeling – primary factors

Driver Receiver
Voltage swing Input Impedance/
Slew Rate (dv/dt) Capacitance
Output Impedance Clamp diodes
Vil
Secondary Factors
Vih
Output Capacitance
(Package Parasitics)
Package Parasitics

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IC Modeling Formats
HL supports the following model types of varying complexity:
IBIS-AMI
S-parameter
Complexity
Eldo, AMS, HSPICE

IBIS, EBD Choose the model
that’s best for your
.PML specific situation.
(HL— Package Models)
Databook .MOD
(HL—Databook Models)
Easy.MOD
(HL—Technology Models)
Information
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Basic structure of an IBIS file
Header
– file name, date, version, source, notes, disclaimer, copyright, etc.
Component model data
component
– Default package data (L_pkg, R_pkg, C_pkg)

– Complete pin list (pin name, signal name, buffer name, and optional L_pin, R_pin, C_pin)
– Differential pin pairs, on-die terminators, buffer selector, etc.
I/O model data
buffer
– All buffer models for the component must be defined in the file
– Each flavor of a programmable buffer is a separate model

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Pre-Layout Signal Integrity
Stackup
Check your Stack up and Materials to

make sure they will give you the target
impedance in the end product.
Use the Stackup Editor to confirm the
Hyperlynx layer order, type and
thicknesses, agree with your desired
stackup (Setup > Stackup)
Also confirm the Material properties are
correct. Typically 3.9-4.5 for FR4
dielectric constant, Er, and .02 for Loss
Tangent.

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People
Pre-Layout Signal Integrity Process Tools
4-T’s Education

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People
Net Length Rule Development Education
How far away could your parts be (min & max) HyperLynx
SI
Simulate for all possible net lengths
Do you have excessive overshoot?
— Yes: You will need termination of some sort
— No: Max length rule into CES DxDesigner
CES
Expedition
PCB
Swept lengths from .5 to 3 inches; .5 inch increments

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People
Series Termination Rule Development Education
Do you need a series termination resistor? HyperLynx

SI
What value (schematic)?
What topology (layout)?
DxDesigner
CES
Expedition
PCB
Type Effect
Series Reduced driver currents give good
performance. Works best when resistor
is very close to driver
DC Pull Less ringing generally reduces EMI.
Up/Down Certain frequencies may increase
AC Similar to DC Parallel, but better if
Parallel capacitor is small
Diode Can generate additional high frequency
emissions
Swept resistor values from 10 to 65 ohms; 5 ohm increments

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People
Cross-Talk Rule Development Education
What are the xtalk thresholds? HyperLynx

SI
Net-class and bus rule development

— Determine max length/min spacing of a coupled pair
DxDesigner
Analyze same layer and adjacent layer rules CES
Expedition
PCB
Swept coupling length from 1 to 10 inches; .5 inch increments

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People
Cross-Talk Rule Development Education
HyperLynx
SI
DxDesigner
CES
Expedition
PCB

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People
Complex Topology Rule Development Education
Will you be given a complex topology?

HyperLynx
Quickly create it in CES (using HyperLynx) SI
Determine where the tolerance for design is?
What should the wave form look like to ensure good signals?
DxDesigner
CES
Expedition
PCB

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People
Process Tools
Constraints & Routing Education
Enter your constraints into CES

Develop auto-router algorithms
Save manual routing for clean-up & critical nets

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People
Post-Layout Signal Integrity Process Tools
Net Rule Verification Education
DRC (hazards) and CES should’ve kept things in check HyperLynx SI

(LineSim)
Analyze to verify it works (interactive)
Troubleshoot if necessary
DxDesigner
CES
Expedition
PCB
HyperLynx SI
(BoardSim)

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People
Post-Layout Signal Integrity Process Tools
Multiple Net Rule Verification Education
Batch mode simulation for ringing/overshoot/xtalk HyperLynx SI

(LineSim)
Collaborate with engineering / SI group to develop rules for nets
and signals
DxDesigner
Get feedback for PCB design
CES
Expedition
PCB
HyperLynx SI
(BoardSim)

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Hyperlynx: Linesim SI
Industry-renowned ease of use
Accurate modeling of trace impedance,

coupling, and frequency-dependent
losses
Terminator wizard recommends optimal

termination strategies
Identify SI issues, perform crosstalk

analysis, parametric sweeps
Stackup planning
Industry-leading support for high-speed

serial interface (SERDES), including fast
eye diagram analysis, S-parameter
simulation, and BER prediction
Advanced via modeling
Provides an early look at likely EMC

failures
Integration with the constraint editing

system
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Hyperlynx: Boardsim SI
Simulate post routed data
from your host PCB system
Run interactive simulations
on individuals nets
Run a comprehensive batch
simulation on many nets at
once
Parametric sweeps
Verify DDR/2/3 bus
structures (single and multi-
board setups)
Crosstalk analysis
Advanced Timing Analysis
Interactive EMC Analysis
Run SERDES Fast-eye
analysis
Run IBIS-AMI channel
analysis
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HyperLynx DDRx Simulation
Validate LPDDR and DDRx
timing and SI designs
‘Wizardized’ Setup
— Save and load previous
configurations
Supports DDR3 timing
alignment for clock and strobe
signals
— Required for new fly-by
architecture
Provides comprehensive timing
margin results
— pass/fail
for setup and hold
– Includes ∆T derating

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Customer Correlation Data – SI
Simulated Vs. Measured
Xilinx Virtex 5 Rocket I/O Transceivers – eye diagram analysis
White paper authored by

Howard Ireland, Xilinx; Kim Owen, MGC

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Eye Diagram Simulations – Simulated vs.
Measurement

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Impact of Vias on a MGbps Channel
Via stubs
— Can be a major contributor to creating a discontinuity
Thru-hole
stub
SDD21
Backdrill
2.5GHz 5.0GHz
short stub
Blind via 0.08dB 0.3dB
Backdrill 0.15dB 0.4dB
Stub 0.35dB 3.5dB
Blind
no stub

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Full-wave 3D via modeling
Some designs require more

accurate via models
— Can contribute significant
loss at higher frequencies
— Designers with technology
faster than 5+ Gbps
— Designing with New
Xilinx/Altera Parts
Need the ability to
accurately tune the via design
— Separation, stitching, entry
angle, etc.
What Type of Structures
Require 3D Models?
Vias, BGA and connector pin
fields, traces over splits,
bends, packages……

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HyperLynx 3D EM - Full-wave EM modeling
HL 3D EM = Full-wave 3D Electromagnetic (EM) Simulation Solution
— Fastest, Highest-Capacity, Full 3D EM Simulation in the Market
Mature technology acquired from Zeland Software in 2010

— Over 1600 Customers Currently Use IE3D
— Long History (since 1992) of Production Proven Use
Creates High-Frequency Parasitic Models Needed for Circuit Simulation

— Frequency-Dependent Parasitic Extraction of Metallic Structures – “S-Parameter Models”
EM Simulation is Used in All High-Frequency Design Applications

Wireless
Cell Phone, Routers, Bluetooth, GPS, LTE, WiMax (802.16)
Antenna and Antenna Arrays
RFID/Zigbee Tag Design
Hi Speed Digital
10G/40G+ Internet, FibreChannel, XAUI, PCIe, Infiniband
On-Chip SerDes, Package
DDR3 Memory I/F Channel
Military/Aerospace
Secure Communications/Network
Large Phase Array/Imaging Antenna
HL 3D EM Employs a Unique 3D Integral Equation Method to Solve Maxwell’s Equation Governing

Electrical Behavior of Metallic Structures
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3D - Partial geometry extraction from BSim
Export the
geometry into
an intermediate
format then to
3D layout
environment
DesignFile:DQ0_3D.ffs
HyperLynxLineSimv8.2.1
TL3 TL5 TL7

Breakout Near Driver V2
Asymetrical
U2 J1 1
56.8 ohms 3D 55.0 ohms
Tuning 55.0 ohms
U1
2 Port1 Port2 J2 J3
119.073 ps 97.931 ps 154.315 ps 1
0.670 in 3 0.660 in 1.040 in
Port3 Port4 Port1 Port2 Port1 Port2
DQ0_N DQ0_N DQ0_N
1
PCIe2Tx
Design1_3ds tru...
TL4
3D Via Model TL6
Port3 Port4 Port3 Port4
TL8 2
TX- Design1_3dstru... Design1_3dstru... PCIe2rx
RX+
Split Plane
56.8 ohms 55.0 ohms 55.0 ohms
119.073 ps 97.931 ps 154.315 ps
0.670 in 0.660 in 1.040 in
DQ0_P DQ0_P DQ0_P
High-Speed Interconnect Model © 2010 Mentor Graphics Corp. Company Confidential

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Model power integrity using Hyperlynx PI Plane
Design Starts with Plane Power Integrity
What is power delivery network?
— The path (or interconnects) from power supply (ex. VRM) to die
— Including PCBs and packages
– Planes, routed traces, and decoupling capacitors
Bypass capacitor
Power planes
Active device PCB VRM
Test point 1 Test point 2
A good PDN should :

— Deliver sufficiently clean supply to the ICs
– Ideally, PDN should not consume power
— Provide low-noise reference path for signals”
– PDN should not introduce SI problems
— Provide Minimal voltage drop to the IC’s

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The 3 Keys to Power Delivery
Minimize DC Drop
— IC Power
Maximize power delivery at all
freq through adequate decoupling
— Capacitors – how many/what values
— Correct placement of caps
Minimize the Noise on planes
— Identify areas on planes where voltage ripple
exceeds IC power pin spec
— Plane noise is a result of target impedance
and core/IO switching currents (V=I*R)

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Power Integrity Process Efforts
Decoupling Capacitor Analysis
— Pre-analysis: 80%
— Post-analysis: 20%
— Board / Plane outline that are close in pre analysis
provide relatively accurate results
— Since the cap quantities & values are needed in the
schematic, there is a lot of value for pre-analysis
Noise Analysis
— The goal here is to find areas of the plane that may
become noisy or have excessive overshoot/undershoot
DC Drop
— DC Drop analysis exposes area’s of the plane that are
narrow or places where voltage drop is excessive.
— Since it’s difficult to determine every little anti-pad and
exact plane shape initially, the best place for this
process is after the planes have been routed
— Pre-analysis can help determine needs for high current
trace widths, stitching via quantities and overall design
insight
— Determine what the max drop is for every rail
— There is a batch mode analysis that is rules driven

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Shift in Design Methodology
Traditional Design Methodology PI Analysis Design Methodology

Pre-determined stackup Stackup Power Budget
Target Impedance
Schematic development Plane Locations
— Engineering power estimation
Schematic Decoupling
— Voltage regulator selection Development Capacitor Analysis
PCB Part Placement

— Part Placements / Routing PCB Design Plane Layout
— Plane routing & refinement DC Drop Analysis
Trace Routing
Post PCB Batch Mode DC
Post PCB Drop Analysis
— Post processing data review Decoupling
(Gerber) Analsys
— DRC Checking
Board fabrication and assembly

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Stackup: Standard Development
Power Budget
Target Impedance
Plane Locations

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Stackup: Adding Analysis
Power Budget
Target Impedance
Plane Locations

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Stackup: Power Budget
Usually created by
Engineering to estimate
total power needed
Excel Table
Add any additional need
to later analyze:
— DC Drop
— Part Voltage
Requirements
— Current demand
Part Power requirements
Voltage (v) Max Dcdrop Max Dcdrop
Voltage Rail name Part / RefDes VRM refdes Ref net Typ Min Max Max Current (A) (Calculated) (mv) (datasheet) (mv)
1.8v U123 U2 gnd 1.8 1.6 2.0 1.25 200
2.5v U5 U3 gnd 2.5 2.25 2.75 0.5 250
0

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Stackup: Target Impedance
1. Calculate Target Impedance
1. PDN_Zmax = Vnoise / Imax
2. Placement of critical planes

1. Lowest Zt should be placed at
the edges (top or bottom)
2. Highest Zt can be sequentially
placed further in the stackup
Target Impedance Schedule

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(A)
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Voltage Net name

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0-9vcc 0.9 2 5% 22.5 1.8

1.8v 1.2 0.5 2.5% 60 0.6
5v 5 2 5% 125 10
0.9v 0.9 5 5% 9 4.5

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Schematics: Decoupling Capacitor Analysis
Decoupling
Capacitor
Development
Import PCB Board

Determine Board Schematic Decoupling
outline Mock Design up in
HL-PI Linesim Development Capacitor Analysis
Simulate PDN
Plane SRF
LRC w/o Models
Target PDN
Impedance Simulate for
Lumped and
Distributed
Add in Capacitors Capacitor Models
Impedance
Profiles
Determine cap
Capacitor Parts to
Values & Schematics
schematics
Quantities
Determine Cap
Locations
Analyze Noise for

Noise / Voltage
Noise Analysis additional Cap
Budget
locations
Decoupling
Planning
Complete

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PCB: Part Placement
Various techniques work here

Concentrate first on the parts
with the low target impedance
— IC placement followed
immediately by decoupling caps
Work down the list

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PCB: Plane Layout
Focus on the critical planes
first
Followed by the next critical
planes
— Can they be on the same layer?
— How close is the voltage
regulator?
DDR
IC DDR
DDR
DDR
uP
DDR

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PCB: DC Drop Analysis
Once each plane is generated,

run a DC Drop test
Minimize voltage drop
View the current density and
target specific areas to focus on
Models needed
- VRM model
- DC current sink
model

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PCB: Batch Mode DC Drop Analysis
Route traces.
After the critical planes are placed, all the
data for DC Drop is setup.
Simply run the simulations in a batch mode
format after significant routing has been
done
Routing causes more plane perforation,
causing tighter areas for current to flow

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PCB: Decoupling Analysis
Quick Capacitor Analysis

Analyze all the capacitors and
check mounting very quickly
Very simple models are usually
the best. Most of the
modeling is done in the
package/board

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PCB: Decoupling Analysis
Plane decoupling analysis
Select a few power pins on the critical parts.
— Center, edges, worst case
Simulate and check capacitor effectiveness
Noise Analysis
Attach AC Supply pin model
Notice noise propagation on plane
Add Decoupling caps in ‘noisy’ areas

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Correlation Data for HL-PI
Simulated Vs. Measured
WhitePaper: “Establishing Confidence in PDN Simulation” – Eric
Bogatin
Setup
— 6 layer brd / 0603 cap (via-in-pad) / 4 SMA connectors
— 2-port VNA measurement (VNA was calibrated using a standard SOLT
(short open load thru) measurement at the end of the coax cables and connected
to the two SMA ports on the test board)

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Transfer Impedance (Z21) measurements

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Perform design rule checks using Hyperlynx DRC
Electromagnetic Design Issues
Items that can be simulated

— Signal Integrity
– Overshoot, undershoot, ringing, crosstalk,
timing, eye diagrams, BER
— Power Integrity
– Decoupling, voltage drop, plane noise
Items that cannot be easily simulated

— EMI (Electromagnetic Interference)
– Return current path issues
– reference plane changes, traces crossing splits
(HL-3D solver)
– Nets near plane edges
– I/O nets coupled to fast signals, proper filter
placement

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Solving EMI Problems
Most EMI problems are caused by return path issues
— Such as lack of stitching vias, traces crossing splits,
traces near the edge
— Cannot be simulated on a system level
Usually corrected by manual PCB inspection
Classic example: Trace crossing a split

— Can model a trace crossing a split in a 3D field solver
– Will take hours of setup and simulation time (maybe longer)
– Can analyze near-field radiation pattern to find failing results
— Can use inspection to quickly find and eliminate the problem

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HyperLynx DRC
Design Rule Checks

— Automates design checks, eliminating errors from manual inspection
— Reduces days of manual design checks to a few hours
Includes built-in rules
— Design rule checks for EMI, SI, PI
– Items not quickly/easily simulated
Allows for rule customization

— Easily access database objects
through automation
— Advanced geometric operations
— Script writing/debugging environment
(Supports VBScript, JavaScript)

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Built-in script writing and debugging
Debugging environment included
— Set break points
— Add variables to watch
Interactive visualization of geometries
Advanced Geometric Engine

Access to all database objects and associated geometries
— Traces, Planes, Vias/ ICs, Pins, Connectors
Comprehensive measurement capabilities
Ability to perform advanced geometric operations
— And, Or, Xor and other logical operations on shapes
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HyperLynx DRC built-in DRCs
19 built-in DRCs included
— With editable parameters
– Adaptable to any design
EMI examples
— Traces crossing splits, reference plane changes, Board Edge shield
— Nets near edge, coupling to I/O nets
— Metal island check
w d
SI examples h
— Long nets (SI risk), termination check h
— Number of vias, shielding

PI examples Excess current
can radiate and
cause EMI/EMC
— Power net width problems
— Decoupling cap proximity

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Reference Plane Change
Purpose
Check for vertical reference plane changes.

Reference plane changes occur when a signal transitions from one layer to another,
and should be accompanied by a stitching capacitor or stitching via, to allow for a
continuous return current path and reduce the risk of common-mode radiation.
Also checks for loss of reference due to extremely large antipad.
Also (optionally) checks that the signal references the correct voltage.
Plane1
MaxAntipadLength
Prerequisites
H1
Object Lists: PowerNets, GroundNets,
Capacitors, ICs
H2
IBIS model assignment [optional]
(uses edge rate and voltage info)
Plane2
CoefAccountable DecouplingDistance
for Plane1 = H2/(H1+H2) StitchingViaDistance
for Plane2 = H1/(H1+H2)
Parameters
DecouplingDistance – Maximum allowable distance of capacitor from reference plane change
StitchingViaDistance – Maximum allowable distance of stitching via from reference plane change
DistancePercentage – Maximum allowable distance of stitching capacitors/vias expressed as
a percentage of the signal edge rate
(only used if DecouplingDistance and/or StitchingViaDistance are set to 0).
MaxAntipadLength – Maximum allowable antipad radius
CoefAccountable – Minimum required percentage of return current through a
plane for the plane to be included in the check
SignalSupplyCheck – Yes = Check that signals reference correct voltage
No = Do not check
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Filter Placement
Purpose
Check that connectors have filters placed close enough to the connector pins to be
effective at suppressing radiated emissions.
High-frequency energy can leave the system through a connector, and one method to
suppress this is to add a filter to the connector pin. This filter must be placed close
enough to the connector pin such that the trace connecting the filter to the
connector does not pick up additional noise.
Prerequisites
ControlDistance
Object Lists: Connectors, Noise Filters, Capacitors,
FerriteBeads, Inductors, Resistors,
ConstantNets
Parameters
ControlDistance – Maximum allowable distance from connector pin to all pins of the filter

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Exposed Length
Purpose
Check that critical traces are properly shielded on all sides.

Highly periodic signals, such as clocks, pose the greatest risk of creating a “spike” of
radiated energy at a specific frequency. In order to ensure this does not happen, the
signals must have continuous return current paths, and be shielded.
These signals must routed against solid planes and, especially on boards without solid
reference planes, be shielded on either side with metal, such as guard traces.
A large enough length of non-shielded trace can act as an antenna which radiates energy.
ExposedPercent = (ExposedLength * propagation velocity) / edge rate

Prerequisites
ExposedLength = L1 + L2 + L4 + L5
Object List: ConstantNets, Radiation_High
L1 L5
IBIS model assignment [optional]
(uses edge rate information) L2 L3 L4
Parameters GuardTraceMaxViaInterval
ExposedPercent – Allowable exposed net length expressed as a multiplier of signal edge rate
ExposedTraceCheckAboveandBelow – Yes = Check for reference planes above and below the net
No = Do not check for reference planes above and below
ExposedTraceCheckCoplanar – Yes = Check for guard traces/area fills on same layer as net
No = Do not check for guard traces/fills
GuardTraceDistance – Maximum allowable distance between guard trace and the net
GuardTraceViaCheck – Yes = Check for stitching vias on guard trace
No = Do not check for stitching vias on guard trace GuardTraceDistance
GuardTraceMaxViaInterval – Maximum allowable distance between stitching vias on guard trace
GuardTraceEdge2ViaDist – Maximum allowable distance between vias and guard trace edge
GuardTraceEdge2ViaDist
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Decoupling Capacitor Placement
Purpose
Check that integrated circuit (IC) components have decoupling capacitors connected close enough to the power pins to be effective.
Decoupling capacitors must provide a low-impedance path between power and ground to meet the power needs of the component.
Capacitors mounted with long traces or too far from the power pins are made less effective by the added inductance of their mounting
connections.
Prerequisites
Object Lists: ICs, PowerNets, GroundNets
Parameters
MaxSearch4CapDist – Distance from IC pin to search for capacitors
IncludeGround – Yes = include ground nets in the analysis
No = don’t include ground nets
SearchPath – Yes = finds the routed length between IC pin and capacitor
No = finds only the distance between the IC pin and capacitor
MaxCapDist – Maximum allowable length of routed connection from IC pin to capacitor
GND PWR
MaxCapDist
MaxSearch4CapDist

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Perform system simulations using SystemVision
Why System-Level Modeling?
■ System-Level modeling and
simulation enables virtual
system integration Multi-Technology Electrical
•Thermal
Analog, Digital, &
Magnetic Electro-
Mixed-Signal circuits
Mechanical Mechanical
Allows engineers to simulate multi- Hydraulic
discipline systems Sensors &
Actuators
Allows the models for these systems to
be built at any level of abstraction Control
— High-level behavioral models (VHDL- Circuits
AMS/C)
— Low-level physics-based models (VHDL- Digital
Control
AMS)
— And everything in between (SPICE) Software Micro- Control
controllers
Eldo/ADMS core simulator Embedded Control Transfer
or Supervisory functions

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CAN Bus Model & Test-bench
Stimulus
Termination
Node-4
Termination
Connector
Node-1
Transmission
Lines
Node-2 Node-3

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Digital and Analog CAN Signals
Enable
Rx Data
Diff Rx 1
Diff Rx 2
Diff Rx 3
Diff Rx 4

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Adjacent Digital and Analog Signals
Transmission Line
Model From HyperLynx

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HyperLynx Field-Solver Generated SPICE Model

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Cross-talk: Digital to Analog (time-domain)
Digital PRBS signal (“logical” vs. “electrical” views)
Analog (op-amp output) signal corrupted by crosstalk noise

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SystemVision Model Development
PSPICE Conversion Utility

— Makes PSPICE models compatible with SystemVision
SPICE format
— Access Tools menu
VHDL-AMS Model Generation Tool
— Auto-generation of VHDL-AMS model using forms
— Code Preview Window (watch model being built)
— Automatic TLU-based modeling
Datasheet Curve Modeler
— Allows piecewise linear descriptions of manufacturer
datasheet curves to be created
— Allows free-form curve data to be created
— Curve data can be used in VHDL-AMS models, or with
the Model Generation Tool (TLU)
Datasheet plug-in models

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Datasheet Curve Modeler
Enable data point
entry.
As mouse is clicked
over curve, data point
is entered into table.

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SystemVision and Simulink
The Best of Both Worlds
Example: Embedded Controller Simulation Results (SL or SV)
Cmd Stimulus
(SystemVision)
Control Algorithm (Simulink) Actuator/Load Mechanics (SystemVision)

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Get to Know HyperLynx Better
HyperLynx QuickTour introduces users to capabilities

in HyperLynx
— Audio and Video guide with demonstrations
— Quickly come up to speed on core functionality in HyperLynx SI
Hands-on with HyperLynx PI
— Mentor Virtual Labs provide guided tutorials teaching you steps to
perform PI analysis - http://go.mentor.com/hl-vlab/

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Overview of Resources
Resources are available on

— SupportNet – http://supportnet.mentor.com
— Mentor.com – http://www.mentor.com/products/pcb-system-
design/circuit-simulation/hyperlynx-signal-integrity/
Types of collateral available
— Webinars
— Whitepapers
— Application Notes
— Tech Notes
— Tutorials

www.mentor.com
Webinar Content
Overviews of various SI and PI design issues and how you

can address them with HyperLynx
Technology Specific Content
— PCIe Basics, PCIe Validation
— DDR3 Design and Validation
Understanding Tool Capabilities
— HyperLynx SI and PI Overview
— Multi-Gbps Channel Design with HyperLynx – Part 1 – Part 2
— HyperLynx Thermal Overview
— Using HyperLynx in any design flow

www.mentor.com
Webinar Content
Educational Content - SI
— Stackup Design Practices
— Transmission lines and Termination
— Learn How to Start Simulating
— Modeling Transceivers for MGbps Design
— Checking Quality of S-Parameter Models
— Controlling Crosstalk
— Managing Trace Lengths for Timing
Educational Content – PI
— Design Strategies for PCB Decoupling
— HDI’s Impact on Power Delivery
— Solving IR Drop Issues on the PCB

www.mentor.com
Whitepapers
Provide insight into Mentor technologies

— Improving Channel Characterization for BER Analysis
— Predicting BER to Low Probabilities
— S-Parameter Modeling in HyperLynx
— Correlation study on HyperLynx PI
Offer information on design challenges
— Fundamentals of Signal Integrity
— Capturing Effects of Plane Noise on Signals
— Understanding Power Delivery in PCB Design
— Addressing Fiber Weave
— Power Integrity Effects with HDI
— Effective Stackup Design

www.mentor.com
SupportNet
Reference collateral covers tool usage

and answers common questions
— How-to and Tutorial videos
— AppNotes on certain features
— TechNotes provide answers to common questions
Hop Topics include aggregated assets on topics
— Includes Tutorials, AppNotes, & TechNotes
– DDRx Design and Simulation
– Multi-Gbps Channel Simulation
– Power Integrity Analysis
– BoardSim Batch Analysis

www.mentor.com
Hot Topics Example
DDRx Design and Simulation

— Step-by-Step video tutorial
— AppNotes on
– Simulation Preparation (IBIS and Timing models)
– Setup and Running Simulations
– Analyzing Results
— Design Examples to get
started with
– Pre-Layout Planning
– Post-Layout Verification

www.mentor.com
MGC Higher Education Program
HEP started in 1985

Partnered with >1200 universities worldwide
Program Benefits
— Access to millions of $ worth of MGC s/w for minimal customer
support fee
— Free access to regular customer training for all faculty/staff
— Access to technical support services and SupportNet for faculty/
staff
Contact email: Higher_education@mentor.com

www.mentor.com
www.mentor.com

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Model, Simulate & Correlate PCB

designs using Mentor Graphics

Senior Applications Engineer

© 2010 Mentor Graphics Corp. Company Confidential

Behavior Digital Integrity

ModelSim / Questa Digital Logic

Signal Integrity (SI) Power Integrity (PI)

Boardsim (Post route) Boardsim (Post Route)

© 2010 Mentor Graphics Corp. Company Confidential

Traditional signal integrity

© 2010 Mentor Graphics Corp. Company Confidential

The Generic Design Process Education

Data sheet rules

Thermal lab Signal integrity Power delivery EMC chamber

© 2010 Mentor Graphics Corp. Company Confidential

Improved Process & Tools Education

HyperLynx HyperLynx HyperLynx

Thermal lab Signal integrity Power delivery EMC chamber

© 2010 Mentor Graphics Corp. Company Confidential

Driver Interconnect Receiver

IC modeling – primary factors

© 2010 Mentor Graphics Corp. Company Confidential

Eldo, AMS, HSPICE

– Default package data (L_pkg, R_pkg, C_pkg)

© 2010 Mentor Graphics Corp. Company Confidential

Check your Stack up and Materials to

© 2010 Mentor Graphics Corp. Company Confidential

Pre-Layout Signal Integrity Process Tools

© 2010 Mentor Graphics Corp. Company Confidential

Pre-Layout Signal Integrity Process Tools

Net Length Rule Development Education

Swept lengths from .5 to 3 inches; .5 inch increments

© 2010 Mentor Graphics Corp. Company Confidential

Pre-Layout Signal Integrity Process Tools

Series Termination Rule Development Education

Do you need a series termination resistor? HyperLynx

Swept resistor values from 10 to 65 ohms; 5 ohm increments

© 2010 Mentor Graphics Corp. Company Confidential

Pre-Layout Signal Integrity Process Tools

Cross-Talk Rule Development Education

What are the xtalk thresholds? HyperLynx

Net-class and bus rule development

Analyze same layer and adjacent layer rules CES

Swept coupling length from 1 to 10 inches; .5 inch increments

© 2010 Mentor Graphics Corp. Company Confidential

Pre-Layout Signal Integrity Process Tools

Cross-Talk Rule Development Education

© 2010 Mentor Graphics Corp. Company Confidential

Pre-Layout Signal Integrity Process Tools

Complex Topology Rule Development Education

Will you be given a complex topology?

© 2010 Mentor Graphics Corp. Company Confidential

Constraints & Routing Education

Enter your constraints into CES

© 2010 Mentor Graphics Corp. Company Confidential

Post-Layout Signal Integrity Process Tools

Net Rule Verification Education

DRC (hazards) and CES should’ve kept things in check HyperLynx SI

© 2010 Mentor Graphics Corp. Company Confidential

Post-Layout Signal Integrity Process Tools

Multiple Net Rule Verification Education

Batch mode simulation for ringing/overshoot/xtalk HyperLynx SI

© 2010 Mentor Graphics Corp. Company Confidential