3410 Lecture Notes v0.1

ECE 3410
MICROELECTRONICS I
LECTURE NOTES
Spring 2016
Chris Winstead
Associate Professor
Electrical and Computer Engineering
chris.winstead@usu.edu
Copyright © 2016
published by utah state university

department of electrical and computer engineering
http://www.ece.usu.edu
Licensed for redistribution and adaptation under the Creative Commons

Attribution-ShareAlike International 4.0 License, CC-BY-SA-4.0.
Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of Netlists . . . . . . . . . . . . . . . . . . . . . . . . . 8
List of Examples . . . . . . . . . . . . . . . . . . . . . . . . 9
List of EveryCircuit Demos . . . . . . . . . . . . . . . . . 11
Read Me 15
Introduction 17
Signal sources . . . . . . . . . . . . . . . . . . . . . . . . . 17
Ideal Amplifier Models . . . . . . . . . . . . . . . . . . . . 21
Real Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . 25
Equivalent small-signal resistance and impedance . . . . 30
Frequency Response of Amplifiers . . . . . . . . . . . . . 30
Harmonic distortion . . . . . . . . . . . . . . . . . . . . . 37
Operational Amplifier Circuits 39

Amplifiers with finite open-loop gain . . . . . . . . . . . 39
Difference amplifiers . . . . . . . . . . . . . . . . . . . . . 45
Instrumentation amplifiers . . . . . . . . . . . . . . . . . . 48
Non-Ideal Op Amp Characteristics . . . . . . . . . . . . . 50
Frequency Response of Op Amps . . . . . . . . . . . . . . 54
Slewing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Full Power Bandwidth (FPBW) . . . . . . . . . . . . . . . 60
Op Amp Integrators and Differentiators . . . . . . . . . . 61
Introduction to Diodes 67
Ideal switch model . . . . . . . . . . . . . . . . . . . . . . 67
Exponential model . . . . . . . . . . . . . . . . . . . . . . 69
Constant voltage-drop model . . . . . . . . . . . . . . . . 69
Iterative Analysis . . . . . . . . . . . . . . . . . . . . . . . 70
Linearized Model . . . . . . . . . . . . . . . . . . . . . . . 72
Diode Circuits 75
Half-Wave Rectifier . . . . . . . . . . . . . . . . . . . . . . 75
Resistor-diode regulator . . . . . . . . . . . . . . . . . . . 77
4
Peak rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Envelope detector . . . . . . . . . . . . . . . . . . . . . . . 79
Bridge Rectifier . . . . . . . . . . . . . . . . . . . . . . . . 81
Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . 83
Super Diode, Precision Rectifier . . . . . . . . . . . . . . . 87
DC Restoration, Clamped Capacitor . . . . . . . . . . . . 89
Boost converter . . . . . . . . . . . . . . . . . . . . . . . . 90
List of Figures
1 Thévenin equivalent voltage signal source. . . . . . 17

2 Norton equivalent current signal source. . . . . . . 17
3 Example FFT display on an oscilloscope. . . . . . . 17
4 A sinusoid has a single Fourier component that ap-
pears as an impulse function on the spectral repre-
sentation. In this case the magnitude is 40 dB, which
corresponds to a time-domain zero-to-peak amplitude
of 200 V. . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 Passive linear components and their equivalent Laplace-
domain impedances. . . . . . . . . . . . . . . . . . . 18
6 Low-pass configuration. . . . . . . . . . . . . . . . . 19
7 High-pass configuration. . . . . . . . . . . . . . . . . 20
8 Ideal linear voltage amplifier model at low or mid-
band frequencies. . . . . . . . . . . . . . . . . . . . . 21
9 Coupling interactions in voltage amplifiers. Resistive
voltage dividers appear at the input and output in-
terfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10 Ideal linear current amplifier model at low or mid-
band frequencies. . . . . . . . . . . . . . . . . . . . . 23
11 Coupling interactions in current amplifiers. Resistive
current dividers appear at the input and output in-
terfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12 Coupling interactions in transconductance amplifiers.
A resistive voltage divider appears at the input inter-
face and a current divider at the output interface. . 24
13 Coupling interactions in transresistance amplifiers.
A resistive current divider appears at the input inter-
face and a voltage divider at the output interface. . 24
14 DC transfer characteristic of an ideal amplifier. . . 25
15 Non-linear transfer characteristic showing non-constant
slope. The amplifier saturates when the gain falls be-
low 1 V/V. . . . . . . . . . . . . . . . . . . . . . . . . 25
6
16 Zoomed transfer characteristic showing approximately

linear behavior for small signal variations. . . . . . 26
17 Offset point of a non-linear transfer characteristic. . 26
18 Small-signal activity overlaid on the nonlinear trans-
fer characteristic. . . . . . . . . . . . . . . . . . . . . 26
19 Linear temperature sensor model. The DC offset VS
is set to zero (i.e. shorted out) for small-signal anal-
ysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
20 Small-signal equivalent temperature sensor model.
The lower-case signals vs and vout represent the vari-
ations in the corresponding physical signals. . . . . 28
21 Linearized approximation of thermistor resistance for
temperatures near 300 K . . . . . . . . . . . . . . . . 29
22 An example amplifier model showing parasitic capac-
itances. . . . . . . . . . . . . . . . . . . . . . . . . . . 30
23 General “black-box” model of a linearized amplifier
circuit. Zeros are roots of s in the numerator and poles
are roots in the denominator. . . . . . . . . . . . . . 31
24 Bode plot of a low-pass system with transfer function
1
H (s) = K ,
1 + s/ω p0
with a single pole at ω p0 and no zeros, and with gain

constant K = 104 corresponding to 80 dB. In this
example the pole is at 100 rad/s. The phase response
begins to decrease at 10 rad/s, loses 45° per decade,
and the phase change concludes at 1 × 103 rad/s. . 32
25 Bode plot of a high-pass system with transfer func-
tion
s
H (s) = K ,
1 + s/ω p0
which has a single zero at the origin, and a single pole
at 100 rad/s. The gain constant is K = 104 , corre-
sponding to 80 dB. The phase response is due to the
pole; the zero contributes no phase change since it oc-
curs at the origin. . . . . . . . . . . . . . . . . . . . 33
26 Bandpass amplifier model where coupling capacitors
CC1 and CC2 are used to reject or replace the DC off-
sets VSIG and VOUT . . . . . . . . . . . . . . . . . . . . . 34
27 Bode plot of a band-pass system with a single zero
at the origin, and two poles at 100 rad/s and 1 × 106 rad/s
. The gain constant is K = 104 , corresponding to
80 dB. The phase response is due to the two poles, ap-
proaching −180° at higher frequencies. . . . . . . . 35
7
28 Harmonic “spurs” appear at integer multiples of the

fundamental frequency, and represent distortion. . 37
29 Operational amplifier symbol . . . . . . . . . . . . . 39

30 Inverting op amp configuration . . . . . . . . . . . . 40
31 Non-inverting amplifier configuration . . . . . . . . 42
32 Voltage follower configuration . . . . . . . . . . . . 44
33 Difference amplifier configuration . . . . . . . . . . 45
34 Instrumentation amplifier configuration . . . . . . . 48
35 Inverting configuration showing bias-current sources. 50
36 Inverting configuration showing input offset voltage
source. . . . . . . . . . . . . . . . . . . . . . . . . . . 52
37 Saturation due to offset voltage . . . . . . . . . . . . 52
38 Standard op amp frequency response . . . . . . . . 54
39 Closed-loop frequency response . . . . . . . . . . . 56
40 Slew-rate distortion in an op amp circuit. . . . . . . 58
41 Generalized inverting configuration with complex impedances. 61
42 Ideal Miller integrator. . . . . . . . . . . . . . . . . . 61
43 Idealized capacitive inverting configuration. . . . . 61
44 Practical capacitive configuration with DC bypass re-
sistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
45 Practical capacitive configuration with switched DC
bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . 62
46 The two switching phases of a capacitive inverting
configuration. . . . . . . . . . . . . . . . . . . . . . . 62
47 Miller integrator with DC bypass resistor R F . . . . . 64
48 Miller integrator with switched DC bypass. . . . . . 64
49 Diode symbol and notation. . . . . . . . . . . . . . . 67

50 Diode max-value circuit. . . . . . . . . . . . . . . . . 68
51 Diode min-value circuit. . . . . . . . . . . . . . . . . 68
52 Diode transfer characteristic. The current increases
very rapidly when v D ≈ 0.7 V. . . . . . . . . . . . . 69
53 Iterative solution for resistor-diode series configura-
tion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
54 Linearized diode model. . . . . . . . . . . . . . . . . 72
55 Iterative solution of linearized model parameters. . 72
56 Iterative solution of the resistor-diode series config-
uration using the linearized model. . . . . . . . . . 73
57 Half-wave rectifier circuit. . . . . . . . . . . . . . . . 75

58 Behavior of the half-wave rectifier. The ideal switch
model is compared to the more accurate constant-0.7 V
drop model. . . . . . . . . . . . . . . . . . . . . . . . 75
59 Linearized model of half-wave rectifier. . . . . . . . 76
8
60 Single-diode regulator circuit. . . . . . . . . . . . . . 77

61 Diode regulator simulation . . . . . . . . . . . . . . 77
62 Linearized model of the single-diode regulator. . . 77
63 Current delivered into the capacitor in the peak de-
tector circuit. . . . . . . . . . . . . . . . . . . . . . . . 79
64 Envelope detector circuit. . . . . . . . . . . . . . . . 79
65 Behavior of the envelope detector circuit. . . . . . . 79
66 Full wave bridge rectifier circuit. . . . . . . . . . . . 81
67 A four-diode voltage regulator. . . . . . . . . . . . . 83
68 Small-signal equivalent circuit model of the four-diode
2.8 V regulator. . . . . . . . . . . . . . . . . . . . . . . 83
69 Behavior of the four-diode regulator from SPICE sim-
ulation. . . . . . . . . . . . . . . . . . . . . . . . . . . 85
70 Zoomed view of the ripple voltage on vOUT . . . . . 86
71 Precision rectifier circuit with op amp feedback. . . 87
72 Clamped capacitor circuit. . . . . . . . . . . . . . . . 89
73 Behavior of DC restorer (clamped capacitor) circuit
simulated in SPICE. . . . . . . . . . . . . . . . . . . . 89
74 Idealized boost converter circuit. . . . . . . . . . . . 90
75 Output voltage from the boost converter when initial-
ized at zero. . . . . . . . . . . . . . . . . . . . . . . . 91
List of Netlists
1 envelope_detector.sp . . . . . . . . . . . . . . . . . . 80
2 bridge_rectifier.sp . . . . . . . . . . . . . . . . . . . . 82
3 basic_regulator.sp . . . . . . . . . . . . . . . . . . . . 85
4 superdiode.sp . . . . . . . . . . . . . . . . . . . . . . 88
5 741.sp (top lines showing port order) . . . . . . . . 88
6 dc_restorer.sp . . . . . . . . . . . . . . . . . . . . . . 90
diodes/boost_converter.sp . . . . . . . . . . . . . . . . . . 91
List of Examples
1 Low-pass RC circuit . . . . . . . . . . . . . . . . . . . . . 19
2 High-pass RC circuit . . . . . . . . . . . . . . . . . . . . . 19
3 Linearization of a sensor . . . . . . . . . . . . . . . . . . . 27
4 Linearization of a thermistor model . . . . . . . . . . . . 28
5 Bias current in inverting configuration . . . . . . . . . . . 50
6 Maximum resistance due to Ibias . . . . . . . . . . . . . . 50
7 Inverting configuration with offset voltage . . . . . . . . 52
8 Closed-loop frequency response, low-gain . . . . . . . . 56
9 Closed-loop frequency response, high-gain . . . . . . . . 56
11 Max-Value Circuit . . . . . . . . . . . . . . . . . . . . . . . 68
12 Min-Value Circuit . . . . . . . . . . . . . . . . . . . . . . . 68
13 Min-value circuit with 0.7V drop model . . . . . . . . . . 69
14 Iterative analysis . . . . . . . . . . . . . . . . . . . . . . . 70
15 Iteration with linearized model . . . . . . . . . . . . . . . 73
16 Half-wave rectifier with vin < 0 . . . . . . . . . . . . . . . 75
17 Half-wave rectifier with vin = 1V . . . . . . . . . . . . . . 75
18 Four-diode voltage regulator design . . . . . . . . . . . . 83
19 Two Diode Regulator with Op Amp Buffer . . . . . . . . 86
List of EveryCircuit Demonstrations
2 Ideal Voltage Amplifier . . . . . . . . . . . . . . . . . . . . 21

4 Ideal Band-Pass Amplifier Model . . . . . . . . . . . . . . 35
6 Capacitive Coupling . . . . . . . . . . . . . . . . . . . . . 36
8 Inverting configuration . . . . . . . . . . . . . . . . . . . . 41
10 Non-inverting configuration . . . . . . . . . . . . . . . . . 43
12 Voltage follower configuration . . . . . . . . . . . . . . . 44
14 Difference amplifier (differential mode) . . . . . . . . . . 45
16 Non-inverting circuit with bias and offset . . . . . . . . . 52
18 Closed-loop frequency response . . . . . . . . . . . . . . 57
Read Me
These lecture notes are intended as a companion for Sedra and

Smith’s Microelectronic Circuits. The order of topics contained in
these notes should roughly correspond to the lecture presenta-
tions in ECE 3410 at Utah State University.
We will make use of two software applications for simulating
electronic circuits:
• The EveryCircuit Simulator is a very simple application
for drawing schematics and simulating basic circuits. It is
available as an app for iOS and Android devices, and can
be used as a web-based application on desktop and laptop
computers. A class license is available so that you can use
EveryCircuit for free. The license code will be posted on
Canvas. Throughout these notes you will find EveryCircuit
demonstrations. You can directly access these demonstrations
by clicking on the link in the title of each demonstration.
Note: you will need to use Google Chrome to run the web
demonstrations. EveryCircuit is a very convenient tool that
allows you to rapidly test out course concepts and design
ideas, and is strongly recommended for this course.
• The NGSpice Simulator is a free, open-source implemen-

tation of the classic Berkeley SPICE software, which is the
ancestor of all modern electronic simulation software. Al-
though Berkeley SPICE was first developed in 1973 (see
the overview of SPICE history at Wikipedia), it continues
to be maintained and updated to the present day, and new
research ideas are periodically incorporated into its code.
SPICE therefore represents both the history and the state-of-
the-art in electronic design. NGSpice is able to run on Linux,
Mac and Windows platforms, and is free to use. While SPICE
is a little harder to use than EveryCircuit, we will see that
it is vastly more powerful and there are many circuits and
analyses that can’t be done at all in EveryCircuit.
You will also need to familiarize yourself with the Linux
16
operating system as it is widely used in the electronics and

semiconductor industries, especially for cutting-edge design
of micro- and nano-scale integrated circuits and systems. If
you want to make chips, you have to do it in Linux. Our lab
sessions will make use of the Linux-based Design Automation
Lab (DAL) and you will have an opportunity to get introduced
to Linux and do some tutorials during the first two weeks of the
semester.
It is not mandatory to use these notes, but you will likely
find a lot of benefit to studying the examples and alternative
explanations here in addition to reading the textbook. These
notes will be updated frequently as I add more examples and
sections.
Introduction
Rsig
Signal sources +
+
vsig −
Electronic circuits and systems can be loosely divided into two
classes: those that process signals, which are electrical repre- −
sentations of information, and those that convey or convert Figure 1: Thévenin equivalent voltage signal source.
electrical power. In this course we are primarily concerned with
circuits that process signals, in the broadest possible sense. A
signal may convey physical information, e.g. an audio signal +
produced from a microphone, or it may convey discrete or vsig Rsig

digital information as part of a computational process. Regard-
less of the context, we will always view signals as electrical −
information, either a current or voltage. Figure 2: Norton equivalent current signal source.
A transducer is a device that converts a physical signal into
an electrical one. From the circuit perspective, we usually model1
a transducer as either a voltage source or a current source. 1
A model is a useful approximation of a physical
Every signal source has an associated internal impedance, device or system. We use models to simplify our
understanding of complex electronic components.
represented by Thévenin or Norton equivalent circuits.
Spectrum and Frequency Response

Most information-bearing signals are not constant. A signal x (t)
that changes over time can be represented as a superposition
of sinusoidal signals with various magnitudes, frequencies
and phases. The function that characterizes the magnitudes
and phases at each frequency is called the signal’s complex-
valued Fourier spectrum, written X ( jω ). The theory of spectral
transforms is quite sophisticated, but in this course we mostly
require a simplified version known as the steady-state. For our
purposes, we may consider the Laplace transform X (s) to be
equivalent to the Fourier spectrum, with s = jω.
On a modern digital oscilloscope, a signal’s spectrum can be
viewed by selecting a Fast Fourier Transform (FFT) display,
which reports the signal’s magnitude spectrum, equal to the
complex magnitude | X ( jω )|. Since X ( jω ) is a complex function,
Figure 3: Example FFT display on an oscilloscope.

18 ece3410 lecture notes
the magnitude is obtained as
| X ( jω )|2 = X ( jω ) × X ∗ ( jω ).
The magnitude spectrum is typically expressed in units of 40
decibels, and the complex phase ∠X ( jω ) is usually expressed
VS (s) (dB)
in degrees (0◦ to 360◦ ).
The individual sinusoidal signal components are expressed 20
as
v a (t) = VA sin (ω0 t + φ) ,
0
where VA is the zero-to-peak amplitude, ωs is the signal fre- 101 102 103 104 105
quency in radians per second, t is the time in seconds, and φ is ω (rad/sec)
the phase-shift in radians. Figure 4: A sinusoid has a single Fourier component
A pure or single-tone sinusoid has a magnitude spectrum that appears as an impulse function on the spectral
representation. In this case the magnitude is 40 dB,
represented by a single impulse function which corresponds to a time-domain zero-to-peak
amplitude of 200 V.
1
VA (ω ) = V δ ( ω − ωs ) .
2 A
The impulse height in decibels is 20 log10 (VA /2). So a zero-to-
peak magnitude of 1 V corresponds to −6 dB, 10 V corresponds
to 14 dB, 100 V corresponds to 34 dB, and so on. Frequency Units:
When signals pass through electronic circuits, their magni- • ω = 2π f
tude and phase are altered. The circuit’s transfer function is the • f is in Hz (cycles per second)
ratio of the output spectrum to the input spectrum. If a circuit’s • ω is in radians per second.
input is X (s) and its output is Y (s), then the transfer function is • ω is “omega”, not w.
• A magnitude V in dB is 20 log10 (V )
Y (s)
H (s) = . • A power P in dB is 10 log10 ( P).
X (s)
We may interpret the transfer function in terms of frequency by

substituting s = jω. The transfer function’s magnitude response
is usually expressed in decibels as
| H (ω )| (dB) = 20 log10 | H (ω )|
= 10 log10 | H (ω )|2 .
When expressed in decibels, the magnitude reveals useful in- R R

formation about the circuit. When | H (ω )| = 0 dB, the output’s
amplitude is equal to the input. When | H (ω )| is positive, the
output’s amplitude is greater than the input, and the circuit is
C 1
said to have gain. When | H (ω )| is negative, the output’s ampli- Cs
tude is less than the input, and the circuit is said to attenuate
the signal.
For a linear circuit, the transfer function is obtained using
complex impedances for capacitors and inductors. A capacitor L Ls
with capacitance C has impedance 1/(sC ), and an inductor with
Figure 5: Passive linear components and their
equivalent Laplace-domain impedances.
introduction 19
inductance L has impedance sL. Once components are replaced

by their equivalent impedances, they can be analyzed as though
they were resistors where the resistance values are polynomials
in s.
Example 1 (Low-pass RC circuit).
The low-pass configuration is like a simple voltage divider. The

impedances are Z1 = R and Z2 = 1/sC. Then R
VIN (s) VOUT (s)
Z2
VOUT (s) = VIN (s)
Z1 + Z2 1/sC
VOUT (s) 1/sC
⇒ H (s) = =
VIN (s) R + 1/sC
Figure 6: Low-pass configuration.
1
=
1 + sRC
The low-pass transfer function is commonly represented as
1
H ( jω ) =
1 + jω/ω3dB
. The magnitude response is then

2 1 1
| H (ω )| =
1 + jω/ω3dB 1 − jω/ω3dB
!
1
= 2
1 + ω 2 /ω3dB
At low frequencies where ω ω3dB , the magnitude response is flat, approximately equal to one. At
higher frequencies where ω ω3dB , the magnitude drops rapidly. At these high frequencies, since
ω/ω3dB 1, we can make an approximation:
ω/ω3dB + 1 ≈ ω/ω3dB
⇒ | H (ω )| ≈ ω3dB /ω (high frequencies above ω3dB )
When represented in decibels, we find that

ω
3dB
| H (ω )| ≈ 20 log10
ω
= 20 log10 ω3dB − 20 log10 ω.
So as ω increases, the magnitude decreases by 20 dB per decade.

Example 2 (High-pass RC circuit).
The high-pass configuration has impedances are Z1 = 1/sC and Z2 =

R. Then 1/sC
VIN (s) VOUT (s)

Z2
VOUT (s) = VIN (s)
Z1 + Z2
R
VOUT (s) R
⇒ H (s) = =
VIN (s) R + 1/sC
sRC Figure 7: High-pass configuration.
=
1 + sRC
The high-pass transfer function is commonly represented as
jω/ω3dB
H ( jω ) =
1 + jω/ω3dB
. The magnitude response is then
− jω/ω3dB

jω/ω3dB
| H (ω )|2 =
1 + jω/ω3dB 1 − jω/ω3dB
!
ω 2 /ω3dB
2
= 2
1 + ω 2 /ω3dB
At high frequencies where ω ω3dB , the magnitude response is flat, approximately equal to one. At
lower frequencies where ω ω3dB , the magnitude drops rapidly. Since ω/ω3dB 1, we can make
an approximation:
ω/ω3dB + 1 ≈ 1
⇒ | H (ω )| ≈ ω/ω3dB (low frequencies below ω3dB )
When represented in decibels, we find that

ω
| H (ω )| ≈ 20 log10
ω3dB
= 20 log10 ω − 20 log10 ω3dB .
So as ω increases from very low frequencies, the magnitude increases by 20 dB per decade.
A note on approximations: in these examples we used a

If A B then:
very common method of large-value approximation. We will
use this procedure many times. Suppose two quantities A and A+B ≈ A
1 1 1
B differ greatly in value, so that A B. The notion of “much + ≈
A B B
greater than” is somewhat fuzzy, but in this course we will A
≈1
define it as more than a 10× difference between two quantities. A+B
B B
≈
A+B A
and so on...
introduction 21
Rout
Ideal Amplifier Models + +
+
An ideal linear amplifier is a circuit which receives an input vin Rin Av vin − vout
signal X and produces an output signal Y = AX. In other
− −
words, the output is larger than the input by a constant multiple
Figure 8: Ideal linear voltage amplifier model at low
A, called the gain. The input/output signals can be either or mid-band frequencies.
current or voltage, which introduces four possible amplifier
configurations:
Input Output Amplifier Type Gain Name and Symbol

Voltage Voltage Voltage Amplifier Gain Av
Current Current Current Amplifier Gain Ai
Voltage Current Transconductance Amplifier Transconductance Gm
Current Voltage Transresistance Amplifier Transresistance Rm
In order to use an amplifier, it has to be connected to its

signal source on the input side and its load on the output side.
This creates a coupling interaction between the amplifiers
internal resistances and the neighboring signal resistances. In
the voltage amplifier, we see a voltage-divider effect at both the
input and output interfaces:
Rsig Rout
+ +
Rin

vIN = vSIG
+ Rin + Rsig
vsig +
− vin Rin Av vin − vout RL
RL
vOUT = Av vIN
Rout + R L
− −
Figure 9: Coupling interactions in voltage amplifiers.

Resistive voltage dividers appear at the input and
As a result the complete system is described by the gain output interfaces.
equation in combination with the coupling divider ratios. To

describe this effect, we distinguish the open-circuit gain from
the loaded gain:
vOUT
open-circuit gain: Avo , = Av
vIN

vOUT Rin RL
loaded gain: AvL , = Av .
vIN Rin + Rsig Rout + R L
To maximize the amplifier’s gain, we want to eliminate the

coupling ratios by making them very close to one. This is Maximum gain in voltage amp: Rout R L and
achieved when the amplifier has large input resistance and a Rin Rsig . In the limit, a truly ideal voltage amp has
Rin → ∞ and Rout → 0.
small output resistance.
EveryCircuit Demonstration 2 (Ideal Voltage Amplifier).
This demonstration implements the ideal voltage amplifier model from Figure 9 with Rsig , Rin , Rout and
R L all equal to 1 kΩ, and a voltage gain Av = 10 V/V. The simulation traces show an attenuation by
half at each signal port due to the voltage-divider couplings.
Exercise: Increase Rin to 10 kΩ and then 100 kΩ, and observe what happens to the amplitude of vin
compared to vsig for these values. Then do the same for R L . You should notice that the coupling
effects disappear when R L Rout and Rin Rsig . Verify that your observations match the value of the
loaded gain predicted by our analysis in this section.
introduction 23
iin iout
The ideal linear current amplifier is very similar to the
voltage amplifier, except that we get current dividers instead of
voltage dividers at the input and output terminals. In a current vsig Rin Ai iin Rout load
divider, the opposite resistance appears in the numerator, so the
conditions for achieving maximum are reversed.
For current amplifiers, the most ideal gain is called the short-
circuit gain Ais , since we can eliminate the coupling ratios by Figure 10: Ideal linear current amplifier model at low
setting R L to zero, hence short-circuiting the output. The gain or mid-band frequencies.
expressions for a current amplifier are:
iOUT
short-circuit gain: Ais , = Ai
iIN

i Rsig Rout
loaded gain: AiL , OUT = Ai .
iIN Rin + Rsig Rout + R L
Maximum gain in current amp: Rout R L and
To maximize the current amplifier’s gain, we want to elimi- Rin Rsig . In the limit, a truly ideal current amp has
nate the coupling ratios by making them very close to one. This Rin → 0 and Rout → ∞.
is achieved when the amplifier has small input resistance and

a large output resistance, the opposite of what we found for
voltage amplifiers.
iin iout

Rsig
iIN = vSIG
Rin + Rsig
isig Rsig Rin Ai iin Rout RL
Rout

iOUT = Ai iIN
Rout + R L
Figure 11: Coupling interactions in current amplifiers.

Resistive current dividers appear at the input and
output interfaces.
The remaining amplifier types are mixtures of voltage and

current amplifiers. The transconductance amplifier takes Transconductance amplifiers are especially important
voltage input and delivers a current output. Then we see a since they are the basis of transistor device models.
voltage divider at the input interface and a current divider at

the output interface/
Rsig iout
+
Rin

vIN = vSIG
Rin + Rsig
vsig +
− vin Rin Gm vin Rout RL
Rout
iOUT = Gm vIN
Rout + R L
−
Figure 12: Coupling interactions in transconductance

amplifiers. A resistive voltage divider appears at the
For the transconductance amplifier, the gain expressions are:
input interface and a current divider at the output
iOUT interface.
short-circuit gain: Gms , = Gm
vIN

i Rin Rout
loaded gain: GmL , OUT = Gm .
vIN Rin + Rsig Rout + R L
Maximum gain in transconductance amp: Rout R L
To maximize the transconductance amplifier’s gain, we want and Rin Rsig . In the limit, a truly ideal transconduc-
to eliminate the coupling ratios by making them very close tance amp has Rin → ∞ and Rout → ∞.
to one. This is achieved when the amplifier has large input

resistance and a large output resistance.
Lastly, The transresistance amplifier takes current input and
delivers a voltage output. Then we see a current divider at the
input interface and a voltage divider at the output interface/
iin Rout
+
Rsig

iIN = vSIG
+ Rin + Rsig
isig Rsig Rin Rm iin − vout RL
RL

vOUT = Rm iIN
Rout + R L
−
Figure 13: Coupling interactions in transresistance

amplifiers. A resistive current divider appears at the
For the transresistance amplifier, the gain expressions are:
input interface and a voltage divider at the output
vOUT interface.
open-circuit gain: Rmo , = Rm
iIN

vOUT Rsig RL
loaded gain: RmL , = Rm .
iIN Rin + Rsig Rout + R L
Maximum gain in transresistance amp: Rout R L
To maximize the transresistance amplifier’s gain, we want to and Rin Rsig . In the limit, a truly ideal transconduc-
eliminate the coupling ratios by making them very close to one. tance amp has Rin → 0 and Rout → 0.
This is achieved when the amplifier has small input resistance

and a small output resistance, the opposite of what we found
for transconductance amplifiers.
introduction 25
Real Amplifiers Ideal Linear Amplifier
Real amplifiers are affected by nonlinear transfer characteris- 100 Output

tics between the input and the output.
Input
The ideal transfer characteristic is a straight line, extend-
−10 10
ing from −∞ to +∞ with a constant slope. The gain of this
amplifier is the slope of its transfer characteristic: −100
Figure 14: DC transfer characteristic of an ideal
dv amplifier.
Gain , OUT .
dvIN
Real amplifiers do not exhibit such ideal behavior. A more real-

istic transfer characteristic is a curve that saturates at maximum
and minimum values of vOUT , with a non-constant slope in
between.
100 Output 100 Gain
Input Input
−15 −10 −5 5 10 15 −15 −10 −5 5 10 15
−100 −100
Figure 15: Non-linear transfer characteristic showing

non-constant slope. The amplifier saturates when the
Since the slope varies, the gain is non-constant. This introduces gain falls below 1 V/V.
distortion into the signal being amplified. Due to this nonlinear
behavior, we are unable to use linear circuit methods to analyze
the amplifier system. As a result, analysis and design can
become very complex tasks. To simplify our understanding of
nonlinear systems, we rely on the concepts of linearization and
small-signal analysis.
A linearized model is a direct application of the first-order
Taylor series approximation. For a non-linear function f ( x ), the
Taylor approximation is defined around an offset x0 as

∂ f
f ( x ) ≈ f ( x0 ) + ( x − x0 ) .
∂x x0
= f 0 + A ( x − x0 )
This approximation is only valid for small variations, i.e. when

| x − x0 | is small (the meaning of “small” here is fuzzy; the
variation is considered small enough if the approximation is
sufficiently accurate for our needs). The Taylor approximation
can be interpreted as zooming-in on the original function, such
that the zoomed portion is a nearly straight line:
Real Non-Linear Amplifier Zoomed Non-Linear Amplifier

10
Output Output
100
5
Input Input
−15 −10 −5 5 10 15 −1 −0.5 0.5 1
−5
−100
−10
Figure 16: Zoomed transfer characteristic showing
approximately linear behavior for small signal
Small-signal equivalent circuit models variations.
The Taylor linearization reveals an extremely useful aspect of

linearized circuits: thanks to the principle of superposition, we
can separate the circuit’s behavior into two parts: the DC offset
or bias point x0 , f 0 and the small signal variation ( x − x0 ). In
the circuit context, the transfer characteristic shows the large-
signal relationship between two signals vIN and vOUT . We
VOUT Q Point,
refer to these as the total instantaneous signals, i.e. the precise Bias Point,
physical signal value at an instant in time. DC Offset
For non-linear circuits, it is often difficult to analyze the total VIN
instantaneous signal, so we split it into a superposition of two
parts:
DC offset – the central or average value of a signal; what you

would measure on an oscilloscope as the signal’s MEAN. We Figure 17: Offset point of a non-linear transfer
write DC offsets using all capital letters, as in VIN or VOUT. characteristic.
Small-signal – the amount by which the signal varies from the

offset; what you would measure on an oscilloscope set to AC
vOUT = VOUT + vout
Coupling. We write small-signal quantities in all-lowercase,
as in vin or vout .
Total Instantaneous Small Signal
Total instantaneous signal – the superposition of the offset and Signal DC part part
small signal; what you would measure on an oscilloscope
set to DC coupling. We write the total instantaneous signal
using lowercase letters with uppercase subscripts, as in vIN or
vOUT .
vout
The uppercase/lowercase notation is useful to keep track of
our separate analysis domains, but is not entirely perfect. For
example, we also use uppercase symbols to represent sinusoidal
amplitudes, which can sometimes create ambiguity. To help
distinguish these quantities, we will try and use calligraphic vin
font for sinusoidal amplitudes, as in VA .
Figure 18: Small-signal activity overlaid on the

nonlinear transfer characteristic.
introduction 27
Procedure for small-signal analysis

When analyzing a linearized circuit, we often want to analyze
just the signals, without being distracted by their DC offsets.
We want to know, for example, the AC amplitude and phase
shift of signals at various points in a circuit. The principle of
superposition allows us to extract the small-signal behavior by
following these steps:
1. Solve the circuit’s DC operating point. In many cases we

may only need to find part of the DC solution in order to do
the next step.
2. Linearize the circuit by applying a Taylor approximation

centered at the DC operating point.
3. Replace any non-linear components with their linearized

equivalents.
4. Set all DC independent sources (both current and voltage)

to zero. Voltage sources become short-circuits, and current
sources become open-circuits. Note: do not modify any
time-varying or dependent sources.
Example 3 (Linearization of a sensor).
A temperature sensor provides a change of 2mV per ◦ C, connected to a load of 10kΩ. The output
changes by 10mV when T is changed by 10◦C. What is the source resistance of the sensor?
The sensor model is linearized:

dvS RS
vs = VS + ∆T +
dT T0
where T0 is the reference temperature and ∆T is the variation vs

from that temperature. To consider only the variation in vOUT ,
we isolate the small signal portion: RL vOUT
0
dvS
∆T
+
vout = VS −
dT T0
The problem statement tells us that −

Figure 19: Linear temperature sensor model.
dvS
= 2mV/ ◦C The DC offset VS is set to zero (i.e. shorted
dT T0 out) for small-signal analysis.
It also tells us that vout = 10 mV, so we can solve for RS :

RS
RL +
vout = vs
R L + RS
RL
= (2 mV/ ◦C) (10 ◦C) vs RL vout
R L + RS
(2 mV/ ◦C) (10 ◦C) R L
→ RS = − RL −
vout
Figure 20: Small-signal equivalent tempera-
= 10 kΩ ture sensor model. The lower-case signals
vs and vout represent the variations in the
corresponding physical signals.
introduction 29
Example 4 (Linearization of a thermistor model).
A thermistor is modeled by the Steinhart-Hart equation:

−B 1 1
T0 − T
R = R0 e
where R0 and T0 are reference measurements, T and

T0 are in Kelvin, and B is a device-specific parame- ·104
1.02
ter. For small temperature changes (e.g. changes in a Actual
room’s temperature), we can approximate this using a Linearized
linearized model centered around T0 : 1.01
R (Ω)
1

d − B T1 − T1
R ≈ R0 + ∆T

R0 e 0
dT
T =T
0
− B T1 − T1 d 1 1 0.99
= R0 + ∆T R0 e

0 −B −
dT T0 T
T = T0
! 280 290 300 310 320
B
= R0 − ∆TR0 T (Kelvin)
T02
Figure 21: Linearized approximation of thermistor
resistance for temperatures near 300 K
So if T0 = 300 K , R0 = 10 kΩ and B = 50 K−1 , then for
temperatures near 300 K we have
R ≈ 10 kΩ − ∆T × 5.5 Ω
So we should see a difference of about 5.5 Ω/K. To

check the accuracy of this approximation, we can compare the actual (nonlinear) equation to the
linearized result, as shown in Figure 21. Note that the accuracy is best for very small ∆T, and the
error begins to grow as |∆T | increases.
Equivalent small-signal resistance and impedance
In example 3 we determined the series internal resistance of a

temperature sensor. Since this resistance affected the sensor’s
incremental or differential behavior, we can refer to it as a
small-signal resistance. By definition, a small-signal resistance
is the ratio of the small change in current in a branch that
results from a small change in voltage across the corresponding
terminals. This can be stated mathematically in a few different
ways:

∂v X
large-signal definition: r X =
∂i X DC
vx
small-signal definition: =
ix
From this definition we can define an analysis procedure for

determining a circuit’s small-signal equivalent resistance:
1. Linearize the circuit and obtain the small-signal equivalent

model.
2. Set any independent signal sources to zero.
3. Insert a test voltage source v x across the terminals of interest.
4. Solve the current i x that flows through the test source v x .

vx
5. The equivalent resistance is r x = ix .
Note that this procedure only works for small-signal models.

Do not use the large-signal ratio v X /i X !
Frequency Response of Amplifiers
Every circuit has a frequency response. At the very least, there

is a hidden capacitance between every pair of nodes, called the
parasitic capacitance. These capacitances introduce multiple
poles and zeros into the circuit’s frequency response.
Rsig Cf
Rout
+ +
+
vsig +
− vin Cin Rin Av vin − Cout vout RL
− −
Figure 22: An example amplifier model showing

parasitic capacitances.
introduction 31
The general “ZPK” form of the transfer response is
∏k (1 − s/ωzk )
H (s) = K
∏m 1 − s/ω pm

where ωzk are the zeros, indexed by k and ω pm are the poles, + +
indexed by m. In this course we will concern ourselves almost
VY (s) vy
exclusively with “simple” poles and zeros in the left half-plane. vX H (s) = VX (s)
In other words, we’ll assume that all poles and zeros are real-
valued (not complex or imaginary), are all well separated (they − −
do not overlap in value), and are negative valued. If these
conditions are satisfied, then we can use a simplified “stick- Figure 23: General “black-box” model of a linearized
amplifier circuit. Zeros are roots of s in the numera-
figure” method to produce approximate magnitude and phase tor and poles are roots in the denominator.
response diagrams, which are called Bode plots.
Low-pass systems
For every pole ω pm , the magnitude decreases by 20 dB per
decade at frequencies above the pole. The phase response
decreases by 90° between the frequencies 0.1ω pm and 10ω pm ,
and crosses −45° at ω pm .
100
ω p0
Gain Magnitude (dB)
-20dB/decade
50
100 101 102 103 104 105 106 107 108 109
0
45◦ Phase Loss
Phase (°)
−50
−100
100 101 102 103 104 105 106 107 108 109
Frequency
Figure 24: Bode plot of a low-pass system with

transfer function
1
H (s) = K ,
1 + s/ω p0
with a single pole at ω p0 and no zeros, and with gain
constant K = 104 corresponding to 80 dB. In this
example the pole is at 100 rad/s. The phase response
begins to decrease at 10 rad/s, loses 45° per decade,
and the phase change concludes at 1 × 103 rad/s.
introduction 33
High-pass systems
For every zero ωzk , the transfer function increases by 20 dB
per decade at frequencies above the pole. The phase response
increases by 90° between the frequencies 0.1ω pm and 10ω pm ,
and crosses −45° at ω pm .
In high-pass systems, there is usually a zero at the origin.
In that case, there is no phase response associated with the
zero (it occurs at infinitely low frequency on the logarithmic
scale), and the zero must be canceled by one or more poles at
higher frequencies. On the Bode plot, the magnitude response
reaches its maximum value and becomes constant after the first
pole, ω p0 . For frequencies below ω p0 , the magnitude response
decreases by 20 dB per decade.
100
ω p0
+20dB/decade
Gain Magnitude (dB)
50
100 101 102 103 104 105 106 107 108 109
0
45◦ Phase Loss
Phase (°)
−50
−100
100 101 102 103 104 105 106 107 108 109
Frequency
Figure 25: Bode plot of a high-pass system with

transfer function
s
H (s) = K ,
1 + s/ω p0
which has a single zero at the origin, and a single
pole at 100 rad/s. The gain constant is K = 104 ,
corresponding to 80 dB. The phase response is due to
the pole; the zero contributes no phase change since
it occurs at the origin.
Band-pass systems
Many circuit’s exhibit a mix of high-pass and low-pass char-

acteristics. We will especially see this in circuits that use ca-
pacitive coupling to separate the DC offset from an AC small
signal. In a bandpass system, the transfer function’s magnitude
is highest for middle frequencies between two pole frequencies
ω L and ω H . This zone is referred to as the circuit’s mid-band or
pass band.
A typical band-pass amplifier model is shown below. The
signal source has a DC offset voltage VSIG , which is usually
undesirable since it will be amplifier along with the signal. In
order to amplify just the signal, the offset is rejected by using
a coupling capacitor CC1 to create a high-pass response at the
input. The amplifier’s output similarly has an undesired DC
offset VOUT , which is rejected using the coupling capacitor CC2 .
Rsig CC1 Rout

+ +
+
vsig Av vin −
vin Rin Cout vout RL

+ +
VSIG − VOUT −
− −
Figure 26: Bandpass amplifier model where coupling

capacitors CC1 and CC2 are used to reject or replace
To analyze the bandpass circuit, we replace capacitors by the DC offsets VSIG and VOUT .
their Laplace domain equivalent impedances. We then have

sCC1 Rin
vin = vsig
1 + sCC1 ( Rin + Rsig )

RL
vout = Av vin
R L + Rout + sCout Rout R L

sCC1 Rin RL
= vsig Av
1 + sCC1 ( Rin + Rsig ) R L + Rout + sCout Rout R L
The transfer function is
vout
H (s) =
vsig

RL sCC1 Rin
= Av
R L + Rout (1 + sCC1 ( Rin + Rsig )) (1 + sCout ( R L k Rout ))
In this case there is a zero at the origin and two poles located at
introduction 35
two frequencies:
1
ω p0 =
CC1 ( Rin + Rsig )
1
ω p1 =
Cout ( R L k Rout )
Under ideal conditions, the voltage amplifier should have

very high Rout which places ω p0 at a low frequency, and it
should have a very low Rout which places ω p0 at a high fre-
quency. Since there is a zero at the origin, the magnitude rises
by 20 dB per decade for frequencies below ω p0 , and then be-
comes flat between ω p0 and ω p1 . For frequencies higher than
ω p1 the magnitude falls by 20 dB per decade.
100
ω p0 ω p1
Gain Magnitude (dB)
+20dB/decade -20dB/decade
50
midband
100 101 102 103 104 105 106 107 108 109
0
45◦ Phase Loss
→ 90◦ Phase Loss
−50
Phase (°)
−100
135◦ Phase Loss
−150
→ 180◦ Phase Loss
100 101 102 103 104 105 106 107 108 109
Frequency
Figure 27: Bode plot of a band-pass system with a

single zero at the origin, and two poles at 100 rad/s
and 1 × 106 rad/s . The gain constant is K = 104 ,
corresponding to 80 dB. The phase response is
due to the two poles, approaching −180° at higher
frequencies.
EveryCircuit Demonstration 4 (Ideal Band-Pass Amplifier Model).
This demonstration shows an implementation of the band-pass model from Figure 26. Examine this
circuit and perform both AC simulations (frequency mode) and transient simulations (time mode).
Try increasing and decreasing both CC1 and Cout by 10× (for a total of four different cases), and
observe how the pole frequencies change. Verify that the observations match the predictions from our
analysis in this section.
EveryCircuit Demonstration 6 (Capacitive Coupling).
This capacitive coupling demonstration shows how we can remove a signal’s DC offset and replace
it with a different offset. The circuit works through superposition of high-pass and low-pass signal
paths. The input AC signal has an offset of 10 V and a zero-to-peak amplitude of 1 V. At the out-
put, the original offset is rejected by the coupling capacitor. A new offset of 1 V is provided by an
independent DC voltage source, and is superimposed through the 1 kΩ resistor on the output side.
introduction 37
Harmonic distortion
40
When a pure sinusoid is input to perfectly linear amplifier, the
VS (s) (dB)
output is expected to be a pure sinusoid, and its magnitude
spectrum should have a single impulse. Real amplifiers are not
20
perfectly linear though, so the output is usually not a perfect
sinusoid.
As a result, unexpected features called harmonics appear
0
in the output magnitude spectrum. Harmonics are spuri- 103 104
ous impulses that appear at integer multiples of the original ω (rad/sec)
fundamental signal frequency. So if the input sinusoid has a Figure 28: Harmonic “spurs” appear at integer mul-
fundamental frequency component at f 0 , the distorted output tiples of the fundamental frequency, and represent
distortion.
sinusoid has harmonic components spaced at integer multiples
fk = k f0 .
Aliasing
Since the harmonic components can extend to very high fre-
quencies, they may contribute to aliasing effects in a digital
oscilliscope’s FFT display. Aliasing occurs when a signal vio-
lates the Shannon-Nyqvist Sampling Theorem, which states that
the sampling rate must be at least twice the highest frequency
present in the signal. On a typical digital oscilloscope, we must
be aware of the following considerations:
• The Sec/Div knob sets the sampling rate f S .
• If the signal frequency f > f S /2, then the scope will show an
image at f − f S /2. So if you increase f beyond f S /2, the signal
peak on the FFT will appear to move backwards.
• When many high-frequency harmonics are present, their

images will overlap again and again over the FFT display,
creating an erroneous and confusing plot.
• Higher frequency harmonics can be suppressed by activating

an internal bandwidth limit on the oscilloscope’s input
channel.
• When zooming in to see more detail on the FFT display, do

not use the Sec/Div knob. Instead, look for a digital zoom
setting in the FFT menu.
Operational Amplifier Circuits
v−
− −
Amplifiers with finite open-loop gain
vid vOUT
Operational amplifiers (op amps) are nearly ideal differential v+

+ +
amplifiers. This means that their output is proportional to the
difference of their inputs, and is governed by the characteristic
Figure 29: An op amp has two input terminals and
equation one output. The input signal is differential, with
vid , v+ − v− . The output is single-ended, with
vOUT = A v+ − v− ,

vOUT = Avid .
where gain is the amplifier’s voltage gain. Since op amps are

nearly ideal, we expect them to have very high Rin and very low
Rout . Furthermore, there should be zero current passing into the
op amp’s input terminals.
Op amps are almost always used in negative feedback con-
figurations where there is some path for current to flow be-
tween the amplifier’s output and its inverting input terminal.
To analyze realistic op amp circuits with feedback, we need to
introduce some more refined notation:
G ? = The desired or ideal or nominal closed-loop gain

⇒ Gi? = for an inverting configuration
?
⇒ Gni = for a non-inverting configuration
G = The actual achieved closed-loop gain.
A = The op amp’s finite open-loop gain, in volts per volt.
e = The error coefficient
⇒ G = G? e
Notice that the concept of “open-loop gain” is distinct from

the “open circuit gain,” but in this chapter we will consider
them to be approximately the same. The open-loop gain refers
to the amplifier’s gain without feedback, whereas the open-circuit
gain refers to the gain without a load. Since an op amp is ex-
pected to have a very low Rout , we will assume that loading
effects are negligible.
Inverting amplifier
The standard inverting configuration includes an input resistor

R1 and a feedback resistor R2 . Whenever an op amp is con-
R2
nected in a negative feedback configuration, it will exhibit a
virtual short effect that forces v− to be approximately equal to i2
v+ . The virtual short occurs because the op amp’s open-loop
R1
gain tends to be very large. We can prove the virtual short effect v−
vIN −
under the most ideal condition: that the op amp’s open loop i1
vOUT
v+
+
gain is so large it effectively approaches infinity.
Figure 30: Inverting op amp configuration. No
current flows into the op amp’s terminals, so i2 = i1 .
Proof. First suppose v− > v+ . Then we expect to see a large Summary: This configuration’s characteristics are:
negative voltage at vOUT . By superposition, R2

G? = −
R1
R2 R1 G = eG ?
v− = vIN + vOUT .
R1 + R2 R1 + R2 A
e= R2
1+A+ R1
But if the op amp’s gain A → ∞, then vOUT → −∞ and
consequently v− → −∞. This creates a contradiction, since
we supposed that v− > v+ . On the other hand, if v− < v+ ,
then vOUT → ∞ and consequently v− → ∞, which is another
contradiction. The only non-contradictory scenario is if v− =
v+ .
Thanks to the virtual short effect, we can say that ideally

v− = 0, so the current passing through R1 is
vIN
i1 = .
R1
Since there is no current passing into the op amp’s input termi-

nals, the entire current i1 must pass through R2 . Then i2 = i1
and vOUT = −i1 R2 = −vIN ( R2 /R1 ). This result is based on The closed-loop gain is the ratio vOUT /vIN when a
ideal assumptions, so we can say that the ideal closed-loop negative feedback connection is present.
gain is
R2
Gi? = − .
R1
The ideal analysis assumes that the op amp’s open-loop gain

goes to infinity. We can perform a more realistic analysis by
accounting for the op amp’s finite open-loop gain. In this case,
the op amp has an inexact virtual short, so we should not rely
on it in our analysis. Instead, we can solve for the closed-loop
gain beginning from the op amp’s characteristic equation:
operational amplifier circuits 41
vout = A v+ − v−

⇒ vout = A 0 − v−

vout
⇒ v− = −
A
vout − v−
i2 = i1 =
R2
−
v − vin
=
R1
Then we have
v
1 out

R1 vout 1 + = R2 − − vin
A A

1 R2 R2
⇒ vout 1 + + = − vin
A R1 A R1

vout R2 A
⇒ Gi = = −
vin R1 A + 1 + R2 /R1
Notice that, in this form, we can express the circuit’s actual

gain as the product of two terms:
Gi = Gi? × e
R2
Gi? = −
R1
A
e=
A + 1 + R2 /R1
The first term, G ? , is the gain expected if we used an ideal op

amp. The second term, e, is an error coefficient that quantifies
the effect of using an op amp with finite open-loop gain A.
EveryCircuit Demonstration 8 (Inverting configuration).
This circuit implements an inverting configuration where the op amp’s open-loop gain is A =
10 V/ V (i.e. 20 dB). The resistor values are R1 = 1 kΩ and R1 = 2 kΩ, so we expect an ideal closed-
loop gain of G ? = −2 V/ V. The input signal has a zero-to-peak amplitude of 1 V, so the output
amplitude should be 2 V. Simulate this circuit and observe the output amplitude. It should be 1.54 V.
To verify that this matches the prediction from our theory, solve for e and G using the methods de-
scribed in this section. Then, try increasing the op amp’s open-loop gain to 20 V/V and repeat your
calculations to verify that the theory holds up.
Non-inverting amplifier R2
The non-inverting configuration is similar to the inverting

configuration, except the input signal is applied at v+ . Under R1
i2
v−
ideal assumptions, we may appeal to the virtual short so that −
vOUT
v− = vIN , and i2 = i1 . Then i1 v+
+
+
vIN − vIN
i1 = −
R1
vOUT = vIN − i1 R2
Figure 31: Non-inverting amplifier configuration.
The “virtual short” effect causes the op-amp’s
R1 input terminals to have nearly equal potentials, so
= vIN + vIN v− ≈ v+ .
R2 Summary: This configuration’s characteristics are:
? R1
⇒ Gni = 1+
R2 R2
G? = 1 +
R1
To obtain the more realistic gain accounting for finite open- G = eG ?

A
loop gain, we begin from the characteristic equation as before: e= R2
1+A+ R1
vout = A vin − v−

vout
⇒ v− = vin −
A
vout − v−
i2 = i1 =
R2
v−
=
R1
Rearranging we get:
R1 vout − v− = R2 v −

vout vout
⇒ R1 vout − vin + = R2 vin −
A A
1 R2
⇒ vout 1 + (1 + R2 /R1 ) = vin 1 +
A R1
G?

?
⇒ vout 1 + ni = vin Gni
A
?
A + Gni ?
⇒ vout = vin Gni
A

vout ? A
⇒G= = Gni ?
vin A + Gni

? A
⇒ G = Gni
A + 1 + R2 /R1
Once again we may express the result in two parts, G ? and e:
? R2
Gni = 1+
R1
A
e=
A + 1 + R2 /R1
?
Gni = Gni ×e
Notice that the error coefficient, e, is the same for both the
inverting and non-inverting configurations.
Generalized Result
Since the error coefficient is the same in both configurations, the
closed-loop gain can be generally expressed as
G = G? × e

? A
=G
A + 1 + R2 /R1
EveryCircuit Demonstration 10 (Non-inverting configuration).
Make a copy of the inverting configuration circuit and modify it to implement a non-inverting config-
uration. Keep the parameters from the original exampe, R1 = 1 kΩ, R2 = 2 kΩ and A = 10 V/V, and
set the input signal amplitude to 1 V. For these parameters, calculate the expected values of G ? , e and
G. Simulate the circuit and verify that the output amplitude agrees with your calculations.
Voltage Follower
−
The voltage follower represents a slightly different case, since
vOUT
there are no resistors. vIN +
In this configuration, we have the following device equations:
Figure 32: Voltage follower configuration. Due to the
vOUT = A v+ − v−

“virtual short” effect, vOUT ≈ vIN .
Summary: This configuration’s characteristics are:
= A (vIN − vOUT )
v A
⇒ G = OUT = G? = 1
vIN A+1
G = eG ?
In this case, the gain can be expressed as A
e=
1+A
Gv? f = 1
A
ev f =
A+1
Gv f = Gv? f × ev f
EveryCircuit Demonstration 12 (Voltage follower configuration).
Make a copy of the inverting configuration circuit and modify it to implement a voltage follower
configuration. Keep the same op amp gain from the original example, A = 10 V/V, and set the input
signal amplitude to 1 V. Calculate the expected values of G ? , e and G. Simulate the circuit and verify
that the output amplitude agrees with your calculations.
Difference amplifiers
To make an amplifier with fully-differential input, we can com-

bine inverting and non-inverting configurations. This gives us
two gains: R2
? R2
Gni = 1+
R1
− −
R2
Gi? = − vIN R1 vOUT
R1 + +
R3
To achieve proper differential operation, the inverting and R4

non-inverting gains must be balanced, i.e. Gni = Gi . In their
usual configurations, this is not the case. In order to balance the
inverting and non-inverting gains, we insert the voltage divider Figure 33: Difference amplifier configuration for
R3 , R4 , so that: amplifying a differential signal. Inverting and non-
inverting configurations are superimposed. The
resistor-divider R3 − − R4 is used to ensure the same
gain for the inverting and non-inverting signal paths.

? R2 R4
Gni → 1+
R1 R3 + R4
R2
=
(condition for balance)
R1

R4 R2 R
⇒ 1+ = 2
R3 + R4 R1 R1
Then solving for R4 /R3 we find that

R3 R2 R1
=
R3 + R4 R1 R2 + R1
R2
=
R1 + R2
Then we can invert both sides:
R3 R
1+ = 1+ 1
R4 R2
R3 R1
⇒ =
R4 R2
So the resistor ratios need to be matched.

EveryCircuit Demonstration 14 (Difference amplifier (differential mode)).
This circuit implements a difference amplifier with

both differential and common-mode input circuits. R2
In the initial setup, you should see that the two dif-
ferential input signals, vip and vin , have zero-to-peak
amplitudes of 1 V and a frequency of 1 kHz. One of
the sources, vip , has a phase of 180° in order to have −
opposite polarity from vin . The common-mode signal R1 vOUT
+
vCM is shared by both of the input signals, i.e. they vin R3
share this signal component; it is common to both vip
R4
of them. In the example design, vCM has a small
amplitude of 100 mV and a frequency of 300 Hz. We
expect the common-mode signal to be canceled out, vCM
so it should not appear at all in the output signal.
To verify this, increase the amplitude of vCM to 5 V,
so it will be clearly visible. Notice that the output
waveform doesn’t change.
Next, modify the value of R4 by increasing it to 4 kΩ. Keep the amplitude of vCM at 5 V, and let the
simulation run for a while. You should observe that a 300 Hz fluctuation is superimposed onto the
output signal. The common-mode is no longer canceled.
The importance of matching

If the inverting and non-inverting gains are imbalanced, then
the common-mode signal is not perfectly cancelled. To see this,
we now consider the actual gains Gi and Gni , which may differ
due to imprecision in actual resistor values:
1 +
vIN + = v + vCM
2 sig
1 −
vIN − = vsig + vCM
2
1
⇒ vOUT = ( Gni + Gi ) vsig + ( Gni − Gi ) vCM
2
The latter part of this result is called the common-mode gain,
ACM = ( Gni − Gi ). The Common Mode Rejection Ratio
(CMRR) is the ratio of the effective differential gain, Ad =
1
2 ( Gni + Gi ), to ACM :
Ad
CMRR =
ACM
This figure is often specified in dB. Ideally it should be infinite.
Input resistance in the difference amplifier

One source of mismatch in the difference amplifier is that the
input resistances are unmatched between the two input legs. To
evaluate the input resistance, we apply the method described in
?? separately for each leg of the input signal.
At the inverting input, we find that the input resistance is
equal to R1 , since vip = 0, so that v+ = 0 and, due to the virtual
short, v− = 0. At the non-inverting input, the equivalent resis-
tance is equal to R3 + R4 . If the input signals have a significant
series resistance, we will see signal attenuation due to resistive
coupling effects, which modifies the gain. Let us assume that
both vip and vin are both connected in series with a resistance
equal to Rsig . Then this resistance is effectively added in series
with R1 and R3 , so that after accounting for this loading effect
the gain becomes
R2
GL? = .
R1 + Rsig
In other words
R1
GL? =G ?
.
R1 + Rsig
If we repeat this analysis on the non-inverting signal path,
we will find the same ratio. Finally, accounting for finite gain
together with the loading effect:

? R1
GL = G e,
R1 + Rsig
where e is now modified due to the presence of Rsig :
A
e= R2
.
1+ A+ R1 + Rsig
Instrumentation amplifiers
vi1 + R3 R4
vx
Advantages over difference amplifiers: − ix
• Very high input resistance (Rin → ∞).

R2
• Gain controlled by a single resistor (2R1 ). −

2R1 i x − iy vout
• CMRR increased by the gain of the pre-amp stage. +
R20
Disadvantages:
• Needs three op amps.
− iy
R3 R4
• Higher power consumption. vy
vi2 +
Instrumentation amplifier A D analysis. Figure 34: Instrumentation amplifier configuration

for amplifying differential signals. Since both inputs
are connected to the op amps’ non-inverting termi-
We have three amplifiers. The first two are non-inverting con-
nals, they should both have high input resistance
figurations. Together they are described as a fully-differential and matched electrical characteristics. Compared
pre-amplifier. The third op amp is configured as a difference am- to difference amplifiers, this configuration is less
sensitive to resistor mismatch and has improved
plifier. The differential gain may be analyzed as a superposition CMRR.
of two non-inverting configurations:

R2 R
v x = vi1 1 + − vi2 2
R1 R1

R2 R
vy = vi12 1 + − vi1 2
R1 R1
The overall gain of the pre-amplifier stage is then
v x − vy
A D1 =
vi1 − vi2
2R
= 1+ 2
2R1
R
= 1+ 2.
R1
The difference amplifier contributes a gain of R4 /R3 , so the
total differential gain is

R2 R4
AD = 1 + .
R1 R3
Instrumentation amplifier ACM analysis.

We expect to obtain a net improvement in CMRR through
this configuration, compared to the difference amplifier. In
fact, the instrumentation amplifier achieves the following two
advantages:
• Eliminates sensitivity to R1 in the non-inverting configura-

tions by sharing R1 between the two circuits.
• Eliminates sensitivity to mismatch in R2 .
In the Common-Mode case, set vi1 = vi2 = vicm . Then, due

to the virtual short effect, the op amp’s inverting terminals are
also equal to vicm . Therefore the voltage drop across R1 is zero,
so that
i x − iy = 0
⇒ v x = vy
Note that this result does not depend on the matching be-
tween R2 and R20 . We may conclude that the pre-amplifier’s
common-mode gain is
ACM1 = 1V/ V
.
Finally, the overall CMRR is the ratio of the total differential
gain over the total common-mode gain:
A D1 A D2
CMRR =
ACM2
= A D1 CMRRdiff.
where CMRRdiff. is the original CMRR of the difference ampli-

fier.
Conclusion: By using an instrumentation amplifier instead of
a difference amplifier, the CMRR is boosted by 1 + R2 /R1 .
Non-Ideal Op Amp Characteristics
We have already discussed finite open-loop gain, finite input

resistance and common-mode gain as non-ideal features of op
amp circuits. Now we will examine two additional features:
• Input bias current
• Offset voltage
Input Bias Current
Every op amp has a small but non-zero bias current flowing

into its input terminals; a typical value might be 10 µA, but this
can vary across a wide range for different products. The bias
current is typically a fixed current that can be modeled as a DC
current source.
Example 5 (Bias current in inverting configuration).
In this example we analyze the effect of bias current on an inverting configuration.

The theorem of superposition allows us to set vin = 0 to
analyze the contribution of Ibias . In this case, we see that R2
v− = 0 (virtual short) ⇒ vout = Ibias R2
By superposition, we can add in the contribution from vIN −

R1 v− vOUT
vin , resulting in Ibias +

R2
vout = vin − + R2 Ibias .
R1
Based on this example, we can see that the effect of Ibias Ibias
is to introduce a DC offset voltage on vout . This places Figure 35: Inverting configuration showing bias-
current sources.
a limitation on the size of R2 that can be used. Suppose,
for instance, that we have
Ibias = 10µA R2 = 1MΩ VR = 5V
and the op amp’s power rails are at ±VR . In this case, the bias current induces an output offset
voltage equal to
Ibias R2 = 10V,
which is greater than the rail of the op amp. As a result, the op amp will simply saturate.
Example 6 (Maximum resistance due to Ibias ).
Given Ibias , an input signal vIN and a desired closed-loop gain G, how can we determine the maxi-
mum allowable value for R2 ? Suppose vmax is the maximum value of vIN , and vmin is the minimum
(note that vmin can be a negative voltage). Then our circuit must satisfy
VR + Gvmin
Ibias R2 + Gvmin < VR ⇒ R2 < .
Ibias
So returning to our example where Ibias = 10 µA and VR = 5 V, and let G = −10 V/V and vmin =
−0.1 V, we find
(5 V) + (1 V)
R2 < = 600 kΩ.
10 µA
Offset Voltage
Every op amp has a DC offset voltage so that its equation is
vout = A v+ − v− + Vofs .

When used in high-gain circuits, this offset voltage gets ampli-

fied, which may lead to erroneous signal processing in some
circuits.
Vofs is random, usually varying in the range ±10mV. Vofs can
also change slowly over time, making it difficult to zero it out
by design.
Example 7 (Inverting configuration with offset voltage).
R2
R1
vin −
v− vout
+
Vofs
−
+
Suppose an inverting op amp configuration
Figure 36: Inverting configuration showing input
has supply rails equal to +5V and −5V, and offset voltage source.
is configured to have a closed loop gain Effect of Vofs
G = − R2 /R1 = −100V/ V. The input signal
is a sinusoid with peak-to-peak amplitude 5 ∗
vout
Output Voltage [V]
45mV, and the op amp has an offset voltage vout

Vofs = 10mV. Draw the output waveform.
Answer: the output amplitude is 4.5V, but 0

since the offset voltage is also amplified,
the output will contain a DC offset equal to
1.01V, hence the output waveform is −5
0 5 10
vout = 1.01 + 4.5 sin (2π f t) .
Time [s]
This will result in clipping of the waveform. Figure 37: Waveform saturation caused by unde-
sired amplification of the op amp’s input offset
voltage.
EveryCircuit Demonstration 16 (Non-inverting circuit with bias and offset).
This circuit implements models of both Ibias and VOFS in a non-inverting op amp configuration. Since
the EveryCircuit op amp model is very ideal, a slight circuit trick is used to model the bias current by
steering it into ground instead of into the op amp terminal. This trick doesn’t change anything at all
about the circuit’s behavior. The model uses typical values of 10 µA and −10 mV for the bias current
and offset voltage, respectively.
We see that the output waveform has a significant DC offset due to the bias and offset effects, and
part of the waveform is saturated. To get some experience with these effects, you can experiment
with larger and smaller values of each, and with positive and negative values of VOFS . Occasionally
the simulation will halt and complain that it can’t find a solution. Usually in these cases you can just
restart the simulation and will proceed without any problems.
Design question: how can the circuit be modified to minimize the undesirable offset and avoid
saturating the output waveform?
Frequency Response of Op Amps
General-purpose op amps are said to be internally compen-

sated devices, meaning they are deliberately designed to have
a single-pole frequency response with a very low cutoff fre-
quency:
A0
A (s) =
1 + s/ωc
where
ωc = The low cutoff frequency

A0 = The DC open-loop gain, in V/V
The frequency response looks like this:
100
Gain Magnitude (dB)
ωc
50
ωt
0
100 101 102 103 104 105 106 107 108
0
−50
Phase (°)
−100
−150 PM
100 101 102 103 104 105 106 107 108
Figure 38: Standard op amp frequency response. In

The phase response loses 45° about the dominant pole ωc . this example, ωc = 100 rad/s, ωt = 1 × 106 rad/s,
and Av0 = 80 dB. In real op amp products these
There are typically additional poles at frequencies above ωt , parameters can vary significantly for different
which can cause additional phase loss just prior to ωt . The products. For a given product, ωt typically shows
low part-to-part variation and is a useful figure-of-
Phase Margin (PM) measures how much phase is lost at ωt . merit.
Specifically,
PM = 180° + ∠ A ( jωt )
(note that ∠ A ( jωt ) is negative).

For our (introductory) purposes, we will assume that PM =
90°.
Unity-Gain Frequency
A typical op amp has a a very large DC open-loop gain, often
greater than 80 dB or 10 000 V/V. Then the magnitude response
can be approximated as
s
A20
A (ω ) =
1 + ω 2 /ωc2
A ωc
≈ 0
ω
The unity-gain frequency ωt is where the gain magnitude is

equal to unity, i.e. 1 V/V:
A0
1 = ωc
ωt
⇒ ω t = ω c A0 Note A0 is in V/V
Because of this result, the unity-gain frequency is often referred

to as the Gain-Bandwidth Product (GBP). We can also write the
transfer function in terms of ωt as follows:
A0
A (s) =
1 + sA0 /ωt
Closed-Loop Frequency Response

Consider the inverting configuration using an op amp with a
one-pole response:

R2 A (s)
ACL (s) = −
R1 A (s) + 1 + R2 /R1
A 0
!
1+s/ωc
⇒ ACL (s) = G ? A0
1+s/ωc + 1 − G?

? A0
⇒ ACL (s) = G
A0 + 1 − G + s (1 − G ? ) /ωc
?

? A0
≈G since A0 1 − G ?
A0 + s (1 − G ? ) /ωc

? 1
=G
1 + s (1 − G ? ) /ωt
We can re-write this as a single-pole transfer function with pole
ωCL = ωt / (1 − G ? )
= ωt / (1 + R2 /R1 ) .
This result introduces the universal Gain-Bandwidth Trade-

off. By using feedback, we can convert between bandwidth and
closed-loop gain according to an approximate one-to-one ratio.

Note that for a given op amp, all configurations have the same
unity-gain frequency. Hence we consider ωt to be the universal
parameter of an op amp’s frequency response.
The closed-loop frequency response looks like this:
100
Gain Magnitude (dB)
ωc
50
ωCL
ωt
0
100 101 102 103 104 105 106 107 108
Figure 39: Closed-loop magnitude response (in

red) for an op-amp feedback configuration. The
open-loop response is also shown (in blue). For fre-
quencies greater than ωCL , the closed-loop response
approximately matches the open-loop response.
Example 8 (Closed-loop frequency response, low-gain).
Consider the following parameters:
ωt = 10MHz
R2 /R1 = 10
What are the closed-loop DC gain, the 3dB cutoff frequency, and the unity-gain frequency for these
parameters?
V
ACL = −10
V
ωt = 10MHz
ωc = 909kHz
Example 9 (Closed-loop frequency response, high-gain).
Consider the following parameters:
ωt = 10MHz
R2 /R1 = 100
What are the closed-loop DC gain, the 3dB cutoff frequency, and the unity-gain frequency for these
parameters?
V
ACL = −100
V
ωt = 10MHz
ωc = 99kHz
Notice that as the desired gain G grows to be very large, the cutoff frequency approximates to ωt /G.
EveryCircuit Demonstration 18 (Closed-loop frequency response).
This circuit models an op amp with a single-pole transfer function connected in a non-inverting
configuration. Since EveryCircuit’s built-in op amp model is basically ideal, we have to insert extra
components to introduce a pole at the op amp’s output node. This is accomplished using an RC
low-pass network followed by a voltage buffer comprised of a dependent voltage source with a gain
of 1 V/V.
Perform a frequency simulation of the closed-loop system and observe the major parameters: the
DC gain ACL (in dB), the 3 dB cutoff frequency ωc , and the unity-gain frequency ωt . Next, increase
the value of R2 by 10× and then 100×, and observe how it changes ACL and ωc . Convert ACL to
V/V in order to test the predictions from the theory presented in this section. Verify that ωt remains
constant and is approximately equal to ACL ωc .
Slewing
Slewing is very different from ordinary transfer-function based A signal affected by slewing
0 , i.e.
behavior. Slewing can be thought of as saturation of vout
a second-order saturation effect. As such, it is fundamentally 1
non-linear and introduces harmonic distortion into the signal.
vout
SR = max vout given in V/µs. 0
dt
Slewing tends to turn the output signal into a triangle wave.
If the op amp’s input signal is a pure sinusoid, then we can
−1
determine if the output will be affected by slewing:
0 2 4 6 8 10
∗ Time
vout = ACL VA sin (2π f t)
Figure 40: Slew-rate distortion in an op amp circuit.
d ∗
⇒ v = 2π f ACL VA cos (2π f t)
dt out
where VA is the input signal amplitude. This tells us that slew-
ing may occur if VA is large, or if the frequency f is large, or if
the closed-loop gain ACL is large. The maximum rate of signal
change must be less than the slew-rate:
2π f ACL VA ≤ SR
Example 10.
Slew-rate limiting Suppose an amplifier has the following characteristics:
SR = 1V/µs
ACL = 2 V/V
f = 100kHz
What is the maximum input amplitude VA which can guarantee no slewing?
SR
VA max =
2π f ACL
= 0.796V.
Clearly the slew rate can present real limitations for a circuit.
Although slewing distortion occurs commonly in op amp

circuits, there is no easy way to model it in simple simulators
like EasyCircuit. To get an accurate prediction of slew-rate
limiting, we need to use a more advanced simulator like SPICE.

This is one of the first instances where we can see the need for
sophisticated engineering software.
Full Power Bandwidth (FPBW)
The FPBW is the maximum frequency at which an op amp

can deliver its full-swing output signal (i.e. rail-to-rail output
amplitude). If the op amp has rails at ±VR , then the maximum
output amplitude is VO = VR . Then
SR
FPBW =
2πVR
If the op amp is single-supply, then the maximum amplitude

is VR /2, so
SR
FPBW =
πVR
The circuit will process any frequency less than the FPBW
distortion-free. For higher frequencies, you may begin to see
spurious harmonics in the output spectrum.
Once the FPBW is known, the slewing limit can be predicted
as follows:
FPBW
VO max = VR
f
Hence if you know the FPBW and the rail voltage, you can
estimate the maximum allowable amplitude at a given high
frequency.
Z2
Op Amp Integrators and Differentiators
If the circuit is analyzed in the Laplace domain, we can con- Z1

sider arbitrary impedances to behave as through they were vin −
vn
resistors. Then vout
vout (s) Z (s) +
ACL = =− 2
vin (s) Z1 (s)
Figure 41: Generalized inverting configuration with
complex impedances.
Differentiator: Z1 is a capacitor
If Z1 is a capacitor C1 , and Z2 is a resistor R2 , then
1
Z1 (s) =
sC1
⇒ ACL (s) = −sC1 R2 .
In this transfer function, −C1 R2 is just a scale constant. The

signal is multiplied by s, resulting in differentiation in the
C2
time-domain.
Integrator: Z2 is a capacitor R1
vin −
vn
If Z2 is a capacitor C2 , and Z1 is a resistor R1 , then vout
+
1
Z2 (s) = Figure 42: Ideal Miller integrator.
sC2
R
⇒ ACL (s) = − 1 .
sC2
In this transfer function, − R2 /C1 is just a scale constant.
The signal is multiplied by 1/s, resulting in integration in the C2
time-domain.
C1
Z1 and Z2 are both capacitors
vin −
vn
If both of the impedances are capacitors, then the behavior is vout
+
similar to an inverting configuration.
1 Figure 43: Idealized capacitive inverting configura-

Z1 (s) = tion.
sC1
1
Z2 (s) =
sC2
C
⇒ ACL (s) = − 1 .
C2
In this transfer function, −C1 /C2 is the amplifier’s gain. The s
terms cancel out, resulting in no integrating or differentiating
behavior.
Practical Considerations RF
In practice, capacitors cannot simply be left floating at the C2

op amp terminals. Consider the circuit shown in Figure 43.
Node vn is left floating, which means there is nothing to define
C1
its potential. It could literally be anything, which could be
vin −
disastrous. vn
vout
Additionally, there is no path for the op amp’s DC bias +
current to flow. To address these problems, we have some

options: Figure 44: Practical capacitive configuration with DC
bypass resistor.
(a) Include large resistances to passively clear the charge on v− .
(b) Use ideal switches to periodically reset charge on v− . C2
Method (b) is commonly used in integrated circuits, where

capacitors are easier to make than resistors, and switches are C1
made using MOSFET transistors. One of the key advantages vin −
vn
to the circuit in Figure 45 is that it can cancel out the op amp’s vout
+
offset voltage. When used for this purpose it is often called an
auto-zeroing circuit. We can analyze the auto-zeroing circuit
Figure 45: Practical capacitive configuration with
in two phases. In Phase 1, the switches are configured to short switched DC bypass.
across C2 and to connect the top plate of C1 to ground. In this
phase, the op amp is basically in a voltage-follower configura-
tion. Due to the virtual short effect, vn should be equal to VOFS ,
so C1 gets charged up to a voltage equal to VOFS . Meanwhile C2
is discharged to a voltage of zero.
C2 C2
C1 C1
vin − vin −
vn vout vn vout
+ +
+ +
− VOFS − VOFS
Phase 1 Phase 2
Figure 46: The two switching phases of a capacitive
inverting configuration.
In Phase 2, the input is connected, and node vn is left float-
ing, so that no charge can be added or removed from vn . So
any charge added to the outside plate of C1 has to be balanced
by an opposite charge on the outside plate of C2 . The charge
Q1 = vIN /C1 must be balanced by Q2 = vOUT /C2 = − Q1 .
Therefore
vOUT v
= − IN
C2 C1
vOUT C2
⇒ =− .
vIN C1
This interpretation allows us to build practical op amp configu-

rations using only capacitors. There’s a good reason for doing
this: resistors are big but capacitors are small. When making
circuits at the micro or nano scale, it is usually preferred to use
capacitors and avoid resistors whenever possible.
Miller Integrator
When Z2 is a capacitor and Z1 is a resistor, as in Figure 42,

the circuit is called a Miller integrator. The ideal circuit from
Figure 42 suffers from a few practical difficulties:
1. What determines the Initial Condition of the integrator?

Usually we want vout = 0 at some starting time t = 0.
2. When vin = 0, we expect vout = 0 for all t > 0. However the op

amp’s systematic offset voltage creates a “ghost input” that
gets integrated, so the charge on C2 will go to ∞.
RF
3. There is no reset mechanism to zero the charge on C2 . If vin C2
is a sinusoid centered at 0, the offset will keep charging C2

without limit.
R1
vin −
vn
To resolve these difficulties, there are two common solutions. vout
The first solution is to use a large passive bypass resistor R F +
connected in the feedback path, as shown in Figure 47. The

Figure 47: Miller integrator with DC bypass resistor
bypass resistor serves to zero the DC charge on C2 . If R F is RF .
sufficiently large, then it will have minimal influence on the
frequency response above DC, however it may contribute to
offset effects due to the op amp’s bias current and offset voltage.
It will also tend to amplify any DC offset present in the input
signal. At very low frequencies, we can treat the capacitor C2
as an open-circuit, i.e. we simply remove it from the circuit.
C2
This reveals the circuit’s DC behavior, an inverting integrator
with gain − R F /R1 . Similarly at higher frequencies where
(ωC2 )−1 R F , we can ignore the presence of R F and the circuit R1
should behave like an ideal integrator. vin −
vn
vout
The second solution is to use a switching reset in the feed-
+
back path. We use a switch which is closed periodically to
zero the charge on C2 . This method has the advantage of being Figure 48: Miller integrator with switched DC
insensitive to the op amp’s bias current, and is only weakly bypass.
sensitive to the input offset voltage. The main drawback is that
the switch also resets the signal integration result, so it is not
possible to integrate over a long period of time.
Frequency Analysis
The Miller Integrator introduces an interesting frequency re-

sponse. We can solve the unity-gain frequency by evaluating
the magnitude:
1
ACL ( jω ) =
ωR1 C2
1
⇒ ωt = .
R1 C2
We can draw the magnitude response by placing a point at ωt ,

then draw backwards adding 20dB per decade at frequencies
below ωt . The response grows toward ∞ as the frequency
approaches DC.
Introduction to Diodes
+ vD −
A diode is like a valve that lets current flow one direction
vA vB
but not the other. It is a nonlinear device, which means the
traditional linear analysis techniques cannot be directly applied.
iD
We begin with some simplified models that are useful for
Figure 49: Diode symbol and notation.
building intuition about diode circuits. After that, we’ll build up
to more accurate (but difficult) models and techniques. We’ll see
that accurate simulation using SPICE (or a similar software tool)
is essential for designing nonlinear circuits.
Ideal switch model
The simplest way to understand a diode is to consider it as an

ideal switch.
• When v D > 0, the switch is closed and i D can be any positive

value.
• When v D ≤ 0, the switch is open and i D = 0.
Using the switch model, we first make a hypothesis as to

whether the diode is ON or OFF. Then, we analyze the circuit
to verify it is consistent with that hypothesis. This approach
introduces our first iterative procedure: If the circuit contains
multiple diodes, we initially assume that all diodes are OFF
and then analyze the circuit. Any diode with a forward voltage
is then turned ON. After changing the diode’s state, we must
re-analyze the circuit to see if any additional devices need to be
turned ON.
Example 11 (Max-Value Circuit).
Analysis steps:
D1
1. Suppose both diodes are OFF. Then vC = 0. But then both vA
D1 and D2 have positive potentials across their terminals,
so they cannot both be off. v A = 4V
2. Observe that D2 has the larger forward potential across D2 v B = 7V
its terminals. Based on this, suppose that D2 is ON while vB vC
D1 remains OFF. In this case, vC = v B = 7V, hence the
potential across D1 is vC − v A = −3V, which is consistent R
with the hypothesis.
In this example, we find that D1 is OFF while D2 is ON.

Figure 50: Diode max-value circuit.
Based on our analysis, we can generalize the result and
describe this circuit by the function
vC = max (v A , v B ) .
Example 12 (Min-Value Circuit).
Analysis steps:
VDD
1. Suppose both diodes are OFF. Then vC = VDD .
2. Observe that D1 has the larger forward potential across

its terminals. Based on this, suppose that D1 is ON while R
D2 remains OFF. In this case, vC = v A = 4V, hence the v A = 4V
potential across D2 is v B − vC = −3V, which is consistent
va vC v B = 7V
with the hypothesis.
D1
In this example, we find that D2 is OFF while D1 is ON.
Based on our analysis, we can generalize the result and
describe this circuit by the function vb
D2
vC = min (v A , v B ) .
Figure 51: Diode min-value circuit.
introduction to diodes 69
Exponential model
A more accurate model of the diode is given by this expression: Diode physical device parameters:
IS = Scale current, typ. ≈ 1pA to 1nA
vD
i D = IS exp −1 n = Grading coefficient, typ. ≈ 1
nUT
kB T
UT = Thermal voltage, ≈ 26mV at room temp.
Notice that when v D = 0, the current is also zero. When q
v D > 0, the exponential part rapidly becomes much greater than k B = Boltzmann constant = 8.6173 × 10−5 eV/ K
T = Temperature (K) ≈ 300K at room temp.
one. When v D < 0, the exponential part rapidly becomes much
q = Elementary charge = 1eV/ V
smaller than one. This splits the diode into two different modes:
called forward bias and reverse bias, respectively.
10

vD
Forward bias i D ≈ IS exp nU T
.
8
Reverse bias i D ≈ − IS .
6
i D (mA)
Constant voltage-drop model 4
From the physical model, we can see that the i D curve becomes
2
very steep when v D ≥ 0.7V, so we can say this is approximately
the ON voltage of the diode. When a diode is turned ON, it 0
0 0.2 0.4 0.6 0.8 1
should have a nearly constant forward voltage drop equal to
vD
0.7V.
Figure 52: Diode transfer characteristic. The current
increases very rapidly when v D ≈ 0.7 V.
Example 13 (Min-value circuit with 0.7V drop model).
Analysis steps:
1. Complete the analysis using the ideal switch model. We find that D1 is ON and D2 is OFF.
2. Estimate a more accurate result by adding a 0.7V forward drop to every diode that is ON, hence
vC = v A + 0.7V = 4.7V
Based on our analysis, we can generalize the result and describe this circuit by the function
vC = min (v A , v B ) + 0.7V.
Important Note: If |v A − v B | < 0.7V, then this method does not yield any valid solution. In that case,
we must use the full physical model with iterative analysis to arrive at the correct solution.
Iterative Analysis
The constant voltage drop model gives us an approximation

that is useful for back-of-the-napkin analysis. For a more precise
analysis, we must solve the voltages and currents using the
full physical model. The resulting equations do not often have
closed-form solutions, so we must apply an iterative method
based on this procedure:
1. Obtain an initial solution using the switch model.
2. Improve the solution using the constant voltage drop model.
3. Based on that solution, calculate the resulting currents that

should flow through linear elements (resistors).
4. From those currents, estimate a more exact voltage drop for

each diode.
5. Repeat steps 3 and 4 in a loop until the answers converge to

a stable answer.
Convergence: How to know when the iterations are finished

Most of the time, we do not carry out iterative analysis by
hand; we use SPICE or a similar simulator to perform these
calculations for us. “Under the hood,” SPICE performs iterative
calculations to predict a circuit’s behavior. These simulators use
two criteria to decide when iterations are complete: absolute
tolerance (abstol) and relative tolerance (reltol), defined as:
• abstol – Simulation continues until all voltages and currents

satisfy
|∆x | < abstol
• reltol – Simulation continues until all voltages and currents

satisfy
∆x

x < reltol

Most simulators will allow you to adjust the abstol and reltol
parameters. Smaller values result in better accuracy, but will
take more time to finish.
Example 14 (Iterative analysis).
In this example, the current i is described by two

equations:
R vB
v − vB vA v A = 3V
i= A
R R = 1kΩ
vB
i
i = IS exp i
nVT D
Because of the exponential term, there is no easy
solution. We may solve the circuit by iteration:
1. Using the ideal switch model, we see that D must

Figure 53: Iterative solution for resistor-diode series
be ON. configuration.
2. Using the 0.7V model, we obtain an initial guess

(0)
v B = 0.7V
i(0) = 1mA
3. Using the resistor equation, we obtain a new

estimate for the current:
3 − 0.7
i (1) = = 2.3mA
1kΩ
4. From the diode equation, we can obtain a new

estimate for the voltage:
!
(1) (0) i (1)
v D = v D + nVT ln (0) = 0.72166V.
i
5. We repeat these analyses using the generalized

equations
(k)
( k +1) v A − vB
i =
R !
( k +1) (k) i ( k +1)
vB = vB + nVT ln
i (k)
By following this procedure, we obtain the following sequence of results:

k i [mA] v B [V] ∆i [mA] ∆v B [V]
0 1 0.7 - -
1 2.3 0.72166 1.3 0.02166
2 2.2783 0.72141 −0.021656 −2.5 × 10−4
3 2.2786 0.72141 2.4596 × 10−4 2.8067 × 10−6
Notice that the changes ∆i and ∆v B become smaller with each iteration. This means that the calcula-
tions are converging onto the correct answer, where all equations find perfect agreement.
iD
Linearized Model
+
id
Yet another way of modeling the diode is to use a linear approxi- +
mation. vd rd
Recall the definitions of small-signal notation, ID and VD are
the operating point values, id and vd are small variations, and i D −
and v D are the actual physical signal values. Hence vD ID
i D = ID + i d
+
v D = VD + vd
− VD
Looking at this circuit, it is easy to see that rd = vd /id . Since

vd and id represent small variations, we can interpret rd as the −
derivative: Figure 54: Linearized diode model.
dv
rd = D
di D
di D −1

≈
dv D
−1
IS VD
= exp
nVT nVT
nVT
=
ID
If we use the 0.7V model, and assume room temperature
operation with n = 1 (so nVT = 0.026V), then the values for this
model are
VD = 0.7V
ID = 1mA ( k +1)
iD
rd = 26Ω +
id
+
Iteration with the linearized model
(k)
vd rd
Iterative analysis can be combined with small-signal analysis by
repeatedly recalculating rd . In this version, the diode’s circuit −
( k +1) (k)
model looks like this: vD iD
The analysis procedure is as follows:

+ (k)
1. Use the constant 0.7V model to obtain an initial guess for all − vD
(0)
voltages and currents, and for rd .
( k +1) −
2. Using linear circuit analysis, find the solution for v D .
Figure 55: Iterative solution of linearized model
3. Using the non-linear device current equation, calculate the parameters.
( k +1) ( k +1)
current i D and the small-signal resistance rd :
( k +1) (k)
!
( k +1) (k) vD − vD
iD = i D exp
nVT
4. Repeat the calculations until the answer is sufficiently con-

verged.
(0) (0)
Beginning from the initial conditions i D = 1mA, v D = 0.7V
(0)
and rd = 26Ω, we may solve new values for the voltages and
currents. Those new values may then be used to improve the
calculation of rd .
The chief advantage of using small-signal iteration is that
it provides stable convergence for most circuits, whereas the
method of direct iteration can sometimes fail. This method is
mathematically equivalent to the Newton-Raphson method,
and is the most common type of algorithm used in circuit
simulators like SPICE.
Example 15 (Iteration with linearized model).
For example, we may reconsider our resistor-diode circuit:
R i ( k +1)
vA
+ id
+
R vd (k)
rd
vA
−
≈ ( k +1)
vB i (k)
+ (k)
− vB
Figure 56: Iterative solution of the resistor-diode series configuration using the linearized model.
In this example, the iterative procedure yields the following table of results:
k i [mA] v B [V] rd [Ω] id [mA] vd [V]
0 1 0.7 26 2.25504 0.032943
1 3.5504 0.73294 7.3232 −1.0705 −0.009330
2 2.4799 0.72361 10.4843 −0.1934 −0.002112
3 2.2865 0.7215 11.3713 −0.0000079 −0.00009
4 2.2786 0.72141 11.4106 0 0
Diode Circuits
vin vout
Half-Wave Rectifier
R
The 1/2-wave rectifier circuit passes current only when vout >
0.7V. In this case, the diode’s forward voltage drop is close to
0.7V, regardless of the current that flows, so that vout ≈ vin − 0.7V. Figure 57: Half-wave rectifier circuit.
When the diode is OFF, no current flows, so vout ≈ 0V. This
behavior is approximately described by the expression
vout ≈ max (0, vin − 0.7V) .
vin
1
vout (ideal)
Voltage
vout (0.7V drop)

0
−1
Time
Figure 58: Behavior of the half-wave rectifier. The
ideal switch model is compared to the more accurate
constant-0.7 V drop model.
Example 16 (Half-wave rectifier with vin < 0).
In this example, let vin = −1V and R = 1kΩ. We want to solve for vout . First, we assume the diode is
OFF and check for consistency. We find that vout = 0 and therefore the diode’s forward drop is v D =
−1V. Since v D is negative, the diode must be OFF, so vout = 0V.
Example 17 (Half-wave rectifier with vin = 1V).
In this case the diode is clearly ON. Using the con-

stant voltage drop approximation, we can estimate 1mA
that vout ≈ 0.3V. A more precise estimate may be
obtained using the small-signal model:
vin vout
vout + 0.7V − vin vout
+ − 1mA = 0
26Ω 1kΩ
−
+
1 kΩ
vin − 0.7 26 Ω

1 1 0.7 V
⇒ vout + = 1mA +
26 1kΩ 26
Figure 59: Linearized model of half-wave rectifier.
Now solving for vout :
vin − 0.7
⇒ vout = (1mA) (26Ω k 1kΩ) + (26Ω k 1kΩ)
26
Now notice that (26 k 1000) ≈ 26 (try it). Then we can simplify the approximation:
vout ≈ 26mV + vin − 0.7V

≈ vin − 0.684V.
This provides a more accurate approximation when the resistor R is large. In the case where vout =
1V, we find that
vout ≈ 0.343V
i D ≈ 343µA
diode circuits 77
Resistor-diode regulator
The regulator circuit is similar to the 1/2-wave rectifier, only vin vout
it interchanges the positions of the diode and resistor. In this
circuit, when vin < 0.7V, the diode is either OFF or only weakly
ON, so the current is close to zero. In that case, the voltage drop
across R is nearly zero, so vout ≈ vin . When vin > 0.7V, the diode
is clearly ON. Using the constant voltage drop model, we find
Figure 60: Single-diode regulator circuit.
that vout ≈ 0.7V, so the waveform is “clipped” at 0.7V.
0.7V Regulator Behavior

1
vin
0.8 vout
Voltage
0.6
0.4
0.2
0
Time
Figure 61: Behavior of the single-diode regulator
circuit with R = 100. The results from SPICE
simulation are more accurate than hand analysis.
A more accurate analysis is obtained using the linearized
diode model. By applying the node-voltage method at vout , we
find that
vout − vin vout − 0.7V R

+ + 1mA = 0 vin vout
R 26Ω

1 1 vin 0.7V
⇒ vout + = +
R 26Ω R 26Ω
26Ω R
⇒ vout = vin + 0.7V 26Ω
26Ω + R R + 26Ω
1 mA
As the name implies, regulators are used to produce sta-
ble DC voltages. Ideally, a regulator should produce 0.7V re- +
gardless of vin (so long as vin > 0.7V). The preceding analysis 0.7V −
revealed a slight dependency between vin and vout :

26Ω
∆vout = ∆vin . Figure 62: Linearized model of the single-diode
R + 26Ω regulator.
In practice, the residual ∆vout signal can introduce interference

into the circuits that are interfaced with the regulator. Accord-
ing to this analysis, the regulation works best when R is large.
Peak rectifier
The peak rectifier (or peak detector) circuit is like a rectifier

that uses a capacitor in place of the resistor. This circuit can
vin vout
be interpreted as an integrating rectifier. Unlike the usual
diode circuits, the 0.7V approximation can be misleading when
applied to the peak rectifier. C
This is because the capacitor integrates all of the current that

passes through it:
Z tF
1
vout = i D (t) dt.
C 0
When the diode is OFF, a small current still flows, and that
current is steadily accumulated by the capacitor’s integrating
behavior.
Consider the output from a SPICE simulation where C =
1nF, shown below. In this simulation, we can see that vout rises
initially to 0.263V, which is approximately vin − 0.437V. Clearly
the 0.7V model is not working.
Peak Detector Circuit with 0.7V Input Amplitude
vin
0.5 vout
Voltage
−0.5
Time
To understand why the 0.7V model fails, we may examine

the diode current, shown in the figure below. Although the
current never exceeds 1µA, the small pulses are sufficient to
charge C.
In each cycle of the input waveform, the peak current gets
smaller, so the output waveform marches in smaller and smaller
steps toward the peak value of the input voltage. Given enough
time, vout will eventually rise very close to the actual peak. This
effect can be used to create AC-to-DC converters.
diode circuits 79
Peak Detector Current

·10−8
3
i
2
Current
0
Time
Figure 63: Current delivered into the capacitor in the
peak detector circuit.
Envelope detector
The peak detector circuit can also be used in a variety of ap-

plications for instrumentation and communication. In these
applications, we usually want to detect the envelope of some vin vout
waveform, which requires that vout be allow to drop when vin de-
creases. This is accomplished by adding a resistor R in parallel C R
with C, resulting in an envelope detector:
An example SPICE simulation result is shown in the plot
below. This simulation used the following values:
Figure 64: Envelope detector circuit.
C = 10µF
R = 10kΩ
f = 10Hz
In this circuit, the diode is able to rapidly charge the capaci-

tor C, which is then slowly discharged by R.
Envelope Detector
4
vin
vout
2
Voltage
−2
Time
Figure 65: Behavior of the envelope detector circuit.
When the didoe is OFF, the output waveform is described by
the standard RC discharge equation
vout (t) = vpeak (1 − exp (− RC (t − t0 ))) ,
where t0 is the time when the diode turns OFF.
Netlist 1: envelope_detector.sp
* envelope detector circuit
* Generic diode model:

.model diode d(Is=2.0298e-15, n=1)
* The input is a damped 10Hz sine wave that

* looks like an impulse:
Vin 1 0 SIN(0 5 10 0.25 8)
* Peak detector circuit:

D1 1 2 diode
C1 2 0 10uF
R1 2 0 10k
* Transient simulation:
.tran 1m 1.5
.end
diode circuits 81
Bridge Rectifier
A bridge rectifier circuit, shown below, provides full-wave

rectification. Node numbers in the figure are indicated in blue,
corresponding to the example SPICE description.
D2
1
D
− load +
vIN +
0 3
D3
4
D
vOUT
−
Figure 66: Full wave bridge rectifier circuit.
Analysis:
Case 1: vIN > 0. In this case, we see that the most
positive potential appears at the anode of
D2 . Based on this, we may predict that D2 is
ON while D1 is OFF. Since the most negative
potential appears at the anode of D4 , we may
conclude that D4 is OFF.
Based on this reasoning, we infer that the
current flows in a zig-zag through D2 , then the
load, then D3 . The potential appearing across
the load is
vOUT ≈ vIN − 1.4V.
Case 2: vIN < 0. In this case the most positive potential

appears at the anode of D4 , and the most nega-
tive potential appears at the cathode of D1 . We
may conclude that the current flows in a zig-zag
through D4 , then the load, then D1 . In this case
the potential appearing across the load is
vOUT ≈ |vIN | − 1.4V.
The bridge arrangement ensures that the polarity across the

load is always oriented right-to-left, regardless of the input
polarity.
Bridge Rectifier Circuit with 10V Input Amplitude

10
vin
vout
5
Voltage
−5
−10
Time
SPICE simulation example for the bridge rectifier:
Netlist 2: bridge_rectifier.sp
* bridge rectifier circuit

* The input is a 120Hz sine wave:

Vin 2 1 SIN(0 10 120)
* Bridge rectifier:
D1 0 2 diode
D2 2 3 diode
D3 0 1 diode
D4 1 3 diode
* Load resistor:
Rload 3 0 1k
.tran .1m 0.02
.end
diode circuits 83
VDD
Voltage Regulators
R
We previously considered a 0.7V regulator circuit. We can
vOUT
extend this concept to produce other regulated voltages by
connecting multiple diodes in series. For example, we may
connect four diodes in series to create a 2.8V regulator circuit:
Ripple Analysis: Line Regulation

The regulator is able to reject ripple waveforms that appear in
the supply voltage, however the rejection is not perfect. A close
inspection reveals that a small ripple is injected into vOUT :
The regulator’s quality is measured by the amount of ripple
that appears in vout . More precisely, we want to know the ratio
of output ripple amplitude to input ripple amplitude. This
quantity is called the line regulation, defined as
Figure 67: A four-diode voltage regulator.
∆vOUT
LR =
∆VDD
To predict this, we must calculate the small-signal gain of
AC signals that are transferred from vin to vout . We previously vdd
introduced a small-signal model that allows each diode to
be replaced by a linear approximation. Now we introduce R
the concept of an AC Equivalent Circuit which we can use to vout
analyze the non-DC behavior.
rd
Deriving the AC Equivalent Circuit

rd
Step 1 To obtain the linear circuit approximation,
replace all non-linear devices (e.g. diodes)
rd
with their linearized companion models, as in
previous examples.
rd
Step 2 To obtain the AC equivalent circuit, set all
independent DC sources to zero. This means
that independent current sources are replaced
by open-circuits, and independent voltage Figure 68: Small-signal equivalent circuit model of
the four-diode 2.8 V regulator.
sources are replaced by short-circuits.
After obtaining the AC equivalent circuit, we use all-lower-

case notation to indicate the ripple waveforms vin and vdd . Using
the AC equivalent circuit, we can solve for the line regulation as
the ratio of these small signals: Reminder: The lower-case signal vout represents the
vout small ripple signal appearing in the output. The
LR ≈ all-upper-case notation VOUT is used to represent
vdd the DC (average) value. The actual physical signal is
vOUT (t) = VOUT + vout (t) .
Example 18 (Four-diode voltage regulator design).
Let
vin = 10V + (0.5V) sin (2π f t) .
Basic analysis
Find R to get an average current of 1mA, resulting in vout = 2.8V.
vin − vout
1mA = I =
R
vin − vout
⇒R=
I
= 7.2kΩ
The behavior of this circuit is investigated using SPICE simulation. The results shown below include
a supply ripple with zero-to-peak amplitude of 0.5V at 120Hz. From SPICE simulations, we see
that the actual output voltage is 2.7863V, which is slightly less than the intended value. The ripple
amplitude is also found to be 14.158mV.
By using the small-signal model, we can obtain a reasonable estimate of vout , the small ripple wave-
form that is superimposed on the regulator’s output:
vin = (0.5V) sin (2π f t)

4rd
vout = vin
R + 4rd

104
= vin
7200 + 104
= vin (0.014239)
= (7.12mV) sin (2π f t)
Then the line regulation is
vout
LR =
vdd
7.12mV
=
500mV
= 0.014239
= 1.4239%
diode circuits 85
Netlist 3: basic_regulator.sp
* 2.8V regulator circuit

* The input is a 120Hz sine wave with a 10V offset.

* The supply ripple amplitude is 0.5V
Vin 1 0 SIN(10 0.5 120)
* Regulator circuit
* The output is at node 2
R1 1 2 300
D1 2 3 diode
D2 3 4 diode
D3 4 5 diode
D4 5 0 diode
.tran .1m 0.02
.end
Regulator Circuit with 120Hz Supply Ripple
10 vin
vout
Voltage
0
Time
Figure 69: Behavior of the four-diode regulator from
SPICE simulation.
Regulator Output Ripple
2.79
Voltage
2.79
2.78
Time
Figure 70: Zoomed view of the ripple voltage on
vOUT .
General Analysis
In general, for a diode circuit comprised on N diodes with bias

current ID , generated by an input voltage VIN and resistance R,
we can produce a regulated voltage VOUT = NVD , where VD is
the individual diode voltage associate with ID . Then the line
regulation is
NVT /ID
LR =
R + NVT /ID
NVT
=
RID + NVT
NVT
= .
VDD − VOUT + NVT
The smaller we make this value, the better quality we will

provide on the regulator output. Things that achieve good
quality regulation include:
• A large voltage drop RID , i.e. vin should be significantly

greater than the regulated vout .
• A small number of diodes N.

diode circuits 87
Example 19 (Two Diode Regulator with Op Amp Buffer).
Another approach is to use two diodes at 1mA to create

a 1.4V reference, which is then multiplied using a non- VDD R2
inverting op amp configuration to yield 2.8V:
For this configuration, the line regulation is: R1
R −
2VT vOUT
LR = ( G )
(10V − 1.4V) + 2VT +
= 0.01202 (V/V) .
D1
So it appears that this solution is slightly better, although it
may be affected by the tolerances on R1 and R2 , as well as D2
the op amp’s input bias current and finite gain.
vin +
Super Diode, Precision Rectifier va

−
This circuit operates in two modes. When the diode is forward
biased, it is a unity-gain follower. Note that in this configura-
tion v D can be very near zero, because little current is required vout
to regulate the op amp’s inverting terminal.
When the diode is reverse biased, the op amp is discon- Rload
nected from the output node. Therefore it delivers no current
to the load, and vout = 0. Note that in this configuration, the
op amp’s loop is open, which will cause v a to rail negative. Be-
Figure 71: Precision rectifier circuit with op amp
cause of this issue, this circuit is best used with a single-sided
feedback.
power supply.
Superdiode With Single-Rail Supply

4
vin
2 vout
Voltage
0
−2
−4
Time
Netlist 4: superdiode.sp
* super-diode precision rectifier simulation
* Include model for 741 op amp:

.include 741.sp

VIN 1 0 SIN(0 4 10)

VDD 10 0 DC 10V
* 741 instance
* Pin order: v+ v- VR+ VR- vo
X1 1 2 10 0 3 uA741
D1 3 2 diode
RL 2 0 1k
.tran 1m 0.5
.end
The superdiode netlist uses a SPICE model for the uA741 op

amp. The model is provided by the vendor, and the usage is
documented in the model file:
Netlist 5: 741.sp (top lines showing port order)

* SPICE model for uA741 op amp
*
* To use a subcircuit, the name must begin with ’X’. For example:
* X1 1 2 3 4 5 uA741
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
.subckt uA741 1 2 3 4 5
diode circuits 89
C
vin vout
DC Restoration, Clamped Capacitor
In this circuit the behavior depends on the capacitor’s charge q.

q
vout = vin +
C
Figure 72: Clamped capacitor circuit.
When the diode is forward biased, the capacitor is able to be
charged via current flowing through the diode. When the diode
is reverse biased, no current flows, so that capacitor holds its
charge.
To analyze the circuit, consider the initial condition q (t = 0) =
0, so that initially vout = vin . Suppose vin is initially zero, and in-
creases above zero. Then the diode will stay reverse biased, and
q doesn’t change.
But if vin decreases below zero, then the diode will begin to
switch on. The capacitor will accumulate charge equal to
q (t) = i D t
−vout

= IS exp t.
VT
This current will be greater than zero as long as vout < 0.

Consequently, the capacitor will collect charge until vout = 0.
As a result of this process, the capacitor will store a voltage
equal to the minimum value of vin .
Result: vout is a shifted version of vin , such that its minimum
value is equal to zero.
DC Restorer Circuit with 1V Input Amplitude
vin
vout
2
Voltage
−2
Time
Figure 73: Behavior of DC restorer (clamped capaci-
tor) circuit simulated in SPICE.
Netlist 6: dc_restorer.sp
* DC restoration circuit

* The input is a 10Hz sine wave:

Vin 1 0 SIN(0 2 10)
* Peak detector circuit:

D1 0 2 diode
C1 1 2 10uF
.tran 1m 2
.end
L
VIN VOUT
Boost converter iL
C
Diodes are frequently used in power conversion circuits. In
this appendix we look at one important step-up DC-to-DC con-
verter circuit, known as the boost converter. The boost converter Figure 74: Idealized boost converter circuit.
consists of an inductor, a diode, a switch and a load capacitance:
When the switch closes, the inductor is shorted to ground,
resulting in a large current. When the switch opens, the induc-
tor’s current cannot change instantly, so the current is forced
through the diode into the capacitor. These establishes a large
potential across the capacitor.
More precisely, suppose that the switch is initially open and
the current i L is zero. Then, at time t = 0, the switch closes
abruptly. The current is then
Z t
1 VIN
i L (t) = VIN dτ = × t.
L 0 L
Then if the switch opens again at some time t1 , the inductor
possesses a store energy equal to
1 2
E ( t1 ) =
LI .
2
Since the current must continue flowing through the inductor,
all of this energy is transferred into the capacitor. If the switch
is toggled very rapidly, with period T, then the current i L will
“ripple” up and down, transferring packets of energy in each
cycle.
Suppose the switch is closed for a time DT, where D is the
duty cycle of the switching clock. Then the switch is open for a
diode circuits 91
time (1 − D ) T. At steady state, the current should grow and

shrink by the same amount:
DT
∆i L (on) = VIN
L
(1 − D ) T
∆i L (off) = − (VIN − VOUT )
L
If we set the rise and fall equal to each other (as required for
steady-state operation), then we can solve for VOUT : 50
VIN
VOUT =
vOUT (V)
40
1−D
Note that this analysis only works if the switching is very fast,
30
so that the inductor current never drains completely to zero.
If the switching clock has a 50% duty cycle, then the circuit
20
acts as a voltage doubler. An example SPICE simulation fol-
0 0.5 1 1.5
lows with VIN = 20 V and a switch frequency of 5 MHz with a
Time (s) ·10−3
duty cycle of 62%. The expected output is VOUT = 52.6 V. The
Figure 75: Output voltage from the boost converter
output approaches the expected limit after about 1 ms, which when initialized at zero.
corresponds to five thousand switching cycles in this example.
* Boost converter simulation

* switch model:
.model switch sw(Ron=5, Roff=100000, Vt=0.001, Vh=0.0001)
* The input is 10V DC

Vin 1 0 DC 20V
* The switch control voltage is a high-frequency pulse waveform

Vswitch 4 0 PULSE(0 1 0 1n 1n 125n 200n)
* Boost converter circuit:

* Inductor:
L1 1 2 100u
* Diode, load capacitor and switch:

D1 2 3 diode
CL 3 0 10u
S1 2 0 4 0 switch
.tran 100n 1500u
.end

3410 Lecture Notes v0.1

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

3410 Lecture Notes v0.1

Uploaded by

Copyright:

Available Formats

ECE 3410

published by utah state university

Licensed for redistribution and adaptation under the Creative Commons

Operational Amplifier Circuits 39

1 Thévenin equivalent voltage signal source. . . . . . 17

16 Zoomed transfer characteristic showing approximately

with a single pole at ω p0 and no zeros, and with gain

28 Harmonic “spurs” appear at integer multiples of the

29 Operational amplifier symbol . . . . . . . . . . . . . 39

49 Diode symbol and notation. . . . . . . . . . . . . . . 67

57 Half-wave rectifier circuit. . . . . . . . . . . . . . . . 75

60 Single-diode regulator circuit. . . . . . . . . . . . . . 77

2 Ideal Voltage Amplifier . . . . . . . . . . . . . . . . . . . . 21

These lecture notes are intended as a companion for Sedra and

• The NGSpice Simulator is a free, open-source implemen-

operating system as it is widely used in the electronics and

produced from a microphone, or it may convey discrete or vsig Rsig

Spectrum and Frequency Response

Figure 3: Example FFT display on an oscilloscope.

the magnitude is obtained as

The magnitude spectrum is typically expressed in units of 40

decibels, and the complex phase ∠X ( jω ) is usually expressed

We may interpret the transfer function in terms of frequency by

When expressed in decibels, the magnitude reveals useful in- R R

inductance L has impedance sL. Once components are replaced

Example 1 (Low-pass RC circuit).

The low-pass configuration is like a simple voltage divider. The

. The magnitude response is then

When represented in decibels, we find that

So as ω increases, the magnitude decreases by 20 dB per decade.

Example 2 (High-pass RC circuit).

The high-pass configuration has impedances are Z1 = 1/sC and Z2 =

. The magnitude response is then

When represented in decibels, we find that

A note on approximations: in these examples we used a

Input Output Amplifier Type Gain Name and Symbol

In order to use an amplifier, it has to be connected to its

Figure 9: Coupling interactions in voltage amplifiers.

equation in combination with the coupling divider ratios. To

To maximize the amplifier’s gain, we want to eliminate the

EveryCircuit Demonstration 2 (Ideal Voltage Amplifier).

is achieved when the amplifier has small input resistance and

Figure 11: Coupling interactions in current amplifiers.

The remaining amplifier types are mixtures of voltage and

voltage divider at the input interface and a current divider at

Figure 12: Coupling interactions in transconductance

to one. This is achieved when the amplifier has large input

Figure 13: Coupling interactions in transresistance

This is achieved when the amplifier has small input resistance

Real Amplifiers Ideal Linear Amplifier

Real amplifiers are affected by nonlinear transfer characteris- 100 Output

Real amplifiers do not exhibit such ideal behavior. A more real-

100 Output 100 Gain

Figure 15: Non-linear transfer characteristic showing

This approximation is only valid for small variations, i.e. when

Real Non-Linear Amplifier Zoomed Non-Linear Amplifier

The Taylor linearization reveals an extremely useful aspect of

DC offset – the central or average value of a signal; what you

Small-signal – the amount by which the signal varies from the

Figure 18: Small-signal activity overlaid on the

Procedure for small-signal analysis

1. Solve the circuit’s DC operating point. In many cases we

2. Linearize the circuit by applying a Taylor approximation

3. Replace any non-linear components with their linearized