Lecture 1 - Course Introduction PDF

Lecture 1:
Course introduction
Francisco Rodríguez-Ballester (prodrig@disca.upv.es)
Computing Engineering Dept.
Universitat Politècnica de València, Spain
Outline
(c) 2006-2018 Francisco Rodríguez-Ballester (prodrig@disca.upv.es)
 What is VHDL?
 What is logic synthesis? What it is used for?
 What is a programmable logic device?
 What are FPGAs used for? What are their
benefits?
 Market players
 What are the modern trends in digital design?
Logic synthesis & VHDL course: Lecture 1 - Course introduction, spring 2018
What is VHDL?
 VHDL
 Hardware Description Language (HDL)
 Not a programming language but a descriptive
language
 What are the differences?
 Itcan be used to describe the behaviour of any
digital circuit (at any abstraction level)
 A subset of the language is synthesizable
(automatic translation text-to-circuit)
What is logic synthesis?
 From the Wikipedia, logic synthesis is …

a process by which an abstract form of desired
circuit behaviour is turned into a design
implementation in terms of logic gates.
 Umm … abstract form? of circuit behaviour?
 It means you describe what you want to get from
the circuit (behaviour), not how (actual hardware
in terms of logic gates, storage elements, …)
What is logic synthesis used for?
 Design complex circuits with

 Less effort
 Designing at a higher abstract level is easier
 Concentrate on the required functionality, not on the
implementation details
 Better maintainability
 Better documentation, readability, …
What is logic synthesis used for? (2)
 Example: Design a 4-bits up counter

 Functional description: what we have to design
 Two single-bit inputs
 Reset (name rst) and clock (name clk)
 One four-bits output (name count)
 Asynchronous reset input (name rst) description
 Low level-active: assert/active when low (‘0’)
 Asynchronous:
 Affects output immediately, irrespective of the clock
 Clock edges occurring while reset is asserted are ignored
 Example: Design a 4-bits up counter (cont.)

 Clock input (name clk) description
 Active on its falling-edge (high-to-low transition)
 Output (name count) description
 4-bits output, its value change with rst and clk inputs
 If reset is asserted, count has to change immediately
(asynchronous reset) to the value 00002
 Otherwise if the clock input has an active edge the
count updates: 00002, 00012, …, 11102, 11112, 00002,
00012, …
 Example: Design a 4-bits up counter (cont.)

 Graphical/traditional interface
 Name, inputs, and outputs
rst
inputs count(3:0) output
clk counter
counter count(3:0)
4
clk rst
 Example: 4-bits up counter (traditional

implementation)
Vcc
Vcc
clk
AND logic gate
J-K flip-flop
rst Electrical wire
Note: Image taken from Wikipedia entry “Finite State Machine”
 Example: 4-bits up counter (VHDL interface)

-- To use non-native std_logic data type
library ieee;
use ieee.std_logic_1164.all;
-- Interface declaration
entity counter is
port (
rst: in std_logic;
clk: in std_logic;
count: out integer range 0 to 15
);
end entity counter;
 Example: 4-bits up counter (VHDL

implementation)
 Slightly simplified
-- Implementation description
architecture anyname of counter is
begin
-- Describe the counter
-- behaviour here
-- ...
end architecture anyname;
 Example: 4-bits up counter (VHDL

implementation, cont.)
-- Behavioural description of the circuit,
-- it comes inside the architecture.
behaviour: process (rst, clk) is
begin
if (rst = '0') then
count <= 0;
elsif falling_edge(clk) then
count <= count + 1;
end if;
end process behaviour;
 Summary of 4-bits up counter example

 Traditional
design mixes “what” & “how”
 VHDL design is just a description of “what”
 Which one (traditional vs VHDL) is better?
 Faster, easier to create?
 Easier to understand, maintain?
 Easier to modify (to create a 32-bits counter, for

example)?
Programmable logic devices
 General term, many different types

 The functionality must be created by the
customer
 Circuitis not completely fixed
 Logic gates, storage elements, etc. are inside the
device, but …
 There is a lot of room for customization
 Configurable elements used, internal connections
Programmable logic devices (2)
 Types of programmable logic devices

 Some acronyms
 PLA (Programmable Logic Array)
 GAL (Generic Array Logic)
 (C)PLD (Complex Programmable Logic Device)
 FPGA (Field-Programmable Gate Array)
 Two main “classes”, based on register/logic ratio

 PLDs are said to be “logic-intensive”
 FPGAs are said to be “register-intensive”
 Programmable logic devices benefits

 Reduced time-to-market and design risks
 The design can start without the actual device
 Reconfiguration in-the-field
 Easily adaptable to final customer
 Correct design errors after installation/deployment
 FPGA
internal
structure
(example)
Device
pads
EAB:
LAB: Logic Embedded
Array Block Array Block
 FPGA internal
structure
(example,
single LAB)
Local Interconnect
Matrix
LE: Logic Element
 FPGA internal structure Combinational function

(logic)
(example, single LE)
Output
multiplexer
Flip-flop
(storage)
 Apart from logic and flip-flops modern FPGAs

offer many other elements
 Memory blocks
 General-purpose processors
 DSP (Digital Signal Processing) blocks
 Specialized multiplier blocks
 Clock management units
 Multi gigabit transceivers
…
 How they retain the configuration information

(the device customization)?
 Configuration information is a file known
as the bitstream
 ROM-based devices
 Non-volatile memory inside device
 Most, if not all PLDs
 Few FPGAs
 No additional measures required to retain the bitstream
 How they retain the configuration information

(the device customization)? (cont.)
 RAM-based devices
 Volatile memory inside device
 Most FPGAs
 Require an external ROM to store the bitstream
 On power-up, the FPGA automatically loads the

bitstream from the external ROM into internal RAM
 This part of the device functionality is fixed! (fabric design)
 No custom functionality until the bitstream is loaded
 Some more terms

 IP: Intellectual Property module
 Business model: design, sell and maintain IPs
 Soft-coreIP: a module designed using a HDL like
VHDL, may be added to the customer design
 Hard-core IP: a fabric-designed module inside the
FPGA, so it may not be removed from the FPGA
What are FPGAs used for?
 Examples of use
 Embedded systems
 Digital processing systems
 High-speed communications / connectivity
 Rapid ASIC prototyping
What are the benefits of FPGA use?
 Build classic systems with

 Reduced BOM (Bill Of Materials), size
 Better performance and configurability
 Build systems that were previously impractical

 Parallel circuits with the equivalent of
thousands/millions of logic gates
What are the benefits of FPGA use?
(2)
 You can use a microprocessor for some of
those, but…
A microprocessor executes a program sequentially
 Computational costs translate into execution time
 An FPGA can naturally exploit its inherent
parallelism to perform the same task in less time
 Even if the clock frequency of the microprocessor is much
higher than the operating frequency of the FPGA
Market players
 Two big players in the programmable logic

device market
 Xilinx (homepage http://www.xilinx.com)
 $2.38B net revenues (2014)
 Altera (homepage http://www.altera.com)
 $1.73B net revenues (2014)
 Now an Intel company
 Others
 Atmel, Actel, Lattice
Market players (2)
 FPGA vendors create differentiated device

lines for low power, high-end processing
systems, mid-range systems with high-speed
communication channels, etc.
 Xilinxfamilies: Spartan, Artix, Kintex, Virtex
 Altera families: Cyclone, Arria, Stratix
Modern trends in digital design
 As technology evolves…
 Current trend is to create processor-centric single-
IC solutions
 With off-the-shelf processors, custom logic, etc.
 That single-IC is a large FPGA or contains an FPGA
 These are known as System on Chip (SoC)
Modern trends in digital design (2)
 System on Chip examples (Soft-IP)

 ARM Cortex-M1 series
 ARMv7 ISA processor soft-core specifically designed
for their inclusion inside an FPGA
 PowerPC 405, 440 processors
 Used inside Xilinx’s Virtex-4, Virtex-5 FPGAs
 Xilinx’sPicoBlaze, MicroBlaze processors
 Altera’s NIOS-II processor
…
 System on Chip examples (Hard-IP)

 Intel Atom E6x5C series (codename “Stellarton”)
 The C in E6x5C stands for Configuration
 Single package, separate dies (two devices):
 Intel’s Atom E600 processor (“Tunnel Creek”) designed

for embedded systems plus
 Altera’s Arria-II GX midrange FPGA
 SoC examples (Hard-IP) – Atom E6x5C
 SoC examples (Hard-IP)

 Xilinx’s Extensible Processing Platform,
Zynq-7000 series
 Single die containing:
 ARM’s Cortex-A9 MPCore (dual-core processor)
 Xilinx’s Artix-7/Kintex-7 FPGA’s
 SoC examples (Hard-IP) – Zynq-7000

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Lecture 1:

 From the Wikipedia, logic synthesis is …

 Design complex circuits with

 Example: Design a 4-bits up counter

 Example: Design a 4-bits up counter (cont.)

 Example: Design a 4-bits up counter (cont.)

 Example: 4-bits up counter (traditional

Note: Image taken from Wikipedia entry “Finite State Machine”

 Example: 4-bits up counter (VHDL interface)

 Example: 4-bits up counter (VHDL

end architecture anyname;

 Example: 4-bits up counter (VHDL

 Summary of 4-bits up counter example

 Easier to modify (to create a 32-bits counter, for

 General term, many different types

 Types of programmable logic devices

 (C)PLD (Complex Programmable Logic Device)

 FPGA (Field-Programmable Gate Array)

 Two main “classes”, based on register/logic ratio

 Programmable logic devices benefits

LE: Logic Element

 FPGA internal structure Combinational function

 Apart from logic and flip-flops modern FPGAs

 How they retain the configuration information

 No additional measures required to retain the bitstream

 How they retain the configuration information

 Require an external ROM to store the bitstream

 On power-up, the FPGA automatically loads the

 Some more terms

 Build classic systems with

 Build systems that were previously impractical

 Two big players in the programmable logic

 FPGA vendors create differentiated device

 These are known as System on Chip (SoC)

 System on Chip examples (Soft-IP)

 System on Chip examples (Hard-IP)

 Intel’s Atom E600 processor (“Tunnel Creek”) designed

 SoC examples (Hard-IP) – Atom E6x5C

 SoC examples (Hard-IP)

 Xilinx’s Artix-7/Kintex-7 FPGA’s

 SoC examples (Hard-IP) – Zynq-7000

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