Wang Thesis

DESIGN OF INTEGRATED VOLTAGE-MODE CONTROLLED
DC-DC BUCK CONVERTER
by
Longfei Wang, B.S.E.E
A Thesis
In
ELECTRICAL ENGINEERING
Submitted to the Graduate Faculty

of Texas Tech University in
Partial Fulfillment of
the Requirements for
the Degree of
MASTER OF SCIENCE
IN
ELECTRICAL ENGINEERING
Approved
Dr. Changzhi Li
Chair of Committee
Dr. Stephen Bayne
Dominick Casadonte
Interim Dean of the Graduate School
May, 2013
Copyright 2013, Longfei Wang
Texas Tech University, Longfei Wang, May 2013
ACKNOWLEDGMENTS
It’s a precious and wonderful journey to pursue my Master of Science degree
in Electrical Engineering at Texas Tech University during the past two years. This
journey would not have been started and brought to a satisfying end without the
genuine assistance of many people.
I sincerely thank Dr. Changzhi Li for his guidance during the whole period of
my postgraduate study at Texas Tech University. His Analog IC Design class led me
to the fantastic field of integrated circuits and his suggestions on my thesis topic
brought me a step further and motivated me to continue with my research in this field.
I would like to thank for Dr. Stephen Bayne’s Design and Test of DC-DC
Converters class from which I learned a lot of design and test issues which are really
beneficial for my future research and career and also his continuous support as part of
my thesis committee.
I also would like to thank my family and friends. Their encouragement and
help are crucial and are greatly appreciated.
ii
TABLE OF CONTENTS
ACKNOWLEDGMENTS .................................................................................... ii
ABSTRACT .......................................................................................................... iv
LIST OF TABLES ................................................................................................ v
LIST OF FIGURES ............................................................................................. vi
I. INTRODUCTION ............................................................................................. 1
Background and Motivation.............................................................................. 1

Thesis Organization .......................................................................................... 2
II. SYNCHRONOUS BUCK CONVERTER ..................................................... 3
DC-DC Converters and Synchronous Rectification ......................................... 3

Inductor Operating Mode .................................................................................. 5
Voltage-Mode and Current-Mode Control........................................................ 7
Stability and Type 3 Amplifier ......................................................................... 9
III. SYSTEM DESCRIPTION AND SUBCIRCUITS DESIGN .................... 12
System Description and Design Specifications............................................... 12

Power Stage Design ........................................................................................ 14
Compensation Network Design ...................................................................... 18
Error Amplifier Design ................................................................................... 21
Voltage Comparator Design............................................................................ 23
Dead Time Generator Design.......................................................................... 26
Gate Driver Design ......................................................................................... 31
IV. SYSTEM SIMULATION AND RESULTS ................................................ 32
Voltage and Current ........................................................................................ 32

Line Regulation Results .................................................................................. 34
Load Regulation Results ................................................................................. 36
Efficiency ........................................................................................................ 38
V. CONCLUSIONS AND FUTURE WORK ................................................... 40
REFERENCES .................................................................................................... 41
iii
ABSTRACT
This thesis work focuses on the design of an integrated voltage-mode
controlled synchronous buck converter to achieve high efficiency. The concept of DC-
DC converters are discussed first and synchronous rectification techniques are used for
the design. This design work can be used for a single lithium-ion battery operated
portable electronic system. The input voltage range of the converter is 3.5V-5V and
the maximum load current can be as high as 950mA. A high switching frequency of
1MHz is used for the design to achieve a smaller inductor and capacitor value as well
as a lower voltage ripple.
The functional blocks of this designed synchronous buck converter include
power stage circuit, compensated error amplifier, PWM comparator, dead time
generation circuit and gate driver. Based on AMI0.5 um process, the whole circuit
system as well as each functional block are simulated and the simulation results show
that the output voltage ripple of this synchronous buck converter is smaller than
10mV. At 6Ω load resistance, the synchronous buck converter has efficiency greater
than 96% and at input voltage of 3.7V, the synchronous buck converter has efficiency
greater than 90%.
iv
LIST OF TABLES
3.1 Basic design specifications for the synchronous buck converter .............. 14
4.1 Line regulation simulation results when RL=6Ω....................................... 34
4.2 Load regulation simulation results when Vin=3.7V ................................. 36
4.3 Simulation results for efficiency when RL=6Ω ......................................... 39
4.4 Simulation results for efficiency when Vin=3.7V .................................... 39
v
LIST OF FIGURES
2.1 Schematic of basic buck converter. ............................................................. 4

2.2 Schematic of synchronous buck converter .................................................. 5
2.3 Inductor current in (a) continuous conduction mode (b) discontinuous
conduction mode and (c) boundary conduction mode ................................ 6
2.4 Schematic of voltage-mode control circuitry .............................................. 8
2.5 Schematic of current-mode control circuitry .............................................. 9
2.6 Type 3 amplifier circuitry ......................................................................... 10
3.1 Block diagram of the designed voltage-mode controlled synchronous
buck converter ........................................................................................... 13
3.2 Schematic of power stage for the designed synchronous buck converter . 15
3.3 Schematic of power stage test ................................................................... 17
3.4 Output voltage of power stage alone ......................................................... 18
3.5 Functional block diagram of the buck converter....................................... 18
3.6 Bode plot of the power stage together with PWM controller ................... 19
3.7 Bode plot of the error amplifier with type 3 compensation ...................... 20
3.8 Bode plot of the whole feedback loop....................................................... 20
3.9 Schematic of the error amplifier ............................................................... 21
3.10 Schematic of the error amplifier test ......................................................... 22
3.11 Simulated loop gain and phase of the error amplifier ............................... 22
3.12 Schematic of the compensated error amplifier.......................................... 23
3.13 Schematic of the voltage comparator for PWM generation ...................... 24
3.14 Schematic of the voltage comparator test bench ....................................... 25
3.15 Simulation waveform of the voltage comparator ...................................... 25
3.16 Block diagram of non-overlapping signal generation ............................... 26
3.17 Schematic of the non-overlapping signal generation circuit ..................... 27
3.18 Schematic of NOR gate............................................................................. 28
3.19 Schematic of NAND gate.......................................................................... 29
3.20 Schematic of the dead time generator test bench ...................................... 30
3.21 Simulation results of the dead time generator ........................................... 30
3.22 Schematic of the dead time generator with gate driver ............................. 31
vi
4.1 Output voltage transient response and voltage ripple when Vin=3.7V,
RL=6Ω ....................................................................................................... 32
4.2 Inductor current waveform of the designed synchronous buck converter
operated at Vin=3.7V, RL=6Ω .................................................................. 33
4.3 Dead time of the gate drive signal when the converter is operated at
Vin=3.7V, RL=6Ω ..................................................................................... 34
4.4 Simulation waveform of line transient response when the input voltage
changes from 4.6V (600us) to 4.9V (610us) ............................................. 35
4.5 Simulation waveform of line transient response when the input voltage
changes from 4.9V (600us) to 4.6V (610us) ............................................. 35
4.6 Simulation waveform of load transient response when the output load
changes from 500mA (600us) to 550mA (610us) .................................... 37
4.7 Simulation waveform of load transient response when the output load
changes from 550mA (600us) to 500mA (610us) .................................... 38
vii
CHAPTER I
INTRODUCTION
Background and Motivation
Due to the development of portable electronic systems, power management
integrated circuits (ICs) such as switch mode DC-DC converters have become critical
building blocks and are widely used in laptops, cellular phones, PDAs, GPSs, etc [1]-
[3]. The power management ICs are also widely used in industrial products to provide
power supplies to sensors, microcontrollers, digital and analog circuit boards [1]. In a
complicated integrated circuit, many units like analog blocks, RF blocks and
digital/mixed-signal blocks could be included. These different blocks need different
supply voltages in order to operate properly. Instead of using multiple batteries, DC-
DC converters could be used to convert one DC voltage level to another and thus only
one battery is needed for the whole system, leading to smaller electronic systems. On
the other hand, when the battery for the whole system becomes old or the original
battery is used for different blocks with the same input voltage requirement, the output
voltage of the old battery will change as well as the load resistance of the original one,
in which cases a constant output voltage is desired. Line and load regulation abilities
of DC-DC converters are used to meet this requirement as the environment changes.
Also, the requirement for a smooth supply voltage for different blocks puts forward
the need for the low output voltage ripple of DC-DC converters. Finally, for a certain
portable electronic system or consumer electronic product, the total power one battery
1
could provide for that electronic circuit is fixed. High efficiency energy conversion is
required for long time operations with a single battery. This thesis work was motivated
by the stringent requirement of a single battery operated system and the challenge of
achieving a highly efficient power conversion system.
The Pulse-width modulation (PWM) technique and voltage-mode control
technique are implemented in my design. This design work is suitable for single-cell
lithium-ion (Li-Ion) battery operated portable applications [4]. A high operation
switching frequency is used to obtain lower output voltage ripple, smaller inductor and
capacitor values and smaller power transistors.
Thesis Organization
This thesis work is organized as follows. The techniques related to the design
of the synchronous buck converter including synchronous rectification, inductor
operating mode, voltage-mode and current-mode control, stability and type 3 amplifier
are discussed in Chapter 2. System level description and subcircuits design issues are
presented in Chapter 3. Single block simulation results are also shown in Chapter 3.
System simulation and results are discussed in Chapter 4. Conclusions and future
work are summarized in Chapter 5.
2
CHAPTER II
SYNCHRONOUS BUCK CONVERTER
In this chapter, the basic concept and theories related to the synchronous buck
converter design will be discussed respectively. The DC-DC converter concept and
synchronous rectification techniques will be discussed in the first part. Three kinds of
inductor operating modes will be discussed in the second part. Voltage-mode and
current-mode control schemes will be covered in the third part and the last part will
talk about stability and type 3 amplifier.
DC-DC Converters and Synchronous Rectification
DC-DC converters can convert one voltage level to another voltage level we
want and have different kinds of structures. A simple voltage divider could serve as a
DC-DC converter to get lower voltages than the supply voltage but suffers from an
efficiency problem. Usually, if the difference between the input voltage and output
voltage of a resistive divider is large, there will be large amount of power consumed
by the divider. This is the same for linear regulators. When the voltage difference is
low, a low-dropout (LDO) regulator could be used to get lower voltages as well as
high efficiency.
Compared with the simple voltage divider and LDO, switched-mode power
supply (SMPS) has great advantages. LDO can only get lower output voltage than the
input voltage. By using different structures, SMPS can get voltages either lower or
higher than the input voltage and with the same or opposite polarity. Basic structures
3
of SMPS include buck converter, boost converter and buck-boost converter. Buck
converters can get output voltage lower than the input voltage, boost converters can
get output voltage higher than the input voltage and buck-boost converters can get
output voltage either less or greater than the input voltage. Also, careful design
considerations can achieve high efficiency for SMPS.
This thesis work is focused on the design of synchronous buck converter with a
high efficiency. Synchronous buck converters are modified version of basic buck
converters. Figure 2.1 shows the schematic of a basic buck converter. It’s a square
wave generator followed by an LC filter [5]. When the diode is conducting, the
voltage drop across a common diode can be about 0.7V and 0.3V for a Schottky diode.
There will be a lot of power consumption there. In order to increase the efficiency of
the basic buck converter, synchronous rectification techniques are used. That is, the
diode in the basic buck converter is replaced by another switch, as is shown in Figure
2.2.
Figure 2.1 Schematic of basic buck converter
4
Figure 2.2 Schematic of synchronous buck converter
Since the turn-on resistance of a power MOSFET can be very low when large
size transistors are used, the voltage drop across the power MOSFET is low when it is
conducting. Thus a sufficient amount of power could be saved by using synchronous
buck converters.
Inductor Operating Mode
Based on the current flowing through the inductor, three inductor operating
modes are defined [5]:
1. Continuous conduction mode (CCM): the current never goes back to zero within the
considered switching cycle and the switch always closes with current circulating in the
coil.
2. Discontinuous conduction mode (DCM): the current always goes back to zero
within a switching cycle and the switch always closes in zero-current conditions.
3. Boundary or borderline conduction mode (BCM): a controller observes the current
in the inductance, and when it is detected to be zero, the switch immediately closes.
5
The BCM converter can also be found under the name of critical conduction mode
converter or CRM.
Figure 2.3 shows an example of inductor current waveforms for all three kinds
of inductor operating modes.
Figure 2.3 Inductor current in (a) continuous conduction mode (b) discontinuous
conduction mode and (c) boundary conduction mode
For CCM, power is continuously delivered to the load and thus a higher
efficiency can be expected for high loads operations. CCM is used in this thesis work.
6
Voltage-Mode and Current-Mode Control
For an ideal buck converter operated in CCM, the relationship among input
voltage, output voltage and duty cycle can expressed as [5]:
Vout = DVin (2.1)
Thus, the buck converter output voltage can be modified by playing on the
duty cycle D. There are two commonly used control schemes to adjust the duty cycle
to achieve the desired output voltage. One is the voltage-mode control and the other
one is the current-mode control.
Figure 2.4 shows the schematic of the voltage-mode control circuitry. The
control circuitry is composed of voltage divider, error amplifier, PWM comparator,
gate driver and sawtooth signal generator. The error amplifier amplifies the voltage
difference between the reference voltage and a proportion of output voltage and the
error voltage is gained at the output of the error amplifier. The PWM comparator
compares the error voltage with a sawtooth signal and gets the pulse signal to go
through the gate driver to control power MOSFETs.
7
Figure 2.4 Schematic of voltage-mode control circuitry
Figure 2.5 shows the schematic of current-mode control circuitry. The control
circuitry is composed of voltage divider, error amplifier, PWM comparator, RS latch,
gate driver and clock generator. Current-mode modulators rely upon the instantaneous
inductor current. A clock pulse sets a latch which closes the power switch and the
𝑉𝑉
current goes up in the inductor following a slope. When the current reaches a given
𝐿𝐿
set point value, a comparator detects it and resets the latch. The switch now opens and
waits for the next clock cycle to close again. The feedback loop controls the peak
current set point and indirectly the duty cycle [5].
8
Figure 2.5 Schematic of current-mode control circuitry
The voltage-mode control has the advantage of a simpler circuit structure and
thus lower power loss. Also, the output voltage regulation of the voltage-mode control
is independent of current. This thesis work uses the voltage-mode control for the
feedback loop design.
Stability and Type 3 Amplifier
Since the voltage-mode controlled synchronous buck converter is configured in
a feedback loop, stability issues should be taken into consideration. When designing
the whole system of synchronous buck converter, a phase margin (PM) of 450
represents the absolute minimum but solid designs aim for around 700 to 800 phase
margin, offering a good stability and a fast nonringing transient response [5].
9
When shaping the feedback loop, the type 3 configuration is used where the
phase shift brought by the power stage can reach −1800 . This is the case for the CCM
voltage-mode buck or boost-derived types of converters [5].
Figure 2.6 shows the type 3 amplifier circuitry.
Figure 2.6 Type 3 amplifier circuitry
The transfer function of the type 3 amplifier is [5]:
𝑠𝑠𝑅𝑅2 𝐶𝐶1 +1 𝑠𝑠𝐶𝐶3 (𝑅𝑅1 +𝑅𝑅3 )+1

𝐺𝐺 (𝑠𝑠) = 𝐶𝐶 𝐶𝐶 (2.2)
𝑠𝑠𝑅𝑅1 (𝐶𝐶1 +𝐶𝐶2 )(1+𝑠𝑠𝑅𝑅2 1 2 ) (𝑠𝑠𝑅𝑅3 𝐶𝐶3 +1)
𝐶𝐶 1 +𝐶𝐶 2
The equations for calculating the component values of the type 3 amplifier
using the k factor are listed as follows [5],
𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵 = 𝑃𝑃𝑃𝑃 − 𝑃𝑃𝑃𝑃 − 90 (2.3)
𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏𝑏
𝑘𝑘 = [tan � + 45�]2 (2.4)
4
10
1
𝐶𝐶2 = (2.5)
2𝜋𝜋 𝑓𝑓𝑐𝑐 𝐺𝐺𝑅𝑅1
𝐶𝐶1 = 𝐶𝐶2 (𝑘𝑘 − 1) (2.6)
√𝑘𝑘
𝑅𝑅2 = 2𝜋𝜋 𝑓𝑓 𝐶𝐶 (2.7)
𝑐𝑐 1
1𝑅𝑅
𝑅𝑅3 = 𝑘𝑘 −1 (2.8)
1
𝐶𝐶3 = (2.9)
2𝜋𝜋𝑓𝑓𝑐𝑐 √𝑘𝑘 𝑅𝑅3
The detailed design process will be discussed in chapter 3.
11
CHAPTER III
SYSTEM DESCRIPTION AND SUBCIRCUITS DESIGN
This chapter explains in detail the system level specifications of the designed
synchronous buck converter first. And then circuit schematics of each block are
presented and discussed. Simulations are conducted in each part alone to verify that
each part can work properly before it is added to the whole system. The system block
diagram is shown in chapter 3.1. Power stage design, compensation network design,
error amplifier design, voltage comparator design, dead time generator design and gate
driver design are discussed in chapter 3.2, 3.3, 3.4, 3.5, 3.6 and 3.7, respectively.
System Description and Design Specifications
A voltage-mode controlled synchronous buck converter is designed in this
work. Figure 3.1 shows the block diagram of the designed voltage-mode controlled
synchronous buck converter.
12
Figure 3.1 Block diagram of the designed voltage-mode controlled synchronous buck
converter
There are mainly four parts in this design. The most important part is the
power stage which consists of a power PMOS transistor, a power NMOS transistor
and LC filter. The equivalent series resistance (ESR) of the capacitor and inductor
were also taken into consideration. The second part is a compensated error amplifier
which can generate the error signal as well as maintaining a desired phase margin for
the feedback loop. The third part is a PWM comparator which compares the error
signal with the sawtooth signal to generate the PWM signal. The fourth part is a dead
time generation block together with the gate driver. The dead time generation block is
designed to avoid the shoot-through problem and the gate driver is designed to drive
large size transistors.
13
Table 3.1 summarizes the basic design specifications for this synchronous buck
converter.
Table 3.1 Basic design specifications for the synchronous buck converter
Parameter Specifications
Input Voltage 3.5V-5V
Output Voltage 1.8V
Output Load 250mA-950mA
Output Voltage Ripple Peak-to-Peak <10mV
Switching Frequency 1MHz
Phase Margin 59.12°
Efficiency @ 6 Ohm Load Resistance >96%
Efficiency @ 3.7 V Input Voltage >90%
External Capacitor 10uF
External Capacitor ESR 20mΩ
External Inductor 3.3uH
External Inductor ESR 3mΩ
CMOS Process AMI 0.5um
Power Stage Design
Figure 3.2 shows the schematic of the power stage for the designed
synchronous buck converter.
14
Figure 3.2 Schematic of power stage for the designed synchronous buck converter
For the power stage design of the synchronous buck converter, there are
mainly two issues. The first one is how to decide the width of power MOSFETs and
the other one is how to decide the value of LC filter.
Regarding the width of power MOSFETs, conduction losses decrease as power
MOSFET widths increase since as power MOSFET widths increase, the turn-on
resistance of the power MOSFET will decrease. Switching losses increase as power
MOSFET widths increase since as power MOSFET widths increase, the gate
capacitance of the power MOSFET will increase.
15
The equations for getting the optimum device widths are given as follows [6]-
[7] by equating the conduction losses and switching losses of the switches to minimize
their total power loss.
Δi 2
𝑖𝑖𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 = �(1 − 𝐷𝐷)(𝐼𝐼 2 + ) (3.1)
3
Δi 2
𝑖𝑖𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 = �𝐷𝐷(𝐼𝐼 2 + ) (3.2)
3
𝑖𝑖𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟 ,𝑝𝑝
𝑊𝑊𝑛𝑛 ,𝑝𝑝 = 𝐶𝐶 (3.3)
𝑜𝑜𝑜𝑜 𝑉𝑉 𝑖𝑖𝑖𝑖 �2.5𝑓𝑓𝑠𝑠 𝑢𝑢 𝑛𝑛 ,𝑝𝑝 (𝑉𝑉 𝑖𝑖𝑖𝑖 −𝑉𝑉𝑡𝑡 )
Maple calculations were implemented to get the optimum power MOSFET
widths. The calculation was based on Vin=3.7V, Vout=1.8V, load current=300mA,
switching frequency=1MHz. The optimum width for the power PMOS is 70.3249mm
and the optimum width for the power NMOS is 41.132mm.
As for the value of LC filter, a calculation is conducted based on the
requirement for the maximum output voltage ripple and CCM operation. The inductor
value for buck converter operated at BCM can be calculated using equation (3.4) [5].
(1−𝐷𝐷)𝑅𝑅
𝐿𝐿𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 = (3.4)
2𝐹𝐹𝑠𝑠𝑠𝑠
The output voltage ripple value for a buck converter operated in CCM could be
calculated using equations (3.5) and (3.6) [5].
𝜋𝜋 2 𝑓𝑓 2
Δ𝑉𝑉 = �𝐹𝐹 0 � (1 − 𝐷𝐷)𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 (3.5)
2 𝑠𝑠𝑠𝑠
(1−𝐷𝐷)
Δ𝑉𝑉𝐸𝐸𝐸𝐸𝐸𝐸 = 𝑅𝑅𝐸𝐸𝐸𝐸𝐸𝐸 𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 (3.6)
𝐿𝐿𝐹𝐹𝑠𝑠𝑠𝑠
16
In order for the buck converter to operate in CCM, the inductor value should
be greater than the value calculated in BCM. Also, according to the requirement for
the output voltage ripple, the LC filter value could be easily decided. The calculated
LC filter value for this design is 3.3uH and 10uF, respectively.
Figure 3.3 shows the schematic of power stage test and figure 3.4 shows the
output voltage of power stage alone.
Figure 3.3 Schematic of power stage test
17
Figure 3.4 Output voltage of power stage alone
Compensation Network Design
Figure 3.5 shows the functional block diagram of the buck converter.
Figure 3.5 Functional block diagram of the buck converter
18
Transfer functions of the power stage (taken into consideration of turn-on
resistance of Power MOSFETs and ESR of capacitor and inductor) and the PWM
controller were given in equations (3.7) and (3.8) [2].
𝐸𝐸𝐸𝐸𝐸𝐸 𝐶𝐶 𝑅𝑅 𝐿𝐿 1 𝑅𝑅 𝐿𝐿 2
{�𝑠𝑠+ ��𝑉𝑉𝐼𝐼 −𝑖𝑖 𝐿𝐿 �𝑅𝑅𝑝𝑝 +𝑅𝑅𝑛𝑛 ��+ 2 [𝑉𝑉𝐼𝐼 −𝑖𝑖 𝐿𝐿 �𝑅𝑅𝑝𝑝 +𝑅𝑅𝑛𝑛 �]
𝐿𝐿(𝐸𝐸𝐸𝐸𝐸𝐸 𝐶𝐶 +𝑅𝑅 𝐿𝐿 ) 𝐶𝐶�𝐸𝐸𝐸𝐸𝐸𝐸 𝐶𝐶 +𝑅𝑅 𝐿𝐿 � 𝐿𝐿𝐿𝐿 �𝐸𝐸𝐸𝐸𝐸𝐸 𝐶𝐶 +𝑅𝑅 𝐿𝐿 �
𝑇𝑇3 (𝑠𝑠) = 1 𝐸𝐸𝐸𝐸𝐸𝐸 𝐶𝐶 𝑅𝑅 𝐿𝐿 1
(3.7)
𝑠𝑠 2 +𝑠𝑠 �𝐸𝐸𝐸𝐸𝐸𝐸𝐿𝐿 + +𝐷𝐷�𝑅𝑅𝑝𝑝 +𝑅𝑅𝑛𝑛 �−𝑅𝑅𝑛𝑛 �+ {𝐸𝐸𝐸𝐸𝐸𝐸 𝐿𝐿 +𝐷𝐷�𝑅𝑅𝑝𝑝 +𝑅𝑅𝑛𝑛 �−𝑅𝑅𝑛𝑛 +𝑅𝑅𝐿𝐿 }
𝐿𝐿 𝐸𝐸𝐸𝐸𝐸𝐸 𝐶𝐶 +𝑅𝑅 𝐿𝐿 𝐿𝐿𝐿𝐿 (𝐸𝐸𝐸𝐸𝐸𝐸 𝐶𝐶 +𝑅𝑅 𝐿𝐿 )
1
𝑇𝑇2 (𝑠𝑠) = (3.8)
𝑉𝑉𝑚𝑚
The turn-on resistance of power NMOS and power PMOS transistors could be
obtained through printing DC operating point in Cadence. Vm is set to be 1V. Figure
3.6 shows the Bode plot of the power stage together with PWM controller.
Figure 3.6 Bode plot of the power stage together with PWM controller
Since the phase shift brought by the power stage of the synchronous buck
converter can reach -1800, the type 3 amplifier is used for the compensation network.
Equations (2.3) – (2.9) can be used to calculate the resistor and capacitor value for the
compensation network. As the values of R1 and Rlower are set to be 10kΩ, the
calculated values are C2=507.99pF, C1=16.878nF, R2=1103.3Ω, R3=300.97Ω,
19
C3=1.8078nF. Equation (2.2) can be used to plot the Bode plot of the type 3 amplifier.
Figure 3.7 shows the Bode plot of the error amplifier with type 3 compensation.
Figure 3.7 Bode plot of the error amplifier with type 3 compensation
Figure 3.8 shows the Bode plot of the whole feedback loop.
Figure 3.8 Bode plot of the whole feedback loop
Simulation results show that the whole system has a phase margin of 59.12°at
a crossover frequency of 50.18kHz.
20
Error Amplifier Design
A high DC gain and a unity gain frequency are required for the error amplifier.
Stability issues should be taken into consideration since the error amplifier is
configured in a feedback loop. A miller compensated two-stage differential to single
ended amplifier is implemented. Figure 3.9 shows the schematic of the error amplifier.
Figure 3.9 Schematic of the error amplifier
Through DC simulation, we can get the gm value for N2. The value of R0 can
be obtained through equation (3.9) [8].

1
R0 = (3.9)
gmN 2
After R0 is set, C0 can be adjusted to get the desired phase margin. A unity
gain configuration was used to measure phase margin, gain margin, DC gain and unity
gain frequency of the amplifier. Figure 3.10 shows this configuration. Figure 3.11
shows the simulated loop gain and phase.
21
Figure 3.10 Schematic of the error amplifier test
Figure 3.11 Simulated loop gain and phase of the error amplifier
The simulated phase margin is 61.98 ° , gain margin=13.8dB, unity gain
frequency =51.1013MHz, DC gain=74.47dB. Figure 3.12 shows the schematic of the
compensated error amplifier.
22
Figure 3.12 Schematic of the compensated error amplifier
Voltage Comparator Design
When designing a voltage comparator, there is no need to consider stability
issues since it works in the open loop condition. A three-stage voltage comparator was
designed for the PWM generation. The first stage converts the differential input to
single output. The second stage is a common source amplifier and the third stage is a
push-pull amplifier. The third stage is used to get full amplitude output. Figure 3.13
shows the schematic of the voltage comparator for PWM generation.
23
Figure 3.13 Schematic of the voltage comparator for PWM generation
Figure 3.14 shows the voltage comparator test bench. A 1MHz, 0-1V saw tooth
signal was added to the positive port of the comparator. A 1MHz, average voltage of
600mV, amplitude of 50mV sinusoidal wave was added to the negative port of the
comparator. Figure 3.15 shows simulation waveform of the voltage comparator.
24
Figure 3.14 Schematic of the voltage comparator test bench
Figure 3.15 Simulation waveform of the voltage comparator
25
Dead Time Generator Design
A dead time is needed between control signals for the two power MOSFETs. If
there is no dead time between these two signals, both power MOSFETs may be turned
on at the same time leading to a large current flowing directly from the input port to
the ground and thus decreasing efficiency. Figure 3.16 shows the block diagram of
non-overlapping signal generation. One input pulse goes through the dead time
generator and two branches of signal appear at the two output ports. The two signals at
the output ports have some non-overlapping periods at both the rising and falling
edges of the pulse signal. Vout1 is used to drive power PMOS and Vout2 is used to
drive power NMOS.
Figure 3.16 Block diagram of non-overlapping signal generation
Figure 3.17 shows the schematic of the non-overlapping signal generation
circuit. An inverter chain with alternative transistor sizes is used for the delay part.
The time delay is generated by using the RC delay generated when smaller size
26
transistors charge the gate capacitance of larger size transistors. Figure 3.18 and figure
3.19 show the schematic of the logic gates used in the dead time generator.
Figure 3.17 Schematic of the non-overlapping signal generation circuit
27
Figure 3.18 Schematic of NOR gate
28
Figure 3.19 Schematic of NAND gate
Figure 3.20 shows the schematic of the dead time generator test bench. A
single square wave was applied to the input port of the dead time generator and figure
3.21 shows the simulated waveform and dead time. In figure 3.21, the first picture
shows that the output signals have almost the same waveform. When we zoom in,
picture 2 shows some minor difference. When we further zoom in, the dead time we
get at the rising edge and falling edge of the two signals is 1.95ns and 1.97ns,
respectively.
29
Figure 3.20 Schematic of the dead time generator test bench
Figure 3.21 Simulation results of the dead time generator
30
Gate Driver Design
Since the width of power MOSFETs is large, the gate capacitance is large. The
control signals generated directly from the dead time generator may not be able to
drive the large size power MOSFETS. In order to drive large capacitive loads, an
inverter chain was added to the output of the dead time generator, the size of
transistors in the inverter chain increases by a factor of 3 [9]. Figure 3.22 shows the
schematic of the dead time generator with gate driver.
Figure 3.22 Schematic of the dead time generator with gate driver
31
CHAPTER IV
SYSTEM SIMULATION AND RESULTS
This part simulates and summarizes the performance of the whole synchronous
buck converter system. Output voltages, output voltage ripple, inductor current and
dead time are simulated in Chapter 4.1. The line regulation ability is simulated in
Chapter 4.2. The load regulation ability is simulated in Chapter 4.3. The efficiency is
simulated in Chapter 4.4.
Voltage and Current
Figure 4.1 shows the output voltage transient response and voltage ripple of the
whole system when the input voltage is 3.7V and output load resistance is 6Ω. When
the output voltage becomes stable, it maintains a level of 1.8V. The output voltage
ripple is about 5.57mV, which is smaller than 10mV.
Figure 4.1 Output voltage transient response and voltage ripple when Vin=3.7V,
RL=6Ω
32
Figure 4.2 shows the inductor current waveform of the designed synchronous
buck converter operated at Vin=3.7V, RL=6Ω. As can be seen from the waveform, at
all times, the inductor current value is greater than 0, which means the converter is
operated in CCM.
Figure 4.2 Inductor current waveform of the designed synchronous buck converter
operated at Vin=3.7V, RL=6Ω
Figure 4.3 shows the dead time of the gate drive signal when the converter is
operated at Vin=3.7V, RL=6Ω. The dead time at the rising and falling edge of the
pulse signal is approximately 1.95ns and 1.96ns.
33
Figure 4.3 Dead time of the gate drive signal when the converter is operated at
Vin=3.7V, RL=6Ω
Line Regulation Results
We change input voltage from 3.5V to 5V and measure the output voltage
when the load resistance is 6Ω. The measurement results are summarized in table 4.1.
Table 4.1 Line regulation simulation results when RL=6Ω

Vin (V) Vout (V)
3.5 1.801
3.7 1.799
3.9 1.798
4.1 1.798
4.3 1.799
4.5 1.799
4.7 1.8
4.9 1.8
5 1.8
34
Figure 4.4 shows the simulation waveform of line transient response when the
input voltage changes from 4.6V (600us) to 4.9V (610us). Figure 4.5 shows the
simulation waveform of line transient response when the input voltage changes from
4.9V (600us) to 4.6V (610us).
Figure 4.4 Simulation waveform of line transient response when

the input voltage changes from 4.6V (600us) to 4.9V (610us)
Figure 4.5 Simulation waveform of line transient response when

the input voltage changes from 4.9V (600us) to 4.6V (610us)
35
As we can see from table 4.1, figure 4.4 and figure 4.5, when the input voltage
changes, the output voltage can maintain a constant level. The converter has good line
regulation ability.
Load Regulation Results
We change the output load from 250mA to 950mA and measure the output
voltage when the input voltage is 3.7V. The measurement results are summarized in
table 4.2.
Table 4.2 Load regulation simulation results when Vin=3.7V

IL (mA) Vout (V)
250 1.797
300 1.797
400 1.797
500 1.797
600 1.797
700 1.809
800 1.796
900 1.798
950 1.798
Figure 4.6 shows the simulation waveform of load transient response when the
output load changes from 500mA (600us) to 550mA (610us). Figure 4.7 shows the
simulation waveform of load transient response when the output load changes from
550mA (600us) to 500mA (610us).
36
Figure 4.6 Simulation waveform of load transient response when

the output load changes from 500mA (600us) to 550mA (610us)
37
Figure 4.7 Simulation waveform of load transient response when

the output load changes from 550mA (600us) to 500mA (610us)
As we can see from table 4.2, figure 4.6 and figure 4.7, when the output load
changes, the output voltage can maintain a constant level. The converter has good load
regulation ability.
Efficiency
We change input voltage from 3.5V to 5V and simulate the power
consumption of the whole system and each instance when the load resistance is 6Ω .
The simulation results for different input voltages are summarized in table 4.3.
38
Table 4.3 Simulation results for efficiency when RL=6Ω

Vin (V) Total Power Power Delivered Efficiency
(mW) to Load (mW) (%)
3.5 561.5 540.3 96.224
3.7 560.4 539.4 96.25
3.9 560.5 539.6 96.27
4.1 560 539.3 96.3
4.3 560.2 539.5 96.3
4.5 560.3 539.7 96.32
4.7 560.4 539.7 96.3
4.9 560.5 539.7 96.29
5 560.5 539.7 96.29
We change the output load from 250mA to 950mA and simulate the power
consumption of the whole system and each instance when the input voltage is 3.7V.
The efficiency results for the different output load are summarized in table 4.4.
Table 4.4 Simulation results for efficiency when Vin=3.7V

IL (mA) Total Power Power Delivered Efficiency
(mW) to Load (mW) (%)
250 467.83 450 96.19
300 561.01 540 96.25
400 749.5 720 96.06
500 939.6 900 95.79
600 1132.37 1080 95.38
700 1327.42 1260 94.92
800 1524.95 1440 94.43
900 1724.9 1620 93.92
950 1825.7 1710 93.66
39
CHAPTER V
CONCLUSIONS AND FUTURE WORK
An integrated voltage-mode controlled synchronous buck converter using
AMI0.5 um process is designed and simulated in this work. The designed synchronous
buck converter works properly at input voltage range of 3.5V-5V and output load
range of 250mA-950mA. The synchronous buck converter has a output voltage ripple
smaller than 10mV. At 6Ω load resistance, the synchronous buck converter has
efficiency greater than 96%. At input voltage of 3.7V, the synchronous buck converter
has efficiency greater than 90%. The synchronous buck converter has good line and
load regulation ability for its proper input voltage and output load ranges.
For future work, I will finish the design for saw tooth signal generator and bias
circuit. Layout, fabricate and test the circuit to compare the real performances with
simulated ones if possible. Use new circuit architectures to optimize power
consumption for each building block to further boost efficiency. Implement protection
circuits to protect the converter for large input voltages. Implement under-voltage
lockout circuits for input voltages lower than the required input voltage range.
40
REFERENCES
[1] Yu Du, Qiaoqiao Liu, and Alex Q. Huang, “A Monolithic CMOS Synchronous
Buck Converter with a Fast and Low-cost Current Sensing Scheme,” in IEEE
Energy Conversion Congress and Exposition, Raleigh, NC, Sept. 2012.
[2] Wan-Rone Liou, Mei-Ling Yeh, and Yueh Lung Kuo, “A High Efficiency Dual-
Mode Buck Converter IC For Portable Applications,” in IEEE Transactions on
Power Electronics, vol. 23, no. 2, pp. 667-677, Mar. 2008.
[3] Yeong-Tsair Lin, Mei-Chu Jen, Wen-Yaw Chung, Dong-Shiuh Wu, Ho-Cheng
Lin, and Jiann-Jong Chen, “A Monolithic Buck DC-DC Converter with On-chip
PWM Circuit,” in Microelectronics Journal, vol. 38, no. 8-9, pp. 923-930, Aug.-
Sept. 2007.
[4] Ashis Maity, Amit Patra, Norihisa Yamamura, and Jonathan Knight, “Design of a
20 MHz DC-DC Buck Converter with 84% Efficiency for Portable Applications,”
in IEEE 2011 24th International Conference on VLSI Design, vol., no., pp. 316-
321, 2-7 Jan. 2011.
[5] Christophe P. Basso, Switch-Mode Power Supplies SPICE Simulations and
Practical Designs. McGraw-Hill, 2008.
[6] Volkan Kursun, Siva G. Narendra, Vivek K. De, and Eby G. Friedman, “Low-
Voltage-Swing Monolithic dc-dc Conversion,” in IEEE Transactions on Circuits
and Systems-II: Express Briefs, vol. 51, no.5, pp. 241-248, May 2004.
41
[7] Siamak Abedinpour, Bertan Bakkaloglu, and Sayfe Kiaei, “A 65MHz Switching
Rate, Two-Stage Interleaved Synchronous Buck Converter with Fully Integrated
Output Filter,” in IEEE International Symposium on Circuits and Systems, pp.
5315-5318, Sept. 2006.
[8] Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.
[9] Phillip E. Allen, and Douglas R. Holberg, CMOS Analog Circuit Design, Second
Edition, Oxford University Press, 2002.
42

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DESIGN OF INTEGRATED VOLTAGE-MODE CONTROLLED

DC-DC BUCK CONVERTER

Longfei Wang, B.S.E.E

Submitted to the Graduate Faculty

Dr. Stephen Bayne

It’s a precious and wonderful journey to pursue my Master of Science degree

genuine assistance of many people.

help are crucial and are greatly appreciated.

LIST OF TABLES ................................................................................................ v

LIST OF FIGURES ............................................................................................. vi

Background and Motivation.............................................................................. 1

DC-DC Converters and Synchronous Rectification ......................................... 3

System Description and Design Specifications............................................... 12

Voltage and Current ........................................................................................ 32

This thesis work focuses on the design of an integrated voltage-mode

as a lower voltage ripple.

The functional blocks of this designed synchronous buck converter include

greater than 90%.

2.1 Schematic of basic buck converter. ............................................................. 4

Background and Motivation

Due to the development of portable electronic systems, power management

digital/mixed-signal blocks could be included. These different blocks need different

achieving a highly efficient power conversion system.

The Pulse-width modulation (PWM) technique and voltage-mode control

lithium-ion (Li-Ion) battery operated portable applications [4]. A high operation

capacitor values and smaller power transistors.

of the synchronous buck converter including synchronous rectification, inductor

work are summarized in Chapter 5.

SYNCHRONOUS BUCK CONVERTER

talk about stability and type 3 amplifier.

DC-DC Converters and Synchronous Rectification

considerations can achieve high efficiency for SMPS.

Figure 2.1 Schematic of basic buck converter

Figure 2.2 Schematic of synchronous buck converter

conducting. Thus a sufficient amount of power could be saved by using synchronous

Inductor Operating Mode

modes are defined [5]:

3. Boundary or borderline conduction mode (BCM): a controller observes the current

of inductor operating modes.

Voltage-Mode and Current-Mode Control

voltage, output voltage and duty cycle can expressed as [5]:

Vout = DVin (2.1)

one is the current-mode control.

control circuitry is composed of voltage divider, error amplifier, PWM comparator,

through the gate driver to control power MOSFETs.

Figure 2.4 Schematic of voltage-mode control circuitry

circuitry is composed of voltage divider, error amplifier, PWM comparator, RS latch,

current set point and indirectly the duty cycle [5].

Figure 2.5 Schematic of current-mode control circuitry

feedback loop design.

Stability and Type 3 Amplifier

Since the voltage-mode controlled synchronous buck converter is configured in

voltage-mode buck or boost-derived types of converters [5].

Figure 2.6 shows the type 3 amplifier circuitry.

Figure 2.6 Type 3 amplifier circuitry

The transfer function of the type 3 amplifier is [5]:

𝑠𝑠𝑅𝑅2 𝐶𝐶1 +1 𝑠𝑠𝐶𝐶3 (𝑅𝑅1 +𝑅𝑅3 )+1

using the k factor are listed as follows [5],

𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵 = 𝑃𝑃𝑃𝑃 − 𝑃𝑃𝑃𝑃 − 90 (2.3)

𝐶𝐶1 = 𝐶𝐶2 (𝑘𝑘 − 1) (2.6)

The detailed design process will be discussed in chapter 3.

SYSTEM DESCRIPTION AND SUBCIRCUITS DESIGN

System Description and Design Specifications

A voltage-mode controlled synchronous buck converter is designed in this