Net Physics

126 Operational Amplifier
Chapter 6
Operational Amplifier
+VCC
–
Symbol: Input 1 Output
Input 2 +
–VEE
(+) Non-inverting terminal, (–) Inverting terminal

Input impedance : Few mega  (Very high), Output impedance : Less than 100  (Very low)
Differential and Common Mode Operation: One of the more important features of a differential circuit
connection as provided in an op-amp is the circuit ability to greatly amplify signals that are opposite at the
two inputs while only slightly amplifying signals that are common to both inputs.
An op-amp provides an output component that is due to the amplification of the difference signals applied
to the plus and minus input and a component due to the signals common to both inputs.
Since amplification of the opposite input signals is much greater than that of common input signals the circuit
provides a common-mode rejection as described by a numerical value called COMMON MODE
REJECTION RATIO (CMRR).
Differential Input: When separate inputs are applied to the op-amp, the resulting difference signal is the
difference between the two inputs. Vd  V2  V1  V  V
Common Input: When both input signals applied to an op-amp is common, signal element due to the two
www.careerendeavour.com
V V  1 2
inputs can be defined as the average of the sum of the two signals. VC   2
.
 
Output Voltage: Since any signal applied to op-amp in general have both in phase and out of phase
components the resulting output can be expressed as V0  AdVd  AcVc .
Where Vd = difference voltage, VC = common mode voltage,
Ad = difference mode gain of the amplifier, Ac = Common mode gain of the amplifier.
Ad
CMRR {Common Mode Rejection Ratio}: CMRR 
Ac
The value of CMRR can also be expressed in log term as

Ad
CMRR (in d B )  20 log10 ( dB )
Ac
Operational Amplifier 127
Equivalent Circuit: While an input to the minus (–) input results in on opposite polarity output. The ac
equivalent circuit of the op-amp is shown in figure. As shown the input signal applied between input terminals
sees as input impedance Ri typically very high. The output voltage is shown to be the amplifier gain times
the input signal taken through output impedance R0, which is typically very low. An ideal op-amp circuit,
as shown in figure would have infinite input impedance zero output impedance and infinite voltage gain.
Rf
Vi R1
Ri Vd AdVd –
Vd AdVd V0 V0 op-amp V0
+
Inverting Amplifier: The most widely used constant gain amplifier circuit is the inverting amplifier.
Rf
Vi R1
– Rf
op-amp V0 . We can write V0   V1
+ R1
(–) sign represent 180º phase.

Non-inverting Amplifier: The connection of figures shows an op-amp that works as a non-inverting
amplifier or constant gain multiplier. It should be noted that the inverting amplifier connection is more widely
used because it has better frequency stability.
Vi
+
Vn V0
Vp –
Rf
R1
By virtual ground law: Vn = Vp = Vi

R1  R f Rf  Rf 
RV V
 Vi  1 0  0   1  V0   1   Vi
R1  R f Vi R1 R1  R1 
Voltage Follower or Unity Follower: The unity follower circuit as shown in figure provides a gain of unity
(1) with number polarity or phase reversal. From the equivalent circuit, it is clear that V0  V1 and that
the output is the same polarity and magnitude as the input. The circuit operates like an emitter or source
follower circuit except that the gain is exactly unity.
–
op-amp
+
V1 V0
Summing Amplifier: Three input summing amplifier.
Rf
R1
V1 – R R R 
R2 V0 V0    f V1  f V2  f V3 
V2
V3
R3 +  R1 R2 R3 
Differentiator : A differentiator circuit is shown in figure while not as useful as the circuit forms covered
above the differentiator does provide a useful operation, the resulting far the circuit being
R
Vi(t) C
–
dV (t ) op-amp V0(t)
V0 (t )   RC 1
dt +
where the scale factor is –RC.

C
Vi R
Integrator: – 1
V0 (t )   V1 (t )dt
RC 
op-amp V0(t)
+
Offset Currents and Voltages {d.c. characteristic of op-amp}:
Rf
Vi R1 IB–
–
V1 V0
V2 +
IB+
iB  iB–
(1) Input bias current :
2
(2) Input offset current: I0s = |IB+| – |IB–|
(3) Input offset voltage : V0s = V2 – V1
Note: Due to mismatching between V1 and V2 output voltage may be positive or
negative so we apply offset voltage (Vos).
Slew Rate: Another parameter reflecting the op-amp’s ability to handling varying signal is slew rate, defined
as slew rate = maximum rate at which amplifier output can change in volts per micro second.
V0
SR  V / s with t in  s.
t
SOLVED PROBLEMS
1. Calculate the slew rate of given circuit.
240K
Vi 10K
–
3
(0.02V,  = 300 × 10 ) V0
+
RF 240 K 
Soln. For a gain of magnitude ACL    24 . The output voltage provides.
R1 10 K 
K = ACL, Vi = 24(0.2V)  0.48V
SR 0.5v / s
   1.1 106 rad/sec
K 0.48
Voltage Buffer: A voltage buffer circuit provides a means of isolation on input signal from a load by using
a stage having unity gain with no phase or polarity inversion.
–
V0 V0  Vi
Vi +
Controlled Sources: Op-amp can be used to form various types of controlled sources. An input voltage
can be used to control on output voltage or current or an input current can be used to control on output
voltage or current. There type of connections are suitable far use in various instrument system (circuit). It
has four types:
(1) Voltage Controlled Voltage Source (2) Voltage Controlled Current Source
(3) Current Controlled Current Source (4) Current Controlled Voltage Source
(1) Voltage Controlled Voltage Source: An ideal form of a voltage source whose output V0 is controlled
by on input voltage VJ is shown in figure. The output voltage is seen to be independent on the input voltage.
This type of circuit can be built using an op-amp as shown in figure.
(i) Inverting op-amp: www.careerendeavour.com
Rf
Vi Ri Vn
–
A V0 Rf
+ K 
Vp Ri
By virtual ground condition Vn = Vp = 0
Vi  0 0  V0 V0  Rf 
Now KCL at point A,      
Ri Rf Vi  Ri 
(ii) Non-inverting op-amp:
Rf
Ri Vn Rf
– K  1
AV V0 Ri
p
+
Vi
By virtual ground condition Vp = Vn = Vi

Now KCL at point A
O  Vi Vi  Vo V  R f  Ri  V Rf
  0   Vi  0  1 
Ri Rf R f  R f  Ri  Vi Ri
(2) Voltage Controlled Current Source: An ideal form of circuit providing an output current controlled
by an input voltage is that of figure. The output current is dependent on the input voltage.
Practical Circuit:
Rf
If
Ri
Vi – Vi
Ii V0 Ii 
+ Ri
(3) Current Controlled Voltage Source: An ideal form of a voltage source controlled by a input current
is shown in figure. The output voltage is dependent on the input current.
Practical Circuit:
RL
I0
Vi –
Ii V0   I i RL
+ V0
(4) Current Controlled Current Source: An ideal form of a circuit providing on output current dependent
on an input current is shown in figure. In this type of circuit on output current is provided dependent on
the input current.
Practical Circuit:
R2 RL
I2 I1 I0
R1
– I1 R1  R1 
I1 I 0  I1  I 2  I1   1   I1  K I1
+ R2  R2 
Low Pass Filter: A 1st order, low pass filter using resistor and capacitor as in figure shown has a practical
slope of –20 dB per decade as shown in figure (rather them the ideal response of figure). The voltage gain
below the cutoff frequency is constant at
Rf 1
Av  1  , at a cut off frequency of fOH 
RG 2R1C1
Rf V0/V1
–20 dB/decade
RG (V+)
–
Rf (V0)
+ Output
Vi ~
(V–) voltage fOH
f
Second Order Filter: Connecting two sections of filter as in given figure result in a second order low pass
filter with cut off at 40 dB decade closer to the ideal characteristic.
R4 Rf V0/V1
AV –20 dB/decade
– –40 dB/decade
R1 R2 op-amp V0
Vi + f 2  f1
C2
C1 f
f1 f2
High-Pass Active Filter: First and second order high-pass active filter can be built as shown in figure.
1
The amplifier cut off frequency is fOL  with a second order filter R1 = R2 and C1 = C2 result
2R1C1
is the same cut off frequency as in figure.

R4 Rf R4 Rf
– –
C1 op-amp C1 C2 op-amp V0
V0 Vi +
Vi +
R1 R1 R2
V0/V1
–20dB/decade
–40dB/decade
f
fOL fOH
Band Pass Filter: Figure shows a band pass filter using two stages. The 1st a high pass filter and the
second a low pass filter. The combined operation being the desired band pass response.
R4 Rf
R4 Rf
–
– R2 op-amp V0
C1 op-amp +
Vi +
R1 C2
High Pass Section Low Pass Section

A(mid)
–20dB/decade
20dB/decade
fOL fOH
Instrument Amplifier:
V1 + V1

R1 R2
–

V1 R
R I –
V2 V0
R +
– R1

V2 + V2 RL
Calculation of output voltage:

R2 V1  V2
V0  (V2  V1) I ... (1)
R1 R
V1  V1  IR ... (2)
V2  V2  IR ... (3)
V1  V2
V1 V2  2 IR  V1  V2 I
R
(2 R  R )(V1  V2 )  2 R   R2 
 V1  V2   V0   1     (V2  V1 )
R  R   R1 
2.
An Active filter shown in figure. The DC gain and 3dB out off frequency are nearly.
Rv
Vi –
R1 V0
+
R1 = 15.9K  , R2 = 159K  , C = 1nF

(a) 40dB, 3.14KHz (b) 40dB, 1KHz (c) 20dB, 628KHz (d) 20dB, 1KHz
VD ( s )  R2 / (1  R2 C1 S )  R2
Soln:  
Vi ( S ) R1 R1 (1  R2 C1 S )
R2
AV    10  20 log10 10  20dB {log10 10  1}
R1
V0( S ) 1 1 1
At 3dB frequency  ;  Since, DC gain   0
V1( S ) 2 1  ( R2C1) 2
2
On putting the value of R2, C1 and comparing L.H.S. and R.H.S.  = 1KHz
3. In the given op-amp find, the value of output voltage. Given V1 = 2  V d.c. and V2 = 4  V d.c., AOL =
2 × 105, VCC =  15V..
Inverting terminal
V1 –
V0
V2 –
Non-inverting terminal
Soln: Let AOL is open loop voltage gain. In this care V0 = (V2 – V1)AOL
 V0 = (4.2) × 2 × 105 × 10–6  4 × 10–1 = 0.4V
[Vsat  output will vary between + Vsat and –Vsat]
If V1 = –2  V, V2 =  4  V
V0 = (4 + 2) × 2 × 105 × 10–6 = 12 × 10–1 = 1.2V
For Ideal Op-amp (Open Loop): Input and output voltage characteristic of open loop Op-amp.
V0
+Vsat
Vi
–Vsat
It is clear that open loop op-amp is able to amplify signals of very small amplitude. So, practically, open
loop Op-amp is not used.
For Ideal Op-Amp (Open loop):
(i) Ri =  , (ii) AOL =  , (iii) R0 = 0, (iv) Slew rate =  (v) CMRR = 
(vi) Band width = 
VP Ideal Op-amp AOL =

Vi +
Vn V0
–
R1 Rf
V0
 V0  AOL (V p  Vn )  (V p  Vn )  Vp  Vn
AOL  
I1
–
Concept of Virtual Ground: I2 V0
+
AOL =
V0
V1 – V2 =  0  V1  V2
AOL  (ideal case)
In ideal case, I1 = I2 = 0
4. In the given op-amp circuit. Find the output voltage.
400K
40K
–
VS = 0.1V V0
+
Current R=1K
is zero
Soln. The given op-amp is inverting amplifier. By the inverting amplifier gain formula
V0 R
A   f . Given, R = 400K, R = 40K, V = 0.1V
Vi R1 f 1 i
400
 V0 = –  0.1  1V
40
 V0 
5. For the given op-amp circuit. Find voltage gain  V  .
 i
450K V B 100K
100K
100K A
–
Vi Vn
V0
Vp +
Soln. Applying KCL at point A.
Vi  0 0  V V 100
  i   V  4.5Vi (i)
100 450 V 450
Now KCL at point B.
0 V V V  V0
  (Now by equation (i) V = –4.5 Vi)
450 100 100
4.5Vi 4.5Vi 4.5Vi  V0
 
450 100 100
V0 4.5Vi 4.5Vi 4.5Vi V0 20

On solving      
100 450 100 100 Vi 9
V0
6. In the given figure of OP-amp. Find the value of resistance R. Given  10
Vi
R V2B 100K
100K
Vi A
–
100K Vn V0
Vp +
Soln. By virtual ground condition V p  Vn  0

KCL at point A
Vi  0 0  V2 Vi V
   2
100 K R 100 K R
 R.Vi
 V2  ... (i)
100 K
Now KCL at point B
0  V2 V2  V0 V
  2 ... (ii)
R 100 K 100 K
V0
 10 (Given) ... (A)
Vi
By equation (i), (ii) and (A), R = 450K
7. In the given circuit of op-amp. Find I0 and IL.
100K
10K I
I – 0
V = 1V i V 0
+ I L
25K
V0  Rf   100 
Soln. This is inverting amplifier V    R     10   10
i  i   
V0 = –10V
 For current IL 0  (10)  I L  25 K 
10
 IL   0.4mA  For current I,
25
 0  ( 10)  100K  I  I = 0.1mA
 I0 = I + IL = 0.4 + 0.1  0.5 mA
8. Based on Non-inverting amplifier.
20K
A I
5K
– I0
Vn V
Vp + IL 0
5K . From the above given op-amp. Find IL and I0?
+ V = 1V
– i
0  1 1  V0
Soln. By VGP, Vn = Vp = 1V. KCL at point A,   V0  5V
5 20
5 1 5
IL = 1mA = = 1mA, I = = –0.2mA, I0 = I – IL = –(1 + 0.2) = –(1.2)mA
5 20
So, the current direction of I and I0 will be reverse.
9. In the given figure of op-amp. Find the value of I0 and IL?
4K
1K A I
– I0
Vn V0
Vp + IL
5K
+ 5V
–
Soln. This is non-inverting amplifier. Vp = Vn = 5V by VGP.

Now, KCL at point A,
0  5 5  VD 25 5  25 20
  VD  25V , I L   5mA , I    5mA
1K 4K 5K 4K 4
I 0  I  I L  5  5  10mA
Voltage Follower: Means a unity gain non-inverting op-amp.
–
Open circuit V0 = Vi
+
+
– Vi
(a) R f  0, R1  0 (b) R f  0, R1   (c) R f  0, any value of R1

(d) Rf = R1
For which value of Rf and R1 it makes voltage follower.
 Rin  Very high 

Voltage Follower:  
 Rout  Very low 
This resistance range is used for impedance matching or used as buffer.
Difference Amplifier:
R2
R1 Vn
V1 –
V
R1 V V0
V2 +
Vp
R2
In the above given op-amp figure. Find the value of output voltage in term of V1 and V2.
Soln. By the VGP condition Vp = Vn = V.
V1  V V  V0
For the upper loop,  ... (i)
R1 R2
V2  V V
For the lower loop,  ... (ii)
R1 R2
V2 1 1   R  R1 
 V    V  2 
R1  R1 R2   R1 R2 
V2 .R2
V  ... (A)
( R2  R1 )
Now putting the value of equation (A) in equation (i)
R2
V0  (V2  V1 ) for ideal subtractor circuit CMRR is 
R1
 R 
Super Position, Principle: Let V1 be at ground, then V2   1  2  V
 R1 
V
R2 V2 www.careerendeavour.com
 R  RV
V02   1  2  . 2 2
R1  R2  R1  R1  R2
( R1  R2 ) R2V2 R
 V02  . ; V02  2 V2
R1 ( R1  R2 ) R1
Now, when V2 be at ground, then, V01   R2 .V1 ;V0  V01  V02

R1
R2
Total V0  R (V2  V1 )
1
10. In the given op-amp circuit. Find the output voltage V0?
R2 33K
R1
2V –
11K Vn V0
4V +
R3 = 11K Vp
R4 = 33K
Soln. V0 = 3(4 – 2), V0 = 6 volt

R2 R4 R R
Hence,  , then V0  2 (V1  V2 ) or V0  4 (V1  V2 )
R1 R3 R1 R3
11. In the given op-amp circuit. Find the value of V0.
100K
10K
2V –
10K Vp V0
4V +
90K
Rf 100
Soln. Firstly, considering first inverting loop, V01   Vi   2  20V
R1 10
4  90 360
Now, considering non-inverting loop VP =   3.6V
90  10 100
 100 
 V02 =  1  10  3.6  39.6  V0  (39.6  (20V ))  19.6Volt
 
Adder:
3R
R A Vn
V 1
–
R V
V 2
0
R +
V3 Vp
Soln: By VGP  Vn = Vp = 0
V1 V2 V3 0  V0
KCL at point A     V0  3(V1  V2  V3 )
R R R 3R
So, the above op-amp is working as a inverting adder.
For the given op-amp circuit. Find the value of output voltage.
2R
R
–
R VB V0
V1 +
R I=0
V2
R
V3
V1  V V2  V V3  V 1
Soln. KCL at point B    0 or V  (V1  V2  V3 )
R R R 3
 2R  1
 V0   1   V  V0  (1  2). (V1  V2  V3 ) V0  (V1  V2  V3 )
 R  3
So, this is non-inverting adder.
12. In the given op-amp figure. Find the output voltage.
50K
40K A
2V –
25K Vn B V0
3V
+
10K Vp
4V
20K
5V
Soln. By VGP condition (Virtual Ground Position) (Vp = Vn)

Let Vp = Vp = V.
4  Vp 5  Vp 13
Now, KCL at point B,   0  Vp  Volt
10 20 3
2  Vn 3  Vn Vn  V0 2 3 Vn Vn Vn V0
Now, KCL at point A,   ,     
40 25 50 40 25 40 25 50 50
2 3 13 13 13 V0
Now putting the value of Vn,       V0  9.9V  Vn  Vp
40 25 120 75 150 50
100K
100K
–
Vn V0
13. + .
20K Vp
18V
40K
15V
In the above given op-amp circuit, find output voltage.
Soln. Vp = Vn = V (By VGP)
18  V 15  V 41
KCL at positive terminal,   0  V  Volt .
20 40 3
41 41
0  V0
KCL at positive terminal,  3  3 82
 V0  Volt
100 K 100 3
V01
14. For the given op-amp circuits. Find .
V02
10K –
2 V01 = 11Vi
1K +
–
1 R
+ VA
R –
+ V1
– 3 V02 = –11Vi
+
Soln. For the op-amp ... (1), this is non-inverting amplifier.

 10 
VA   1   Vi  11Vi  Op-amp (2) is working like buffer, V = 11V
 1 01 i
R
 Op-amp (3) is working like inverting amplifier, V02  11Vi  11Vi
R
V01 11Vi
   1
V02 11Vi
15. In the given op-amp circuit find output voltage.
3K 4K
A
I1 V1 2.4mA
12V + –
– V2 V0
I +
2K 2
B 1K
Soln. Because I1 = I2  V1 – V2 = 0 www.careerendeavour.com

2.4 mA
3K
12V +
– 12
I  2.4mA; VB  0  2.4  1  2.4V , VA  2.4V ;
2K 5
I
2.4  V0
  2.4  V0  12.0V
4
16. In the given op-amp circuit find V0 and I0.
8K
R A I
–
Vn V0
0.1mA Vp + I0
2K = RL
2V –+
IL
Soln: By VGP  Vn = Vp = 2V
Now, KCL at point A
2  V0 2.8
0.1 =  V0  2.8Volt , I L   1.4mA , I0 = 1.4 + 0.1 = 1.5mA
8 RL
17. In the given op-amp figure. Find the output voltage.
100K
200K
20K A
V1 = 2V – 50K
25K B –
V2 = 5V + V01
V0
+
V3 = 10V
2 5 0  V0
Soln. By VGP, VB = VA = 0, Now, KCL at point A,    V01  30Volt
20 25 100
10  ( 30) V0  10 40 V0  10
Now, KCL at second OP-amplifier  ; 
50 200 50 200
V0  1T0 Volt
18. In the given Op-amp circuit. Find V0?
300K
100K A
V2=2V –
V
10K Vp n V0
V1=1V +
10K
10  1
Soln. Vp   0.5V , By VGP condition, V = V = 0.5V
10  10 n p
2  0.5 0.5  V0
Now, KCL at point A,    V0  2.5Volt
150 300
19. In the given Op-amp circuit. Find output voltage.
510K
680K
18K 750K
– 22K
– 33K
+ VA
–
+ VB
~V 1 = 20V +
V0
20 106  0 VA  20 106
Soln. We will 1st calculate VA, 
18 510
1 1  VA 528
 20  106     ; VA   20  106 , V  5.86  10 4 Volt
18 510  510 18 A
680
Similarly on solving, VB   5.86  10 4 V , VB  0.081Volt , V = 0.409 Volt
22 0
20. Calculate the output voltage for the circuit with input V1 = 40mV, V2 = 20mV.
470K
47K
V1
V2 12K
B –
A V0
+
Soln. VA = VB = 0, Now applying KCL in inverting loop

V1  0 V2  0 0  V0 40 20 V0 (40  12  20  47)  470
  ,     V0 
47 12 470 47 12 470 47  12
 (480  940)  5 7100
V0    1183.93mV  V0  1.183Volt
6 6
21. www.careerendeavour.com
Calculate the output current I0 in the given circuit.
200K VB
Vi = 10mV –
VA
+ F0
V0
100K 10
Soln. Potential at A and B points are equal by VGP. i.e. VA = VB = 0

Now applying KCL in inverting loop
Vi  0 0  V0 10 100 103  103

  V0  V0  5V
200 100 K 200
5 5
Now, I 0    0.5  0.00005  0.5 A
10 100k 
22. In the given Op-amp circuit. Find I0 and V0?
3K
4k I
– I0
BI =0 V0
12V +
– 2mA
+ IL
6K
3 12 0  V0
Soln. Applying KCL at point B, 2  10  
4K 3K
V0
 2  103  3  103   V0  (15Volt )
3K
V0 0  15
IL   2.5m Amp , I   5mA , I 0  I  I L  7.5mA
6 3K
V0
23. In the given circuit find voltage gain V .
i
2K
1K
Vi –
Vn
V0
Vp + 3K
1K
Soln. In the non-inverting loop applying KCL let Vp = Vn = V
0  V V  V0 V
In the   V0  4V , V  0 .
1 3 4
V0
 V0 V
V
In the inverting loop applying KCL, i  V V  V V 4
www.careerendeavour.com  0  8
0 0
  Vi  
1 2 4 2 Vi
V0
24. In the given circuit. Find ?
V1  V2
V1 –
+
+
V1 6K
I
2K V0
V2
4K
–
–
V2 +
V0 12 I
Soln. V0  6 I  2 I  4 I  12 I ; V1  V2  2 I   6
V1  V2 2 I
25. In the given circuit find V0?
+
V0
3K –
VBV
2K
3K A
–
Vn
6V +
–
V + p
6  0 0  VB
Soln. Vn = Vp = 0{VGP}, Now, KCL at point A,   VB  4V
3 2
0  VB VB  V0 4 4  V0
Now, KCL at point B,   VB  4V ,   V0  10V
2 3 2 3
26. In the circuit calculate the output voltage V0?
D2
3K
6K
D1
2K
Vi –
V=0 V0
+
(i) If Vi = 3V, then V0? (ii) If Vi = –3V, then V0?

Soln. (i) When Vi = 3V, diode D1 will on, Now KCL in D1 loop
3  0 0  V0
  V0  9 Volt
2 6
(ii) When Vi = –3V, diode D2 will on, Now, KCL in D2 loop
Vi  0 0  V0

3 V www.careerendeavour.com
    0  V0  4.5Volt
2 3 2 3
V0
27. In the given circuit calculate .
IS
V0 –
V0 V0
+ 4K
B 2K A
10K
IS
Now, KCL at point A.

V  V0 V  V0 V
   0  5(V  V0 )  10(V  V0 )  2V  0
4 2 10
15V0
 5V  5V0  10V  10V0  2V  0  17V  15V0  V 
17
Now, KCL at point A
V0  V 15V0 2V0 V
 ( I S )  0  V0  V  2 I S  0  V0   2IS   2 I S  0  17
2 17 17 IS
28. In the given circuit find value of IL.
R
R
–
V
R Vp n V0
+
R
Vi +
– IL
RL
Soln. By VGP, Vn = Vp = V. Firstly, KCL in non-inverting terminal

Vi  V V  V0
 IL  ... (i)
R R
Similarly, KCL in inverting terminal
0  V V  V0 V
  V0  2V  V  0 ... (ii)
R R 2
Now, putting value of (ii) in equation (i)
V0 V0
Vi   V0 V0 V0 Vi
2 I  2 , Vi   I L R   V0  I L 
R
L
R 2 2 R
DC Characteristic of Op-amp:
(i) Input bias current (For DC analysis)
(ii) Input offset current
(iii) Input offset voltage
R f
R1
Vi –
IB V0
+
| IB |  | IB |  
(i) Input bias current = . Let | I B  || I B  | , 0  V0 | I B | R f ; V0 | I B | R f
2
To compensate effect of input bias current Rcomp is used.  Rcomp  R1 || R f
(ii) Input offset current; I OS  | I B  |  | I B  | , V0  R f I OS  output if Vi  0 , due to input offset current.
 R 
(iii) Input offset voltage; VOS  V1  V2 , output to input offset; V0  1  f  VOS .
 R1 
10K
1K
–
29. V0
+
+ V
– i
Calculate IL, Given VOS = 10mV, |IB–| = 300nA, IOS = 100pA.

Find (a) Calculate maximum output voltage due to VOS and IB–. (b) Calculate R comperate.
(c) Calculate output voltage if Rcomp is connected.
Soln. (i) If we are considering input bias current then IOS = 0, as we have already assumed | I B  |  | I B  | .
(ii) If Rcomp is connected, then input bias current will not considered, only IOS will be considered.
If Rcomp is connects then for zero input = zero output.
 Rf    10 
(a) V0   1   .VOS  R f .I B =  1  1  .10  10.300nA  110  3mV  113mV
 R1   
10
(b) Rcomp  R1 || Rf  K
11
 Rf   10 
(c) V0   1  R  .VOS  R f I OS =  1   10mV  10 K  100 pA
 1   1
= 110mV  0.001mV  110.001mV
30. If input offset voltage = 4mV, input offset current = 150nA, input bias current = 300nA.
500K
5K –
Vi
V0
+
5K
 R 
500 
Soln. V0  1  f  VOS  R f .I OS =  1   .4mV  500 K  150nA = 101 × 4 + 75
 R1   5 
= 404 + 75 = 479mvolt.
Calculation of CMRR
Ad
CMRR 
AC Ad = differential mode gain, AC = Common mode gain
V1  V2 A  V0 AC 
V0
V0  Ad Vd  ACVC Vd  V1  V2 , VC  , d V
2 d VC  0,
VC Vd  0
31. In the given circuit. Find the value of CMRR?
R
V2 –
V1 R V0
+
R
R
Soln. V0  (V1  V2 ) , V0  (V1  V2 )  Vd  V1  V2 ,  Ad  1
R
1
For AC , V1  V2 .  AC  0 CMRR  
0
32. In the op-amp circuit, CMRR = 40dB and Ad = 50dB. Find AC.
Soln. Here, CMRR = Common Mode Rejection Ratio
Ad = Difference Mode gain, AC = Common Mode gain
CMRR and Ad are given in dB. First off all we will change it in normal value.
40dB = 20 log10 CMRR
40
 CMRR = (10)  102  100  50dB = 20log10 Ad
20
Ad Ad 316.27
 Ad = 102.5 = 316.22  CMRR = A  AC = 
C CMRR 100
AC = 3.16
–
Slew Rate: Vi = sin t +
V0
A=
Ri =
R0 = 0
33. www.careerendeavour.com
What is the maximum value of input voltage given to an voltage follower so, that there is no distortion (Slew
rate is given).
S .R
Soln: V0  Vm sin t , Slew Rate = Vm. cos t , S.R. = Vm. Vm 
2f
34. For the circuit shown below the value of V0 is
10K
10K
–
48K VpVn V0
6V +
5K
6K
4 2 2 4
(a) V (b) – V (c) V (d) – V
3 3 3 3
66 2  Rf   10  2 2 4
Soln. Vp =  V , V0  1   V p   1   . = (2)  
48  6 3  R1   10  3 3 3
35. For the circuit shown below the input resistance is
Vn – i1
Vp
+ is 4K
is 2K
10K
iz
(a) 38K (b) 17K (c) 25K (d) 47K

Soln. Since op-amp is ideal, Vn  V p , 2k is  4k i1  is  2i1 , Vs  2k is  10k i2 , i2  is  i1
is  i  V
Vs  2k is  10k (is  i1 )  i1   Vs  2k is  10k  is  s   s  17 K  Rin
2  2 is
36. The voltage transfer characteristic of an operation amplifier is shown in figure. What are the values of gain
and offset voltage for this op-amp.
V0
10
–6 –4 –2
(mV)
2 4 6 Vin
–10
(a) 10, 1mV (b) 7500, –1mV (c) 20, 2mV (d) 7500, –2mV
Soln. V0  AV (Vin  VOS ), VOS  Offset Voltage, A V  Voltage Gain
dV0 10  (5)
AV    7500 , When V = 0, V = –V
dVin (2  0)mV 0 in OS
Offset voltage is VOS  Vin / V0  0  1mV

37.
An inverting operational amplifier shown in figure has an open gain of 1000 and closed loop gain of 4, gain
error is
R2
R1
–
A0 V0
Vin +
– +
(a) 0.4% (b) 0.5% (c) 2.5% (d) 2%
1  R2 
Soln. Gain error is given as g  A  1  R  , A0 = 1000 (Open loop gain)
0  1 
R2
 4 (Closed loop gain), g  1 (1  4)  0.5%
R1 1000
38. In the following non-inverting amplifier. The op-amp has an open loop gain of 86dB, gain error is
150K
12K
–
V0
+
Vin +
–
(a) 0.0125% (b) 0.13% (c) 0.930% (d) 0.0675%
1  R2 
Soln. Gain error for non-inverting amplifier is given by g  1  
A0  R1 
where A0  open loop gain 20log10 A0  86(given) A0  20, 000 , R2 = 150 K , R1 = 12 K
1  150  4
So, gain error is g  1    6.75  10 or g  0.0675%
20, 000  2 
39. Op-Amp of a given figure has open loop gain of 45. What is closed loop gain of an op-amp.
20K=Rf
R1=2K
–
V0
+
Vin +
–
 Rf   20 
1   1  
 R1   2  11 4 11
Soln. For non-inverting ACL      8.95
 Rf   20  1  11 56
1   1  2  45
1  R1  1  
AOL 45
Differentiator:
if
i Rf
c
N –
Vi dVi
V
C1 Vp n V0 = –R1C1 dt
+
R comp = Rf
d dV
By VGP, Vp = Vn = 0, Now, KCL at point N, iC  C1 (Vi  VN )  C1 i , this is far capacitor current.
dt dt
V0 dVi V0 dVi
For feedback resistor Rf. i f  R  C1 dt  R  0  V0   RfC1
f f dt
We may now write the magnitude of gain A of the differentiator as,
V0 f 1
| A | |  J RfC1 | RfC1 or | A | where fa 
Vi fa 2RfC1
40. In the given differentiator, if Vi = sin(2  × 102t). Draw wave form of V0.
Rf=1.5K
C1
Vi –
0.1F V0
+
dVi
Soln. V0  CR f , V0  0.1 106  1.5  10 3.cos (2  10 2 t ).2 10 2
dt
V0  3 102 cos(2 10 2 t )  0.09 cos(2 10 2 t )
Vi
+1
5m sec
5m sec
–1
+0.9
–0.9
Practical Differentiator:
Zf
Cf
Z1 Rf
Vi –
R1 C1 V0
+
R comp = R1 | | Rf = R1(Rf >> R1)
V0( s ) Zf SR f C1
This is inverting op-amp:  
Vi ( s ) Zi (1  SRf ( f ) (1  SC1 R1 )
V0( S ) SR f C1 SR f C1
For R f C f  R1C1 , we get  2
 2
Vi ( S ) (1  SR1C1 )  f 
1  j 
 fb 
1
Where, fb 
2R1C1

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126 Operational Amplifier

(+) Non-inverting terminal, (–) Inverting terminal

The value of CMRR can also be expressed in log term as

(–) sign represent 180º phase.

By virtual ground law: Vn = Vp = Vi

where the scale factor is –RC.

Offset Currents and Voltages {d.c. characteristic of op-amp}:

By virtual ground condition Vn = Vp = 0

By virtual ground condition Vp = Vn = Vi

is the same cut off frequency as in figure.

High Pass Section Low Pass Section

Calculation of output voltage:

V2  V2  IR ... (3)

R1 = 15.9K  , R2 = 159K  , C = 1nF

VP Ideal Op-amp AOL =

V0 4.5Vi 4.5Vi 4.5Vi V0 20

Soln. By virtual ground condition V p  Vn  0

Soln. This is non-inverting amplifier. Vp = Vn = 5V by VGP.

(a) R f  0, R1  0 (b) R f  0, R1   (c) R f  0, any value of R1

 Rin  Very high 

Now, when V2 be at ground, then, V01   R2 .V1 ;V0  V01  V02

Soln. V0 = 3(4 – 2), V0 = 6 volt

Soln. By VGP condition (Virtual Ground Position) (Vp = Vn)

Soln. For the op-amp ... (1), this is non-inverting amplifier.

Soln. Because I1 = I2  V1 – V2 = 0 www.careerendeavour.com

Soln. VA = VB = 0, Now applying KCL in inverting loop

Soln. Potential at A and B points are equal by VGP. i.e. VA = VB = 0

Vi  0 0  V0 10 100 103  103

Soln. In the non-inverting loop applying KCL let Vp = Vn = V

(i) If Vi = 3V, then V0? (ii) If Vi = –3V, then V0?

Now, KCL at point A.

Soln. By VGP, Vn = Vp = V. Firstly, KCL in non-inverting terminal

To compensate effect of input bias current Rcomp is used.  Rcomp  R1 || R f

(ii) Input offset current; I OS  | I B  |  | I B  | , V0  R f I OS  output if Vi  0 , due to input offset current.

Calculate IL, Given VOS = 10mV, |IB–| = 300nA, IOS = 100pA.

(a) 38K (b) 17K (c) 25K (d) 47K

Offset voltage is VOS  Vin / V0  0  1mV

(a) 0.4% (b) 0.5% (c) 2.5% (d) 2%

(a) 0.0125% (b) 0.13% (c) 0.930% (d) 0.0675%

where A0  open loop gain 20log10 A0  86(given) A0  20, 000 , R2 = 150 K , R1 = 12 K

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