19-1101; Rev 0; 6/96

KIT
ATION
EVALU BLE
V A IL A
A
8-Bit, 150Msps Flash ADC
_______________General Description ____________________________Features
♦

MAX1114
The MAX1114 is a monolithic, flash analog-to-digital Metastable Errors Reduced to 1LSB
converter (ADC) that can digitize a 2V analog input ♦ 10pF Input Capacitance
signal into 8-bit digital words at a typical 150Msps
update rate. ♦ 210MHz Input Bandwidth
For most applications, no external sample-and-hold is ♦ 150Msps Conversion Rate
required for accurate conversion due to the device's ♦ 2.2W Typical Power Dissipation
narrow aperture time, wide bandwidth, and low input ♦ Single -5.2V Supply
capacitance. A single standard -5.2V power supply is
required to operate the MAX1114, with nominal 2.2W
power dissipation. A special decoding scheme reduces ______________Ordering Information
metastable errors to 1LSB. PART TEMP. RANGE PIN-PACKAGE INL (LSBs)
The part is packaged in a 42-pin ceramic sidebraze MAX1114AIDO -20°C to +85°C 42 Ceramic SB ±0.75
that is pin-compatible with the CX20116 and MAX1114BIDO -20°C to +85°C 42 Ceramic SB ±1
CXA1396D. The surface-mount 44-pin CERQUAD
MAX1114AIBH -20°C to +85°C 44 CERQUAD ±0.75
allows access to additional reference ladder taps, an
overrange bit, and a data-ready output. For higher con- MAX1114BIBH -20°C to +85°C 44 CERQUAD ±1
version rates, the pin-compatible 300Msps MAX1125 is Functional Diagram appears at end of data sheet.
available.
________________________Applications ____Pin Configurations (continued)
Digital Oscilloscopes
Transient Capture
TOP VIEW
Radar, EW, ECM
Direct RF Down-Conversion VEE 1 42 N.C.

Medical Electronics N.C. 2 41 VRTF

Ultrasound, CAT Instrumentation LINV 3 40 N.C.
_________________Pin Configurations VEE 4 39 VEE
AGND 5 38 VEE
MAX1114
D8 (MSB)

DGND 37 N.C.
D0 (LSB)

6
DREADY
DGND

TOP VIEW DO (LSB) 7 36 N.C.

D7
D6
D5
D4
D3
D2
D1

D1 8 35 AGND
40

35
37
36
44
43
42
41

39
38

34

D2 9 34 VIN
DGND 1 33 AGND D3 10 33 AGND
AGND 2 32 VEE D4 11 32 VR2
VEE 3 31 LINV
D5 12 31 AGND
MINV 4 30 N.C.
CLK 5 29 DRINV
D6 13 30 VIN

CLK 6
MAX1114 28 N.C. D7 (MSB) 14 29 AGND
VEE 7 27 VEE DGND 15 28 N.C.
AGND 8 26 AGND
AGND 16 27 N.C.
AGND 9 25 AGND
VEE 17 26 VEE
VRBS 10 24 VRTS
VRBF 11 23 VRTF MINV 18 25 VEE

N.C. 19 24 N.C.

CLK 20 23 VRBF
VEE 22
AGND 20
VR3 21
VEE 12
VR1 13
AGND 14
VIN 15
AGND 16
VR2 17
AGND 18
VIN 19

CLK 21 22 N.C.

CERQUAD Ceramic SB

________________________________________________________________ Maxim Integrated Products 1

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
 8-Bit, 150Msps Flash ADC

ABSOLUTE MAXIMUM RATINGS

MAX1114

Negative Supply Voltage (VEE TO GND) ..............-7.0V to +0.5V Digital Output Current ...........................................0mA to -30mA
Ground Voltage Differential ...................................-0.5V to +0.5V Operating Temperature Range ...........................-25°C to +85°C
Analog Input Voltage ...............................................VEE to +0.5V Junction Temperature ......................................................+150°C
Reference Input Voltage ..........................................VEE to +0.5V Storage Temperature Range .............................-65°C to +150°C
Digital Input Voltage.................................................VEE to +0.5V Lead Temperature (soldering, 10sec). ............................+300°C
Reference Current VRTF to VRBF .........................................25mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(VEE = -5.2V, RSOURCE = 50Ω, VRBF = -2.00V, VR2 = -1.00V, VRTF = 0.00V, fCLK = 150MHz, 50% Duty Cycle, TA = TMIN to TMAX,
unless otherwise noted.)
TEST MAX1114A MAX1114B
PARAMETER CONDITIONS UNITS
LEVEL MIN TYP MAX MIN TYP MAX
DC ACCURACY
Integral Linearity fCLK = 100 kHz VI -0.75 ±0.60 +0.75 -0.95 ±0.80 +0.95 LSB
Differential Linearity fCLK = 100 kHz VI -0.75 +0.75 -0.95 +0.95 LSB
No missing codes Guaranteed Guaranteed
ANALOG INPUT
Offset Error VRT IV -30 +30 -30 +30 mV
Offset Error VRB IV -30 +30 -30 +30 mV
Input Voltage Range VI -2.0 0.0 -2.0 0.0 V
Input Capacitance Over full input range V 10 10 pF
Input Resistance V 15 15 kΩ
Input Current VI 250 500 250 500 µA
Input Slew Rate V 1,000 1,000 V/µs
Large-Signal Bandwidth VIN = full scale V 210 210 MHz
Small-Signal Bandwidth IN = 500mVp-p V 335 335 MHz
REFERENCE INPUT
Ladder Resistance VI 100 200 300 100 200 300 Ω
Reference Bandwidth V 10 10 MHz
TIMING CHARACTERISTICS
Maximum Sample Rate VI 125 150 125 150 Msps
Clock to Data Delay V 2.4 2.4 ns
Output Delay Tempco V 2 2 ps/°C
CLK-to-Data Ready Delay (tD) V 2.0 2.0 ns
Aperture Jitter V 5 5 ps
Acquisition Time V 1.5 1.5 ns

2 _______________________________________________________________________________________
 8-Bit, 150Msps Flash ADC

ELECTRICAL CHARACTERISTICS (continued)

MAX1114
VEE = -5.2V, RSOURCE = 50Ω, VRBF = -2.00V, VR2 = -1.00V, VRTF = 0.00V, fCLK = 150MHz, 50% Duty Cycle, TA = TMIN to TMAX,
unless otherwise noted.)

TEST MAX1114A MAX1114B

PARAMETER CONDITIONS UNITS
LEVEL MIN TYP MAX MIN TYP MAX
DYNAMIC PERFORMANCE
fIN = 3.58MHz VI 46 48 45 47
Signal-to-Noise Ratio dB
fIN = 50MHz VI 42 46 40 44
fIN = 3.58MHz VI -48 -52 -46 -50
Total Harmonic Distortion dB
fIN = 50MHz VI -40 -44 -39 -43
Signal-to-Noise and fIN = 3.58MHz VI 45 48 43 46
dB
Distortion (SINAD) fIN = 50MHz VI 39 42 37 40 dB
DIGITAL INPUTS
Digital Input High Voltage
VI -1.1 -0.7 -1.1 -0.7 V
(MINV, LINV)
Digital Input Low Voltage
VI -2.0 -1.5 -2.0 -1.5 V
(MINV, LINV)
Clock Synchronous
V 40 40 µA
Input Currents
Clock Low Width, TPWL VI 4 3 4 3 ns
Clock High Width, TPWH VI 4 3 4 3 ns
DIGITAL OUTPUTS
Digital Output High Voltage 50Ω to -2V VI -1.1 -1.1 V
Digital Output Low Voltage 50Ω to -2V VI -1.5 -1.5 V
POWER SUPPLY REQUIREMENTS V 2.4 2.4 ns
Supply Current TA = +25°C I 425 550 425 550 mA
Power Dissipation TA = +25°C I 2.2 2.9 2.2 2.9 W

TEST LEVEL CODES TEST LEVEL TEST PROCEDURE

All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications are
guaranteed. The Test Level column indicates the
specific device testing actually performed during
production and Quality Assurance inspection.
Any blank section in the data column indicates
that the specification is not tested at the specified
condition.
Unless otherwise noted, all tests are pulsed;
therefore, Tj = TC = TA.
I 100% production tested at the specified temperature.
II 100% production tested at TA = +25°C, and sample tested at the
specified temperatures.
III QA sample tested only at the specified temperatures.
IV Parameter is guaranteed (but not tested) by design and
characterization data.
V Parameter is a typical value for information purposes only.
VI 100% production tested at TA = +25°C. Parameter is guaranteed
over specified temperature range.

_______________________________________________________________________________________ 3
 8-Bit, 150Msps Flash ADC

__________________________________________Typical Operating Characteristics

MAX1114

(Circuit of Figure 1, TA = +25°C, unless otherwise noted.)

SIGNAL-TO-NOISE RATIO TOTAL HARMONIC DISTORTION

vs. INPUT FREQUENCY vs. INPUT FREQUENCY
52

MAX1114 -02
52
MAX1114 -01
fs = 125Msps fs = 125Msps
50 50

48 48

46 46

THD (dB)
SNR (dB)

44 44
42 42

40 40

38 38
36 36

34 34
1 10 100 1 10 100
INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz)

SIGNAL-TO-NOISE AND DISTORTION SNR, THD, SINAD

vs. INPUT FREQUENCY vs. TEMPERATURE
52 50

MAX1114 -04
MAX1114 -03

fs = 125Msps
50 SNR
48
45
SNR, THD, SINAD (dB)

THD
46
SINAD (dB)

44 SINAD
40
42
40

38 35

36 fs = 125Msps
fIN = 50MHz
34 30
1 10 100 -40 -20 0 20 40 60 80
INPUT FREQUENCY (MHz) TEMPERATURE (°C)

4 _______________________________________________________________________________________
 8-Bit, 150Msps Flash ADC

______________________________________________________________Pin Description

MAX1114
PIN
NAME FUNCTION
Ceramic SB CERQUAD

1, 4, 17, 25, 26, 38, 39 3, 7, 12, 22, 27, 32 VEE Negative Analog Supply (nominally -5.2V)

2, 19, 22, 24, 27, 28, 36,

28, 30 N.C. No Connect. Not internally connected.
37, 40, 42

3 31 LINV D0–D6 Output Conversion Control

2, 8, 9, 14, 16, 18, 20,

5, 16, 29, 31, 33, 35 AGND Analog Ground
25, 26, 33

6, 15 1, 34 DGND Digital Ground

7 36 D0 Digital Data Output (LSB)
8–13 37–42 D1–D6 Digital Data Outputs
14 43 D7 Digital Data Output (MSB)
18 4 MINV D7 Output Conversion Control
— 44 D8 Overrange Output
20 5 CLK Inverse ECL Clock Input Pin
21 6 CLK ECL Clock Input Pin
— 10 VRBS Reference Voltage Bottom, Sense
23 11 VRBF Reference Voltage Bottom, Force

Analog Input. Can be connected to the input

30, 34 15, 19 VIN
signal or used as a sense.

— 13 VR1 Reference Voltage Tap 1 (typically -1.5V)

32 17 VR2 Reference Voltage Tap 2 (typically -1V)
— 21 VR3 Reference Voltage Tap 3 (typically -0.5V)
41 23 VRTF Reference Voltage Top, Force
— 24 VRTS Reference Voltage Top, Sense
— 29 DRINV Data-Ready Inverse
— 35 DREADY Data-Ready Output

_______________Detailed Description reduces the effect of the dynamic state of the input sig-
nal on the latching characteristics of the input compara-
The MAX1114 is a 150Msps, monolithic, 8-bit parallel
tors. The preamplifiers act as buffers and stabilize the
flash analog-to-digital converter (ADC) with an analog
input capacitance so it remains constant for varying
bandwidth of over 200MHz. A major advance over pre-
input voltages and frequencies, making the part easier
vious flash converters is the inclusion of 256 input pre-
to drive than previous flash converters. The MAX1114
amplifiers between the reference ladder and input
incorporates a special decoding scheme that reduces
comparators. (See Functional Diagram.) This feature
metastable errors (sparkle codes or flyers) to a maxi-
not only reduces clock-transient kickback to the input
mum of 1LSB.
and reference ladder due to a low AC beta, but also

_______________________________________________________________________________________ 5
 8-Bit, 150Msps Flash ADC

The MAX1114 has true differential analog and digital Clock Inputs CLK, CLK
MAX1114

data paths from the preamplifiers to the output buffers The clock inputs are designed to be driven differentially
(Current-Mode Logic) for reducing potential missing with ECL levels. The clock may be driven single-ended
codes while rejecting common-mode noise. since CLK is internally biased to -1.3V (Figure 5). CLK
Careful layout of the analog circuitry reduces signature may be left open but a 0.01µF bypass capacitor from
errors. Every comparator has a clock buffer to reduce CLK to AGND is recommended. NOTE: System perfor-
differential delays and to improve signal-to-noise ratio. mance may be degraded due to increased clock noise
The output drive capability of the device can provide or jitter.
full ECL swings into 50Ω loads.
Output Logic Control MINV, LINV
___________Typical Interface Circuit These are ECL-compatible digital controls for changing
the output code from straight binary to two's comple-
Figure 1 shows the typical interface circuit. The
ment, etc. (Table 1 and Figure 4). Both MINV and LINV
MAX1114 is relatively easy to apply, depending on the
are in the logic low (0) state when they are left open.
accuracy needed. Wire-wrap may be employed with
The high state can be obtained by tying to AGND
careful point-to-point ground connections if desired, but
through a diode or 3.9kΩ resistor.
a double-sided PC board with a ground plane on the
component side, separated into digital and analog sec-
tions gives the best performance. The converter is Table 1. Output Coding
bonded-out to place the digital pins on the left side of
the package and the analog pins on the right side. MINV 0 0 1 1
Additionally, an RF bead connection through a single LINV 0 1 0 1
point from the analog to digital ground planes reduces 0V 111...11 100...00 011...11 000...00
ground noise pickup. . 111...10 100...01 011...10 000...01
Figure 2 (CERQUAD package only) shows the most . . . . .
elaborate method of achieving the least error by cor- . . . . .
recting for integral nonlinearity, input-induced distor- . . . . .
tion, and power-supply/ground noise. It uses external VIN . 100...00 111...11 000...00 011...11
reference ladder tap connections, an input buffer, and . 011...11 000...00 111...11 100...00
supply decoupling. The function of each pin and exter-
nal connections to other components is as follows: . . . . .
. . . . .
VEE, AGND, DGND . . . . .
V EE is the supply pin with AGND as ground for the . 000...01 011...10 100...01 111...10
device. The power-supply pins should be bypassed as -2V 000...00 011...11 100...00 111...11
close to the device as possible with at least a 0.01µF
ceramic capacitor. A 1µF tantalum should also be used 1: VIH, VOH 0: VIL, VOL
for low-frequency suppression. DGND is the ground for
the ECL outputs and should be referenced to the output Digital Outputs D0 to D7
pulldown voltage and bypassed as shown in Figure 1. The digital outputs can drive ECL levels into 50Ω when
Analog Input VIN pulled down to -2V. When pulled down to -5.2V, the out-
There are two analog input pins that are tied to the puts can drive 150Ω to 1kΩ loads.
same point internally. Either one may be used as an Reference Inputs VRBF, VR2, VRTF
analog input sense and the other for input force. This is There are two reference inputs and one external refer-
convenient for testing the source signal to see if there is ence voltage tap. These are -2V (VRBF), mid-tap (VR2)
sufficient drive capability. The pins can also be tied and AGND (VRTF). The reference pins can be driven as
together and driven by the same source. The MAX1114 shown in Figure 1. VR2 should be bypassed to AGND
is superior to similar devices due to a preamplifier for further noise suppression.
stage before the comparators (Figure 4). This makes
the device easier to drive because it has constant
capacitance and induces less slew-rate distortion. An
optional input buffer may be used.

6 _______________________________________________________________________________________
 8-Bit, 150Msps Flash ADC
Reference Inputs VRBF, VRBS, VR1, VR2,
VR3, VRTF, VRTS (CERQUAD package only)
These are five external reference voltage taps from -2V
(VRBF) to AGND (VRTF) which can be used to control
integral linearity over temperature. The taps can be driv-
en by op amps (Figure 2). These voltage level inputs
can be bypassed to AGND for further noise suppres-
sion, if so desired. VRB and VRT have force and sense
pins for monitoring the top and bottom voltage refer-
ences.
Not Connected (N.C.)
All N.C. pins should be tied to DGND on the left side of
the package and to AGND on the right side of the
package.
Data Ready and Data-Ready Inverse
DREADY, DRINV (CERQUAD package only)
The data-ready pin is a flag that goes high or low at the
output when data is valid or ready to be received. It is
essentially a delay line that accounts for the time nec-
essary for information to be clocked through the
MAX1114’s decoders and latches. This function is use-
ful for interfacing with high-speed memory. Using the
data-ready output to latch the output data ensures mini-
mum setup and hold times. DRINV is a data-ready
inverse control pin (Figure 3).
Overrange Input D8
(CERQUAD package only)
When the MAX1114 is in an overrange condition, D8
goes high and all data outputs go high as well. This
makes it possible to include the MAX1114 in higher res-
olution systems.
_______________________________________________________________________________________
Operation
MAX1114
The MAX1114 has 256 preamp/comparator pairs that
are each supplied with the voltage from VRTF to VRBF
divided equally by the resistive ladder as shown in the
Functional Diagram. This voltage is applied to the posi-
tive input of each preamplifier/comparator pair. An ana-
log input voltage applied at VIN is connected to the
negative inputs of each preamplifier/comparator pair.
The comparator states are then clocked through each
comparator's individual clock buffer. When CLK is low,
the master, or input stage, of the comparators com-
pares the analog input voltage to the respective refer-
ence voltage. When CLK changes from low to high, the
comparators are latched to the state prior to the clock
transition and output logic codes in sequence from the
top comparators, closest to VRTF (0V), down to the
point where the magnitude of the input signal changes
sign (thermometer code). The output of each compara-
tor is then registered into four 64-to-6 bit decoders
when CLK is changed from high to low. At the
decoders' output is a set of four 7-bit latches that are
enabled (track) when CLK changes from high to low.
From here, the outputs of the latches are coded into 6
LSBs from 4 columns and 4 columns are coded into 2
MSBs. Next are the MINV and LINV controls for output
inversions that consist of a set of eight XOR gates.
Finally, 8 ECL output latches and buffers are used to
drive the external loads. The conversion takes one
clock cycle from the input to the data outputs.
_________________Evaluation Boards
The MAX1114/MAX1125 evaluation kit (EV kit) demon-
strates the full performance of the MAX1114. This
board includes a voltage reference circuit, clock driver
circuit, output data latches and an on-board recon-
struction of the digital data. A separate EV kit manual
describing the operation of this board is also available.
Contact the factory for price and delivery.
7
 8-Bit, 150Msps Flash ADC
MAX1114

L VEE
ANALOG INPUT 0.01µF
OPTIONAL -5.2V
CAN BE EITHER
FORCE OR SENSE
BUFFER VIN LINV MINV
VRTF

PREAMP COMPARATOR

256
CLOCK
BUFFER
= AGND
255
= DGND

152

D7 (MSB)
151

D6

ECL
128 256-BIT
TO 8-BIT LATCHES
VR2 AND
ENCODER D5
BUFFERS
0.01µF

127
D4

64 D3

D2
63

D1

D0 (LSB)
1
VREF 10Ω TO
25Ω VRBF
-2V
OP07 0.01µF 50Ω x 8
MAX1114
VIN
100116 CLK
2
CONVERT
CLK
50Ω 50Ω
ANALOG INPUT
CAN BE EITHER
FORCE OR SENSE VEE -2V
-2V 0.01µF 0.01µF -5.2V 0.01µF (DIGITAL)
(ANALOG)

Figure 1. Typical Interface Circuit 1

8 _______________________________________________________________________________________
 8-Bit, 150Msps Flash ADC

MAX1114
OPTIONAL

BUFFER
*
DGND AGND VEE
L 0.01µF
10Ω TO -5.2V
25Ω VRTF
U1
VIN LINV MINV
VRTS

0.01µF
PREAMP COMPARATOR

256
CLOCK
BUFFER
*ANALOG INPUT (FORCE)
255
**ANALOG INPUT (SENSE)
1k,
0.1%
OVERRANGE
152 D8
10Ω TO
25Ω VR3
U2
D7
(MSB)
151
0.01µF
1k,
0.1% D6

256-BIT ECL
10Ω TO 128 LATCHES
NOTE: U1–U5 25Ω VR2 TO 8-BIT
ENCODER AND
ARE OP07 OR U3 BUFFERS D5
EQUIVALENT,
LOW-NOISE,
LOW-OFFSET
AMPLIFIERS. 127
0.01µF D4
1k,
0.1%

10Ω TO 64 D3
25Ω VR1
U4

D2
63
0.01µF

D1

1k, 2
0.1%
D0
(LSB)
VREF 1
-2V 10Ω TO
25Ω VRBF
U5
DRINV
VRBS DREADY
MAX1114
0.01µF 50Ω
100116 CLK x 10
2
CONVERT
CLK
50Ω 50Ω VIN VEE
-2V 0.01µF
** 0.01µF 0.01µF
-2V 0.01µF VEE -2V
(ANALOG) -5.2V (DIGITAL)

Figure 2. Typical Interface Circuit 2 (CERQUAD package only)

_______________________________________________________________________________________ 9
 8-Bit, 150Msps Flash ADC
MAX1114

N+2
N N+1
ANALOG INPUT
VIN
Tpw1 Tpw0
CLK
CLOCK
CLK

MASTER

COMPARATOR OUTPUT

INTERNAL TIMING
SLAVE

6-BIT LATCH OUTPUT

8-BIT LATCH OUTPUT

DATA OUTPUT D0–D7 N-1 N N+1

OVERRANGE D8 tD

DREADY
TIMING FOR CERQUAD PACKAGE ONLY

Figure 3. Timing Diagram

AGND

AGND
AGND DGND
VIN VR
10k

MINV
LINV
-1.3V
DATA OUT

16k

VEE
VEE

INPUT CIRCUIT OUTPUT CIRCUIT MINV, LINV INPUT CIRCUIT

Figure 4. Subcircuit Schematics

10 ______________________________________________________________________________________
 8-Bit, 150Msps Flash ADC

MAX1114
AGND

CLK -1.3V

13k

CLK

13k
VEE

Figure 5. Clock Input

VEE

1N4736
-2V

R4 R4

VREF R1
R1 R1 R1 R1 R1 R1 R1

R3

VRBF VEE
D0

D1

D2
R2
VIN MAX1114
VIN D3

D4

D5

D6
R2
CLK
CLK D7
CLK
CLK
LINV
R2
AGND
DGND

VRTF

R1 = 50Ω 1/4 Watt CC 5% MINV

R2 = 1kΩ 1/4 Watt CC 5%
R3 = 6.5Ω 1/4 Watt CC 5% R2
R4 = 6.5Ω 1/2 Watt CC 5%
VREF = -2.00V
VEE = -6.6V
-2V

Figure 6. Burn-In Circuit (Ceramic SB package only)

______________________________________________________________________________________ 11
 8-Bit, 150Msps Flash ADC

_________________________________________________________Functional Diagram
MAX1114

ANALOG INPUT
(FORCE OR SENSE) AGND DGND VEE LINV MINV

VRTS
VRTF
MAX1114

PREAMP COMPARATOR

256
DRINV
CLOCK
BUFFER
255
D7 (MSB)
DREADY

VR3
152 OVERRANGE

D7 (MSB)
151

D6
ECL
128 256-BIT
TO 8-BIT LATCHES
ENCODER AND
VR2 BUFFERS
D5

127

D4
D6

64
D5
D3

D4
VR1
63 D2
D3

D2
D1
2
D1

D0 (LSB) D0 (LSB)
1

VRBE
VRBS
CLK 2 THESE FUNCTIONS ARE
CONVERT AVAILABLE IN THE
CLK CERQUAD PACKAGE ONLY.

ANALOG INPUT VEE AGND

(FORCE OR SENSE)

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

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