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n-MOS & p-MOS require different channel background doping and source/drain region doping.
In CMOS, the gate is no longer “metal”, it is heavily doped poly-crystalline Si with low resistance.
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CMOS is required by logic circuits
+V
+V
IN1 NOR:
Inverter:
Output = IN1+IN2
Output = Input S
PMO S IN2
D O UTPUT
O UTPUT
INPUT D
NMO S
S Output = GND = 0 if
any Input or both
GND are +V = 1
GND
Inverted to n-type
Body (bulk Si) is commonly tied to ground (0V).
When the gate is at a low voltage: When the gate is at a high voltage:
• P-type body is at low voltage, source-channel- • Positive charge on gate of MOS
drain is N+PN+. capacitor.
• If drain is positive bias (i.e. electrons flow from • Negative charge attracted to the top
the source and ‘drained’ to the drain), the surface just below the gate oxide.
right side PN+ diode is in reverse bias. • Inverts a channel under gate to n-
• Left side N+P is in zero-bias, as source is usually type, source-channel-drain is N+NN+.
connected to the grounded bulk Si. • Now current can flow through n-
• No current flows through the channel, type silicon from source through
transistor is OFF channel to drain, transistor is ON.4
P-MOSFET (field effect transistor) operation
Since voltage has only a relative meaning. This is equivalent to the situation of:
grounded body/bulk Si, grounded source, negative (< 0V) drain voltage (so holes flow
from source and ‘drained’ to drain).
Then transistor is ON when gate is negatively biased, and OFF when gate is grounded.
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Transistors as switches
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CMOS inverter
Inverter:
Output = Input
g=Input=0, NMOS is
off, PMOS is on.
Output=+V=1.
When Input =1,
Output=GND=0
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Cross-section of the CMOS IC
p
This is what we are going to fabricate in this chapter. 8
Fabrication “toolkit”
• Insulating Layers LPCVD: low pressure chemical vapor
deposition.
o Oxidation, nitridation
o Deposition (LPCVD, PECVD, APCVD) PECVD: plasma enhanced CVD.
• Selective doping of silicon APCVD: atmospheric pressure CVD
o Diffusion (in-situ doping) RIE: reactive ion etching
o Ion implantation DRIE: deep RIE.
o Epitaxy (in-situ doping) CMP: chemical mechanical polishing
• Material deposition (silicon, metals, insulators)
o LPCVD
o PECVD
o Sputter deposition
• Patterning of Layers
o Lithography (UV, deep UV, e-beam & x-ray)
• Etching of (deposited) material
o Dry etches—plasma, RIE, sputter etch, DRIE
o Wet etches—etch in liquids, CMP etc
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Choosing the substrate and active region formation
http://en.wikipedia.org/wiki/LOCOS 12
Alternative process to LOCOS isolation:
shallow trench isolation with filled implants (here P+)
LOCOS:
Bird’s Beak
problem,
unsuitable for
small device.
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P-well formation
Wet etch away Si3N4, spin photoresist, lithography, B+ implantation.
Mask #2 blocks a B+ implant to form the wells for the NMOS devices.
Typically dose 1013cm-2 @ 150-200 KeV (very high energy).
(Implant dose is in cm-2, doping concentration is in cm-3)
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N-well formation
Strip photoresist, spin resist and photolithography, ion implantation
Mask #3 blocks a P+ implant to form the wells for the PMOS devices.
Typically 1013 cm-2 @ 300-400 KeV.
(P is heavier than B, so higher energy needed)
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N- and P- well formation
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Threshold voltage (VTH) adjustment
Spin photoresist, photolithography, B+ ion implantation
Implant dose
2 S qN A 2 f qQI
VTH VFB 2 f
COX COX
Figure 2-22
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Note: section 2.2.5 is skipped
Threshold voltage (VTH) adjustment
Remove resist, then spin photoresist, photolithography, As+ ion implantation
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Gate oxide growth
The thin oxide over the active regions is stripped and a new gate oxide
grown, typically 3 - 5nm, which could be grown in 0.5 - 1 hrs @ 800˚C in O2.
19
Poly-crystalline silicon deposition
23
Sidewall spacer formation
24
Sidewall spacer formation
27
Drive-in anneal
Remove resist and anneal (diffusion, damage repair and dopant activation)
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Contact and local interconnect formation
Etch away oxide, deposit Ti
Figure 2-35
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Contact and local interconnect formation
TiN
(conductive)
TiSi2 Anneal in nitrogen
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Multi-level metal formation
Remove resist, deposit SiO2
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Surface planarization
Chemical mechanical polishing (CMP)
Besides CMP, planarization can also be done by spinning resist and etching
back, using a recipe where etching rates for resist and glass are the same.
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Multi-level metal formation
Spin resist, photolithography, oxide etching
Figure 2-40
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W stud (via) formation
Remove resist, deposit TiN diffusion barrier/adhesion layer and W
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W stud (via) formation
Polishing
36
Multi-level metal formation
Deposit Al, spin resist, photolithography, selectively etch Al
P
Inter-metal dielectric and second level metal are deposited and defined in the same way
as level #1.
Mask #14 is used to define contact via-holes.
Mask #15 is used to define metal 2.
Passivation/protection layer of Si3N4 is deposited by PECVD and patterned with Mask #16.
Final anneal (400-500oC, 30min, in forming gas – 10% H2 in N2) to alloy the metal contacts
and reduce electrical charges in the Si/SiO2 interfaces. 38
Finish the device
Wire bonding and packaging
39
Top view of an inverter
40
90 nm
generation
transistor and
interconnect Carrier
moves faster
in strained Si
Ni silicide (not Ti silicide).
Only 1.2nm gate oxide.
Strained silicon.
Low-k dielectric (lower ,
than SiO2,) to reduce
capacitance and RC delay
for faster circuit.
Copper interconnect (not
Al) by electroplating and
chemical mechanical
polishing (see next slide).
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Advanced metallization: Cu based
Dual damascene IC process
42
CMOS interconnects
43