Mindanao State University- Iligan Institute of Technology

EE 270: VLSI Technology

Operational Amplifier
(LAYOUT #2)

Rovil S. Berido
MSEE-Microelectronics I
ID #: 2014-7835
Submission Date: May 2016
Location: /home/rovil_berido/TSMC/TSMC018UM/OP_2016/Op_SPECIAL_x
 INTRODUCTION

In this project, a Miller transconductance operational amplifier

(Miller OTA) was designed and implemented using TSMC 0.18um
technology. The design and implementation was carried out with
Synopsys tool. The Miller OTA was designed for a load capacitance of
10pF.Pre-simulation and post-simulation results for gain, gain
bandwidth, phase margin, CMRR, PSRR and slew rate in TT, SS and
FF corners is presented in this report. Also attached are the waveforms
for each of the simulation results.

Parameter Value
Gain At least 10,000 (equivalent to 80 dB)
Load Capacitance 10 pF
Gain Bandwidth At least 15 MHz for the given load C
Phase Margin At least 60 degrees for the given load C
Transistor Length 1 um
Slew Rate At least 10 V/us

BERIDO OP-AMP LAYOUT

 PROCEDURE

Taking into consideration the parasitic capacitances that may degrade

the frequency response of the design, in the calculation, the following
specifications were used.

Parameter Value Remarks

Gain At least 15,000 (equivalent to 84 dB) 1.5 times the original
Load Capacitance 10 pF ---
Gain Bandwidth At least 20 MHz for the given load C 1.3 times the original
Phase Margin At least 65 degrees for the given load C 1.1 times the original
Transistor Length 1 um ---
Slew Rate At least 15 V/us 1.5 times the original

BERIDO OP-AMP LAYOUT

 PROCEDURE CONT.

Transistor sizes were determined using a combination of hand

calculation and characterization using the Synopsys tool. All transistors
except for transistors used in the current reference are uniformly sized
with W/L (width to length ratio) of 2.5um/1um. Only the multiple
values are varied. In the current reference, W/L used are: 2.5um/1um;
2.5um/6um and 2.5um/ 16um.

BERIDO OP-AMP LAYOUT

 SCHEMATIC

BERIDO OP-AMP LAYOUT

 SCHEMATIC , IREF

BERIDO, ROVIL S. | OP-AMP LAYOUT

 FLOORPLAN

M6
Compensation M3/m M1/M2 M3/m Compensation
Capacitor 4 4 Capacitor

R R

Current Reference

M5/M8
M7 M7
DUMMY

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 IMPLEMENTATION

BERIDO OP-AMP LAYOUT 2016

 IMPLEMENTATION

BERIDO OP-AMP LAYOUT 2016 Constant Gm Iref

 TESTBENCH
Gain, Gain Bandwidth and Phase Margin CMRR

acm=0 acm=1 acm=1 acm=1

SlewRate PSRR

BERIDO OP-AMP LAYOUT

 PRE-SIM RESULTS: Gain, Gain Bandwidth and Phase Margin

P
R
E

S
I
M

R
E
S
Gain=84.6 dB
Gain Bandwidth=21.5 MHz U
Phase Margin=67 degrees
L
T
S
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 PRE-SIM RESULTS: CMRR

P
R
E
CMRR=90.4 dB

S
I
M
PRE-SIM RESULTS: PSRR

R
E
S
PSRR=87.7 dB
U
L
T
S
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PRE-SIM RESULTS: SLEW RATE

P
R
E

S
I
M

R
E
SLEW RATE=15.4V/us
S
U
L
T
S
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 POST-SIM RESULTS: Gain, Gain Bandwidth and Phase Margin

P
O
S
T

S
I
M

R
E
Gain=84.7 dB S
Gain Bandwidth=14 MHz
Phase Margin=70.1degrees U
L
T
S
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 POST-SIM RESULTS: CMRR

P
O
S
CMRR=90.4 dB T

S
I
M
POST-SIM RESULTS: PSRR

R
E
PSRR=88.4 dB S
U
L
T
S
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POST-SIM RESULTS: SLEW RATE

P
O
S
T

S
I
M

R
E
S
SLEW RATE=10.5V/us
U
L
T
S
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 SUMMARY OF RESULTS

TT SS FF
Parameter Target Pre Post Pre Post Pre Post
Gain (dB) 80 84.6 84.7 84.9 84.9 79.4 79.7
Gain Bandwidth (MHz) 15 21.5 14 19.6 13.2 27 16.7
Phase Margin (Degrees) 60 67 80 68 82 63 76
CMRR (dB) --- 90.4 90.4 90.5 90.4 85.8 86.1
PSRR (dB) --- 87.7 88.4 88 88.5 82.9 83.7
Slew Rate (V/us) 10 15.4 10.5 11.9 9.47 17.4 13.9

BERIDO OP-AMP LAYOUT